CA1039364A - Interpolating digital filter - Google Patents
Interpolating digital filterInfo
- Publication number
- CA1039364A CA1039364A CA235,395A CA235395A CA1039364A CA 1039364 A CA1039364 A CA 1039364A CA 235395 A CA235395 A CA 235395A CA 1039364 A CA1039364 A CA 1039364A
- Authority
- CA
- Canada
- Prior art keywords
- input
- code words
- output
- register
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
- H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
- H03H17/0635—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
- H03H17/065—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer
- H03H17/0657—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer where the output-delivery frequency is higher than the input sampling frequency, i.e. interpolation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
- H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
Abstract
ABSTRACT
Non-recursive digital filter producing binary out-put code words at an output sampling frequency "f2" which are related to a sequence of binary input code words which occur at an input sampling frequency "f1", "f2" being an integral multiple (m) of "f1". A storage device is arranged to store a given number (N) of successive input code words and a mult-iplying device is used to form, within one input sampling period l/f1, a number (m) of sets of products of (N) and a number (M) of different sets of weighting factors which correspond to the relationship between the input and output code words. An ad-ding device is coupled to the multiplying device and arranged to generate, within on input sampling period l/f1, a number of output code words which number corresponds to the number of sets of products. Each output code word is at least equal to the mathematical sum of all of the products, of a particular set of products. The storage device is controlled by a clock pulse generator and has a periodically varying storage time. This storage device is provided with an output circuit via which, within one sampling period l/f1, the input code words stored in the device are supplied to the multiplying device a number of times (m) whilst the code words supplied by the output circuit occur sequentially.
Non-recursive digital filter producing binary out-put code words at an output sampling frequency "f2" which are related to a sequence of binary input code words which occur at an input sampling frequency "f1", "f2" being an integral multiple (m) of "f1". A storage device is arranged to store a given number (N) of successive input code words and a mult-iplying device is used to form, within one input sampling period l/f1, a number (m) of sets of products of (N) and a number (M) of different sets of weighting factors which correspond to the relationship between the input and output code words. An ad-ding device is coupled to the multiplying device and arranged to generate, within on input sampling period l/f1, a number of output code words which number corresponds to the number of sets of products. Each output code word is at least equal to the mathematical sum of all of the products, of a particular set of products. The storage device is controlled by a clock pulse generator and has a periodically varying storage time. This storage device is provided with an output circuit via which, within one sampling period l/f1, the input code words stored in the device are supplied to the multiplying device a number of times (m) whilst the code words supplied by the output circuit occur sequentially.
Description
l'l'N, 77'~3 ~; _ 7 - 1 ~ 7 ::1 10;~9364 "Interpolating digital filtcr".
Bacl~,rouJid of the invention.
Field of the inven1;ion.
The invention relates to a non-recursive digital filter for generating binary ou-tput code words which occur at a given output sanlpling frequency f2 and are related in a predetermined manner to a sequence Or binary input code words which occur at an input sampling frequency f1, the output sampling frequency f2 being an integral multiple (m) of the-:input sampling frequency f1. This digital filter comprises a storage device arranged to store a given number (N) of successive input code words; a multiplying device for forming, within one input sampling period l/f1, a number (m) of sets of products of the said given number (N) of input code words and a number (m) of different sets of weighting factors which correspond to the relationship between the input and the output oodè words; an adding device which is coupled to the said multiplying device and is adapted to generate, within one input sampling period l/f1, a number of output codewords, which number corresponds to the number (m) of sets of products, each output code word being at least equal to the mathematical sum of all of the products of one particular set of products.
Such a digital filter arranged for increasing t;he sampling rat;e has already been termed an interpolating digital filter,
Bacl~,rouJid of the invention.
Field of the inven1;ion.
The invention relates to a non-recursive digital filter for generating binary ou-tput code words which occur at a given output sanlpling frequency f2 and are related in a predetermined manner to a sequence Or binary input code words which occur at an input sampling frequency f1, the output sampling frequency f2 being an integral multiple (m) of the-:input sampling frequency f1. This digital filter comprises a storage device arranged to store a given number (N) of successive input code words; a multiplying device for forming, within one input sampling period l/f1, a number (m) of sets of products of the said given number (N) of input code words and a number (m) of different sets of weighting factors which correspond to the relationship between the input and the output oodè words; an adding device which is coupled to the said multiplying device and is adapted to generate, within one input sampling period l/f1, a number of output codewords, which number corresponds to the number (m) of sets of products, each output code word being at least equal to the mathematical sum of all of the products of one particular set of products.
Such a digital filter arranged for increasing t;he sampling rat;e has already been termed an interpolating digital filter,
(2) Description or_th3 prior art.
In a prior art interpolating non-recursive J~IT~ . 7~33 ~-7- 19~
. 1039364 digi-tal f`ilter the stor~ge dev:ice has the fortn Or a delay line comprising a plurality (N) of delay sections each being arranged to store a single input code word. These delay sections are each connected to an adding device via a tapping which includes a multiplier. To each multiplier a weighting factor from a given set of weighting facb~rs is supplied.
In particular, in the said prior art digital filter, the input code words are subjected to a predeternlined sequence of aritlmletical operations to produce an output code word. These operations can mathematically be represented by the convolution sum:
- y ~ ~ q/m)'~ = ~ C ~ k~ x ~ n-- k)~
where ~ = 0~ 1~ 2~ 3~ m - 1.
In this expression:
m is an integer denoting the rëlationship between the input and output sampling frequencies (m = f2/if~);
N is an even number indicating the number of input code words stored in the input circuit;
T is the reciprocal value of the input sampling frequenc~
T = l/f1;
x ~n-- k)~ is one input code word of the code words which occur with a period T = l/f1;
n is the ordinal number of the code word which occurs after the instant t = 0;
y ~n + q/m)~ is one of the output code words which occur with a period T/m;
Cq~ k~ is a weighting factor.
It should be noted that the said weighting .. . .
Pl~r. 77 ~-7-1~75 ~03g364 factors are commonly tcrmed "filter coefficients" and are stored in a storage device such as, for example, a ~OM.
I-Iowever, to permit the above-described interpolating filter to perform the given mathematical operations it must have a size and a di~sipation such that its practical usefulness is greatly restricted, for example with respect to the possibility of time multiplex processing of information signals.
(B). Summaly of the invention.
It is an object of the present invention to provide an interpolating non-recursive digital filter the size and dissipation of which are reduced to an extent ; such that i.t can be manufactured by means of integrated-circuit techniques, such as for example I L, whilst time-sharing can be used for performing various filter functions on a given sequence of input signal samples and /or a single filter function on a given pl~rality of sequences of input signal samples.
According.to the invention this is achieved in that the said storage device for storing the said given number (N) of successive input code words is a circulating storage device which has a periodically changing storage time and is controlled by a clock-pulse generator and has an output circuit via which within one 2~ input sampling period 1/f1 the input code words stored in the storage device are supplied a plurality of times to the said multiplying device, the said plurality of times being equal to the said integral multip].c (rn), whilst the code ~ord.~ delivered by the said output circuit occurs l~ir~'. 77'~'3 ~,-7~ 7~
.. .
sequential.ly .
The said storage device may take the form of a shift-register each register section of which is arranged to s-tore a complete code word, however, as an alternative a l~l may be us~d.
. Brier descripti,on of the drawi}lgs.
Figure 1 shows a non-recursive digital filter according to the invention;
Figure 2 shows waveforms illustrating the operation of the digital filter shown in Figure 1;
Figure 3 shows graphs illustrating the choice of the filter coefficients to be used in an 'interpolating digital filter;
Figure 4 shows a modified embodiment of the interpolating digital filter shown in Figure 1;
Figure 5 shows waveforms illustratlng the operation of the digital filter shown in Figure 4.
(D). Description of the interpolating di~ital filter.
(1) The interpolating digital filter in general.
Figure 1 shows an interpolating non-recursive digital filter according to the invention. This filter may form part, for example, of a receiver of a PCM telccommunication system. It has an input circuit 1 to which the input signal to be filtered is supplied. This input signal, which in the Figure is denoted by x(nT), comprises a sequence of binary-coded samples of an analog information signal, which samples have been taken at a frequency f1 which hereinbefore has been termed the input sampling frequency. The said binary-coded samples, which in general are termed "code l'lf~. 77'~'J
~ _ 7 ~ 1 ',3 ~ 5 words", are generated, for exalllplc, in ~he transmitter of the said PCM telecommunication system. ~or processing in thc digi~al filter shown in Figure 1 tl-e said input code words which occur sequentially with a period T = l/
are Pach suppli~d to a switchil1g device 2 which comprises three AND gates 3, 4 and 5 and an OR gate 6, the ~ND gates
In a prior art interpolating non-recursive J~IT~ . 7~33 ~-7- 19~
. 1039364 digi-tal f`ilter the stor~ge dev:ice has the fortn Or a delay line comprising a plurality (N) of delay sections each being arranged to store a single input code word. These delay sections are each connected to an adding device via a tapping which includes a multiplier. To each multiplier a weighting factor from a given set of weighting facb~rs is supplied.
In particular, in the said prior art digital filter, the input code words are subjected to a predeternlined sequence of aritlmletical operations to produce an output code word. These operations can mathematically be represented by the convolution sum:
- y ~ ~ q/m)'~ = ~ C ~ k~ x ~ n-- k)~
where ~ = 0~ 1~ 2~ 3~ m - 1.
In this expression:
m is an integer denoting the rëlationship between the input and output sampling frequencies (m = f2/if~);
N is an even number indicating the number of input code words stored in the input circuit;
T is the reciprocal value of the input sampling frequenc~
T = l/f1;
x ~n-- k)~ is one input code word of the code words which occur with a period T = l/f1;
n is the ordinal number of the code word which occurs after the instant t = 0;
y ~n + q/m)~ is one of the output code words which occur with a period T/m;
Cq~ k~ is a weighting factor.
It should be noted that the said weighting .. . .
Pl~r. 77 ~-7-1~75 ~03g364 factors are commonly tcrmed "filter coefficients" and are stored in a storage device such as, for example, a ~OM.
I-Iowever, to permit the above-described interpolating filter to perform the given mathematical operations it must have a size and a di~sipation such that its practical usefulness is greatly restricted, for example with respect to the possibility of time multiplex processing of information signals.
(B). Summaly of the invention.
It is an object of the present invention to provide an interpolating non-recursive digital filter the size and dissipation of which are reduced to an extent ; such that i.t can be manufactured by means of integrated-circuit techniques, such as for example I L, whilst time-sharing can be used for performing various filter functions on a given sequence of input signal samples and /or a single filter function on a given pl~rality of sequences of input signal samples.
According.to the invention this is achieved in that the said storage device for storing the said given number (N) of successive input code words is a circulating storage device which has a periodically changing storage time and is controlled by a clock-pulse generator and has an output circuit via which within one 2~ input sampling period 1/f1 the input code words stored in the storage device are supplied a plurality of times to the said multiplying device, the said plurality of times being equal to the said integral multip].c (rn), whilst the code ~ord.~ delivered by the said output circuit occurs l~ir~'. 77'~'3 ~,-7~ 7~
.. .
sequential.ly .
The said storage device may take the form of a shift-register each register section of which is arranged to s-tore a complete code word, however, as an alternative a l~l may be us~d.
. Brier descripti,on of the drawi}lgs.
Figure 1 shows a non-recursive digital filter according to the invention;
Figure 2 shows waveforms illustrating the operation of the digital filter shown in Figure 1;
Figure 3 shows graphs illustrating the choice of the filter coefficients to be used in an 'interpolating digital filter;
Figure 4 shows a modified embodiment of the interpolating digital filter shown in Figure 1;
Figure 5 shows waveforms illustratlng the operation of the digital filter shown in Figure 4.
(D). Description of the interpolating di~ital filter.
(1) The interpolating digital filter in general.
Figure 1 shows an interpolating non-recursive digital filter according to the invention. This filter may form part, for example, of a receiver of a PCM telccommunication system. It has an input circuit 1 to which the input signal to be filtered is supplied. This input signal, which in the Figure is denoted by x(nT), comprises a sequence of binary-coded samples of an analog information signal, which samples have been taken at a frequency f1 which hereinbefore has been termed the input sampling frequency. The said binary-coded samples, which in general are termed "code l'lf~. 77'~'J
~ _ 7 ~ 1 ',3 ~ 5 words", are generated, for exalllplc, in ~he transmitter of the said PCM telecommunication system. ~or processing in thc digi~al filter shown in Figure 1 tl-e said input code words which occur sequentially with a period T = l/
are Pach suppli~d to a switchil1g device 2 which comprises three AND gates 3, 4 and 5 and an OR gate 6, the ~ND gates
3, 4 and 5 having cloclc pulses supplicd to them by a cloclc-pulse generator 7.
In this digital filter thc input code words x(nT) are processed according to the mathematical expression set out hereinbefore, whilst the various sets of filter coefficients C ~, k~ , which are characterized by the values of ~ and in which k = Oj 1, 2, ... , (n-1), are stored in a storage device 8, for example a ROM.
If in the swi-tching device 2 the ~ND gate 3 is opened by a clock pulse from the generator 7, the sequentially occurring code words x(nT) are written in a storage device 9 which in this embodiment is in the form of a shift register having five register sections 10(0) to 10(4) each arranged to store a complete input code word. In this shift register successive input code words are stored in successive register sections. Whenever a new code word is written in this register, the stored code words are shifted one position and the coldest code word stored disappears Irom the register. In symbolic representation, after a new input code word has been written in the register the register sections 10(0) to 10(4) contain the code words x(n), x(n-1), x(n 2), x(n-3) and x(n-4) respectively.
]~lr~. 7733 7-1'~7~
1039~64 . After a new input code word has been written in the store, the ~ND gate 3 is closecl and tho ~D gate 4 is opened by a control pulse from the generator 7, in which condition the last register section 10(4) is connected to the first OI` input register section 10(0) so that a circulating shift register is obtained.
Writing-in a new input code word is followed by a computing cycle in which clocl; pulses are supplied to the register sections and control pulses are supplied . to the ROM 8. As a result, a filter coefficient and the corresponding code.word stored in the last register section 10(4) are supplied to inpu-ts of a multiplier 11 which forms the product of these two code-words and supplies it to an accumulator 12. In this embodiment the accumulator 12 has been reset to zero at the instant at whi~h a new input code word is inserted into the.shift register 9. ~fter all the:input code words stored in the register 9 have been multiplied once by a filter coefficient and the resulting products have been summed in the accumulator 12, that is to say at the end of the computing cycle, the accumulator is reset to zero. However, each time before the accumulator is reset to zero the code word then stored in the accumulator is read out by means of a transfer circuit 13. This code word constitutes the output code word y (n + q/m)T which in this embodiment, for examplo, is written in a buffer 13(1) which may be in the form of a shift rcgister. Under control of clock pulses from the generator 7 the bits Or the said output code words can be rea(1, for example serial].y, from th.e register 13(1).
1'll)'.. 77~3 ~-7 1~75 It should be ment;ioned -that the bits of the numbers x(nT), y ~n ~ q/m)~ and C ~q, k~ can occur in series and in parallel and can be stored in t}le various storage elements in both forms. IIence no distinction will be made between these two forms in the Figures or in the text of this specificati.on.
In order to implement an interpolating digital filter, i.e. in order to generate a given n~ber m of output code words (m> 1), within a period T of the input code words, the abovedescribed computing cycle is repeated a number Or times, namely m -times. For each of these ->
computing cycles the same set of input code words is used, however,- for different computing cycles within the said period T different sets of filter coefficients are used which are interrelated in a manner to be described herein-after.
(2) The interpolatin~ di~ital filter in detail In order to ensure that the output code words y ~n ~ q/m ~ are all available at equal time intervals of T/m, the shift register 9 is constructed as a shift register having a periodically varying s-torage or delay time. More particularly, in this embodiment it is a shift register of periodically varying length. For this purpose the output of the register section 10(3) is connected to the first register section 10(0) by a back-coupling line 14 and via the AND gate 5 and the OR gate 6. At an instant to be defined hereinafter this back-coupling line is activated by the clock pulse generator 7 which for this purpose at the said instant delivers Q pulse which opens ,. . . , , ~ ,. . .
l'il!i. 7/ ,) the ~NI~ ga(;e 5 and closos the ~TD gates 3 and l~
The operation of the shift register 9 will now be described in more detail with referenco to Table I for the case in which m = 2 and N = 5. In this Table I columns 10(0) to 10(11 ) ohow the contents of the register sections 10(0) to 10(4) respectively and column 5 shows the filter coefficient by which the input code word stored in section 10(4) (column 10(4)) is multiplied.
The rows which in this Table I are denoted by three reference characters p, r and s (p = 1, 2, 3, 4; r =
1, 2; s = 1, 2, 3, 4, 5) each indicate the sequence of the stored code words which occurs in the shift register 9 at a given instant. Such a sequence of code words will herein-after be termed the state of the shift register 9. A given state, for example that denoted by 1.1.3, passes to the succeeding state 1.1.4 under eontrol of a shift pulse. The states 1.1.1, 2.1.1, 3.1.1 and 4.1.1 are those which occur immediately after insertion of a new code word, namely the code words x(n), x(n+1), x(n+2) and x(n+3) respectively.
After the insertion of a new input code word, for example the code word x(n), the first computing cycle takes place, the shift register 9 being successively in the states 1.1.1 to 1.15 shown in Table I. When in state 1.1.5 the multiplication x(n).C(0,0) has been performed, the contents of the accumulator are read out and the accumulator is reset to zero. Subsequently the second eomputing cycle takes place, the shift register 9 passing throug~h the states 1.2.1 to 1.2.5. When at the beginning of this seconcl eomput-ing cycle the shift registér 9 has ]~ 77 ~ '~
~--7-- 1 ~ i~
1039~64 been brought into the state 1.2.1, thc AND gate l~ is closed and the AND gate 5 is opened so that on the occurrence of further shirt pulses thc contents of the rcgister section 10(3) is written both in the regist~r section 10(4) and in the first register section 10(0). Consequcntly the oldest code word x(n _ 4) stored in the register 9 is lost from this register 9 after the beginrling of tlle second computing cycle and at each shift pulse a same code word is written in the first and last register sections 10(0) and 10(4) respectively.
~len the last multiplication in the sampling period under consideration has bcen performed, the AND
gate 5 is closed and the AND gate 3 is opened whilst the AND gate 4 remains closed. As a result, at the instant of occurrence of a shift pulse a new input code word x(n+1) is written in the register section 10(0) whilst simultaneously the code words stored in the register 9 are shifted one position. Immediately after insertion of the code word x(n~1) the first of two new computing cycles begins, the shift register states being indicated in the Table by the references in which p has the value 2. Thc Table further shows the two computing cycles which follow after the insertion of the code word x(n + 2). The shift registar states associated with these computing cycles are denoted by the references in which ~ has the value 3.
Thus the use of the feedback line 14 ensures that already during the last computing cycle within a given sampling period the input code words in the shift register are shifted so that the state of the shift register during perrormance oI` the last multiplication ,' . 7733 8~7-1~75 of the said last computing cycle, for example the multiplication x(n).C(1,0) in the state 1.2.5 of the shift register (see the Table), is equal to the state of the shift register immediately after insertion of a new input code word at the beginning of the sampling period considered, however, the initially oldest input code word has disappcared from the register 9 (compare the states 1.2.5 and 1.1.1 of the Table). This ensures that the shift pulses for the shift register 9 continually occur successively with the same period.
That the use of the feedback lines results in the shift register having a periodically varying storage or delay time can be illustrated with reference to column 10(11) of Table I. We will consider, for example, the code word x(n - 1). The Table shows that in order to be multiplied by a filter coefficient this code word is present in the register section 10(4) during the shift register states 1.14; 1.2.4; 2.1.3; 3.1.2; 3.2.2; 4.1.1.
Because the time interval between two successive states of the shift register is equal to one shift period T/Nm, the time interval between shift register states 1.1.4 and 1.2.4 is equal to 5T/Nm, that between states 1.2.4 and 2,1,~, however is equal to 4T/Nm only; that between the states 2.1.3 and 2.2.3 equal to 5T/Nm again; that between states 2.2.3 and 3.1.2 equal to 4T/Nm again, and so on.
As will be seen from Table I, the use of a shift register having a periodically varying delay time ensures that all -the computing cycles have the same duration and the output code words Y E n + q/m) ~ all occur . 77'~3 ~7-1J75 at equidistant instants.
Although after the insertion of an input code word in the register 9 the embodiment sho~n in Figure 1 and described with reference to Table I delivers only two output code words, the number of output code words may be increased at will. ~lowever, such increase also results in an increase in the number of sets of filter coefficient~.
(3) Control circuit As has been mentioned hereinbefore, the various elements of the digital filter are controlled by the clock pulse generator 7. More particularly, this~clock pulse generator includes an oscillator 15 which delivers output pulses at a frequency 3Nmf1, where N is the number of shift register sections of the register 9 and m again is the number of desired output code words per input sampling period T. The output of this oscillator 15 is connected to the input of a first binary`divider or counter 16 which in this embodiment divides the output frequency of the oscillator by a factor ôf three. Given sections of this counter 15 are connected to inputs of AND gates 17, 18 and , 19, The connections are schematically shown in the Figure by a shaded area 16 (1). The output of AND gate 17 is connected to the clock pulse inputs of the shift register sections 10(.). The output of AND gate 19 is connected to the input of a second binary divider or counter 20 the output of which is connected to the input of a third binary divider or counter 21.
The clock pulse generator shown further comprises four AND gates 22 to ,25 and two inverters 26 and 27. These .
, . .
. 77'~'~
~-7-1975 _ 103936~1 AND gates and inverters are connectcd in the Inanner shown in the Figure to the outputs of the counters 20 and 21 and of the AND gates 18 and 19.
The operation of the clock pulse generator sho~n will llOW be described more fully with refcrence to the waveforms shoml in Figurc 2 for the case where N =
5 and m = 2. In Figure 2 the train of clock pulses generated by the oscillator 15 is sho~n at a. The counter 16 divides the output frequency of this(oscillator 15 by a factor of three and thus defines cycles of three successive output pulses of the oscillator 15. The first clock pulse of such a cycle causes the AND gate 17 to deliver an output pulse, the second clock pulse of such a cycle causes the AND gate 18 to deliver an output pulse and the third cloclcpulse of such a cycle causes the AND gate 19 to deliver an output pulse. The resulting trains of output pulses of the AND gates 17, 18 and 19 are sho~n in Figure 2 at b, c and d respectively.
After each cycle of N = 5 output pulses from the AND gate 19 the counter 20 delivers an output pulse and thereby determines the end of a computing cycle of the filter. The output pulses of the counter 20 are sno~m in Figure 2 at e. The output pulse of AND gate 18 which occurs during this output pulse of counter 20 causes the AND gate 25 to deliver an output pulse which results in that the contents of the accumulator 12 are wri-tten, via the transfer circuit 13, in the buffer 13(1). The pulse delivered by the AND gate 19 during the occurrence of the output pulse of counter 20 resets the accumulator 12 to 1 ~ _ '. 773 ~-7-197~
zero via the ANI) gate 24. The said output pulses of the AND gates 25 and 24 are shown in ~`igure 2 at ~ and h respectively.
The counter 21 is arranged to count m output pulses from the counter 20 and in doing so passes cyclically through the coul~ts zero up to and including m `- 1. As long as the counter 21 has not reached the count m - 1, it delivers at its output a binary "0" which is supplied to AND gate 4 via the inverter 27. Thus the AND
gate 4 is opened and during the f`irst m - 1 computing cycles the contents of the shift register 9 are circulated via this AND gate ~I, When the count m - 1 is reached the counter 21 delivers a binary "1". As a result the AND gate
In this digital filter thc input code words x(nT) are processed according to the mathematical expression set out hereinbefore, whilst the various sets of filter coefficients C ~, k~ , which are characterized by the values of ~ and in which k = Oj 1, 2, ... , (n-1), are stored in a storage device 8, for example a ROM.
If in the swi-tching device 2 the ~ND gate 3 is opened by a clock pulse from the generator 7, the sequentially occurring code words x(nT) are written in a storage device 9 which in this embodiment is in the form of a shift register having five register sections 10(0) to 10(4) each arranged to store a complete input code word. In this shift register successive input code words are stored in successive register sections. Whenever a new code word is written in this register, the stored code words are shifted one position and the coldest code word stored disappears Irom the register. In symbolic representation, after a new input code word has been written in the register the register sections 10(0) to 10(4) contain the code words x(n), x(n-1), x(n 2), x(n-3) and x(n-4) respectively.
]~lr~. 7733 7-1'~7~
1039~64 . After a new input code word has been written in the store, the ~ND gate 3 is closecl and tho ~D gate 4 is opened by a control pulse from the generator 7, in which condition the last register section 10(4) is connected to the first OI` input register section 10(0) so that a circulating shift register is obtained.
Writing-in a new input code word is followed by a computing cycle in which clocl; pulses are supplied to the register sections and control pulses are supplied . to the ROM 8. As a result, a filter coefficient and the corresponding code.word stored in the last register section 10(4) are supplied to inpu-ts of a multiplier 11 which forms the product of these two code-words and supplies it to an accumulator 12. In this embodiment the accumulator 12 has been reset to zero at the instant at whi~h a new input code word is inserted into the.shift register 9. ~fter all the:input code words stored in the register 9 have been multiplied once by a filter coefficient and the resulting products have been summed in the accumulator 12, that is to say at the end of the computing cycle, the accumulator is reset to zero. However, each time before the accumulator is reset to zero the code word then stored in the accumulator is read out by means of a transfer circuit 13. This code word constitutes the output code word y (n + q/m)T which in this embodiment, for examplo, is written in a buffer 13(1) which may be in the form of a shift rcgister. Under control of clock pulses from the generator 7 the bits Or the said output code words can be rea(1, for example serial].y, from th.e register 13(1).
1'll)'.. 77~3 ~-7 1~75 It should be ment;ioned -that the bits of the numbers x(nT), y ~n ~ q/m)~ and C ~q, k~ can occur in series and in parallel and can be stored in t}le various storage elements in both forms. IIence no distinction will be made between these two forms in the Figures or in the text of this specificati.on.
In order to implement an interpolating digital filter, i.e. in order to generate a given n~ber m of output code words (m> 1), within a period T of the input code words, the abovedescribed computing cycle is repeated a number Or times, namely m -times. For each of these ->
computing cycles the same set of input code words is used, however,- for different computing cycles within the said period T different sets of filter coefficients are used which are interrelated in a manner to be described herein-after.
(2) The interpolatin~ di~ital filter in detail In order to ensure that the output code words y ~n ~ q/m ~ are all available at equal time intervals of T/m, the shift register 9 is constructed as a shift register having a periodically varying s-torage or delay time. More particularly, in this embodiment it is a shift register of periodically varying length. For this purpose the output of the register section 10(3) is connected to the first register section 10(0) by a back-coupling line 14 and via the AND gate 5 and the OR gate 6. At an instant to be defined hereinafter this back-coupling line is activated by the clock pulse generator 7 which for this purpose at the said instant delivers Q pulse which opens ,. . . , , ~ ,. . .
l'il!i. 7/ ,) the ~NI~ ga(;e 5 and closos the ~TD gates 3 and l~
The operation of the shift register 9 will now be described in more detail with referenco to Table I for the case in which m = 2 and N = 5. In this Table I columns 10(0) to 10(11 ) ohow the contents of the register sections 10(0) to 10(4) respectively and column 5 shows the filter coefficient by which the input code word stored in section 10(4) (column 10(4)) is multiplied.
The rows which in this Table I are denoted by three reference characters p, r and s (p = 1, 2, 3, 4; r =
1, 2; s = 1, 2, 3, 4, 5) each indicate the sequence of the stored code words which occurs in the shift register 9 at a given instant. Such a sequence of code words will herein-after be termed the state of the shift register 9. A given state, for example that denoted by 1.1.3, passes to the succeeding state 1.1.4 under eontrol of a shift pulse. The states 1.1.1, 2.1.1, 3.1.1 and 4.1.1 are those which occur immediately after insertion of a new code word, namely the code words x(n), x(n+1), x(n+2) and x(n+3) respectively.
After the insertion of a new input code word, for example the code word x(n), the first computing cycle takes place, the shift register 9 being successively in the states 1.1.1 to 1.15 shown in Table I. When in state 1.1.5 the multiplication x(n).C(0,0) has been performed, the contents of the accumulator are read out and the accumulator is reset to zero. Subsequently the second eomputing cycle takes place, the shift register 9 passing throug~h the states 1.2.1 to 1.2.5. When at the beginning of this seconcl eomput-ing cycle the shift registér 9 has ]~ 77 ~ '~
~--7-- 1 ~ i~
1039~64 been brought into the state 1.2.1, thc AND gate l~ is closed and the AND gate 5 is opened so that on the occurrence of further shirt pulses thc contents of the rcgister section 10(3) is written both in the regist~r section 10(4) and in the first register section 10(0). Consequcntly the oldest code word x(n _ 4) stored in the register 9 is lost from this register 9 after the beginrling of tlle second computing cycle and at each shift pulse a same code word is written in the first and last register sections 10(0) and 10(4) respectively.
~len the last multiplication in the sampling period under consideration has bcen performed, the AND
gate 5 is closed and the AND gate 3 is opened whilst the AND gate 4 remains closed. As a result, at the instant of occurrence of a shift pulse a new input code word x(n+1) is written in the register section 10(0) whilst simultaneously the code words stored in the register 9 are shifted one position. Immediately after insertion of the code word x(n~1) the first of two new computing cycles begins, the shift register states being indicated in the Table by the references in which p has the value 2. Thc Table further shows the two computing cycles which follow after the insertion of the code word x(n + 2). The shift registar states associated with these computing cycles are denoted by the references in which ~ has the value 3.
Thus the use of the feedback line 14 ensures that already during the last computing cycle within a given sampling period the input code words in the shift register are shifted so that the state of the shift register during perrormance oI` the last multiplication ,' . 7733 8~7-1~75 of the said last computing cycle, for example the multiplication x(n).C(1,0) in the state 1.2.5 of the shift register (see the Table), is equal to the state of the shift register immediately after insertion of a new input code word at the beginning of the sampling period considered, however, the initially oldest input code word has disappcared from the register 9 (compare the states 1.2.5 and 1.1.1 of the Table). This ensures that the shift pulses for the shift register 9 continually occur successively with the same period.
That the use of the feedback lines results in the shift register having a periodically varying storage or delay time can be illustrated with reference to column 10(11) of Table I. We will consider, for example, the code word x(n - 1). The Table shows that in order to be multiplied by a filter coefficient this code word is present in the register section 10(4) during the shift register states 1.14; 1.2.4; 2.1.3; 3.1.2; 3.2.2; 4.1.1.
Because the time interval between two successive states of the shift register is equal to one shift period T/Nm, the time interval between shift register states 1.1.4 and 1.2.4 is equal to 5T/Nm, that between states 1.2.4 and 2,1,~, however is equal to 4T/Nm only; that between the states 2.1.3 and 2.2.3 equal to 5T/Nm again; that between states 2.2.3 and 3.1.2 equal to 4T/Nm again, and so on.
As will be seen from Table I, the use of a shift register having a periodically varying delay time ensures that all -the computing cycles have the same duration and the output code words Y E n + q/m) ~ all occur . 77'~3 ~7-1J75 at equidistant instants.
Although after the insertion of an input code word in the register 9 the embodiment sho~n in Figure 1 and described with reference to Table I delivers only two output code words, the number of output code words may be increased at will. ~lowever, such increase also results in an increase in the number of sets of filter coefficient~.
(3) Control circuit As has been mentioned hereinbefore, the various elements of the digital filter are controlled by the clock pulse generator 7. More particularly, this~clock pulse generator includes an oscillator 15 which delivers output pulses at a frequency 3Nmf1, where N is the number of shift register sections of the register 9 and m again is the number of desired output code words per input sampling period T. The output of this oscillator 15 is connected to the input of a first binary`divider or counter 16 which in this embodiment divides the output frequency of the oscillator by a factor ôf three. Given sections of this counter 15 are connected to inputs of AND gates 17, 18 and , 19, The connections are schematically shown in the Figure by a shaded area 16 (1). The output of AND gate 17 is connected to the clock pulse inputs of the shift register sections 10(.). The output of AND gate 19 is connected to the input of a second binary divider or counter 20 the output of which is connected to the input of a third binary divider or counter 21.
The clock pulse generator shown further comprises four AND gates 22 to ,25 and two inverters 26 and 27. These .
, . .
. 77'~'~
~-7-1975 _ 103936~1 AND gates and inverters are connectcd in the Inanner shown in the Figure to the outputs of the counters 20 and 21 and of the AND gates 18 and 19.
The operation of the clock pulse generator sho~n will llOW be described more fully with refcrence to the waveforms shoml in Figurc 2 for the case where N =
5 and m = 2. In Figure 2 the train of clock pulses generated by the oscillator 15 is sho~n at a. The counter 16 divides the output frequency of this(oscillator 15 by a factor of three and thus defines cycles of three successive output pulses of the oscillator 15. The first clock pulse of such a cycle causes the AND gate 17 to deliver an output pulse, the second clock pulse of such a cycle causes the AND gate 18 to deliver an output pulse and the third cloclcpulse of such a cycle causes the AND gate 19 to deliver an output pulse. The resulting trains of output pulses of the AND gates 17, 18 and 19 are sho~n in Figure 2 at b, c and d respectively.
After each cycle of N = 5 output pulses from the AND gate 19 the counter 20 delivers an output pulse and thereby determines the end of a computing cycle of the filter. The output pulses of the counter 20 are sno~m in Figure 2 at e. The output pulse of AND gate 18 which occurs during this output pulse of counter 20 causes the AND gate 25 to deliver an output pulse which results in that the contents of the accumulator 12 are wri-tten, via the transfer circuit 13, in the buffer 13(1). The pulse delivered by the AND gate 19 during the occurrence of the output pulse of counter 20 resets the accumulator 12 to 1 ~ _ '. 773 ~-7-197~
zero via the ANI) gate 24. The said output pulses of the AND gates 25 and 24 are shown in ~`igure 2 at ~ and h respectively.
The counter 21 is arranged to count m output pulses from the counter 20 and in doing so passes cyclically through the coul~ts zero up to and including m `- 1. As long as the counter 21 has not reached the count m - 1, it delivers at its output a binary "0" which is supplied to AND gate 4 via the inverter 27. Thus the AND
gate 4 is opened and during the f`irst m - 1 computing cycles the contents of the shift register 9 are circulated via this AND gate ~I, When the count m - 1 is reached the counter 21 delivers a binary "1". As a result the AND gate
4 is closed and the AND gates 22 and 23 are opened. During the following new cycle of the counter 20 the AND gate 22 is open owing to the provision of the inverter 26 and delivers a binary "1" so that the AND gate 5 is opened and during the last computing cycle within a given samplin~
period T the circulating state of the shift register is established via the AND gate 5. ~hen eventually in this last cycle of the counter 20 the N output pulse from the AND gate 19 is applied to the counter 20, the AND gate 22 again delivers a binary "0" so that the AND gate,5 is closed and hence all back-coupling paths of the register 9 are interrupted. Mso the AND gate 23 now supplies a binary "1" to the AND gate 3, permitting a new code word to be written in the register, and finally the said Nth pulse resets the counter 21 to zero. l`he output pulses delivered by the counter 21, the inverter 27 and thc AND gates 22 and _ 14 -, 7~ 3 7-1'~75 23 are shown in Figure 2 a-t f, i. l~ and p respectively, It should be mentioned that reading a filter coefficient from the ~OM 8 can be effected in known manner, for example in that each instant the counts of the counters 20 and 21 are jointly considered as one address code for the ROM. ~or this purposQ all the sections of the two counters 20 and 21 are connected to`corresponding inputs of the ~0~1 8, as is shown schematically in Figure 1 by the~
shaded area 8(1).
(4) The relationship betweell the filt;er coefficients ~to be used in the interpolatin~ di~ital filter.
As has been mentioned with reference to Table I, each computing cycle within a given input sampling period is associated with a set of filter coefficients C (q, k).
In the said Table, for the firsttcomputing cycle within the said sampling period the set of filter coefficients C(q, k) is characterized by q = O, and for the second computing cycle within the sampling period considered, which cycle is the last one in the Table, the said set is characterized by q = 1. As has been mentioned hereinbefore and as is indicated in the Table, for a given filter these sets ~f filter coefficients are the same for all sampling periods.
The filter coefficients of a set are equal in magnitude to the individual samples of a sequence of samplings of the pulse response of the desired filter. For use in the filter the said samples are usually quantized and encoded, for example in a binary number.
To illustrate the relationship between the ffets of filter coefficients Fig~ro 3a shows the pulse 3!1lN 7r/S3 7-1'~75 ~039;}64 respollse, limi~,ed to the time intorval from -~'l` to ~10T, of an ideal low-pass filter having a cut-off frequency ~ /2. ~s is k~own, this pul.se rcspollse has a shape given by the functioll (sin x)/x. ~lore particularly -the pulse response shown can be represented by the mathelnati.cal expression sin (t - 2T) ~o/2 ;~ o ~ (~ 2T) ~o/2 First we will consider the said low-pass filter as a non-interpolating one, that is to say a filter in which the input and output sampling frequencies are equal. It is assumed that these sampling frequencies are equal to four times the cut-off frequency of the filter. Th~ sampling period then is equal to T = ~ ~0.
To determine the filter coefficients the pulse response of the filter is sampled with the train of sampling pulses shown in Figure 3b. It is assumed that these sampling pulses occur at instants t = k.T. In known manner this train can be represented mathematically by C~
' ~(t - kT) k = - C~
The five filter coefficients which are used in the filter shown in Figure 1 for approximating to the desired transfer characteristic now are constituted by those samples of the pulse re-sponse which occur at the instants for which k - 0, 1, 2, 3, I~, rcspectively. For the resulting filter coefficients which together form a set C (0, k.) the - - 1G _ 1'JIi`i. 77,3 (~-7-1'~75 r~spective magnitudes are shown at d in I`igure 3. In this - Figure not only the parameter values k but also the instants at which the relevant filter coefficient occurs as an instantaneous signal value for the pulse response . shown in Figure 3a are plo-tted along the abscissa.
1~len the low-pass filter having the pulse response shown in Figure 3a is to be used as an interpol.ating filter in wllich the output sampling frequency is equal to twice the input sampling frequency, i.e. with an output sampling period equal to T/2 = ~/2 ~0, in order to obtain a first output code word the input code words stored in the register 9 shown in Figure 1 are first multiplied by the above-mentioned set of filter coefficients C(0, k), whilst for obtaining a second output code words are also multiplied by a second set of filter coefficients C (1, k). This second set of filter coefficients is shown in Figure 3e. These filter coefficients agai.n are equal to the samples of the pulse response shown in Figure 3a and sampled with a period T. Here also said sampling of the pulse response has been effected with a.pulse train of the shape shown in Figure 3b, however, with respect to this pulse train it has been shifted in time by T/2 = + ~/2 W0, so that the train of sampling pulses for the second set of filter coefficients can be represented mathematically by:
_ (kT + T/2)~
k = ~
Thus the filter coefficients C(1, k) are -the samples of the pulse response shown in Figure 3a which are taken at l7 7^i','~
9 ~ 7 :>
, ~
~039;~64 the instants kT + 1`/2, where k = 0, 1, 2, 3, 4.
For completeness Figure 3 at f and ~ shows the sets of filter coefficients for the case where the output sampling frequency of the interpolating filter is thrice its input sampling frequency. In this case, within an input sampling period the input code words storod must be multiplied once by the set of filter coefficients C(0, k) (see Figure 3d), once by the set of coefficients C(2, k) (see Figure 3~), and once by the set C(3, k) (see Figure 3g). The said sets of filter coefficients C(2, k) and Ct3, k) also are obtained by sampling the pulse response shown in Figure 3a, the train of sampling pulses again having the same shape as in Figure 3b, however, the said trains are shifted with respect to the latter train by time intervals T/3 and 2T/3 respectively. In analogy with the above, the latter pulses can be mathematically represented by:
~ kT ~ T/3)¦
k = _ and C~ .
(kT ~ 2T/3)~
k = - c~ ~
respectively.
~ n interpolating digital filter has effects not only in the time domain but also in the frequency domain, for if a band-l:imited analog base-band signal is sampled at an input sampling f`requency f1 the frequency - 1 l'3 ,, ,. ' 1'll~'. 77',~
~~7~1'J75 .
sp-ctrwn ol` this sampled sjgnal is constitutcd by the initial base-band spectrum and by repetitions of this spectrum at integral multiples of the sarnpling frequency ~; f1. Thus the first repetition of the initial base-band spectrum lies around the sampling frequency fl. In PC~I
transmission systems this frequency f1 is usually selected so that the first repetition immediately adjoins the base-band spectrum. By increasing the sampling frequency f1 by a factor of m by means of an interpolating digital filter the first repetition of the'base-band spectrum occurs around the output sampling frequency mf . This ensures that the said first repetition of the spectrum no longer immediately adjoins this base-band spectrum and consequently the latter can be selected by means of a simple low-pass f`ilter.
Hereinbefore it was set out how signal samples can be interpolated in a sequence of signal samples of a base-band signal by means of a low-pass filter.
Similarly signal samples may be interpolated, for example by means of a band-pass filter, in a sequence of signal samples which is obtained by sampling a signal not situated in the base band, for example a single-sideband signal modulating a carrier.
period T the circulating state of the shift register is established via the AND gate 5. ~hen eventually in this last cycle of the counter 20 the N output pulse from the AND gate 19 is applied to the counter 20, the AND gate 22 again delivers a binary "0" so that the AND gate,5 is closed and hence all back-coupling paths of the register 9 are interrupted. Mso the AND gate 23 now supplies a binary "1" to the AND gate 3, permitting a new code word to be written in the register, and finally the said Nth pulse resets the counter 21 to zero. l`he output pulses delivered by the counter 21, the inverter 27 and thc AND gates 22 and _ 14 -, 7~ 3 7-1'~75 23 are shown in Figure 2 a-t f, i. l~ and p respectively, It should be mentioned that reading a filter coefficient from the ~OM 8 can be effected in known manner, for example in that each instant the counts of the counters 20 and 21 are jointly considered as one address code for the ROM. ~or this purposQ all the sections of the two counters 20 and 21 are connected to`corresponding inputs of the ~0~1 8, as is shown schematically in Figure 1 by the~
shaded area 8(1).
(4) The relationship betweell the filt;er coefficients ~to be used in the interpolatin~ di~ital filter.
As has been mentioned with reference to Table I, each computing cycle within a given input sampling period is associated with a set of filter coefficients C (q, k).
In the said Table, for the firsttcomputing cycle within the said sampling period the set of filter coefficients C(q, k) is characterized by q = O, and for the second computing cycle within the sampling period considered, which cycle is the last one in the Table, the said set is characterized by q = 1. As has been mentioned hereinbefore and as is indicated in the Table, for a given filter these sets ~f filter coefficients are the same for all sampling periods.
The filter coefficients of a set are equal in magnitude to the individual samples of a sequence of samplings of the pulse response of the desired filter. For use in the filter the said samples are usually quantized and encoded, for example in a binary number.
To illustrate the relationship between the ffets of filter coefficients Fig~ro 3a shows the pulse 3!1lN 7r/S3 7-1'~75 ~039;}64 respollse, limi~,ed to the time intorval from -~'l` to ~10T, of an ideal low-pass filter having a cut-off frequency ~ /2. ~s is k~own, this pul.se rcspollse has a shape given by the functioll (sin x)/x. ~lore particularly -the pulse response shown can be represented by the mathelnati.cal expression sin (t - 2T) ~o/2 ;~ o ~ (~ 2T) ~o/2 First we will consider the said low-pass filter as a non-interpolating one, that is to say a filter in which the input and output sampling frequencies are equal. It is assumed that these sampling frequencies are equal to four times the cut-off frequency of the filter. Th~ sampling period then is equal to T = ~ ~0.
To determine the filter coefficients the pulse response of the filter is sampled with the train of sampling pulses shown in Figure 3b. It is assumed that these sampling pulses occur at instants t = k.T. In known manner this train can be represented mathematically by C~
' ~(t - kT) k = - C~
The five filter coefficients which are used in the filter shown in Figure 1 for approximating to the desired transfer characteristic now are constituted by those samples of the pulse re-sponse which occur at the instants for which k - 0, 1, 2, 3, I~, rcspectively. For the resulting filter coefficients which together form a set C (0, k.) the - - 1G _ 1'JIi`i. 77,3 (~-7-1'~75 r~spective magnitudes are shown at d in I`igure 3. In this - Figure not only the parameter values k but also the instants at which the relevant filter coefficient occurs as an instantaneous signal value for the pulse response . shown in Figure 3a are plo-tted along the abscissa.
1~len the low-pass filter having the pulse response shown in Figure 3a is to be used as an interpol.ating filter in wllich the output sampling frequency is equal to twice the input sampling frequency, i.e. with an output sampling period equal to T/2 = ~/2 ~0, in order to obtain a first output code word the input code words stored in the register 9 shown in Figure 1 are first multiplied by the above-mentioned set of filter coefficients C(0, k), whilst for obtaining a second output code words are also multiplied by a second set of filter coefficients C (1, k). This second set of filter coefficients is shown in Figure 3e. These filter coefficients agai.n are equal to the samples of the pulse response shown in Figure 3a and sampled with a period T. Here also said sampling of the pulse response has been effected with a.pulse train of the shape shown in Figure 3b, however, with respect to this pulse train it has been shifted in time by T/2 = + ~/2 W0, so that the train of sampling pulses for the second set of filter coefficients can be represented mathematically by:
_ (kT + T/2)~
k = ~
Thus the filter coefficients C(1, k) are -the samples of the pulse response shown in Figure 3a which are taken at l7 7^i','~
9 ~ 7 :>
, ~
~039;~64 the instants kT + 1`/2, where k = 0, 1, 2, 3, 4.
For completeness Figure 3 at f and ~ shows the sets of filter coefficients for the case where the output sampling frequency of the interpolating filter is thrice its input sampling frequency. In this case, within an input sampling period the input code words storod must be multiplied once by the set of filter coefficients C(0, k) (see Figure 3d), once by the set of coefficients C(2, k) (see Figure 3~), and once by the set C(3, k) (see Figure 3g). The said sets of filter coefficients C(2, k) and Ct3, k) also are obtained by sampling the pulse response shown in Figure 3a, the train of sampling pulses again having the same shape as in Figure 3b, however, the said trains are shifted with respect to the latter train by time intervals T/3 and 2T/3 respectively. In analogy with the above, the latter pulses can be mathematically represented by:
~ kT ~ T/3)¦
k = _ and C~ .
(kT ~ 2T/3)~
k = - c~ ~
respectively.
~ n interpolating digital filter has effects not only in the time domain but also in the frequency domain, for if a band-l:imited analog base-band signal is sampled at an input sampling f`requency f1 the frequency - 1 l'3 ,, ,. ' 1'll~'. 77',~
~~7~1'J75 .
sp-ctrwn ol` this sampled sjgnal is constitutcd by the initial base-band spectrum and by repetitions of this spectrum at integral multiples of the sarnpling frequency ~; f1. Thus the first repetition of the initial base-band spectrum lies around the sampling frequency fl. In PC~I
transmission systems this frequency f1 is usually selected so that the first repetition immediately adjoins the base-band spectrum. By increasing the sampling frequency f1 by a factor of m by means of an interpolating digital filter the first repetition of the'base-band spectrum occurs around the output sampling frequency mf . This ensures that the said first repetition of the spectrum no longer immediately adjoins this base-band spectrum and consequently the latter can be selected by means of a simple low-pass f`ilter.
Hereinbefore it was set out how signal samples can be interpolated in a sequence of signal samples of a base-band signal by means of a low-pass filter.
Similarly signal samples may be interpolated, for example by means of a band-pass filter, in a sequence of signal samples which is obtained by sampling a signal not situated in the base band, for example a single-sideband signal modulating a carrier.
(5) Description of` Fi~ure 4.
Figure 4 shows a modified embodiment of the interpolating digital filter shown in Figure 1. The embodiment of ~igure 4 is largely similar to that of Figure 1 and elements corresponding to those shown in ~icure 1 are designated by like reference numerals. The . 77'~
~-7-1'375 , ~ -1~393~4 ell1bOd:imelilt ShOWlI in Figure l1 diffcrs from that shown in ~igure 1, however, in that in order to obtain a shift register 9 having a periodically varying storage or delay time and to obtain computing cycles of equal duration the input of the last register section 10 (4) is not connected via a feedback line and an associated gate circuit to the input of the first register section 10(0), as is the case in ~igure 1, but in that given shift pulscs for the register 9 are suppressed. Thus in the embodiment shown in Figure 4 the periodically varying delay time of the register 9 is obtained only by the operation of the clock pulse generator 7.
This clock pulse generator 7 is partly constructed in the same manner as the clock pulse generator shown in Figure 1 and also includes a clock pulse oscillator 15 which delivers clock pulses at a frequency 3Nmf1. Here also N represents the number of sections of the shift x~egister 9, m represents the number of output samples to be generated in an inp~t sampling period T and f1 represents -, the input sampling frequency, where f1 = 1/T. The said clock pulses are supplied to a binary divider or counter 16 which divides the pulse frequency of this oscillater 15 by a factor of three. Similarly to the embodiments of ~igure 1 given ~ements of the counter 16 are connected to AND gates 17, 18 and 19 which within the cycle of three clock pulses considered are caused to deliver a pulse by the first, second and third cloclc pulses respectively of the oscillator 15. l`he pulses delivered by the AND gates 18 and 19 are applied to the transfex circuit 13 and the - 2~) -.
~- 7- 1 ~7, 1039;}64 accumulator 12 via AND gates 25 and 211 :respect:i.vely.
The output pulse of the ANO gate 19, which occurs at each third clock pulse from the oscillator 15, is supplied to a counter 28 which in this embod;Tnent counts N + 1 output pulses of the counter 16 and after every (N + l) th one of these output pulse supplies an output pulse to a counter 29. Just as in the embodiment shown in ~igure 1, the output pulse of the counter 28 denotes the end of a computing cyc]e. In this embodiment the counter 29 counts m outpu1; pulses of the counter 28 and then itself` supplies an output pulse. In the embodiment shown in Figure 4 the output of` the AND gate 17 and the outputs of the counters 28 and 29 are further ~ connected in the manner shown to AND gates 30 and 31, a NAND gate 32, an OI~ gate 33 and an inverter 34.
The operation of the interpolating digital filter shown in ~igure 4 is illustrated, for the case in~
which N = 5 and m = 2, by the waveforrns shown in Figure -- 5 and by a Table II which is arranged in the same manner as Table I. In particular, Figure 5a shows the pulse train generated by the oscillator 15. This train is divided in the nlanner shown into two computlng cycles which each are characterized by 18 output pulses of the oscillator 15. These computing cycles are numbered I and II respectively, Figure 5 further shows the output pulses of the ~ND gates 17, 18 and 19 at b, c, and d respectively, the output pulses of the counters 28 and 29 at e and f respectively, and the output signals of the NAND g~ate 32, the AND gate 31 and the 0~ gate 33 at ~, h and ~ respectivel.y The l)l~. ~733 '~-7-1~75 shift pulscs for the register 9 which are dorived from the AND gate 30 are shown at k. For completeness line 1 shows the pulse train dclivered by the AND gate 25 for transferring the contents of the accumulator 12 to the buffer 14, and line ~ sho~s the pulse train deliverd by the AND gate 24 for resétting the accumulator 12 to zero on completion of a computing cycle.
On the occurrence of each first shift pulse in a computing cycle I, a new input code word is inserted in the register 9 whilst -the oldest input code word stored is lost, for during this invertion the AND gate 4 is closed.
The state of the shift register after the occurrence of each Pirst shift pulse in a computing cycle I is shown in Table II by p.1.1 (p = 1, 2, 3, l~). Because during a first computing cycle, which is characterized in the Table by the shift register states for which r = 1, only five of the six output pulses of the AND gate 17 are supplied as shift pulses to the register 9, the shift register states p.1.5 and p.1.6 (p = 1, 2, 3, 4) are equal. The input code word~; stored in the last register section 10(4) in the said shift register states p.1.6, for example the code words x(n), x(n +1) and x(n + 2), then is multiplied only by a filter coefficient of zero value. As an alternative, the latter multiplication may be dispensed with. As is shown in Figure 5k, in the embodiment under consideration, in which m = 2, during the last, i.e. second, oomputing cycle II the sixth output pulse of the AND gate 17 which occurs within this computing cycle is, however, supplied as a shift pulse to the shift regis-ter 9. As a result, on ~ ~2 _ . 7733 termination of each last compu-ting cycle wi-thin an input sampling period the state of the register 9 is equal to the state of this register 9 immediately after the insertion of a new input code word at the beginning of the sampling period T considered. Compare the shift register states 1.2.5 and 1.1.1; 2.2.6 and 2.2.1; 3.2.6 and 3.1.1 in Table II. In these shift register states p.2.6 (p = 1, 2, 3) also the input ~de word stored in the shift register section 10(4) is not multiplied or multiplied by a filter coefficient of zero value.
That for the above-described interpolating digital filter a shift register having a periodically varying delay time is again realized can be illustrated with reference to column 10(4) of Table II. We will consider, for example, the code word x(n - 1). Table II
shows that for multiplication by a filter coefficient this code word is contained in the register section 10(4) in the shift register states 1.1 ~, 1.2.4, 2.1.3, 2.2.3, 3.1.2, 3.2.2, 4.1.1. Because the-interval between two consecutive shift register states is equal to a period T/ rm(N ~ , the time interval between the shift register states 1.1.4 and 1.2.4 is equal to 6T/Lm(N ~
that between the shift register states 1.2.4 and 2.1.3, however, is equal to 5T/ ~m(N ~ only, and so on.
Just as in the embodiment shown in ~igure 1, here also all the computing cycles are of equal duration and the output code words y ~(n ~ q/M)~ all occur at equidistant instants (compare in particular waveforms 1 and ~ of I~ u:re 5).
~ '. 7733 '~-7-1~7~
1~39~64 It should be ment:ioned that in thi.s embodiment the clock pulse generator 7 may be constructed so that each sixth output pulse of ~ND gate 17 within a first computing cycle I shifts the contents of the shift register 9, whereas the first output puise of ~ND gate 17 in the second computing cycle does not effect such a shift. ~lso, the number of shift register states in which there is no multiplication of the code word stored in the last register section 10(4) by a filter coefficient ~0 may be more than one. Similarly to the embodiment shown in Figure 1, in the embodiment shown in Eigure 4 more than the two output code words considered may be generated after the insertion of an input code word in the register 9. However, this again results in a proportional increase of the number of sets of filter coefPicients.
(E) Remarks.
. In the embodiments described the register sections 10(.) are constructed 80 that a new input code word can only be written in the,section 10(0) via AND
gate 3 and OR gate 6 under controi of a shift pulse from generator 7. However, at least the section 10(0) may be implemented by an,element such that a new input code word can be written in it without a shif't pulse being -' required. In this case, before~the insertion of this new code word the oldest input code word also must be stored in the section 10(0). In contrast with the above-described embodiment the multiplier 11 then has an input connected to the input of this first section 10(0). Just as in the embodimen-t shown in ~`igure 1, no additional shif't pulses i,~
1'JIN. 7733 9-7-1~75 ._~
~039364 need be supplied to the shift register or be suppressed within a computing cycle. When such a section 10(0) is used and the clock pulse genera-tor 7 is appropriately constructed the multiplier 11 may even have an input connected to an input of anyone register section 10(.) of the shift register 9.
~though in the embodiment described the input code words are stored in a circulating shift register, this may be replaced by an equivalent storage device such as, for example~ a RAM. However, in this case the clock pulse generator must be constructed so that the interval between the instants at which a given input code word stored in this RAM is supplied to the multiplying device for multiplication by a filter coefficient varies periodically.
~inally it should be mentioned that with a suitable choice of the counter 16, which in the embodiments described is a di~ide-by-three counter, the frequency of the oscillator 15 may be in a different ratio to the shift frequency Nm/T.
,.~ ,' P~J, 7733.
14-~1975~
1039~64 / ~1].1, I
10(0) 10(1) 10(2) 10(3) 1C)(!1) 5 P ~
2 ~ 5 ~ x ~ n ) x ~ ? x ( l~ ) c ( ~
!1-1.3 x(n-3) X(n-~J) x~n) x(n-1) X(11-2)C(O, '~) 1-1-S X(1l 1 ) X(ll ") x(n-3) X(n-lJ) X(ll) C~ ~
~ -1 X(ll) x(n-1) x(n-2) x(n-3) Xtll-4) C(1,!l) ,1.2.2 x(n-3) X(JI) x(n-1) X~ 2) X~11-3)Cl1,3) ~ (Jl-'~ ) ~ ~-3) x(~ 1-1) x(1~ 2)C~',2) 1 . 2 . !~ n- l ) x n--2 ) .~; ( 11 - '3 )X ( ll ) .~ ( ~1 1 ) C ( ! . 1 ) ,1.2.; `~ ) x n-1) x(n-.?) ~(n-3) ~(1l)C(1,0j ~ 2.1. 1 . !;(111 1 ) x(n) X(ll- 1 ) X(n-2)X(n -'~) cto, ll ) ,2.1.~ ~(n-3) x~1l+1) x(n) x~l1-1)X(ll-~ 0,3) 2.1.3 x(n-2) X(11-3) ~(1l+1) X~Jl) ~ j C(~ 2) 2.1.4 ~ -1) x~ ) .Y~n-3) ~-(n+1) X ( ll ) C ( r~
l2.1-5 X(J~) X(ll-1) x(n~~J) X(Jl-3) X(ll-~ 1)C(C),C~j l2.2.1 x(n-1) X(~l) x(n-1) x(l1-2j X(ll-~)C(1,4) ~2.2.2 x~n-2) ~ nr1 ) X IJ) X Il~ -1-2) C( 1, '~ .
~2.2.3 X511-l) x(n-2) x 1l+1) x n) x(l1-1) C~
~2.2.1l x~n) x(n-1) x n-2) X 11~ 1 ) X(II) C( 'I ~ I ) j2.2.5 x(n+1) x(n) x(n-1) ~(n-~) x(n~l) C~
3.1.1 . x(n*~) x(rl*-1) x(]~) x(]1-1) x(n-.~) c~o,4 ;3-1.2 x(n-~) .Y(~1+2) x(r-+1) X(]l) x(n-l ) C(O~
-3.1.~ x~n-1) x(r'-2) X ( n+ '2 ) x(n+1~ 1) C(~J,2) .-,3-1-~J x~n) X(]l-1 ) .`;111- ) :x(n~-2) x(n~1 ) C'(O, 1 ) 3-1-S x(n~1) X ( JI ) X ( J~ X ( 1l- 2 ) .~ 2 ) C ( ~), O ) 3.2.1 x(n~2) x~n+1) ~(~)x(n--1) x(n-2) C(1,4) ;3.2.2 x5n-1) x~n+2) x~]l~(n) x(n-1) C(1 3) s3 2-3 x5n) x(n-1) x rl-r;~) x(n*1) X(ll) C~"''`~
;3.2.!l x5n+1~ ~-5n). x 1l-1) ;Y(n-~2) x(n-r1) C(1,1) 3.2.5 xt~+2) x(n+1) x n) x(n-1) x(n+2) C~1,0) : -¦4.1.1 . x(n+3) x(n~2) x ll+1) x(n) X(31--1) c(o,4) - . _ _ _ . _ _ .. , .. __ .
-- 2~ :
.
, - ~
, 773~-14-8-1975.
. ,` ' ~ ' . .
1039;164 ;, .... . . ... .. ... .. .. . . .. ... .. . . . . . . . . . . . . .. . . ..
~ .'i'J, ~I -! 10(0) 10(1)10(2) 10(3)lo(ll) 5 i ;
. I~.r.s i 1.1.1 x(n) x(n-l) x(n-2) x(n-3) x(n-~) c(o.4) 1 1.1.2 x(n-'~ n) x~l~-1) x(n--?) x(~ ) C(o,~) .1.3 ~(n-3) X ( ~ (r~ 2) 4 ~ -3) ~(n-~ ) C(~),1j X ~ ? X ( ~1- 2 ) x(l~-3) ~ ) c(c),o 1.1.6 x(n-l) X ( n- 2 ) x(n-3) x(n-'~
~ 1.2.1 x(n) x(n-l) x(n-2) X(rl-~) x(n-/~ ) C( ~
1.2.2 X(n-`l) x(n) x(1l-1) x(n- 7) X(11-3) C(1.3) j 1.2.3 x(n-3) x(n-'l) ~(n) x(n-l) x(n-2) C~1,?) ~ 1.2.4 x n-~) x rl-3) x(l~ ) x n) x(n-1) C(1,1j i 1.".5 ~- ll-l) x n-2) x(;~ n-~ (n) C(1,0) . 1.2.6 ~(n) x 1l-1) x(n-2) ~ n-~) x(n~
~.1.1 x(n+l! x(n) x(n-1) ~-(n-") ~ ~3) c(o,4~
~ x ~ ) x(~l+1) ~ n) ~ ) C(() 3) 1 2.1.3 x n-2) x(n-3) x n l) x(n) x(n-1) c(o;'i , 2.1.4 x n-l) x(~ ) x ~-3) ~ ) C(0,1) , 2.1-5 x ll) ~(J~3) x~ 1) C(O,O) I 2.1.-~ x ll) x(n-1) x(ll ~-) X(~1-3) ~(rl+1?
Z.2.1 X(~l+1) x(~l) . X(~ -') x(n-~) f-(-1,4) 2.2.~ X(ll-~) X(~l+ 1 ) X(~l) ~;(11--1 ) `:(11-:' ) C( 1, 3) 2.~.3 x n-2~ x n-3) x(n+l) x(n) x(ll-1) C(1,~) 2.2.4 x n-l) x n-2) x(n-3) x(~ ) X(l~) C~
2.2._, x n) x ~1-1) x(n--J) x(n-3) X(ll+i) C(~jf~) 2.2.~ x n+1) -x n) x(n-1) x(n~(n-3) 3.1.1 X(~ ) x(n-11) x(n) x(n-1) x(n-") c(o.4) 3 1 X ~ Jl 2 ) X ( ~1 1- 2 ) ( T ) .~; ( ) ' ( ) C ( O 3) 3.1.3 x(n-1) x(n-~) x(n~:~) X(l~ (n) C(O,-') 3.1.4 x(n) ~ ) x(l. -) X~ -(rl+1) c(0,1i 3.1.5 x(n~1) X(~l) x(n-1) X(n-2) x(n+2) f~O,~) ' 3.1.~ x(n+l) x(~) x(n-l) x(n-2) X(11+'7) ~, 3.2.1 x(n~Z) x~n-i1) x(n) x(n-1) X(1~-2) C(1,!i)3.2.2 x ~1-2) x ni-~) x(n-il) X(ll) x(n-l) C(1.3)~i 3.2.3 x n-l) x ~1-2) x(n+2) x(n+1) X(~l) C(1,2) ! 3.2.4 x(n) x n-l) x(n-2) X(J~+'~) x(n+l) C(1.1) !~ 3.2.5 x~n+1) x n) x(n-l) x(n-2) x~n+2) C(1,0) .1 3.2.6 x(n+2) x n+1~ x(n) x(n-l) x(n-2) ¦ 4.1.1 x(n+3) x(~i+2) x(n+1) x(n) x(n-l) C(O,~) I' ; .
.
.
.
... . . . . . . . . . .. . . .
.
.. - ! ~
Figure 4 shows a modified embodiment of the interpolating digital filter shown in Figure 1. The embodiment of ~igure 4 is largely similar to that of Figure 1 and elements corresponding to those shown in ~icure 1 are designated by like reference numerals. The . 77'~
~-7-1'375 , ~ -1~393~4 ell1bOd:imelilt ShOWlI in Figure l1 diffcrs from that shown in ~igure 1, however, in that in order to obtain a shift register 9 having a periodically varying storage or delay time and to obtain computing cycles of equal duration the input of the last register section 10 (4) is not connected via a feedback line and an associated gate circuit to the input of the first register section 10(0), as is the case in ~igure 1, but in that given shift pulscs for the register 9 are suppressed. Thus in the embodiment shown in Figure 4 the periodically varying delay time of the register 9 is obtained only by the operation of the clock pulse generator 7.
This clock pulse generator 7 is partly constructed in the same manner as the clock pulse generator shown in Figure 1 and also includes a clock pulse oscillator 15 which delivers clock pulses at a frequency 3Nmf1. Here also N represents the number of sections of the shift x~egister 9, m represents the number of output samples to be generated in an inp~t sampling period T and f1 represents -, the input sampling frequency, where f1 = 1/T. The said clock pulses are supplied to a binary divider or counter 16 which divides the pulse frequency of this oscillater 15 by a factor of three. Similarly to the embodiments of ~igure 1 given ~ements of the counter 16 are connected to AND gates 17, 18 and 19 which within the cycle of three clock pulses considered are caused to deliver a pulse by the first, second and third cloclc pulses respectively of the oscillator 15. l`he pulses delivered by the AND gates 18 and 19 are applied to the transfex circuit 13 and the - 2~) -.
~- 7- 1 ~7, 1039;}64 accumulator 12 via AND gates 25 and 211 :respect:i.vely.
The output pulse of the ANO gate 19, which occurs at each third clock pulse from the oscillator 15, is supplied to a counter 28 which in this embod;Tnent counts N + 1 output pulses of the counter 16 and after every (N + l) th one of these output pulse supplies an output pulse to a counter 29. Just as in the embodiment shown in ~igure 1, the output pulse of the counter 28 denotes the end of a computing cyc]e. In this embodiment the counter 29 counts m outpu1; pulses of the counter 28 and then itself` supplies an output pulse. In the embodiment shown in Figure 4 the output of` the AND gate 17 and the outputs of the counters 28 and 29 are further ~ connected in the manner shown to AND gates 30 and 31, a NAND gate 32, an OI~ gate 33 and an inverter 34.
The operation of the interpolating digital filter shown in ~igure 4 is illustrated, for the case in~
which N = 5 and m = 2, by the waveforrns shown in Figure -- 5 and by a Table II which is arranged in the same manner as Table I. In particular, Figure 5a shows the pulse train generated by the oscillator 15. This train is divided in the nlanner shown into two computlng cycles which each are characterized by 18 output pulses of the oscillator 15. These computing cycles are numbered I and II respectively, Figure 5 further shows the output pulses of the ~ND gates 17, 18 and 19 at b, c, and d respectively, the output pulses of the counters 28 and 29 at e and f respectively, and the output signals of the NAND g~ate 32, the AND gate 31 and the 0~ gate 33 at ~, h and ~ respectivel.y The l)l~. ~733 '~-7-1~75 shift pulscs for the register 9 which are dorived from the AND gate 30 are shown at k. For completeness line 1 shows the pulse train dclivered by the AND gate 25 for transferring the contents of the accumulator 12 to the buffer 14, and line ~ sho~s the pulse train deliverd by the AND gate 24 for resétting the accumulator 12 to zero on completion of a computing cycle.
On the occurrence of each first shift pulse in a computing cycle I, a new input code word is inserted in the register 9 whilst -the oldest input code word stored is lost, for during this invertion the AND gate 4 is closed.
The state of the shift register after the occurrence of each Pirst shift pulse in a computing cycle I is shown in Table II by p.1.1 (p = 1, 2, 3, l~). Because during a first computing cycle, which is characterized in the Table by the shift register states for which r = 1, only five of the six output pulses of the AND gate 17 are supplied as shift pulses to the register 9, the shift register states p.1.5 and p.1.6 (p = 1, 2, 3, 4) are equal. The input code word~; stored in the last register section 10(4) in the said shift register states p.1.6, for example the code words x(n), x(n +1) and x(n + 2), then is multiplied only by a filter coefficient of zero value. As an alternative, the latter multiplication may be dispensed with. As is shown in Figure 5k, in the embodiment under consideration, in which m = 2, during the last, i.e. second, oomputing cycle II the sixth output pulse of the AND gate 17 which occurs within this computing cycle is, however, supplied as a shift pulse to the shift regis-ter 9. As a result, on ~ ~2 _ . 7733 termination of each last compu-ting cycle wi-thin an input sampling period the state of the register 9 is equal to the state of this register 9 immediately after the insertion of a new input code word at the beginning of the sampling period T considered. Compare the shift register states 1.2.5 and 1.1.1; 2.2.6 and 2.2.1; 3.2.6 and 3.1.1 in Table II. In these shift register states p.2.6 (p = 1, 2, 3) also the input ~de word stored in the shift register section 10(4) is not multiplied or multiplied by a filter coefficient of zero value.
That for the above-described interpolating digital filter a shift register having a periodically varying delay time is again realized can be illustrated with reference to column 10(4) of Table II. We will consider, for example, the code word x(n - 1). Table II
shows that for multiplication by a filter coefficient this code word is contained in the register section 10(4) in the shift register states 1.1 ~, 1.2.4, 2.1.3, 2.2.3, 3.1.2, 3.2.2, 4.1.1. Because the-interval between two consecutive shift register states is equal to a period T/ rm(N ~ , the time interval between the shift register states 1.1.4 and 1.2.4 is equal to 6T/Lm(N ~
that between the shift register states 1.2.4 and 2.1.3, however, is equal to 5T/ ~m(N ~ only, and so on.
Just as in the embodiment shown in ~igure 1, here also all the computing cycles are of equal duration and the output code words y ~(n ~ q/M)~ all occur at equidistant instants (compare in particular waveforms 1 and ~ of I~ u:re 5).
~ '. 7733 '~-7-1~7~
1~39~64 It should be ment:ioned that in thi.s embodiment the clock pulse generator 7 may be constructed so that each sixth output pulse of ~ND gate 17 within a first computing cycle I shifts the contents of the shift register 9, whereas the first output puise of ~ND gate 17 in the second computing cycle does not effect such a shift. ~lso, the number of shift register states in which there is no multiplication of the code word stored in the last register section 10(4) by a filter coefficient ~0 may be more than one. Similarly to the embodiment shown in Figure 1, in the embodiment shown in Eigure 4 more than the two output code words considered may be generated after the insertion of an input code word in the register 9. However, this again results in a proportional increase of the number of sets of filter coefPicients.
(E) Remarks.
. In the embodiments described the register sections 10(.) are constructed 80 that a new input code word can only be written in the,section 10(0) via AND
gate 3 and OR gate 6 under controi of a shift pulse from generator 7. However, at least the section 10(0) may be implemented by an,element such that a new input code word can be written in it without a shif't pulse being -' required. In this case, before~the insertion of this new code word the oldest input code word also must be stored in the section 10(0). In contrast with the above-described embodiment the multiplier 11 then has an input connected to the input of this first section 10(0). Just as in the embodimen-t shown in ~`igure 1, no additional shif't pulses i,~
1'JIN. 7733 9-7-1~75 ._~
~039364 need be supplied to the shift register or be suppressed within a computing cycle. When such a section 10(0) is used and the clock pulse genera-tor 7 is appropriately constructed the multiplier 11 may even have an input connected to an input of anyone register section 10(.) of the shift register 9.
~though in the embodiment described the input code words are stored in a circulating shift register, this may be replaced by an equivalent storage device such as, for example~ a RAM. However, in this case the clock pulse generator must be constructed so that the interval between the instants at which a given input code word stored in this RAM is supplied to the multiplying device for multiplication by a filter coefficient varies periodically.
~inally it should be mentioned that with a suitable choice of the counter 16, which in the embodiments described is a di~ide-by-three counter, the frequency of the oscillator 15 may be in a different ratio to the shift frequency Nm/T.
,.~ ,' P~J, 7733.
14-~1975~
1039~64 / ~1].1, I
10(0) 10(1) 10(2) 10(3) 1C)(!1) 5 P ~
2 ~ 5 ~ x ~ n ) x ~ ? x ( l~ ) c ( ~
!1-1.3 x(n-3) X(n-~J) x~n) x(n-1) X(11-2)C(O, '~) 1-1-S X(1l 1 ) X(ll ") x(n-3) X(n-lJ) X(ll) C~ ~
~ -1 X(ll) x(n-1) x(n-2) x(n-3) Xtll-4) C(1,!l) ,1.2.2 x(n-3) X(JI) x(n-1) X~ 2) X~11-3)Cl1,3) ~ (Jl-'~ ) ~ ~-3) x(~ 1-1) x(1~ 2)C~',2) 1 . 2 . !~ n- l ) x n--2 ) .~; ( 11 - '3 )X ( ll ) .~ ( ~1 1 ) C ( ! . 1 ) ,1.2.; `~ ) x n-1) x(n-.?) ~(n-3) ~(1l)C(1,0j ~ 2.1. 1 . !;(111 1 ) x(n) X(ll- 1 ) X(n-2)X(n -'~) cto, ll ) ,2.1.~ ~(n-3) x~1l+1) x(n) x~l1-1)X(ll-~ 0,3) 2.1.3 x(n-2) X(11-3) ~(1l+1) X~Jl) ~ j C(~ 2) 2.1.4 ~ -1) x~ ) .Y~n-3) ~-(n+1) X ( ll ) C ( r~
l2.1-5 X(J~) X(ll-1) x(n~~J) X(Jl-3) X(ll-~ 1)C(C),C~j l2.2.1 x(n-1) X(~l) x(n-1) x(l1-2j X(ll-~)C(1,4) ~2.2.2 x~n-2) ~ nr1 ) X IJ) X Il~ -1-2) C( 1, '~ .
~2.2.3 X511-l) x(n-2) x 1l+1) x n) x(l1-1) C~
~2.2.1l x~n) x(n-1) x n-2) X 11~ 1 ) X(II) C( 'I ~ I ) j2.2.5 x(n+1) x(n) x(n-1) ~(n-~) x(n~l) C~
3.1.1 . x(n*~) x(rl*-1) x(]~) x(]1-1) x(n-.~) c~o,4 ;3-1.2 x(n-~) .Y(~1+2) x(r-+1) X(]l) x(n-l ) C(O~
-3.1.~ x~n-1) x(r'-2) X ( n+ '2 ) x(n+1~ 1) C(~J,2) .-,3-1-~J x~n) X(]l-1 ) .`;111- ) :x(n~-2) x(n~1 ) C'(O, 1 ) 3-1-S x(n~1) X ( JI ) X ( J~ X ( 1l- 2 ) .~ 2 ) C ( ~), O ) 3.2.1 x(n~2) x~n+1) ~(~)x(n--1) x(n-2) C(1,4) ;3.2.2 x5n-1) x~n+2) x~]l~(n) x(n-1) C(1 3) s3 2-3 x5n) x(n-1) x rl-r;~) x(n*1) X(ll) C~"''`~
;3.2.!l x5n+1~ ~-5n). x 1l-1) ;Y(n-~2) x(n-r1) C(1,1) 3.2.5 xt~+2) x(n+1) x n) x(n-1) x(n+2) C~1,0) : -¦4.1.1 . x(n+3) x(n~2) x ll+1) x(n) X(31--1) c(o,4) - . _ _ _ . _ _ .. , .. __ .
-- 2~ :
.
, - ~
, 773~-14-8-1975.
. ,` ' ~ ' . .
1039;164 ;, .... . . ... .. ... .. .. . . .. ... .. . . . . . . . . . . . . .. . . ..
~ .'i'J, ~I -! 10(0) 10(1)10(2) 10(3)lo(ll) 5 i ;
. I~.r.s i 1.1.1 x(n) x(n-l) x(n-2) x(n-3) x(n-~) c(o.4) 1 1.1.2 x(n-'~ n) x~l~-1) x(n--?) x(~ ) C(o,~) .1.3 ~(n-3) X ( ~ (r~ 2) 4 ~ -3) ~(n-~ ) C(~),1j X ~ ? X ( ~1- 2 ) x(l~-3) ~ ) c(c),o 1.1.6 x(n-l) X ( n- 2 ) x(n-3) x(n-'~
~ 1.2.1 x(n) x(n-l) x(n-2) X(rl-~) x(n-/~ ) C( ~
1.2.2 X(n-`l) x(n) x(1l-1) x(n- 7) X(11-3) C(1.3) j 1.2.3 x(n-3) x(n-'l) ~(n) x(n-l) x(n-2) C~1,?) ~ 1.2.4 x n-~) x rl-3) x(l~ ) x n) x(n-1) C(1,1j i 1.".5 ~- ll-l) x n-2) x(;~ n-~ (n) C(1,0) . 1.2.6 ~(n) x 1l-1) x(n-2) ~ n-~) x(n~
~.1.1 x(n+l! x(n) x(n-1) ~-(n-") ~ ~3) c(o,4~
~ x ~ ) x(~l+1) ~ n) ~ ) C(() 3) 1 2.1.3 x n-2) x(n-3) x n l) x(n) x(n-1) c(o;'i , 2.1.4 x n-l) x(~ ) x ~-3) ~ ) C(0,1) , 2.1-5 x ll) ~(J~3) x~ 1) C(O,O) I 2.1.-~ x ll) x(n-1) x(ll ~-) X(~1-3) ~(rl+1?
Z.2.1 X(~l+1) x(~l) . X(~ -') x(n-~) f-(-1,4) 2.2.~ X(ll-~) X(~l+ 1 ) X(~l) ~;(11--1 ) `:(11-:' ) C( 1, 3) 2.~.3 x n-2~ x n-3) x(n+l) x(n) x(ll-1) C(1,~) 2.2.4 x n-l) x n-2) x(n-3) x(~ ) X(l~) C~
2.2._, x n) x ~1-1) x(n--J) x(n-3) X(ll+i) C(~jf~) 2.2.~ x n+1) -x n) x(n-1) x(n~(n-3) 3.1.1 X(~ ) x(n-11) x(n) x(n-1) x(n-") c(o.4) 3 1 X ~ Jl 2 ) X ( ~1 1- 2 ) ( T ) .~; ( ) ' ( ) C ( O 3) 3.1.3 x(n-1) x(n-~) x(n~:~) X(l~ (n) C(O,-') 3.1.4 x(n) ~ ) x(l. -) X~ -(rl+1) c(0,1i 3.1.5 x(n~1) X(~l) x(n-1) X(n-2) x(n+2) f~O,~) ' 3.1.~ x(n+l) x(~) x(n-l) x(n-2) X(11+'7) ~, 3.2.1 x(n~Z) x~n-i1) x(n) x(n-1) X(1~-2) C(1,!i)3.2.2 x ~1-2) x ni-~) x(n-il) X(ll) x(n-l) C(1.3)~i 3.2.3 x n-l) x ~1-2) x(n+2) x(n+1) X(~l) C(1,2) ! 3.2.4 x(n) x n-l) x(n-2) X(J~+'~) x(n+l) C(1.1) !~ 3.2.5 x~n+1) x n) x(n-l) x(n-2) x~n+2) C(1,0) .1 3.2.6 x(n+2) x n+1~ x(n) x(n-l) x(n-2) ¦ 4.1.1 x(n+3) x(~i+2) x(n+1) x(n) x(n-l) C(O,~) I' ; .
.
.
.
... . . . . . . . . . .. . . .
.
.. - ! ~
Claims (6)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. Non-recursive digital filter for generating binary output code words which occur at a given output sampling frequency f2 and are related in a predetermined manner to a sequence of binary input code words which occur at an input sampling frequency f1, the output sampling frequency f2 being an integral multiple (m) of the input sampling frequency f1, which filter comprises a storage device arranged to store a given number (N) of successive input code words; a multiplying device for forming, within one input sampling period l/f1, a number (m) of sets of products of the said given number (N) of input code words and a number (M) of different sets of weighting factors which correspond to the relationship between the input and output code words; an adding device which is coupled to the said multiplying device and is arranged to generate, within one input sampling period l/f1, the said number of output code words, which number corresponds to the number of sets of products, each output code words being at least equal to the mathematical sum of all of the products of a particular sot of products, characterized in that the said storage device (9) for storing the said given number (N) of successive input code words is a storage device having a periodically varying storage time, which storage device (9) is controlled by a clock pulse generator (7) and is provided with an output circuit via which, within one input sampling period l/fl, the input code words stored in the storage device (9) are supplied to the said multiplying device (11) a number of times, which number of times is equal to the said integral multiple (m) whilst the code words supplied by the said output circuit occur sequentially.
2. Non-recursive digital filter as claimed in Claim 1, characterized in. that the said storage device is a shift register (9) having a given number (N) of register sections (10(.)).each section being arranged to store an input code word, the output of the last register section (10(4)) being coupled to an input of the said multiplying device (11) and also to the input of the shift register (9).
3. Non-recursive digital filter as claimed in Claim 2, characterized in that the input of the said last register section (10(4)) is coupled via a feedback line (14) to the input of the shift register (9), in which digital filter the input and the output of the said last register section (10(4)) are alternately connected, under the control of the said clock pulse generator, to the input of the shift register (9) (Figure 1).
4. Non-recursive digital filter as claimed in Claim 2, characterized in that the clock pulse generator (7) includes means (15, 16) for generating equidistant shift pulses for the shift register (9) and a first counting device (20; 28) which after each cycle consisting of a given number of shift pulses supplies a pulse to a second counting device (21;29), the said number of shifting pulses being at least equal to the number (N) of register sections (10(.)) of the shift register (9) (Figures 2 and 4 respectively).
5. Non-recursive digital filter as claimed in Claims 3 and 4, characterized in that the said second counting device (21) after each sequence of m output pulses of the first counting device returns to the rest condition, where m is equal to the number of output code words which are to be generated within an input sampling period l/f1 (Figures 1 and 2).
6. Non-recursive digital filter as claimed in Claim 4, characterized in that the said counting-devices are connected to means (30, 33, 34) for suppressing at least one of the shift pulses of a cycle of shift pulses which are to be supplied to the shift register (9).
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NLAANVRAGE7412224,A NL176211C (en) | 1974-09-16 | 1974-09-16 | INTERPOLING DIGITAL FILTER. |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1039364A true CA1039364A (en) | 1978-09-26 |
Family
ID=19822103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA235,395A Expired CA1039364A (en) | 1974-09-16 | 1975-09-11 | Interpolating digital filter |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US3988607A (en) |
| JP (1) | JPS5528252B2 (en) |
| AU (1) | AU498189B2 (en) |
| BE (1) | BE833466A (en) |
| CA (1) | CA1039364A (en) |
| FR (1) | FR2285025A1 (en) |
| GB (1) | GB1506010A (en) |
| NL (1) | NL176211C (en) |
| SE (1) | SE406683B (en) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL179620C (en) * | 1975-05-29 | 1986-10-01 | Philips Nv | NON-RECURSIVE, INTERPOLATING, DIGITAL FILTER. |
| JPS5376726A (en) * | 1976-12-20 | 1978-07-07 | Toshiba Corp | Synchronizing system digital filter |
| US4313195A (en) * | 1979-04-23 | 1982-01-26 | Sangamo Weston, Inc. | Reduced sample rate data acquisition system |
| NL7905332A (en) * | 1979-07-09 | 1981-01-13 | Philips Nv | DECIMERING, LINEAR PHASE, DIGITAL FIR FILTER. |
| US4302631A (en) * | 1979-11-28 | 1981-11-24 | International Telephone And Telegraph Corporation | Decimator apparatus for decreasing the word rate of a digital signal of the type employed in digital telephone systems |
| US4270026A (en) * | 1979-11-28 | 1981-05-26 | International Telephone And Telegraph Corporation | Interpolator apparatus for increasing the word rate of a digital signal of the type employed in digital telephone systems |
| FR2495857B1 (en) * | 1980-08-27 | 1987-11-27 | Petit Jean | RECURRING DIGITAL FILTER OF OVERSAMPLE IN DISTRIBUTED ARITHMETICS |
| JPS5749792U (en) * | 1980-09-01 | 1982-03-20 | ||
| US4602285A (en) * | 1983-04-08 | 1986-07-22 | Ampex Corporation | System and method for transforming and filtering a video image |
| ATE41840T1 (en) * | 1983-10-06 | 1989-04-15 | Studer Willi Ag | METHOD AND DEVICE FOR CONVERTING AN INPUT SCAN INTO AN OUTPUT SCAN. |
| GB8421378D0 (en) * | 1984-08-23 | 1984-09-26 | British Broadcasting Corp | Variable speed replay |
| US4588979A (en) * | 1984-10-05 | 1986-05-13 | Dbx, Inc. | Analog-to-digital converter |
| US4691293A (en) * | 1984-12-28 | 1987-09-01 | Ford Aerospace & Communications Corporation | High frequency, wide range FIR filter |
| JPS61177016A (en) * | 1985-01-31 | 1986-08-08 | Anritsu Corp | Digital transversal filter |
| US4835723A (en) * | 1987-04-03 | 1989-05-30 | Tektronix, Inc. | Phase coordinated multistage digital filter |
| US5068813A (en) * | 1989-11-07 | 1991-11-26 | Mts Systems Corporation | Phased digital filtering in multichannel environment |
| US5342990A (en) * | 1990-01-05 | 1994-08-30 | E-Mu Systems, Inc. | Digital sampling instrument employing cache-memory |
| US5058139A (en) * | 1990-08-10 | 1991-10-15 | Siemens Medical Electronics, Inc. | Notch filter for digital transmission system |
| US5818870A (en) * | 1990-08-28 | 1998-10-06 | Canon Kabushiki Kaisha | Digital communication device |
| US5825805A (en) * | 1991-10-29 | 1998-10-20 | Canon | Spread spectrum communication system |
| US5475628A (en) * | 1992-09-30 | 1995-12-12 | Analog Devices, Inc. | Asynchronous digital sample rate converter |
| US5638010A (en) * | 1995-06-07 | 1997-06-10 | Analog Devices, Inc. | Digitally controlled oscillator for a phase-locked loop providing a residue signal for use in continuously variable interpolation and decimation filters |
| US7873101B2 (en) * | 2005-03-25 | 2011-01-18 | Broadcom Corporation | Low latency digital filter and method |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3303335A (en) * | 1963-04-25 | 1967-02-07 | Cabell N Pryor | Digital correlation system having an adjustable impulse generator |
| US3639848A (en) * | 1970-02-20 | 1972-02-01 | Electronic Communications | Transverse digital filter |
| US3633014A (en) * | 1970-03-13 | 1972-01-04 | Bell Telephone Labor Inc | Digital equalizer in which tap adjusting signals are derived by modifying the signal code format |
| US3633105A (en) * | 1970-04-01 | 1972-01-04 | Gte Automatic Electric Lab Inc | Digital adaptive equalizer system |
| FR2129290A5 (en) * | 1971-03-17 | 1972-10-27 | Ibm | |
| US3699321A (en) * | 1971-04-01 | 1972-10-17 | North American Rockwell | Automatic adaptive equalizer implementation amenable to mos |
| FR2273419B1 (en) * | 1973-01-25 | 1976-09-10 | Trt Telecom Radio Electr | |
| FR2229336A5 (en) * | 1973-05-11 | 1974-12-06 | Trt Telecom Radio Electr | |
| NL7307237A (en) * | 1973-05-24 | 1974-11-26 |
-
1974
- 1974-09-16 NL NLAANVRAGE7412224,A patent/NL176211C/en not_active IP Right Cessation
-
1975
- 1975-08-25 US US05/607,630 patent/US3988607A/en not_active Expired - Lifetime
- 1975-09-11 CA CA235,395A patent/CA1039364A/en not_active Expired
- 1975-09-12 SE SE7510161A patent/SE406683B/en unknown
- 1975-09-12 GB GB37641/75A patent/GB1506010A/en not_active Expired
- 1975-09-13 JP JP11052975A patent/JPS5528252B2/ja not_active Expired
- 1975-09-15 AU AU84807/75A patent/AU498189B2/en not_active Expired
- 1975-09-16 BE BE160083A patent/BE833466A/en not_active IP Right Cessation
- 1975-09-16 FR FR7528350A patent/FR2285025A1/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5528252B2 (en) | 1980-07-26 |
| NL7412224A (en) | 1976-03-18 |
| DE2540176A1 (en) | 1976-04-01 |
| SE406683B (en) | 1979-02-19 |
| FR2285025A1 (en) | 1976-04-09 |
| FR2285025B1 (en) | 1979-04-27 |
| AU498189B2 (en) | 1979-02-15 |
| NL176211C (en) | 1985-03-01 |
| SE7510161L (en) | 1976-03-17 |
| AU8480775A (en) | 1977-03-24 |
| JPS5155649A (en) | 1976-05-15 |
| BE833466A (en) | 1976-03-16 |
| US3988607A (en) | 1976-10-26 |
| DE2540176B2 (en) | 1977-05-05 |
| GB1506010A (en) | 1978-04-05 |
| NL176211B (en) | 1984-10-01 |
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