CA1041225A - High density wafer contacting and test system - Google Patents
High density wafer contacting and test systemInfo
- Publication number
- CA1041225A CA1041225A CA239,720A CA239720A CA1041225A CA 1041225 A CA1041225 A CA 1041225A CA 239720 A CA239720 A CA 239720A CA 1041225 A CA1041225 A CA 1041225A
- Authority
- CA
- Canada
- Prior art keywords
- space transformer
- binary
- electrical
- circuit
- test system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07314—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
Abstract
HIGH DENSITY WAFER CONTACTING AND TEST SYSTEM
ABSTRACT
The instant invention is more particularly directed to a contractor structure employed in a high speed electronic test system for testing the electrical integrity of the conductive paths (or lines) in the packaging substrate prior to the mounting and connection thereto of the high circuit density monolithic devices. The contactor structure includes a plurality of discrete electrical probes geometrically arranged, or oriented, to respectively electrically contact a discrete one of said array of con-ductive pads on said packaging substrate or said semiconductor device. The contactor structure further includes a semiconductor space transformer fabricated by large scale integration techniques and containing a plurality of discrete first integrated circuits. The first integrated circuits of the space transformer being respectively electrically connected to said electrical probes. Second integrated circuitry interconnecting said first integrated circuits is also contained within said semiconductor space transformer. Under control of said test system said second integrated circuitry selectively energizes, selected first and second ones of said first integrated circuits. Each of said first integrated circuits contains cir-cuitry, whereby said selected first and second ones of said first circuits will manifest the electrical integrity of the electrical path there between.
Namely, the electrical path whose integrity is manifested is the conductive path in the device or substrate under test.
ABSTRACT
The instant invention is more particularly directed to a contractor structure employed in a high speed electronic test system for testing the electrical integrity of the conductive paths (or lines) in the packaging substrate prior to the mounting and connection thereto of the high circuit density monolithic devices. The contactor structure includes a plurality of discrete electrical probes geometrically arranged, or oriented, to respectively electrically contact a discrete one of said array of con-ductive pads on said packaging substrate or said semiconductor device. The contactor structure further includes a semiconductor space transformer fabricated by large scale integration techniques and containing a plurality of discrete first integrated circuits. The first integrated circuits of the space transformer being respectively electrically connected to said electrical probes. Second integrated circuitry interconnecting said first integrated circuits is also contained within said semiconductor space transformer. Under control of said test system said second integrated circuitry selectively energizes, selected first and second ones of said first integrated circuits. Each of said first integrated circuits contains cir-cuitry, whereby said selected first and second ones of said first circuits will manifest the electrical integrity of the electrical path there between.
Namely, the electrical path whose integrity is manifested is the conductive path in the device or substrate under test.
Description
S
1 BACKGROUND OF T~E INVENTION
In obtaining the electrical characteristics of components and packaging structures, such as integrated circuits and multilayer ceramic substrates, it is imperative that the connecting paths from the ; tester to the device or structure under test, have a controlled electrical environment so as not to distort the test signals and test results. This is especially important in light o~ the ever increasing circuit speeds and density of the components under test.
Also increasing, in addition to the circuit speeds of the the integrated circuits are the number and density of the interconnection pads on the integrated circuit device and the packaging substrate. Namely, the density of the circuitry on a monolithic device is increasing as the art advances. This increase in circuit density in an integrated circuit, in many, if not all instances, dictates a greater number and density of the connection ,:
.
1 BACKGROUND OF T~E INVENTION
In obtaining the electrical characteristics of components and packaging structures, such as integrated circuits and multilayer ceramic substrates, it is imperative that the connecting paths from the ; tester to the device or structure under test, have a controlled electrical environment so as not to distort the test signals and test results. This is especially important in light o~ the ever increasing circuit speeds and density of the components under test.
Also increasing, in addition to the circuit speeds of the the integrated circuits are the number and density of the interconnection pads on the integrated circuit device and the packaging substrate. Namely, the density of the circuitry on a monolithic device is increasing as the art advances. This increase in circuit density in an integrated circuit, in many, if not all instances, dictates a greater number and density of the connection ,:
.
- 2 `-:
.
1 pads on an integrated circuit. Correspondingly, the 2 number and density of connection pads on the packaging
.
1 pads on an integrated circuit. Correspondingly, the 2 number and density of connection pads on the packaging
3 substrate must be increased to accommodate the increase
4 in number and density of connection pads of the high S circuit density integrated circuit. Further, as the 6 circuit density and speed of the integrated circuit 7 increases the conductive paths wi,thin the packaging 8 substrate increase in numoer and density and their 9 length must be reduced or at least not increased. These factors oppose from a practical, or fabrication point 11 of view, the ability of a contacting system to achieve 12 a mi.nimum acceptable distortion environment. These 13 factors, as the art progresses, render the testing of 14 integrated circuit devices, and interconnecting packaging structures more difficult. ~s the art progresses, the 16 testing problems requiring solution are many and complex.
17 Included in these ~est problems are the electrical 18 environment, namely the electrical contacting of a 19 densely spaced array of pads with each electrical ~0 connection having substantially equal and minimum 21 uniform impedance characteristics. In testing the 22 electrical connections to the pads must be made rapidly, -23 and precisely, and must not place undue stress on, or 24 mechanically dama~e the pads.
A major portion of the electrical path from the ;
26 tester to the device under test and return is used 27 for the space transformation function. Its purpose 28 is to take a large multiplicity of electrical conductors 29 from the tester which are spaciously arrayed and transform them into a highly dense array, similar to, or identical 31 to, the device input output pad density pattern. Since _ 3 ~04~ZZS
1 the conducting path length from the tester to the device under test is dominated by the space transformer, for electrical test-ing to be done successfully, a constant impedance environment is necessitated.
Reference is made to United States Patent 3,911,361, issued October 7, 1975 to Ronald Bove et al, entitled "Coaxial Array Space Transformer" and of common assignee herewith.
U.S. Patent No. 3,911,361 is directed to circuit means for connecting a high speed electronic tester to a high circuit density monolithic device under test and where said circuit means includes a unitary structural combination of a space transformer and a probe structure, said space transformer and said probe structure being mechanically and electrically mated to provide a plurali~y of dis-crete physical electrical contacts with said device under test, said space transformer including: a printed circuit board having a plurality of discrete electrically conductive contact areas and at least one relatively large contact area; a densely spaced array of ,~ discrete electrical contacts; said densely spaced array of dis-crete electrical contacts being supported by and maintained in spaced relationship one to another by a material having predetermined di-electric characteristics; a plurality of coaxial cables; each~ of said coaxial cables having an inner conductor, an outer ground shield and dielectric material maintaining said inner conductor and said out ground shield in spaced ; .
.~
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~ FI9-74-027 - 4 -:: , 1~41~5 1 relationship; each of said inner conductors of said 2 plurality of coaxial cables being connected between 3 a predetermined one of said plurality of discrete 4 electrically conductive contact areas on said printed
17 Included in these ~est problems are the electrical 18 environment, namely the electrical contacting of a 19 densely spaced array of pads with each electrical ~0 connection having substantially equal and minimum 21 uniform impedance characteristics. In testing the 22 electrical connections to the pads must be made rapidly, -23 and precisely, and must not place undue stress on, or 24 mechanically dama~e the pads.
A major portion of the electrical path from the ;
26 tester to the device under test and return is used 27 for the space transformation function. Its purpose 28 is to take a large multiplicity of electrical conductors 29 from the tester which are spaciously arrayed and transform them into a highly dense array, similar to, or identical 31 to, the device input output pad density pattern. Since _ 3 ~04~ZZS
1 the conducting path length from the tester to the device under test is dominated by the space transformer, for electrical test-ing to be done successfully, a constant impedance environment is necessitated.
Reference is made to United States Patent 3,911,361, issued October 7, 1975 to Ronald Bove et al, entitled "Coaxial Array Space Transformer" and of common assignee herewith.
U.S. Patent No. 3,911,361 is directed to circuit means for connecting a high speed electronic tester to a high circuit density monolithic device under test and where said circuit means includes a unitary structural combination of a space transformer and a probe structure, said space transformer and said probe structure being mechanically and electrically mated to provide a plurali~y of dis-crete physical electrical contacts with said device under test, said space transformer including: a printed circuit board having a plurality of discrete electrically conductive contact areas and at least one relatively large contact area; a densely spaced array of ,~ discrete electrical contacts; said densely spaced array of dis-crete electrical contacts being supported by and maintained in spaced relationship one to another by a material having predetermined di-electric characteristics; a plurality of coaxial cables; each~ of said coaxial cables having an inner conductor, an outer ground shield and dielectric material maintaining said inner conductor and said out ground shield in spaced ; .
.~
:~`
~ FI9-74-027 - 4 -:: , 1~41~5 1 relationship; each of said inner conductors of said 2 plurality of coaxial cables being connected between 3 a predetermined one of said plurality of discrete 4 electrically conductive contact areas on said printed
5 circuit board and a predetermined one of said densely
6 spaced array of electrical contacts; a plurality of
7 metallic plates for supporting said plurality of
8 coaxial cables in spaced relationship; connection means
9 for electrically connecting in common each of said plurality of metallic plates, each of said outer 11 ground shields of said plurality of coaxial cables, 12 and said relatively large contact area on said printed 13 circuit board; said probe structure having a pluralit~
14 of electrically discrete buckling beam probes; each of said buckling beam probes making physical and 16electrical contact with a predetermined one of said ;~
17 densely spaced array of discrete electrical contacts;
18 each of said buckling beam probes having a length many 19 times its cross-sectional area whereby the probes buckle when an axial load is .applied thereto.
21Reference is made to U. S. Patent No. 3,731,191 22granted May 1, 1973 for a "Micro-~iniature Probe 23 Assembly" to Robert L. Bullard et al and of common 24 assignee herewith.
25Patent No. 3,731,191 is directed to a multi-probe 26test circuit assembly particularly adapted for producing .
27 low resistance electrical connections to a semiconductor 28 component of which the electrical parameters are to be 29 evaluated.
30In accordance with the invention disclosed and 31 ' claimed in U. S. Patent ~o. 3,731,191,'a contact apparatus - 5 - :
~l~4~ 5 1 is provided in which a plurality of probe elements 2 are fixedly held by a common support housing in a 3 fixed array corresponding with the terminal contact 4 pattern of the circuit device *o be engaged for testing.
Essentially, the probe elements comprise individual 6 tubular probe guides with individual probe wires, or 7 the like, removably contained and'compressible within 8 the probe guides. Fixation of the probe elements in 9 the desired array is provided by an encapsulation housing including a support plate portion o the support 11 housing having a plurality of openings arranged to 12 correspond with the test contact pattern of the circuit 13 device. One end of each of the tubular probe guides 14 is attached to the support plate within the plate , 15 openings while the other end is held within the 16 housing preferable adjacent and in abutment with a 17 pressure plate opposite the remote ends o~ the probe 18 guides. The probe wires are designed such that when 19 fully inserted within the probe guide, they extend a controlled amount beyond the end of the housing support 21 plate while the remote ends of the probe wires abut the 22 pressure plate. The tubular probe guides are high 23 conductivity material while the probe wires are conductive ~ 24 material having high resistance to abrasive wearing.
; 25 Electrical circuit concinuity is made by surface contact ~`1 ; " r of the probe wires within the probe guides which are 27 in turn connected to external connector boards or the 28 li~e mounted on the housing and having provision for 29 connection to external test circuits or the like.
, FI 9-74-027 - 6 -~ ~
1 In U. S. Patent No. 3,731,191, the probe ~uides 2 are preferably curved between their ends within the 3 housing. Thus, when contact is made with a test 4 terminal, the probe wires have a spring-like quality and are compressible within the probe guides, the 6 curvature and spring-like qualities of the probe 7 wires causing electrical contact to occur very close 8 to the contact end of the probe g,uide. Thus, only a g short length of the relatively high resistance probe wire is in the electrical circuit while the high 11 conductivity probe guide acts as the principal electrical 12 connection with the external circuits. Since the probe 13 guides and probe wires are conductive, the contact 14 apparatus is essentially made of dielectric materials, 15particularly the support plate and the pressure plates. ~, 16 In addition, the probe guides are completely encapsulated 17 within a dielectric material so t:hat the probe elements 18 are mutually electrically insulated as well as being 19 held rigidly in position.
20Reference is made to U. S. Patent ~o. 3,806,801 `-21granted April 23, 1974 to Ronald Bove, directed to a 22 "Probe Contactor Having Buckling Beam Probes", and 23 of common assignee herewith.
24U. S. Patent No. 3,806,801, discloses a probe contactor in which each of the probes will exert a 26 substantially constant force on each of the pads on 27 the chip irrespective of the relative heights of the 28 pads on the chip as long as the pads on the chip have 29 their height within the predetermined range in which the probes can engage the pads. This is accomplished 31 by forming each of the probes with a length many times 32its cross sectional area so that each of the probes may ~-1 be deemed to be a beam~ Each of the probes is designed 2 so that it will deflect over a range when a predetermined 3 force is applied at its end engaging the pad to axially 4 load the probe so as to prevent any additional force, beyond the predetermined force, being applied to the 6 pad due to engagement of the pad with the probe.
7 Reference is made to U. S. Patent No. 3,806,800, granted April 23, 1974, to Ronal~ Bove and Eric M. Hubacher, 9 directed to "r~ethod and Apparatus for Determining the Location of Electrically Conductive Members on a Structure", 11 and of common assignee herewith. In Patent No. 3,806,800, 12 the electrically conductive pads on a semiconductor 13 chip or the engineering change pads on a multilayer 14 substrate are located electronically relative to probes which are in a predetermined orthogonal orientation, 16 so that the particular probe or probes in engage~ent 17 with each of the pads is determined. Then, the electrical 18 characteristics of any electrical unit connected to each 19 of the pads is ascertained through selectively controlling the electrical power supplied through the probes to the . .
21 pads in a controlled manner.
22 U. S. Patent No. 3,835,3~1, granted September 10, 1974 23 to O. R. Garretson et al, entitled "Probe Card Including .
24 A Multiplicity of Probe Contacts and Methods of Making"
discloses a probe card useful in testing the effectiveness 26 and utility of semiconductor devices and hybrid circuit 27 substrates prior to the application to such devices and 28 substrates of terminal leads for interconnection with 29 other components. The probe card includes a unitary electrically conductive probe assembly including a FI ~~74-027 J~41'~
1 multiplicity of closely spaced conductive probes 2 arranged in a radiating arra~ to provide a multiplicity 3 of contact tips adapted to be pressed with uniform 4 pressure and contact resistance on the terminal pads of semiconductor devices and hybrid circuit substrates.
6 Summark~ the Invention 7 The integrity of closely spaced electrical conductive 8 paths or lines on a semiconductor wafer or multilayered 9 ceramic substrate are verified by use of a plurality of 1~ probes arranged in a predetermined orientation in 11 conjunction with a semiconductor space transformer 12 containing switching logic fa~ricated therein by Large 13 Scale Integration Techniques. The orientation of the 14 probes is identical to the orientation of the conductive pads on the substrate to be tested. The switching logic -~
16 within the semiconductor space transformer is selectively 17 connected to the probes by an electrical interface 18 between the probe structure and the semiconductor space 19 transformer. The space transformer includes circuitry actuating selected portions of said switching logic and 21 the probes discretely connected to said portions. The 22 switching logic further includes circuitry for manifesting 23 the electrical integrity of the conductive path, if any, 24 extending between the conductive substrate pads contacted ~
25 by said actuated probes. Thus, a large multiplicity of ;
26 densely spaced interconnections contained within a 27 packaging substrate may be tested in a rapid, efficlent, 28 practical, reliable and economical manner. Further, the 29 practice of the invention, as will be more fully apparent .:
- FI 9-74-027 _ 9 _ 1 by the more detail description set-forth hereinafter, 2 accomplishes the "tailoring" of the electrical environment 3 to the device under test.
4 Fur~her, as will also be more apparent to persons skilled in the art from the description that follows 6 the practice of the invention is not limited to electrical 7 D.C. testing of passive structures. The invention is 8 clearly applicable to A.C. and D.C. testing of passive 9 and active devices such as integrated circuit structures having a high circuit density.
11 Semiconductor or multilayered products with electrically 12 conductive paths ~lines) incorporated therein are utilized 13 as substrates on which semiconductor chips are mounted.
14 These substrates may be generically term packaging structures, or substrates, as known in tlle art, they 16 may have a wide variation in material, form, and 17 structure. The interconnecting paths are embedded in 18 these packaqing substrates and interconnect the various 19 devices which are attached in later process steps. With increased miniaturization of semiconductor products, the 21 multiplicity, and the density of these paths, has 22 increased and continues to increase. In this environment 23 it is imperative to rigorously test, or verify, the 2~ electrical integrity of the interconnecting paths in the packaging substrate. The term electrical integrity may 26 be defined as including the "open" or "short" condition 27 of the electrical path and the electrical characteristics 2~ of the path such as resistance capacitance, inductance, 29 impedance, cross talk, etc. The use of two single probes, as heretofore, widely practiced in the art has become 1~41Z~S
impractical since it necessi tates that the probes 2 repeatedly contact each pair of test points (pads) 3 on the semiconductor or multilayer substrate (packaging 4 structure). The use of two single probes has numerous 5 recognized disadvantages. It is time consuming. It 6 requires repeated precise alignments of the probes with 7 the very small pads. The two probe technique results 8 in damage to the pads of tl~e packaging structure due to 9 the repeated contacting of the pads, and high production lQ - ` costs are incurred due to the numerous lengthy steps of 11 the align and test procedure required. -12 The use of two contactors, each comprising a 13 multiplicity of probes reduces the stepping and repeated 14 contact of the pads on the packag~ng substrate. I~owever, i 15 this approach requires several cornplex alignments and 16 places a severe physical constraint on the probe-space 17 transformer assembly which must be designed to contact ,, 18 adjacent test point (pad) clusters on tl~e packaging substrate. -The present invention obviates the foregoing 21 problems by utilizing a contactor consisting essentially 22 of a plurality of probes and a solid state integrated 23 circuit space transformer. The plurality of probes are 24 arranged in a predetermined orientation which is identical ~5 to the orientation of the test pads on the packaging 26 substrate to be tested. The assembly of probes readily ~-27 permits physical contacting of each of a relatively 28 large number of closely spaced test points (pads) on a 29 packaging substrate. The assembly of probes preferably 30 may be similar to, or patterned after the probe assembly -"
31 disclosed and claimed and in the afore-identified 32 and discussed Bove Patent No. 3,806,801.
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1 The contactor of the invention consisting 2 essentially of the electrically and mechanically mated 3 assembly of test probes and the solid state space 4 transformer provides conductive paths from the tester to the product, device, or structure under test. The 6 solid state space transformer is preferably a silicon 7 wafer containing integrated circuitry and metallized 8 conductive paths (lands). The se~iconductor space 9 transformer may be fabricated by Large Scale Integration techniques known to the art. Entering the periphery 11 of the solid state space transformer are control signal 12 and power supply conductors which are used to functionally 13 activate the circuitry including logic circuitry contained 14 within the space transformer. By externally addressing the control signal conductors, for example, via an input 16 from a tester under control of a computer, the solid 17 state space transformer circuitry activates two selected 18 probes within the assembly of probes contacting the 19 test points, or pads, on the product, or packaging substrate under test. Once activated, the selected 21 probes and associated circuitry within the space transformer 22 determines the electrical integrity, for example, "open"
23 or "short", existing between the two test points or 24 pads on the device, product, or packaging substrate under test. The circuitry within the solid state 26 transformer provides an electrical manifestation 27 indicative of the merit, or lack of merit, of the 28 electrical path, or circuitry contained within the device 29 under test electrically connected to the pads contacted by the actuated probes. This electrical manifestation 31 is communicated from the solid state space transformer ~ ' . .... . .. __ ---.-l~lZ;Z5 ,~.
l tilrough one or more of the periphery conductors 2 thereo~ to a compu-ter. The com~uter compares this 3 electrical manifestation with a known correct result 4 stored therein. It is to be appreciated that the full data processing capability of the computer system 6 may be envoked to further process the test results.
7 Such further processing of test data is well known 8 in the art and no further discussion thereof is deemed 9 necessary or required to a full understanding and -appreciation of applicants' invention ll It is a primary o~ject of the invention to provide 12 an improved High Density Wafter Contacting and Test 13 System.
14 It is`a primary object of the invention to provide lS an improved contactor structure and circuitry for use 16 in a high speed electronic test system wherein the 17 merit, or lack of merit, of electronic devices, and 18 structures employed therewith, is determined. --l9 It is a primary object of the invention to 2a provide, in a high speed electronic test system, an 21 improved contactor structure for contacting test points 22 on a device under test.
23 It is a primary object of the invention to provide 2~ an improved device under test contactor structure for use in a high speed electronic test system, where said .. , ..
26 contactor structure comprises a precision probe assembly 27 electrically interfaced with a solid state integrated 28 circuit space transformer. The ~space transformer ' .
~41~ZS :
l circuitry is adapted to provide via the probe assembly 2 predetermined electrical conditions on ~he device under test or selected portions thereof. The space transformer 4 circuitry is further adapted to provide an electrical manifestation, or manifestations, as to the merit or 6 integrity of the device under test, or portion thereof 7 under test.
8 It is a primary object of the invention to provide 9 a solid state space transformer havin~ integrated circuitry contained therein and particularly adapted ll to function in electronic test systems for testing 12 electrical devices.
13 It is an object oE the invention to provide 14 means to efficiently, reliably and economically test for "shorts" and "opens" in an electronic structure, 16 such as a chip site areas on undiced semiconductor wafers.
17 It is an object of the invention to provide a 18 semiconductor space transforming ~afer which reduces 19 wiring complexity and hardware when employed in an electronic test system.
21 It is an object of the invention to provide in a 22 test system a device under test contacting structure 23 for reducing test time.
24 It is an object of the invention to provide in a test system a device under test contacting structure 26 t~hich prevents damage to the device under test by 2~7 obviating the need for multiple probing of the device 28 under test~
29 It is a still further object of the invention to provide in a test system a device under test contacting ,_. , , . _ __.. _ _ . . .. . .. .. _ ` ~
~¢~43.Z~5 ~.
1 structure containing a plurality of selectable integrated 2 circuits, whereby the software requirements of the 3 test system are reduced. -~
4 It is an object of this invention to provide in a test system a device under test contacting 6 structure which eliminates stepping across a 7 semiconductor wafer under test.
8 It is an object of this invention to provide in ; 9 a test system a device under test contacting structure la where all products having the same grid pattern of test 11 points may be tested by said test system.
12 It is an object of this invention to provide 13 in a test system a device under test contacting structure 14 comprising a solid state integ.rated circuit space lS transformer electrically and mechanically mated to a 16 precision probe assembly, whereby said probe assembly, 17 which is wear sensitive and subject to damage, may be 18 readily replaced.
19 The foregoing and other objects, features and advantages of the invention will be more apparent from 21 the following more particular description of the 22 preferred e~bodiment of the invention, as illustrated in ,~
23 the accompanying drawings.
24 sr ef Description of the Drawin~s In the drawings:
26 Figure 1 schematically discloses a high speed 27 electronic test system in accordance with the invention 28 for testing electronic devices, packaging substrates, ~.~4~
1 integrated circuit devices, etc. The system includes 2 the interconnection of a computer, a tester, and a 3 device under test contacting structure. The device 4 under test contacting structure is schematically depicted in cross-section and includes a solid-state space transformer and a probe assembly.
7 Figure 2 discloses a representative logical 8 circuit (one of a plurality) fabricated by large scale 9 integration techniques within a silicon wafer space transformer of the invention.
11 Figure 3 discloses two representative lo~ical 12 circuits of the plurality or matrix thereof, fabricated 13 by large scale inte~ration techniques within the solid 14 state space transformer portion of the invention. The two representative logical circuits are depicted with 16 their respective probes contacting test points on a 17 structure undergoing test.
1~ Figure 4 schematically depicts additional logic 19 circuitry, fabricated by large scale integration techniques within th~ solid state space transformer 21 portion of the invention. The additional logic circuitry 22 is employed to select and energize, under control of the ~ -23 test system, an array of circuitry of the type depicted 24 in Figures 2 and 3.
Figure 5 is an enlarged cross-sectional view of 26 a representative portion of the electrical interface 27 between the solid state space transformer and the probe 28 assembly of the invention.
29 Description of the Preferred ~n~odiment _ . . . ~
Reference is made to the drawing and, in particular, . _ . . .
1 Figure 1. The device under test contacting structure, 2 namely contactor 12, shown partially unassembled in Figure 1, 3 comprises the solid state space transformer 13 and probe 4 assembly 20. The probe assembly comprises a plurality of - 5 probes 19 arranged in an array or pattern corresponding 6 to the pattern of test points or pads 16a on the device 7 under test 16.
8 The solid state space transformer holder 22 may 9 be constructed from aluminum with a recessed portion in which the space transformer is seated. An epoxy adhesive 11 may be employed to maintain the space transformer 12 securely in position within the recess. The probe 13 assembly 20 is secured to the memher 22 by any one of 14 a number of mechanical means, or mechanisms, known to the ~`
15 art. For example, fastening of the probe assemhly 20 to the 16 member 22 may be accomplished by diametrically disposed machine ~:
17 screws, or a suitable mechanical spring latch means.
18 Although no means is expressly shown in the drawing 19 for securing the probe assembly 20 to the member 22, which 2Q forms a backing or rigidity structure for the solid 21 state space transformer, it is to be appreciated that 22 the fastening means must provide precise alignment of ; 23 the probe assembly and solid state space transformer.
24 One suitable alignment means is precision machined dowels 17 carried by the probe assembly and mating with machined 26 openings 17a provided in the solid state space transformer .
27 housing or holder 22.
28 The conductive lands 13a carried by on the lower ~-29 planar surface of the solid state space transformer are also arranged in an array, or pattern, corresponding to 31 the array, or pattern, in which the probes 19 are arranged.
.. .. _ _ r~
12~5 1 Thus, when the contactor 12 is in an assembled state, the 2 conductive lands 13a respectively make elec~rical contact 3 wlth the spherical end portions l9a of the probes 19.
4 Thus, at the mating of the probe assembly 20 and the solid state space transformer 13 a large multiplicity 6 of densely arrayed electrical connections are made on 7 an easily separable electrical interface.
The easily separable electrical interface 9 between the probe assembly 20 and the solid state space transformer 13 comprises the electrical connection 11 of each land 13a of the space transformer with one of 12 the end portions 19a of the prohe assembly 20 as shown 13 in Figure 1.
14 In Figure 5 an enlarged cross-sectional portion of the afore-identified electrical interface is shown.
16 As is well known to persons skill~!d in the electronic 17 testing art the connection between the lands 13a and 18 the probe ends l9a must be a vary low ohmic resistance 19 connection having good wear characteristics.
As depicted in Figure 1, the electronic test 21 system includes a computer 14, tester 15 and contactor~12.
.
22 The computer 14 communicates with the contactor 12 and 23 and more specifically, the space transformer 13 via ~-24 leads Ll and with tester 1~ via leads L2. The tester 15 communicates with the contactor 12 and 26 more specifically the space transformer 13 via 27 leads L3, and with the computer system 14 via leads L2.
28 It will ~e appreciated the term computer as here employed ~
29 is generic to a computer system having input~output devices, a memory, data processin~ a~ility, etc.. The 31 tester may be any one of a number of testers known FI 9-74-027 - 18~
~' ..
- , -iL~3~ 5 l to, and available to the art. For example, the computer system may be a dedicated mini-computer or a more sizeable time shared computer. Numerous suitable computers and computer systems are known to the art and commercially available.
As will be appreciated by persons skilled in the testing art, from the detailed description of the invention hereinafter, the device under test contacting structure may be employed in a test system consisting essentially of a computer system and suitable interface circuitry interconnecting the contactor structure with l the computer system.
The practice of applicants' invention is not limited to the architecture of any particular electronic test system for testing electronic devices. An electron;c test system generally of the type disclosed in U.S. Patent No. 3,9l6,306, issued October 28, l975, to Michael J. Patti, entitled "Method and Apparatus for Testing High Circuit Density Devices" and of common assignee herewith, or generally of the type disclosed in U.S. Patent No. 3,873,8l8, issued March 25, l975 by John D. Barnard, entitled "Electronic Tester for Testing Devices having High Circuit Density", of common assignee herewith, may be employed to practice applicants' invention.
Referring to U.S. Patent No. 3,806,800, of common assignee herewith, the electronic test system may be generally of the type disclosed therein. Namely, one suitable example of the tester l5 is of the type sold ~ ' , .~
FI9-74-027 - l9 -.~ ~
1 by Fairchild Systems Technology~ Inc., Sunnyvale, California as model No.
5000. One suitable example of the computer 14 is an IBM* 1800 computer.
In summary, the tester supplies a sequence of test patterns to the space transformer. The computer allows automatic programmable se-lection of test lines to be achieved to encompass various product families and part numbers. The computer also provides data acquisition, tabulation, processing etc.
The solid-state space transformer 13 is preferably a silicon wafer containing a plurality oF interconnected integrated circuits. The solid-state space transformer has contacts thereon for the connection of leads Ll and L2 and an array of conductive lands 13a for electrically interfacing with probes 19. The solid-state space transformer is fabricated by state of the art large scale integration technique known to persons skilled in the art.
An understanding of the fabrication process for constructing the solid-state-space transformer is not nec:essary to a full understanding of, and the ability to practice the invent;on disclosed and claimed herein.
The circuitry fabricated on and within the solid-state-space transformer will now be described in detail. Referring to Figure 4, the sol;d-state transformer contains a total of four decoders. Namely, they are as labelled for convenience of explanation in Figure 4, .
*Registered Trade Mark ,S
1 "Force X Decoder", "Force Y Decoder", "~ense X Decoder", 2 and "Sense Y Decoder". Each decoder may be a binary 3 decoder adapted to receive m inputs and select one 4 out of 2m outputs. Two of the decoders, namely the "Force X Decoder", and the "Force Y Decoder"
6 provide a first matrix, herein after for convenience 7 of explanation referred to as the "Force Matrix". The 8 remaining two of the four decoders, namely, the "Sense X
9 Decoder" and "Sense Y Decoder" provide a second matrix, hereinafter for convenience of explanation referred to 11 as the "Sense Matrix". The "Sense Matrix" and "Force 12 Matrix" are equal in logical dimension. Also, the 13 selected output of the "Force X Decoder" is a logical 14 "UP" condition: the selected output of the "Force Y
Decoder" is a logical "UP" condition; the selected output 16 of the "Sense X Decoder" is a logical "DOWN" condition;
17 and the selected output of the "Sense Y Decoder is a logical 18 "DO~" condition. Thus, it ~ill be apparent the "Force"
19 and "Sense" decoder operations are logically complementary.
. 1 In Figure 4, each of the four decoders has 21 four inputs and each provides a selection of one output 22 of sixteen possible outputs. M = 4 inputs, providing 23 the ability to select one out of sixteen outputs is an - 24 arbitrary selection, chosen for convenience of ~' :
explanation. It will be appreciated the invention may be 26 practiced with m less than, or greater than four.
27 Still referring to Figure 4, the outputs of 23 the decoders are preferably discrete metalli~ed lines.
29 The output lines FXl through FX16 of the "Force X
Decoder" and the output lines SXl throu~h SX16 of the ,, ....... , .. _ -. .
1q~4~LZ~S
.
1 "Sense X Decoder" may ~re~exa~ly be fabricated on a 2 first level of metalllzation. The output lines FYl 3 through FY16 of the "Force Y Decoder" and the output 4 lines "SYl through SY16" of the "Sense Y Decoder" may 5 preferably be fabricated on a second level of metallization.
6 The circuitry fabricated on and within the solid-7 state space transformer includes a plurality of logic 8 circuits. A typical one of which is shown in Figure 2.
9 As will be fully apparent from the description that follows, each logic circuit functions under control of 11 the "Sense Matrix", and the "Force Matrix". Each logic 12 circuit is electricall~ connected to a discrete probe 19 13 of the probe assembly 20.
14 In the preferred embodiment each of the plurality of logic circuits is represented by the 16 logic circuit shown in Figure 2. The logic circuit 17 shown in Figure 2 may be considered as one of a matrix . ~ . .
~ 18 of logic circuits, where each logic circuit is interconnected . . .
~ 19 between the "Force Matrix", the "Sense Matrix" and a .
probe 19. The representative logical circuit in 21 Figure 2 is shown connected to, the output FXl of 22 the "Force X Decoder", the output FYl of the "Force Y
23 Decoder", the output SXl of the "Sense X Decoder", 24 the output SYl of the "Sense Y Decoder", and via the electrical interface (13a and l9a, see Figure 1) to a 26 discrete probe 19 of the assembly. The connèction of 27 the logical circuit of Figure 2 is representative of 28 the connection of eac'n of the plurality of logic circuits.
29 Thus, the plurality of logic circuits may be considered .
FI 9-7~-027 ~ 22 , _ . . . ... . ------ ., ., . .. , . .-- . _ .. _ ___ . . . _ . .. _ . .. _ _ 41'~25 1 to a matrix of logic circuits selectiveiy connected to 2 the "Force Matrix", the "Sense ~latrix" and the probe 3 assembly 20. In summary, each logic circuit of the 4 matrix of logic circuits is represented by the circuit of Figure 2. Each logic circuit of the matrix of 6 logic circuits has, the base of its transistor Tl 7 connected to an output of the "Fo~ce X Decoder", the 8 base of its transistor T2 connected to an output of 9 the "Force Y Decoder", the base of its ~ransistor T7 la connected to an output of the "Sense X Decoder", the 11 hase of its transistor T8 connected to an output of the 12 "Sense Y Decoder", and the collector of transistor T5, 13 together with the base of transistor T6 connected to 14 a discrete probè 19 of the probe assembly 20. Further lS as shown schematically in Figure ,', the collector of 16 transistor T9 of each of the logia circuits i5 commonly 17 connected through resistor R7 to a reference potential 18 ~ground) and to a common output terminal.
19 Thus, it will be apparent that the preferred embodiment of the invention as illustrated in the 21 drawings may have two hundred and fiftysix probes 22 each discretely controlled by a single logic circuit 23 within the matrix of logic circuits. The logical operation 24 of the circuit of Figure 2 will be fully apparent from a detailed explanation hereinafter of how any two selected 26 circuits of the logical circuit matrix are employed to 27 determine the electrical integrity of a conductive path 28 between two pads on a device under test.
29 In the following table, Table ~o. 1, the interconnection of a (16 x 16) Force Matrix, a (16 x 16) 31 Sense Matrix, a (256) logical circuit Matrix and a probe E'I 9-74-027 - 23 -1 assembly having 256 probes is tabulated. The content of Table No. 1, namely the particular numbering, and particular interconnections are not to be taken as a limitation of the invention. The content of Table No. l is illustrative, representative and a convenience in ex-planation.
TABLE N0. 1 Logical CircuitProbe Number Force Matrix Sense Matrix Number of Logical In Probe Connections Connections to Circuits in Matrix Assembly to Logical Lo~ical Circuit Circuit 1 1 FXl, FYl SYl, SXl 2 2 FX2, FYl SYl, SX2 3 3 FX3, FYl SYl, SX3 4 4 FX4, FYl SYl, SX4 ~, . ' ,, ' 14 14 FX14,FYl SYl, SX14 FX15,FYl SYl, SX15 16 16 FX16,FYl SYl, SX16 17 17 FXl, FY2 SY2, SXl 18 18 FX2, FY2 SY2, SX2 :: ::
31 31 FX15,FY2 SY2, SX15 32 32 FX16,FY2 SY2, SX16 33 33 FX 1,FY3 SY2, SX16 34 34 FX 2,FY3 SY3, SX2 .
.
. 47 47 FX15,FY3 SY3, SX15 48 48 FX16,FY3 SY3, SX16 ~ 49 49 FXl, FY4 SY4, SXl : ~50 50 FX2, FY4 SY4, SX2 :': . . . . . .
:
63 63 FX15,FY4 SY4, SX15 ; 64 64 FXl6,FY4 SY4, SX16 FXl, FY5 SY5, SXl 66 66 FX2, FY5 SY5, SX2 .
254 254 FX14,FYl6 SY16,SX14 ; 255 255 FX15,FY16 SY16,SX15 256 256 FX16,FY16 SY16,SX16 ~, 1 Each logical circuit of the matrix of logical 2 circuits may be selected to function or perform as a 3 "Force" circuit, or as a "Sense" circuit. A logical 4 circuit selected to perform as a "Force circuit"
has each of its Force inputs, FX _ and FY _, in a logical 6 UP condition, and one, or both, of its Sense inputs, SX
7 and SY _ , in an UP condition. Correspondingly, when 8 a logical circuit is selected to perform as a "Sense 9 Circuit", it has each of its Sense inputs, SX and 1~ SY in, a DOWN condition an-d one, or both, of 11 its Force inputs, FX _ _ and FY _ in a ~OWN condition.
12 Thus, for example, referring to Table No. 1, it will be 13 seen that logical circuit Number ].7 is selected to perform 14 a Force function when Force Inputs FXl and FY2 are respectively in an UP condition, cmd one, or both, of 16 the Sense inputs SY2 and SXl are i.n an UP condition.
17 Correspondingly, still referring to Table No. 1, logical 18 circuit Number 33 is selected to perform a Sense function 19 when Sense Inputs SY3 and SXl, are respectively in a 2Q DOWN condition, and one, or both, of the Force inputs FXl 21 and FY3 are in a DOWN condition. It will now be 22 apparent from the preceding description that any one ~:' 23 of the two hundred and fifty-six logical circuits 24 comprising the monolithic logical circuit matrix may be selected by the "Force Matrix" to perform a 26 "Force Function". Also, any one of the-two hundred 27 and fifty-six logical circuits comprising the monolithic 28 logical circuit matrix may be selected by the "Sense 29 Matrix" to perform a "Sense Function". ~s will be ~ 30 apparent from the further description set-forth ~-.
1C1 412~S
1 hereinafter, except for testing the logical circui~, ;
2 the same logical circuit of the logical circuit matrix 3 is not concurrently selected by the "Force Matrix" and 4 the "Sense Matrix".
In the further description of the operation of the 6 invention set forth below, it will he apparent that the 7 logical circuit performing the "F~rce Operation" and 8 the logical circuit performing the "Sense Operation"
9 are customarily discrete different ones of the plurality of logical circuits comprisiny the monolithic logical 11 circuit matrix.
12 It is to be appreciated -that with each of the 13 two hundred and fifty-six logical circuits, a discrete 1~ probe 19 of probe assembly 20 is associated and interconnected therewith. Thus, it is apparent any one of the probes 19 16 may be addressed to perform a "Force ~unction" and any 17 one, other than a probe addressed to perform a "Force 18 function" may be addressed to perform a "Sense function".
19 With reference to Figure 3, the practice of the invention, in a representative application thereof, will ~ . .
21 be explained in detail. In Figure 3, it will be seen 22 that two logical circuits of the type shown in Figure 2 23 are shown. The upper logical circuit in this illustrative 24 example is performing the "Force operation", as depicted by the legend "Force Function". In the upper 26 circuit, the Force inputs FX2 and FYl thereof are 27 respectively in an UP condition and at least one of 28 the Sense inputs, SX2 and SYl, is in an UP condition.
29 With an UP potential level on FX2 and FYl, transistors Tl ~`
1 and T2 are respectively conductive, T3 and T4 are rendered 2 non-conductive and T5 conductive. The potential at the 3 collector of conductive transistor T5 is DOWN. This 4 DOWN potential is impressed via probe #2 (See Table No. 1) of the plurality of probes 19 on a land 16a of the 6 device under test, or wafer 16, as shown in Figure 3.
7 The lower logical circuit in~this illustrative 8 example (Figure 3) has been selected to perform the "5ense 2 Operation", as depicted by the legend "Sense Function".
lQ In the lower circuit as viewed in Figure 3, Sense 11 Inputs, SX16 and SY2, thereof are respectively in a ~` 12 DOWN condition and at least one of the Force inputs, 13 FX16 and FY2, is in a DOWN condition. Transistor T5 14 of the logical circuit selected to perform the sense function, namely the lower circuit: as viewed in Figure 3 16 is non-conductive since at least one of the inpu~s FX16 17 ~nd FY2 is DOWN.
18 It will now be apparent from viewing Figure 3 ~ 19 and the immediately preceding discussion that the `l 20 following conditions may exist. (1) If the conductive 21 path under test as shown in Figure 3 is "open" (or very 22 high resistance) the base of transistor T6 in the Sense 23 circuit will be in an UP condition. The "common output 24 Terminal", connected in common to the collectors of transistors T9 and via resistor R7 to ground, will be in 26 an UP condition. (2) If the conductive path under 27 test as shown in Figure 3 is "closed" (or very low 28 resistance) the base of transistor T6 in the Sense 29 circuit will be at a DOWN condition. (Same potential as collector of conductive transistor T5 of the Force 3L~ 5 1 circuit). The "Common Output Terminal" will be DOWN.
2 In summary, when the upper logic circuit as viewed 3 in Figure 3 is selected as a "Force Circuit" and the 4 lower circuit as a "Sense Circuit" the "Common Output Terminal" will be "DOWN" if the circuit path under ;~ 6 test is "closed", and "UP" if the circuit path under j 7 test is "open". It will be appreciated that in the 8 illustrative example of operation as depic-ted in Figure 3 9 the lower circuit could have been selected as the Force . . .
circuit and the upper circuit as the Sense circuit.
11 Summary of the Solid-State Space 12 Transformer of the Preferred Embodiment 13 There are total of four decoders, two identified 14 as "Force" and two identified as "Sense". Each is a binary decoder with a number of inputs (m) that provide a greater 16 number of outputs (2m). The decoders are arranged to 17 provide two matrices, a "Force" and a ".5ense". The "X"
18 and "Y" dimensions of the "Force" matrix are equal to 19 the corresponding "X" and "Y" dimensions of the "Sense"
matrix. Metallized lines from each output of the decoders 21 run to a matrix of monolithic circuits. The "Force"
22 and "Sense" decod`er operations are logically reversed, 23 that is r the selected output of each "Force" decoder is 24 "UP" while the selected output of each "Sense" decoder is "DOWN".
26 Correspondin~ to the common dimensions of the 27 "Force" and "Sense" matrices is a matrix of monolithic 28 circuits. These circuits perform the desired "Force" or 29 "Sense" operation determined by the decoders. Since only one output of each "Force" decoder can be at an 31 "UP" level, only one monolithic circuit in the matrix _.. ....
' 1~412i~5 l can be selected to perform a "Force" function at any 2 given time. Likewise, since only one output of each 3 "Sense" decoder can be at a "DOWN" level, only one 4 monolithic circuit in the matrix can be selected to perform a "Sense" function at any given time.
6 ~ monolithic circuit is selected to perform a 7 "Force" function when both Force Inputs thereof namely 8 "FX _ " and "FY _ " are "UP". It is selected to 9 perform a "Sense" function when both Sense Inputs l~ thereof "SX _ " and "SY " are "DOWN". The outputs of 11 the monolithic circuits are dotted together through , 12 metallized lands and connected to a resistor. The output 13 at the resistor is "DOWN", if, and only if, a short exists ~4 between the monolithic circuit selected as "Force"
and the monolithic circuit selected as "Sense". The 16 output at the resistor is "UP" if, and only if, an open 17 exists between the monolithic circuit selected as "Force"
18 and the monolithic circuit selected as "Sense".
19 It is to be appreciated that the practice of the 2a invention may vary in form and structure without departing 21 from the spirit of the invention.
22 For example, the solid state transformer may with 23 appropriated designed circuitry fabricated therein provide 24 inputs, and accept outputs from integrated circuit devices, such as a logical devices, under test.
26 The solid state space transformer may wit'n appropriately 27 designed circuitry fabricated therein be employed 28 advantageously in the testing of integrated circuit devices 29 fabricated by large scale integration techniques and containing combinatorial and sequential logic.
FI 9~74-027 - 29~-~;.
3L~4~ 5 l The solid state space transformer has the capability to electrically switch the testing to any two points on a closely spaced grid pattern.
The solid state space trans~ormer may be employed with an array of probes utilized to contact test pads on a device under test where the pads on the device under test are spaced one from another on a 0.25 millimeter grid or less.
The solid state space transformer may be employed to test the interconnection between chip islands on an undiced wafer.
The solid state space transformer may be employed to test the interconnections within a Multi-Layer-Ceramic structure.
It is to be appreciated that test systems (AC and DC) may be designed where the solid state, preferably silicon, space transformer is fabricated to contain monolithic circuits for providing pulses o~ proper rise time, shape and level for application t~ a device under test.
While the invention has been described and shown particularly with reference to one of its preferred embodlments, it will be understood by those skilled in the art to which the work is directed that various changes in form and detail may be made withowt departing from either the 2~ spirit or scope of the invention.
14 of electrically discrete buckling beam probes; each of said buckling beam probes making physical and 16electrical contact with a predetermined one of said ;~
17 densely spaced array of discrete electrical contacts;
18 each of said buckling beam probes having a length many 19 times its cross-sectional area whereby the probes buckle when an axial load is .applied thereto.
21Reference is made to U. S. Patent No. 3,731,191 22granted May 1, 1973 for a "Micro-~iniature Probe 23 Assembly" to Robert L. Bullard et al and of common 24 assignee herewith.
25Patent No. 3,731,191 is directed to a multi-probe 26test circuit assembly particularly adapted for producing .
27 low resistance electrical connections to a semiconductor 28 component of which the electrical parameters are to be 29 evaluated.
30In accordance with the invention disclosed and 31 ' claimed in U. S. Patent ~o. 3,731,191,'a contact apparatus - 5 - :
~l~4~ 5 1 is provided in which a plurality of probe elements 2 are fixedly held by a common support housing in a 3 fixed array corresponding with the terminal contact 4 pattern of the circuit device *o be engaged for testing.
Essentially, the probe elements comprise individual 6 tubular probe guides with individual probe wires, or 7 the like, removably contained and'compressible within 8 the probe guides. Fixation of the probe elements in 9 the desired array is provided by an encapsulation housing including a support plate portion o the support 11 housing having a plurality of openings arranged to 12 correspond with the test contact pattern of the circuit 13 device. One end of each of the tubular probe guides 14 is attached to the support plate within the plate , 15 openings while the other end is held within the 16 housing preferable adjacent and in abutment with a 17 pressure plate opposite the remote ends o~ the probe 18 guides. The probe wires are designed such that when 19 fully inserted within the probe guide, they extend a controlled amount beyond the end of the housing support 21 plate while the remote ends of the probe wires abut the 22 pressure plate. The tubular probe guides are high 23 conductivity material while the probe wires are conductive ~ 24 material having high resistance to abrasive wearing.
; 25 Electrical circuit concinuity is made by surface contact ~`1 ; " r of the probe wires within the probe guides which are 27 in turn connected to external connector boards or the 28 li~e mounted on the housing and having provision for 29 connection to external test circuits or the like.
, FI 9-74-027 - 6 -~ ~
1 In U. S. Patent No. 3,731,191, the probe ~uides 2 are preferably curved between their ends within the 3 housing. Thus, when contact is made with a test 4 terminal, the probe wires have a spring-like quality and are compressible within the probe guides, the 6 curvature and spring-like qualities of the probe 7 wires causing electrical contact to occur very close 8 to the contact end of the probe g,uide. Thus, only a g short length of the relatively high resistance probe wire is in the electrical circuit while the high 11 conductivity probe guide acts as the principal electrical 12 connection with the external circuits. Since the probe 13 guides and probe wires are conductive, the contact 14 apparatus is essentially made of dielectric materials, 15particularly the support plate and the pressure plates. ~, 16 In addition, the probe guides are completely encapsulated 17 within a dielectric material so t:hat the probe elements 18 are mutually electrically insulated as well as being 19 held rigidly in position.
20Reference is made to U. S. Patent ~o. 3,806,801 `-21granted April 23, 1974 to Ronald Bove, directed to a 22 "Probe Contactor Having Buckling Beam Probes", and 23 of common assignee herewith.
24U. S. Patent No. 3,806,801, discloses a probe contactor in which each of the probes will exert a 26 substantially constant force on each of the pads on 27 the chip irrespective of the relative heights of the 28 pads on the chip as long as the pads on the chip have 29 their height within the predetermined range in which the probes can engage the pads. This is accomplished 31 by forming each of the probes with a length many times 32its cross sectional area so that each of the probes may ~-1 be deemed to be a beam~ Each of the probes is designed 2 so that it will deflect over a range when a predetermined 3 force is applied at its end engaging the pad to axially 4 load the probe so as to prevent any additional force, beyond the predetermined force, being applied to the 6 pad due to engagement of the pad with the probe.
7 Reference is made to U. S. Patent No. 3,806,800, granted April 23, 1974, to Ronal~ Bove and Eric M. Hubacher, 9 directed to "r~ethod and Apparatus for Determining the Location of Electrically Conductive Members on a Structure", 11 and of common assignee herewith. In Patent No. 3,806,800, 12 the electrically conductive pads on a semiconductor 13 chip or the engineering change pads on a multilayer 14 substrate are located electronically relative to probes which are in a predetermined orthogonal orientation, 16 so that the particular probe or probes in engage~ent 17 with each of the pads is determined. Then, the electrical 18 characteristics of any electrical unit connected to each 19 of the pads is ascertained through selectively controlling the electrical power supplied through the probes to the . .
21 pads in a controlled manner.
22 U. S. Patent No. 3,835,3~1, granted September 10, 1974 23 to O. R. Garretson et al, entitled "Probe Card Including .
24 A Multiplicity of Probe Contacts and Methods of Making"
discloses a probe card useful in testing the effectiveness 26 and utility of semiconductor devices and hybrid circuit 27 substrates prior to the application to such devices and 28 substrates of terminal leads for interconnection with 29 other components. The probe card includes a unitary electrically conductive probe assembly including a FI ~~74-027 J~41'~
1 multiplicity of closely spaced conductive probes 2 arranged in a radiating arra~ to provide a multiplicity 3 of contact tips adapted to be pressed with uniform 4 pressure and contact resistance on the terminal pads of semiconductor devices and hybrid circuit substrates.
6 Summark~ the Invention 7 The integrity of closely spaced electrical conductive 8 paths or lines on a semiconductor wafer or multilayered 9 ceramic substrate are verified by use of a plurality of 1~ probes arranged in a predetermined orientation in 11 conjunction with a semiconductor space transformer 12 containing switching logic fa~ricated therein by Large 13 Scale Integration Techniques. The orientation of the 14 probes is identical to the orientation of the conductive pads on the substrate to be tested. The switching logic -~
16 within the semiconductor space transformer is selectively 17 connected to the probes by an electrical interface 18 between the probe structure and the semiconductor space 19 transformer. The space transformer includes circuitry actuating selected portions of said switching logic and 21 the probes discretely connected to said portions. The 22 switching logic further includes circuitry for manifesting 23 the electrical integrity of the conductive path, if any, 24 extending between the conductive substrate pads contacted ~
25 by said actuated probes. Thus, a large multiplicity of ;
26 densely spaced interconnections contained within a 27 packaging substrate may be tested in a rapid, efficlent, 28 practical, reliable and economical manner. Further, the 29 practice of the invention, as will be more fully apparent .:
- FI 9-74-027 _ 9 _ 1 by the more detail description set-forth hereinafter, 2 accomplishes the "tailoring" of the electrical environment 3 to the device under test.
4 Fur~her, as will also be more apparent to persons skilled in the art from the description that follows 6 the practice of the invention is not limited to electrical 7 D.C. testing of passive structures. The invention is 8 clearly applicable to A.C. and D.C. testing of passive 9 and active devices such as integrated circuit structures having a high circuit density.
11 Semiconductor or multilayered products with electrically 12 conductive paths ~lines) incorporated therein are utilized 13 as substrates on which semiconductor chips are mounted.
14 These substrates may be generically term packaging structures, or substrates, as known in tlle art, they 16 may have a wide variation in material, form, and 17 structure. The interconnecting paths are embedded in 18 these packaqing substrates and interconnect the various 19 devices which are attached in later process steps. With increased miniaturization of semiconductor products, the 21 multiplicity, and the density of these paths, has 22 increased and continues to increase. In this environment 23 it is imperative to rigorously test, or verify, the 2~ electrical integrity of the interconnecting paths in the packaging substrate. The term electrical integrity may 26 be defined as including the "open" or "short" condition 27 of the electrical path and the electrical characteristics 2~ of the path such as resistance capacitance, inductance, 29 impedance, cross talk, etc. The use of two single probes, as heretofore, widely practiced in the art has become 1~41Z~S
impractical since it necessi tates that the probes 2 repeatedly contact each pair of test points (pads) 3 on the semiconductor or multilayer substrate (packaging 4 structure). The use of two single probes has numerous 5 recognized disadvantages. It is time consuming. It 6 requires repeated precise alignments of the probes with 7 the very small pads. The two probe technique results 8 in damage to the pads of tl~e packaging structure due to 9 the repeated contacting of the pads, and high production lQ - ` costs are incurred due to the numerous lengthy steps of 11 the align and test procedure required. -12 The use of two contactors, each comprising a 13 multiplicity of probes reduces the stepping and repeated 14 contact of the pads on the packag~ng substrate. I~owever, i 15 this approach requires several cornplex alignments and 16 places a severe physical constraint on the probe-space 17 transformer assembly which must be designed to contact ,, 18 adjacent test point (pad) clusters on tl~e packaging substrate. -The present invention obviates the foregoing 21 problems by utilizing a contactor consisting essentially 22 of a plurality of probes and a solid state integrated 23 circuit space transformer. The plurality of probes are 24 arranged in a predetermined orientation which is identical ~5 to the orientation of the test pads on the packaging 26 substrate to be tested. The assembly of probes readily ~-27 permits physical contacting of each of a relatively 28 large number of closely spaced test points (pads) on a 29 packaging substrate. The assembly of probes preferably 30 may be similar to, or patterned after the probe assembly -"
31 disclosed and claimed and in the afore-identified 32 and discussed Bove Patent No. 3,806,801.
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1 The contactor of the invention consisting 2 essentially of the electrically and mechanically mated 3 assembly of test probes and the solid state space 4 transformer provides conductive paths from the tester to the product, device, or structure under test. The 6 solid state space transformer is preferably a silicon 7 wafer containing integrated circuitry and metallized 8 conductive paths (lands). The se~iconductor space 9 transformer may be fabricated by Large Scale Integration techniques known to the art. Entering the periphery 11 of the solid state space transformer are control signal 12 and power supply conductors which are used to functionally 13 activate the circuitry including logic circuitry contained 14 within the space transformer. By externally addressing the control signal conductors, for example, via an input 16 from a tester under control of a computer, the solid 17 state space transformer circuitry activates two selected 18 probes within the assembly of probes contacting the 19 test points, or pads, on the product, or packaging substrate under test. Once activated, the selected 21 probes and associated circuitry within the space transformer 22 determines the electrical integrity, for example, "open"
23 or "short", existing between the two test points or 24 pads on the device, product, or packaging substrate under test. The circuitry within the solid state 26 transformer provides an electrical manifestation 27 indicative of the merit, or lack of merit, of the 28 electrical path, or circuitry contained within the device 29 under test electrically connected to the pads contacted by the actuated probes. This electrical manifestation 31 is communicated from the solid state space transformer ~ ' . .... . .. __ ---.-l~lZ;Z5 ,~.
l tilrough one or more of the periphery conductors 2 thereo~ to a compu-ter. The com~uter compares this 3 electrical manifestation with a known correct result 4 stored therein. It is to be appreciated that the full data processing capability of the computer system 6 may be envoked to further process the test results.
7 Such further processing of test data is well known 8 in the art and no further discussion thereof is deemed 9 necessary or required to a full understanding and -appreciation of applicants' invention ll It is a primary o~ject of the invention to provide 12 an improved High Density Wafter Contacting and Test 13 System.
14 It is`a primary object of the invention to provide lS an improved contactor structure and circuitry for use 16 in a high speed electronic test system wherein the 17 merit, or lack of merit, of electronic devices, and 18 structures employed therewith, is determined. --l9 It is a primary object of the invention to 2a provide, in a high speed electronic test system, an 21 improved contactor structure for contacting test points 22 on a device under test.
23 It is a primary object of the invention to provide 2~ an improved device under test contactor structure for use in a high speed electronic test system, where said .. , ..
26 contactor structure comprises a precision probe assembly 27 electrically interfaced with a solid state integrated 28 circuit space transformer. The ~space transformer ' .
~41~ZS :
l circuitry is adapted to provide via the probe assembly 2 predetermined electrical conditions on ~he device under test or selected portions thereof. The space transformer 4 circuitry is further adapted to provide an electrical manifestation, or manifestations, as to the merit or 6 integrity of the device under test, or portion thereof 7 under test.
8 It is a primary object of the invention to provide 9 a solid state space transformer havin~ integrated circuitry contained therein and particularly adapted ll to function in electronic test systems for testing 12 electrical devices.
13 It is an object oE the invention to provide 14 means to efficiently, reliably and economically test for "shorts" and "opens" in an electronic structure, 16 such as a chip site areas on undiced semiconductor wafers.
17 It is an object of the invention to provide a 18 semiconductor space transforming ~afer which reduces 19 wiring complexity and hardware when employed in an electronic test system.
21 It is an object of the invention to provide in a 22 test system a device under test contacting structure 23 for reducing test time.
24 It is an object of the invention to provide in a test system a device under test contacting structure 26 t~hich prevents damage to the device under test by 2~7 obviating the need for multiple probing of the device 28 under test~
29 It is a still further object of the invention to provide in a test system a device under test contacting ,_. , , . _ __.. _ _ . . .. . .. .. _ ` ~
~¢~43.Z~5 ~.
1 structure containing a plurality of selectable integrated 2 circuits, whereby the software requirements of the 3 test system are reduced. -~
4 It is an object of this invention to provide in a test system a device under test contacting 6 structure which eliminates stepping across a 7 semiconductor wafer under test.
8 It is an object of this invention to provide in ; 9 a test system a device under test contacting structure la where all products having the same grid pattern of test 11 points may be tested by said test system.
12 It is an object of this invention to provide 13 in a test system a device under test contacting structure 14 comprising a solid state integ.rated circuit space lS transformer electrically and mechanically mated to a 16 precision probe assembly, whereby said probe assembly, 17 which is wear sensitive and subject to damage, may be 18 readily replaced.
19 The foregoing and other objects, features and advantages of the invention will be more apparent from 21 the following more particular description of the 22 preferred e~bodiment of the invention, as illustrated in ,~
23 the accompanying drawings.
24 sr ef Description of the Drawin~s In the drawings:
26 Figure 1 schematically discloses a high speed 27 electronic test system in accordance with the invention 28 for testing electronic devices, packaging substrates, ~.~4~
1 integrated circuit devices, etc. The system includes 2 the interconnection of a computer, a tester, and a 3 device under test contacting structure. The device 4 under test contacting structure is schematically depicted in cross-section and includes a solid-state space transformer and a probe assembly.
7 Figure 2 discloses a representative logical 8 circuit (one of a plurality) fabricated by large scale 9 integration techniques within a silicon wafer space transformer of the invention.
11 Figure 3 discloses two representative lo~ical 12 circuits of the plurality or matrix thereof, fabricated 13 by large scale inte~ration techniques within the solid 14 state space transformer portion of the invention. The two representative logical circuits are depicted with 16 their respective probes contacting test points on a 17 structure undergoing test.
1~ Figure 4 schematically depicts additional logic 19 circuitry, fabricated by large scale integration techniques within th~ solid state space transformer 21 portion of the invention. The additional logic circuitry 22 is employed to select and energize, under control of the ~ -23 test system, an array of circuitry of the type depicted 24 in Figures 2 and 3.
Figure 5 is an enlarged cross-sectional view of 26 a representative portion of the electrical interface 27 between the solid state space transformer and the probe 28 assembly of the invention.
29 Description of the Preferred ~n~odiment _ . . . ~
Reference is made to the drawing and, in particular, . _ . . .
1 Figure 1. The device under test contacting structure, 2 namely contactor 12, shown partially unassembled in Figure 1, 3 comprises the solid state space transformer 13 and probe 4 assembly 20. The probe assembly comprises a plurality of - 5 probes 19 arranged in an array or pattern corresponding 6 to the pattern of test points or pads 16a on the device 7 under test 16.
8 The solid state space transformer holder 22 may 9 be constructed from aluminum with a recessed portion in which the space transformer is seated. An epoxy adhesive 11 may be employed to maintain the space transformer 12 securely in position within the recess. The probe 13 assembly 20 is secured to the memher 22 by any one of 14 a number of mechanical means, or mechanisms, known to the ~`
15 art. For example, fastening of the probe assemhly 20 to the 16 member 22 may be accomplished by diametrically disposed machine ~:
17 screws, or a suitable mechanical spring latch means.
18 Although no means is expressly shown in the drawing 19 for securing the probe assembly 20 to the member 22, which 2Q forms a backing or rigidity structure for the solid 21 state space transformer, it is to be appreciated that 22 the fastening means must provide precise alignment of ; 23 the probe assembly and solid state space transformer.
24 One suitable alignment means is precision machined dowels 17 carried by the probe assembly and mating with machined 26 openings 17a provided in the solid state space transformer .
27 housing or holder 22.
28 The conductive lands 13a carried by on the lower ~-29 planar surface of the solid state space transformer are also arranged in an array, or pattern, corresponding to 31 the array, or pattern, in which the probes 19 are arranged.
.. .. _ _ r~
12~5 1 Thus, when the contactor 12 is in an assembled state, the 2 conductive lands 13a respectively make elec~rical contact 3 wlth the spherical end portions l9a of the probes 19.
4 Thus, at the mating of the probe assembly 20 and the solid state space transformer 13 a large multiplicity 6 of densely arrayed electrical connections are made on 7 an easily separable electrical interface.
The easily separable electrical interface 9 between the probe assembly 20 and the solid state space transformer 13 comprises the electrical connection 11 of each land 13a of the space transformer with one of 12 the end portions 19a of the prohe assembly 20 as shown 13 in Figure 1.
14 In Figure 5 an enlarged cross-sectional portion of the afore-identified electrical interface is shown.
16 As is well known to persons skill~!d in the electronic 17 testing art the connection between the lands 13a and 18 the probe ends l9a must be a vary low ohmic resistance 19 connection having good wear characteristics.
As depicted in Figure 1, the electronic test 21 system includes a computer 14, tester 15 and contactor~12.
.
22 The computer 14 communicates with the contactor 12 and 23 and more specifically, the space transformer 13 via ~-24 leads Ll and with tester 1~ via leads L2. The tester 15 communicates with the contactor 12 and 26 more specifically the space transformer 13 via 27 leads L3, and with the computer system 14 via leads L2.
28 It will ~e appreciated the term computer as here employed ~
29 is generic to a computer system having input~output devices, a memory, data processin~ a~ility, etc.. The 31 tester may be any one of a number of testers known FI 9-74-027 - 18~
~' ..
- , -iL~3~ 5 l to, and available to the art. For example, the computer system may be a dedicated mini-computer or a more sizeable time shared computer. Numerous suitable computers and computer systems are known to the art and commercially available.
As will be appreciated by persons skilled in the testing art, from the detailed description of the invention hereinafter, the device under test contacting structure may be employed in a test system consisting essentially of a computer system and suitable interface circuitry interconnecting the contactor structure with l the computer system.
The practice of applicants' invention is not limited to the architecture of any particular electronic test system for testing electronic devices. An electron;c test system generally of the type disclosed in U.S. Patent No. 3,9l6,306, issued October 28, l975, to Michael J. Patti, entitled "Method and Apparatus for Testing High Circuit Density Devices" and of common assignee herewith, or generally of the type disclosed in U.S. Patent No. 3,873,8l8, issued March 25, l975 by John D. Barnard, entitled "Electronic Tester for Testing Devices having High Circuit Density", of common assignee herewith, may be employed to practice applicants' invention.
Referring to U.S. Patent No. 3,806,800, of common assignee herewith, the electronic test system may be generally of the type disclosed therein. Namely, one suitable example of the tester l5 is of the type sold ~ ' , .~
FI9-74-027 - l9 -.~ ~
1 by Fairchild Systems Technology~ Inc., Sunnyvale, California as model No.
5000. One suitable example of the computer 14 is an IBM* 1800 computer.
In summary, the tester supplies a sequence of test patterns to the space transformer. The computer allows automatic programmable se-lection of test lines to be achieved to encompass various product families and part numbers. The computer also provides data acquisition, tabulation, processing etc.
The solid-state space transformer 13 is preferably a silicon wafer containing a plurality oF interconnected integrated circuits. The solid-state space transformer has contacts thereon for the connection of leads Ll and L2 and an array of conductive lands 13a for electrically interfacing with probes 19. The solid-state space transformer is fabricated by state of the art large scale integration technique known to persons skilled in the art.
An understanding of the fabrication process for constructing the solid-state-space transformer is not nec:essary to a full understanding of, and the ability to practice the invent;on disclosed and claimed herein.
The circuitry fabricated on and within the solid-state-space transformer will now be described in detail. Referring to Figure 4, the sol;d-state transformer contains a total of four decoders. Namely, they are as labelled for convenience of explanation in Figure 4, .
*Registered Trade Mark ,S
1 "Force X Decoder", "Force Y Decoder", "~ense X Decoder", 2 and "Sense Y Decoder". Each decoder may be a binary 3 decoder adapted to receive m inputs and select one 4 out of 2m outputs. Two of the decoders, namely the "Force X Decoder", and the "Force Y Decoder"
6 provide a first matrix, herein after for convenience 7 of explanation referred to as the "Force Matrix". The 8 remaining two of the four decoders, namely, the "Sense X
9 Decoder" and "Sense Y Decoder" provide a second matrix, hereinafter for convenience of explanation referred to 11 as the "Sense Matrix". The "Sense Matrix" and "Force 12 Matrix" are equal in logical dimension. Also, the 13 selected output of the "Force X Decoder" is a logical 14 "UP" condition: the selected output of the "Force Y
Decoder" is a logical "UP" condition; the selected output 16 of the "Sense X Decoder" is a logical "DOWN" condition;
17 and the selected output of the "Sense Y Decoder is a logical 18 "DO~" condition. Thus, it ~ill be apparent the "Force"
19 and "Sense" decoder operations are logically complementary.
. 1 In Figure 4, each of the four decoders has 21 four inputs and each provides a selection of one output 22 of sixteen possible outputs. M = 4 inputs, providing 23 the ability to select one out of sixteen outputs is an - 24 arbitrary selection, chosen for convenience of ~' :
explanation. It will be appreciated the invention may be 26 practiced with m less than, or greater than four.
27 Still referring to Figure 4, the outputs of 23 the decoders are preferably discrete metalli~ed lines.
29 The output lines FXl through FX16 of the "Force X
Decoder" and the output lines SXl throu~h SX16 of the ,, ....... , .. _ -. .
1q~4~LZ~S
.
1 "Sense X Decoder" may ~re~exa~ly be fabricated on a 2 first level of metalllzation. The output lines FYl 3 through FY16 of the "Force Y Decoder" and the output 4 lines "SYl through SY16" of the "Sense Y Decoder" may 5 preferably be fabricated on a second level of metallization.
6 The circuitry fabricated on and within the solid-7 state space transformer includes a plurality of logic 8 circuits. A typical one of which is shown in Figure 2.
9 As will be fully apparent from the description that follows, each logic circuit functions under control of 11 the "Sense Matrix", and the "Force Matrix". Each logic 12 circuit is electricall~ connected to a discrete probe 19 13 of the probe assembly 20.
14 In the preferred embodiment each of the plurality of logic circuits is represented by the 16 logic circuit shown in Figure 2. The logic circuit 17 shown in Figure 2 may be considered as one of a matrix . ~ . .
~ 18 of logic circuits, where each logic circuit is interconnected . . .
~ 19 between the "Force Matrix", the "Sense Matrix" and a .
probe 19. The representative logical circuit in 21 Figure 2 is shown connected to, the output FXl of 22 the "Force X Decoder", the output FYl of the "Force Y
23 Decoder", the output SXl of the "Sense X Decoder", 24 the output SYl of the "Sense Y Decoder", and via the electrical interface (13a and l9a, see Figure 1) to a 26 discrete probe 19 of the assembly. The connèction of 27 the logical circuit of Figure 2 is representative of 28 the connection of eac'n of the plurality of logic circuits.
29 Thus, the plurality of logic circuits may be considered .
FI 9-7~-027 ~ 22 , _ . . . ... . ------ ., ., . .. , . .-- . _ .. _ ___ . . . _ . .. _ . .. _ _ 41'~25 1 to a matrix of logic circuits selectiveiy connected to 2 the "Force Matrix", the "Sense ~latrix" and the probe 3 assembly 20. In summary, each logic circuit of the 4 matrix of logic circuits is represented by the circuit of Figure 2. Each logic circuit of the matrix of 6 logic circuits has, the base of its transistor Tl 7 connected to an output of the "Fo~ce X Decoder", the 8 base of its transistor T2 connected to an output of 9 the "Force Y Decoder", the base of its ~ransistor T7 la connected to an output of the "Sense X Decoder", the 11 hase of its transistor T8 connected to an output of the 12 "Sense Y Decoder", and the collector of transistor T5, 13 together with the base of transistor T6 connected to 14 a discrete probè 19 of the probe assembly 20. Further lS as shown schematically in Figure ,', the collector of 16 transistor T9 of each of the logia circuits i5 commonly 17 connected through resistor R7 to a reference potential 18 ~ground) and to a common output terminal.
19 Thus, it will be apparent that the preferred embodiment of the invention as illustrated in the 21 drawings may have two hundred and fiftysix probes 22 each discretely controlled by a single logic circuit 23 within the matrix of logic circuits. The logical operation 24 of the circuit of Figure 2 will be fully apparent from a detailed explanation hereinafter of how any two selected 26 circuits of the logical circuit matrix are employed to 27 determine the electrical integrity of a conductive path 28 between two pads on a device under test.
29 In the following table, Table ~o. 1, the interconnection of a (16 x 16) Force Matrix, a (16 x 16) 31 Sense Matrix, a (256) logical circuit Matrix and a probe E'I 9-74-027 - 23 -1 assembly having 256 probes is tabulated. The content of Table No. 1, namely the particular numbering, and particular interconnections are not to be taken as a limitation of the invention. The content of Table No. l is illustrative, representative and a convenience in ex-planation.
TABLE N0. 1 Logical CircuitProbe Number Force Matrix Sense Matrix Number of Logical In Probe Connections Connections to Circuits in Matrix Assembly to Logical Lo~ical Circuit Circuit 1 1 FXl, FYl SYl, SXl 2 2 FX2, FYl SYl, SX2 3 3 FX3, FYl SYl, SX3 4 4 FX4, FYl SYl, SX4 ~, . ' ,, ' 14 14 FX14,FYl SYl, SX14 FX15,FYl SYl, SX15 16 16 FX16,FYl SYl, SX16 17 17 FXl, FY2 SY2, SXl 18 18 FX2, FY2 SY2, SX2 :: ::
31 31 FX15,FY2 SY2, SX15 32 32 FX16,FY2 SY2, SX16 33 33 FX 1,FY3 SY2, SX16 34 34 FX 2,FY3 SY3, SX2 .
.
. 47 47 FX15,FY3 SY3, SX15 48 48 FX16,FY3 SY3, SX16 ~ 49 49 FXl, FY4 SY4, SXl : ~50 50 FX2, FY4 SY4, SX2 :': . . . . . .
:
63 63 FX15,FY4 SY4, SX15 ; 64 64 FXl6,FY4 SY4, SX16 FXl, FY5 SY5, SXl 66 66 FX2, FY5 SY5, SX2 .
254 254 FX14,FYl6 SY16,SX14 ; 255 255 FX15,FY16 SY16,SX15 256 256 FX16,FY16 SY16,SX16 ~, 1 Each logical circuit of the matrix of logical 2 circuits may be selected to function or perform as a 3 "Force" circuit, or as a "Sense" circuit. A logical 4 circuit selected to perform as a "Force circuit"
has each of its Force inputs, FX _ and FY _, in a logical 6 UP condition, and one, or both, of its Sense inputs, SX
7 and SY _ , in an UP condition. Correspondingly, when 8 a logical circuit is selected to perform as a "Sense 9 Circuit", it has each of its Sense inputs, SX and 1~ SY in, a DOWN condition an-d one, or both, of 11 its Force inputs, FX _ _ and FY _ in a ~OWN condition.
12 Thus, for example, referring to Table No. 1, it will be 13 seen that logical circuit Number ].7 is selected to perform 14 a Force function when Force Inputs FXl and FY2 are respectively in an UP condition, cmd one, or both, of 16 the Sense inputs SY2 and SXl are i.n an UP condition.
17 Correspondingly, still referring to Table No. 1, logical 18 circuit Number 33 is selected to perform a Sense function 19 when Sense Inputs SY3 and SXl, are respectively in a 2Q DOWN condition, and one, or both, of the Force inputs FXl 21 and FY3 are in a DOWN condition. It will now be 22 apparent from the preceding description that any one ~:' 23 of the two hundred and fifty-six logical circuits 24 comprising the monolithic logical circuit matrix may be selected by the "Force Matrix" to perform a 26 "Force Function". Also, any one of the-two hundred 27 and fifty-six logical circuits comprising the monolithic 28 logical circuit matrix may be selected by the "Sense 29 Matrix" to perform a "Sense Function". ~s will be ~ 30 apparent from the further description set-forth ~-.
1C1 412~S
1 hereinafter, except for testing the logical circui~, ;
2 the same logical circuit of the logical circuit matrix 3 is not concurrently selected by the "Force Matrix" and 4 the "Sense Matrix".
In the further description of the operation of the 6 invention set forth below, it will he apparent that the 7 logical circuit performing the "F~rce Operation" and 8 the logical circuit performing the "Sense Operation"
9 are customarily discrete different ones of the plurality of logical circuits comprisiny the monolithic logical 11 circuit matrix.
12 It is to be appreciated -that with each of the 13 two hundred and fifty-six logical circuits, a discrete 1~ probe 19 of probe assembly 20 is associated and interconnected therewith. Thus, it is apparent any one of the probes 19 16 may be addressed to perform a "Force ~unction" and any 17 one, other than a probe addressed to perform a "Force 18 function" may be addressed to perform a "Sense function".
19 With reference to Figure 3, the practice of the invention, in a representative application thereof, will ~ . .
21 be explained in detail. In Figure 3, it will be seen 22 that two logical circuits of the type shown in Figure 2 23 are shown. The upper logical circuit in this illustrative 24 example is performing the "Force operation", as depicted by the legend "Force Function". In the upper 26 circuit, the Force inputs FX2 and FYl thereof are 27 respectively in an UP condition and at least one of 28 the Sense inputs, SX2 and SYl, is in an UP condition.
29 With an UP potential level on FX2 and FYl, transistors Tl ~`
1 and T2 are respectively conductive, T3 and T4 are rendered 2 non-conductive and T5 conductive. The potential at the 3 collector of conductive transistor T5 is DOWN. This 4 DOWN potential is impressed via probe #2 (See Table No. 1) of the plurality of probes 19 on a land 16a of the 6 device under test, or wafer 16, as shown in Figure 3.
7 The lower logical circuit in~this illustrative 8 example (Figure 3) has been selected to perform the "5ense 2 Operation", as depicted by the legend "Sense Function".
lQ In the lower circuit as viewed in Figure 3, Sense 11 Inputs, SX16 and SY2, thereof are respectively in a ~` 12 DOWN condition and at least one of the Force inputs, 13 FX16 and FY2, is in a DOWN condition. Transistor T5 14 of the logical circuit selected to perform the sense function, namely the lower circuit: as viewed in Figure 3 16 is non-conductive since at least one of the inpu~s FX16 17 ~nd FY2 is DOWN.
18 It will now be apparent from viewing Figure 3 ~ 19 and the immediately preceding discussion that the `l 20 following conditions may exist. (1) If the conductive 21 path under test as shown in Figure 3 is "open" (or very 22 high resistance) the base of transistor T6 in the Sense 23 circuit will be in an UP condition. The "common output 24 Terminal", connected in common to the collectors of transistors T9 and via resistor R7 to ground, will be in 26 an UP condition. (2) If the conductive path under 27 test as shown in Figure 3 is "closed" (or very low 28 resistance) the base of transistor T6 in the Sense 29 circuit will be at a DOWN condition. (Same potential as collector of conductive transistor T5 of the Force 3L~ 5 1 circuit). The "Common Output Terminal" will be DOWN.
2 In summary, when the upper logic circuit as viewed 3 in Figure 3 is selected as a "Force Circuit" and the 4 lower circuit as a "Sense Circuit" the "Common Output Terminal" will be "DOWN" if the circuit path under ;~ 6 test is "closed", and "UP" if the circuit path under j 7 test is "open". It will be appreciated that in the 8 illustrative example of operation as depic-ted in Figure 3 9 the lower circuit could have been selected as the Force . . .
circuit and the upper circuit as the Sense circuit.
11 Summary of the Solid-State Space 12 Transformer of the Preferred Embodiment 13 There are total of four decoders, two identified 14 as "Force" and two identified as "Sense". Each is a binary decoder with a number of inputs (m) that provide a greater 16 number of outputs (2m). The decoders are arranged to 17 provide two matrices, a "Force" and a ".5ense". The "X"
18 and "Y" dimensions of the "Force" matrix are equal to 19 the corresponding "X" and "Y" dimensions of the "Sense"
matrix. Metallized lines from each output of the decoders 21 run to a matrix of monolithic circuits. The "Force"
22 and "Sense" decod`er operations are logically reversed, 23 that is r the selected output of each "Force" decoder is 24 "UP" while the selected output of each "Sense" decoder is "DOWN".
26 Correspondin~ to the common dimensions of the 27 "Force" and "Sense" matrices is a matrix of monolithic 28 circuits. These circuits perform the desired "Force" or 29 "Sense" operation determined by the decoders. Since only one output of each "Force" decoder can be at an 31 "UP" level, only one monolithic circuit in the matrix _.. ....
' 1~412i~5 l can be selected to perform a "Force" function at any 2 given time. Likewise, since only one output of each 3 "Sense" decoder can be at a "DOWN" level, only one 4 monolithic circuit in the matrix can be selected to perform a "Sense" function at any given time.
6 ~ monolithic circuit is selected to perform a 7 "Force" function when both Force Inputs thereof namely 8 "FX _ " and "FY _ " are "UP". It is selected to 9 perform a "Sense" function when both Sense Inputs l~ thereof "SX _ " and "SY " are "DOWN". The outputs of 11 the monolithic circuits are dotted together through , 12 metallized lands and connected to a resistor. The output 13 at the resistor is "DOWN", if, and only if, a short exists ~4 between the monolithic circuit selected as "Force"
and the monolithic circuit selected as "Sense". The 16 output at the resistor is "UP" if, and only if, an open 17 exists between the monolithic circuit selected as "Force"
18 and the monolithic circuit selected as "Sense".
19 It is to be appreciated that the practice of the 2a invention may vary in form and structure without departing 21 from the spirit of the invention.
22 For example, the solid state transformer may with 23 appropriated designed circuitry fabricated therein provide 24 inputs, and accept outputs from integrated circuit devices, such as a logical devices, under test.
26 The solid state space transformer may wit'n appropriately 27 designed circuitry fabricated therein be employed 28 advantageously in the testing of integrated circuit devices 29 fabricated by large scale integration techniques and containing combinatorial and sequential logic.
FI 9~74-027 - 29~-~;.
3L~4~ 5 l The solid state space transformer has the capability to electrically switch the testing to any two points on a closely spaced grid pattern.
The solid state space trans~ormer may be employed with an array of probes utilized to contact test pads on a device under test where the pads on the device under test are spaced one from another on a 0.25 millimeter grid or less.
The solid state space transformer may be employed to test the interconnection between chip islands on an undiced wafer.
The solid state space transformer may be employed to test the interconnections within a Multi-Layer-Ceramic structure.
It is to be appreciated that test systems (AC and DC) may be designed where the solid state, preferably silicon, space transformer is fabricated to contain monolithic circuits for providing pulses o~ proper rise time, shape and level for application t~ a device under test.
While the invention has been described and shown particularly with reference to one of its preferred embodlments, it will be understood by those skilled in the art to which the work is directed that various changes in form and detail may be made withowt departing from either the 2~ spirit or scope of the invention.
Claims (5)
1. A space transformer for use in an electronic test system for testing micro-miniature electronic devices, said space transformer comprising:
a monolithic silicon structure;
said silicon structure containing, a first binary decoder cir-cuit adapted to receive a first set of m binary inputs and provide a first set of 2m binary outputs, a second binary decoder circuit adapted to receive a second set of m binary inputs and provide a second set of 2m binary outputs, a third binary decoder circuit adapted to receive a third set of m binary inputs and provide a third set of 2m binary outputs, a fourth binary decoder circuit adapted to receive a fourth set of m binary inputs and provide a fourth set of 2m binary outputs, where m may be any integer number, a plurality of logic circuits selectively connected to said outputs of said first, second, third and fourth binary decoders, an array of exposed conduc-tive pads connected to said plurality of logic circuits.
a monolithic silicon structure;
said silicon structure containing, a first binary decoder cir-cuit adapted to receive a first set of m binary inputs and provide a first set of 2m binary outputs, a second binary decoder circuit adapted to receive a second set of m binary inputs and provide a second set of 2m binary outputs, a third binary decoder circuit adapted to receive a third set of m binary inputs and provide a third set of 2m binary outputs, a fourth binary decoder circuit adapted to receive a fourth set of m binary inputs and provide a fourth set of 2m binary outputs, where m may be any integer number, a plurality of logic circuits selectively connected to said outputs of said first, second, third and fourth binary decoders, an array of exposed conduc-tive pads connected to said plurality of logic circuits.
2. A space transformer for use in an electronic test system for testing micro-miniature electronic devices as recited in claim 1 further characterized in that said plurality of logic circuits is equal in number of m2.
3. A space transformer for use in an electronic test system for testing micro-miniature electronic devices as recited in claim 2 fur-ther characterized in that each of said m2 logic circuits is connected to a discrete output of each of said first, second third and fourth binary decoders, whereby each of said m2 logic circuits is uniquely connected to said first, second, third and fourth binary decoders, whereby said first, second, third and fourth sets of m binary inputs may be employed to select and condition a predetermined first and second ones of said m2 logic circuits.
4. A space transformer for use in an electronic test system for testing micro-miniature electronic devices as recited in claim 3 wherein each of said m2 logic circuits is essentially identical to each other one of said m2 logic circuits and said predetermined first one of said m2 logic circuits is adapted to perform a first function and said predetermined second one of said m2 logic circuits is adapted to perform a second function.
5. In an electronic test system for electrically testing very small electronic structures, a contactor structure for making electrical contact with an electrical structure undergoing test, said contactor comprising:
a space transformer as recited in claim 4, a probe assembly electrically and mechanically mated with said contactor structure, said probe assembly having a plurality of probes each of said probes being in electrical contact with one of said array of exposed conductive pads of said space transformer.
a space transformer as recited in claim 4, a probe assembly electrically and mechanically mated with said contactor structure, said probe assembly having a plurality of probes each of said probes being in electrical contact with one of said array of exposed conductive pads of said space transformer.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/537,514 US4038599A (en) | 1974-12-30 | 1974-12-30 | High density wafer contacting and test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1041225A true CA1041225A (en) | 1978-10-24 |
Family
ID=24142962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA239,720A Expired CA1041225A (en) | 1974-12-30 | 1975-11-14 | High density wafer contacting and test system |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4038599A (en) |
| JP (1) | JPS5423226B2 (en) |
| CA (1) | CA1041225A (en) |
| DE (1) | DE2557621C2 (en) |
| FR (1) | FR2296854A1 (en) |
| GB (1) | GB1498719A (en) |
| IT (1) | IT1049489B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3246240A (en) * | 1962-05-09 | 1966-04-12 | Ibm | System and method for electrical analysis of network interconnections |
| US3835381A (en) * | 1969-02-14 | 1974-09-10 | Tieco Inc | Probe card including a multiplicity of probe contacts and methods of making |
| US3590369A (en) * | 1969-02-14 | 1971-06-29 | British Aircraft Corp Ltd | Switching means for automatic testing equipment |
| US3731191A (en) * | 1969-12-22 | 1973-05-01 | Ibm | Micro-miniature probe assembly |
| GB1386092A (en) * | 1971-04-20 | 1975-03-05 | Plessey Co Ltd | Electrical testing apparatus |
| JPS4840670A (en) * | 1971-09-30 | 1973-06-14 | ||
| US3815025A (en) * | 1971-10-18 | 1974-06-04 | Ibm | Large-scale integrated circuit testing structure |
| US3806800A (en) * | 1972-12-26 | 1974-04-23 | Ibm | Method and apparatus for determining the location of electrically conductive members on a structure |
| US3806801A (en) * | 1972-12-26 | 1974-04-23 | Ibm | Probe contactor having buckling beam probes |
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| US3963986A (en) * | 1975-02-10 | 1976-06-15 | International Business Machines Corporation | Programmable interface contactor structure |
-
1974
- 1974-12-30 US US05/537,514 patent/US4038599A/en not_active Expired - Lifetime
-
1975
- 1975-10-29 FR FR7533879A patent/FR2296854A1/en active Granted
- 1975-11-14 CA CA239,720A patent/CA1041225A/en not_active Expired
- 1975-11-18 IT IT29371/75A patent/IT1049489B/en active
- 1975-12-02 JP JP14246675A patent/JPS5423226B2/ja not_active Expired
- 1975-12-02 GB GB49365/75A patent/GB1498719A/en not_active Expired
- 1975-12-20 DE DE2557621A patent/DE2557621C2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2557621C2 (en) | 1986-12-18 |
| FR2296854B1 (en) | 1978-05-12 |
| JPS5423226B2 (en) | 1979-08-11 |
| US4038599A (en) | 1977-07-26 |
| DE2557621A1 (en) | 1976-07-08 |
| FR2296854A1 (en) | 1976-07-30 |
| JPS5178990A (en) | 1976-07-09 |
| GB1498719A (en) | 1978-01-25 |
| IT1049489B (en) | 1981-01-20 |
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