CA1041615A - Multiple phase clock generator - Google Patents
Multiple phase clock generatorInfo
- Publication number
- CA1041615A CA1041615A CA249,019A CA249019A CA1041615A CA 1041615 A CA1041615 A CA 1041615A CA 249019 A CA249019 A CA 249019A CA 1041615 A CA1041615 A CA 1041615A
- Authority
- CA
- Canada
- Prior art keywords
- clock
- amplifier
- phase
- pulse
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
- H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping
Abstract
MULTIPLE PHASE CLOCK GENERATOR
ABSTRACT OF THE DISCLOSURE
A two phase clock signal with separation between the two phases is produced from a single phase clock. Two complementary input signals are derived from the single phase clock and are transferred by separate transfer gates to individual push/pull amplifiers. Each gated input sig-nal is applied to the first input of one of the amplifiers while the complementary input signals are connected directly to the second input of the amplifiers. The output of each push/pull amplifier is one of the clock phases, and each is also applied to a sensing circuit. The sensing circuit produces delayed outputs which are cross-coupled to con-trol the transfer gate associated with the other output phase. By judicious selection of the parameters of the sensing circuit, the time and speed of "turn-on" for each transfer gate can be controlled. Accordingly, the separa-tion between the two clock phases as well as the shape of each can be selected.
ABSTRACT OF THE DISCLOSURE
A two phase clock signal with separation between the two phases is produced from a single phase clock. Two complementary input signals are derived from the single phase clock and are transferred by separate transfer gates to individual push/pull amplifiers. Each gated input sig-nal is applied to the first input of one of the amplifiers while the complementary input signals are connected directly to the second input of the amplifiers. The output of each push/pull amplifier is one of the clock phases, and each is also applied to a sensing circuit. The sensing circuit produces delayed outputs which are cross-coupled to con-trol the transfer gate associated with the other output phase. By judicious selection of the parameters of the sensing circuit, the time and speed of "turn-on" for each transfer gate can be controlled. Accordingly, the separa-tion between the two clock phases as well as the shape of each can be selected.
Description
Alvarc~ 1 ~L0~L6~15 1EACK~ROUND 0~ THE INVENTION_ 2Thls lnvention relates to electronic tlmlng circuits 3 and particularly to multlple phase clock slgnal generators.
4 More ~pecifically, it relate~ to ~uch generator~ which pro-vide ad~ustable spacing between the multlple phase clock 6 slgnals~
7Electronic logic circuits require accurate tlming 8 ln~ormation and ln many application~ a number Or clock sig-9 nal~ having interdapendent relation~hlps are necessary, As it ha~ been ~ound generally pre~erable to deri~e the~e mul-11 tiple clock signalsJ or multiple phase clock slgnals, from 12 a common source, clock circuit~ have been designed to oper-13 ate upon a single clock input (generated by an external or 14internal os~illator) to produce thererrom the multlple ; ;~
clo~k ~lgnals having the desired pha~al relationship.
16The prior art is replete w.Lth multlple phase 17lo¢k ~ircuit~. For example, in U. S. patent 3,735,277, ~18~ls~ued May 22~ 1973, to Mr. F. M. Wanla~, two-blt shlft I9 regl~ter~ are used to pro~ide four distinct and overlapping ~olook pulses. In many cases~ however, it is deslrable to 21 have multlple phase clock si~nal~ which do not overlap in 22 time. One ~uch circult3 whlch provides nonoverlapping 23 mulkiple pha~e clo¢k signals9 i~ ~hown in U. S. Patent 24 ~39668,436, i~sued June 6, 1972, to S. H. Ba~on. In that -25~ ~ir~uit a pa~r o~ complementary logic slgnals i9 provided 26 by an osclllator, One signal is gated to each o~ two amplifier~
27 and the output o~ each ampli~ier is used to dlrectly control the 28 gatlng to the other amplifier~ The gating 1~ arranged RO that 29 an output from one amplirier ls prevented by groundl~g its lnput whenever the other ampllrier 1~ producing an output.
4 More ~pecifically, it relate~ to ~uch generator~ which pro-vide ad~ustable spacing between the multlple phase clock 6 slgnals~
7Electronic logic circuits require accurate tlming 8 ln~ormation and ln many application~ a number Or clock sig-9 nal~ having interdapendent relation~hlps are necessary, As it ha~ been ~ound generally pre~erable to deri~e the~e mul-11 tiple clock signalsJ or multiple phase clock slgnals, from 12 a common source, clock circuit~ have been designed to oper-13 ate upon a single clock input (generated by an external or 14internal os~illator) to produce thererrom the multlple ; ;~
clo~k ~lgnals having the desired pha~al relationship.
16The prior art is replete w.Lth multlple phase 17lo¢k ~ircuit~. For example, in U. S. patent 3,735,277, ~18~ls~ued May 22~ 1973, to Mr. F. M. Wanla~, two-blt shlft I9 regl~ter~ are used to pro~ide four distinct and overlapping ~olook pulses. In many cases~ however, it is deslrable to 21 have multlple phase clock si~nal~ which do not overlap in 22 time. One ~uch circult3 whlch provides nonoverlapping 23 mulkiple pha~e clo¢k signals9 i~ ~hown in U. S. Patent 24 ~39668,436, i~sued June 6, 1972, to S. H. Ba~on. In that -25~ ~ir~uit a pa~r o~ complementary logic slgnals i9 provided 26 by an osclllator, One signal is gated to each o~ two amplifier~
27 and the output o~ each ampli~ier is used to dlrectly control the 28 gatlng to the other amplifier~ The gating 1~ arranged RO that 29 an output from one amplirier ls prevented by groundl~g its lnput whenever the other ampllrier 1~ producing an output.
-2-J
Alvarez 1 lS
1 Hence9 the ampll~ler which would normslly begln to operate 2 ~o~ turn ON) 15 maintained in an OFF state as long a~ the
Alvarez 1 lS
1 Hence9 the ampll~ler which would normslly begln to operate 2 ~o~ turn ON) 15 maintained in an OFF state as long a~ the
3 gating ~ignal ~rom the other ampll~ier cau~es it~ input
4 to be grounded. This arrangement prevent~ ~lmultaneous productlon o~ clock pulse~ ~rom both ampli~iers and there-6 ~ore ln~ure~ that no ~ignl~lcant overlap will occur between 7 the multiple phase output 6ignals. However, lt doe~ not 8 provlde separatlon between the pha~e~, and a de~ined ~pacing 9 between clock pha~e~ i9, 0~ cour~e, u~eful ~n many applica-tlon~. In addition~ an inherent e~ect o~ groundlng the 11 lnput i3 to create a large power dls~lpation when the ampli~ier 12 i8 m2intalned OFF, and ~ince reduced power conhumption i8 a 13 ~enerally deslrable gOal9 this is an unattracti~e aspeck o~
14 the ~ircuit.
Accordlngl~, it i8 an obJec,tlve of the pre ent 16 lnventlon to provlde an improved multlple pha~e clock circuit.
17 It i~ a partlcular obJect o~ the inventlon to 18 provlde a mul~ple phase clock circult whlch produc~s mul-19 tiple clock phase~ ~eparated by de~lned and selectable time inte~vals.
21 It i~ al~o an obJect of the inven~ion to proYlde ~: -2~ a multlple phase circuit whlch avold~ unnece~sary power ;~
23 di~ipation.
24 It i~ a further ob~ect to provlde a multiple phase ¢lock circuit ~hich permits control o~ the rlse ~-nd 26 rall characteri~tics of the multiple elock pha~e3.
27 It ~s an addltional obJe~t to provide a multiple 28 pha~e clock clrcuit which provides more than two clock 29 pha~s. `~
Alvarez 1 ~4~6~5 2 In accordance with the invention/ a two-phase 3 output clock signal with separatlon between the two phases 4 is produced ~rom a single phase clock pulse train provided
14 the ~ircuit.
Accordlngl~, it i8 an obJec,tlve of the pre ent 16 lnventlon to provlde an improved multlple pha~e clock circuit.
17 It i~ a partlcular obJect o~ the inventlon to 18 provlde a mul~ple phase clock circult whlch produc~s mul-19 tiple clock phase~ ~eparated by de~lned and selectable time inte~vals.
21 It i~ al~o an obJect of the inven~ion to proYlde ~: -2~ a multlple phase circuit whlch avold~ unnece~sary power ;~
23 di~ipation.
24 It i~ a further ob~ect to provlde a multiple phase ¢lock circuit ~hich permits control o~ the rlse ~-nd 26 rall characteri~tics of the multiple elock pha~e3.
27 It ~s an addltional obJe~t to provide a multiple 28 pha~e clock clrcuit which provides more than two clock 29 pha~s. `~
Alvarez 1 ~4~6~5 2 In accordance with the invention/ a two-phase 3 output clock signal with separatlon between the two phases 4 is produced ~rom a single phase clock pulse train provided
5 by an osclllator source. Two complementary input signals
6 are derived ~rom this single phase clock pulse train and
7 are trans~erred via separate transfer gates to individual
8 push/pull amplifiers. The gated input signals are applied
9 to a ~irst input of each ampll~ier and the complementary input signals are connected directly to the second inputs, 11 The output o~ each push/pull amplifier is a bilevel pulse 12 train which is one of the output clock phases. ~ ~ -13 A~ least one ampli~ier output is also applied 14 to a sensing clrcuit, whioh introduces a defined delayJ
and the dela~ed output from the sensing circuit is cross-16 coupled to control the transfer gate associated with the 17 other output phase. By ~udicious selection o~ the parameters 18 o~ the sensing circuits, the time and speed of "turn-ON" ~or 19 the transfer gate can be controlled. Accordingly, the time between one phase and the other can be controlledO Where 21 two sen~ing circuits are used the separation between the 22 pulses of ~he ~wo clock phasss, as well as the shape of 23 each pulse, can be selectedO `
2~ The dou~le coupling to each amplifier in con~unction with th transfer gates avoids the power dissipation common in 26 the prlor art, since the ampli~iers are normally OFF and the 27 ¢ross-coupled gate control is used to turn the ampli~ier ON
28 only when the clock phase is to be produced, 29 The multiple phase clock generator can be embodied using any approprlate ~abrication technique~ In addition 31 the trans~er gates, double-coupled ampli~iers and sensing 32 circults can be provided by numerous current configurations.
. .. ~ .
~ O 4 ~ ~ 5 As an example clrcuits using metal-o~lde-~emlconductor-~ield-errect translstor~, hereina~ter re~erred to as MOSFETs, is shown. In one particular embodiment, the ~enslng olrcuit~
consl~t o~ a ~erle~ Or bootstrap lnverters; each tran~rer gat0 1~ ~lmply a ~lngle MOSF~l wlth a cro~s-coupled ~eed-back ~lgnal applied ~rom the other sensing circult to it~
gate3 and the push/pull ampll~ler~ are boot~trap "lnverter~
with the direct coupled input applied to the gate o~ the pull-down MOSFET and the lnput ~rom the trans~er gate being applled to the gate Or the load or pull-up MOSFET, ~ ;
Since the spacing between the pulse~ o~ the two :-.
clock phase~ can be controlled, the s0paration between them can be made large enough ~or the insertlon o~ an addi-tional third clock phase with its pulses occurrlng durlng the time both of the two prlmary phase~ are OFF; i.e., between pul~es. The generation o~ a thLrd clock phase can be provided simply by the addltion Or a NOR-gate to detect when the first and second phases are OFF, an inYerter to generate the complement o~ the NOR-gate output~ and a 2~ push/pull amplifier to produce the thlrd clock phase inter-mediate 'co the ~ir~t two~, Wlth approprlate cirouitry, spacing ~or a rourth~ th, sixth, etc. clock phase can ~ :
be provided, and thus, theoreticallyD the space bet~een pulse~ o~ any two clock phases can be ~illed wlth the pulse~
of a~other additlonal clock phaseO
In accordance with one aspect of the present invention there is provided a multiple-phase clock generator circuit for providing at least two clock phases, each consisting of an individual pulse train comprising:
-~A ~ - 5 ~
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means for produclng a ~irst lnput pulse train at a ~irst node and a second input pulse tr~in at a second node, the first and second input pulse trains being complemen~ary;
rirst amplifier means for produclng one o~ the clock phases;
first connection means for coupling the first and ~econd nodes to the first amplifier means;
the first amplifier means being turned on to start a pulse of the one clock phase when a pulse from the ~irst lo input pulse train is coupled to the first amplifier means, and the first amplifier mean~ being turned o~f to end the pulse of the one clock phase when a pul~e from the second input pulse train is coupled to the first amplifier means;
second ampll~ier means ~or producing another o~ the clock phases;
second connection means for coupling the first and second nodes to the second amplifier means;
the second amplifier means being turned on to start a pulse of the other clock phase when a pulse from the second ~nput pulse train is coupled to the second ampli~ier meansJ and the second amplifier means being turned o~f to end the pulse o~ the other clock phase when a pulse from the first input pulse traln i~ coupled to the second amplifier means;
feedback means ~or producing from the other clock phase at the output o~ the second ampli~ier means, a first con-trol pulse train whose pulses are delayed by a fir~k ;~
selected time from the end of the corresponding pulses of the other clock phase; and said first connection means including means responsive `
to the control pulse train for coupling the first input pulse ' .
5 a -~ - , . . .
, ~0416~5;
train at the fi~st node to the first ~mplifier means only ~uring the occurrence o~ the pulse of the first control pulse train;
whereby a p~lse of the one clock phase will begin only the ~irst preselected time a~ter a pulse of the other clock phase has ended.
In accordance with another aspect of the present invention there is provided a multiple phase clock. ~-generator circuit for producing at le~st two spaced apart ;
0 clock phases comprising:
means for generating ~n input pulse train and a complementary pulse train which is a logical complement of the input pulse train;
a first amplifier and a second amplifier, each having two inputs and each producing one of the clock phases at its output;
first conductive means for directly coupling the ~ ~
complementary pulse train to one input of the first amplifier; ~ .
second conductive means for directly coupling the input ;~ ~.
pulse train to one input of the second amplifier; `~
first gatlng means for applying the input pulse train to .
the second input of the first amplifier in response to a first control signal; . :~
second gating means for applying the complementary pulse .`~
.
train to a second input of the second amplifer in response to a second control slgnal; i.
first feedback means for monitoring the output of the first ~ :
amplifier and producing the second control signal to which the .
second gating means responds, said first feedback means includ~
ing means for delaying the output of the first amplifier; and second feedback means for monitoring the output of the second amplifier and providing the first control signal to which ' . ' f~ ~ - Sb -~ . . . .. . . . . . . . .
~L~4~L~;1S
the first gating means responds, said second feedback means including means for delaying the output of the second amplifier;
whereby specified spacings are provided between the pulses of one of the clock phases and the pulses of the other of the clock phases.
BRIEF DESCRIPTION OF THE DRAWINGS
In drawings which illustrate embodiments of the invention:
FIG. 1 is a block diagram illustrative of a two phase clock circuit in accordance with the present invention.
FIG. 2 iS a timing diagram illustrative of the :`
operation of the circuit of FIG. 1. ~
' ::
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. . . .. . ~., . . . ~
f Alvareæ 1 ~ `
1~416~S
1 FI~. 3 i~ a ~chem~tic diagram o~ a multiple pha~e 2 clock clrcult in accordance wlth the pre~ent inventlon, 3 FIG. 4 1~ a schematic diagram ~howlng an intermediate 4 clock pha~e circuit suitable ~or u~e with the two phase clock circult o~ FI~. 30 6 FI~, 5 1~ a timlng diagram helpful in describing 7 the operation o~ the circult of FI~. 4.
9 The block diagram o~ FI~. 1 illustrates the baslc elemen~ Or a two-p~as~ clock circult which provide~ ~wo ~ .
11 independently controllable clock phases 01 and 0~ ~or applica- j :
12 tion to ~eparate l~ad~ 14 and 24, re3pecti~ely, ~hown, ~or 13 example~ as capa¢itive l~ads. An o~lllator 10 produce~ :
14 two output~ ~N and ~IN whlch are ¢omplementary pul~e tralns as ~hown in FIG. 2A. One output o~ the osclllator 10~ ~ -16 ~ , 1~ directly coupled to an lnput Al_l o~ a rlr~t 17 ampli~ier 11. Thl~ lnput provide~ a path to dls¢harge 18 the output, 01. ~ the ~irst ampllrler 11 to a low or reference : :
lg~ level (no pulee; ~hown a~ ~round in the timing dla~ram o~
FIa. 2F) whenever this input i~ at a high level9 (pul~e 21 pre~ent; ~V ~n the timing diagram or FI~. 2C~. The out-22 put, 01> ~ the first ampli~ler 11 is allowed to rl~e to 23 the high level only wh~n there exist~ a hlgh level enable 24 puls~ at the other input Al-2 to ampli~ier 11 (~ee FI~. 2B), ~ Thl~ hl~h level at the A1N2 input i8 produced by the AND
26 trans~er gate 12 only when itY inputs (the output ~SI from 27 a rirst delay circuit 13 and the other output, 0IN~ ~
28 osclllator 10) are high. Hence the ~l clock pulse i8 turned 29 oN (pulse begin~) when a pulse o~ the 0IN output ~rom os¢lllator 10 i8 passed to the ampli~ier 11 in respon~e 31 to a pulse ~rom circuit 13.
.. .. ..
, -, . . .. .
. , ~ , - .
Alvarez 1 1 The ~irst d~lay clrcuit 13 i8 part Or a ~eedback 2 pakh ~rom the output o~ a second ampllrler 21 to the trans-3 ~er gate 12. The lnput to the first delay circult 13 i~
4 thuæ the output clock signal 02 and thi~ i~ delayed9 and loglcally ln~erted to produce a control output ~Sl- ThU50 6 a de~ined interval after ~2 goe~ low (ground), the ~Sl 7 control ~lgnal exhiblt~ a high level pulse whlchj when 8 ooincldent with the high level pul~e o~ the other comple-9 mentary pul~e kraln ~IN at khe output of the o~cillator 10 cau~es AND tran~er gate 12 to produce the enable pulse at 11 the input Al-2 of the ~lr~t ampll~ier ll o The amount o~
12 the delay and in addltlon, the ri~e tlme o~ the control 13 signal 0Sl therefore determine the turn-on characteri~tl¢s 14 o~ the output clock pha~e 01~ and the~e characteristlcs can be adJu~ted by choosing approprl.ate parameters within 16 the delay circuit 13. The ~l clock pha~e turns O~F (pul~e 17 end~) in respon~e to a change in the level Or the ~N out- :
18 put ~rom o~cillator 10 (and hence an equiYalent change in : l9 the ~tate o~ the output ~
Th~ ~econd hal~ Or khe clrcuit lncludes identical 21 elemsnt~ and works ln the same ~ er to produce the other 22 clock phase 02~ The oscillator outputs 0IN and ~ are, 23 o~ cour3e~ connected in reverse order to the second ampli~ier 21 ~ -24 and the gate 22; the feedback to the second delay circult 23 i~
the clock pul~e ~l ~rom the output o~ the first ampli~ ll, 26 ~ ln~tead o~ khe clock pha~e 02~ and the control output 0S2 is 27 applied to gate 22. The 0IN ~ignal applied to one lnput A2 28 o~ the ampli~ler 21 (FIa. 2D) provides a path to dl~charge ~ ~
29 clock ~ignal 02 to the low level (no pulse shown a~ ground - :
in FI~. 2~) whenever 0IN 13 hlgh. The delayed output Or .
Alvarez 1 ~ 0~ ,5 the delay ¢lrcult 23 provldes a high level pulse (J2ls2 in 2 FIa~o 2I) a rlxed interval a~ clo~k pha~e 02 ~FIG, 2~) 3 ~oe~ low. The coincidence Or a hlgh 0S2 ~ignal and a high 4 ~ ~lgnal applied to the AND tran~f`er gate 22 produce~ a 5 hlgh level pul~e at the lnput A2-2 c~ the amplirier 21, 6 q~h~9 in turn, cause~ a hlgh state o~ output cloc~ si~snal 02 7 at the ampll~ier output~ The characteri~tics (delay and 8 rise tl~ae ) of the control sign~l ~2 are, o~ cour~e, adJu~t-9 able by varlatlon o~ the parameter~ within the delay circuit 230 Thu~ a ~ pul~e ~-V in FI~. 2G~ is produced 11 only when ~ ls hlgh and coincldentally 01 ha~ been low 12 ~or a de~lned delay time, deslgnated tl_2o SimilarlyJ 01 13 can e~hiblt a pul~e (-V in FIG. 2F) only when ~IN i9 high 14 and aolncidentally ~2 (the other output clock) ha~ been ~ :
15 low for a derined delay time~ deslgn~.ted t2_1~ which may 16 be dir~erent from tl_2. Accordln~ly, the pul~e~ o~ the ~ ~ .
17 two output clock signals ~ and 02 c~nnot overlap in tlme 18 and ~helr spacing can b~ indlv~dua~ly controll~d by parameter 19 variation~ especially in the delay circuit~ 13 and 23.
~ .. . .
20 ~ In FI~S~ 2H and 2I the de~ignationa trl and tr2 " ~
21 repre~ent, re~pectively, the rise time ~ 0$1~ and the : ~ :
rl~e ~ti~e ~ 0'S2~ S~nce 0'Sl and ~S2~ the output~ Or the 23 delay circuits 13 and 239 re~pectively, trigger th~ rise 24 o~ the ampli~ler output~ the parameters of the delay circuits 13 and 23 control the ri~e time~ o~ the clock signals 01 and 02J and 26 the ri~e tlm~ ~ 01 and 02 are dependent upon trl and tr2, 27 respeotively. The ~all time~ ~ 0'1 and 02 are controlled 28 by the lnput clock ~ignal ~IN and its complement ~ and 29 by the parameter~ o~ power ampll~ier~ lI and 21 respe¢tlvely.
l~he delay between the end o~ a 0'2 pul~e (when 31 ~2 reaohes ground in FI~. 2~) and the beginnlng o~ a 01 32 pulse (~hen 01~ ~tarts to go toward -V in FIG. 2~ design~ted ~. . . , . . - ..
.. , ,, . ~', : . , . :
. . .
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t2_1, and the delay between th~ rall of ~1 and the rlse ~ ~2 is deslgnated t1~2J as shown in FI~. 2~ and lndlcated 3 hereinberore.
4 Whlle the multiple pha~e clock circult can be 5 embodi2d uslng numerous alternatlve technologle includ-6 ing vacuum tube~3 bipolar tran~istors, etc., FI~. 3 illustrates 7 an embodlmenk o~ a two-phase cir¢uit u~lng MCS~ETs or field-8 errect translstors o~ the metal-oxlde-semlconductor type.
9 It 1~ as~um~d that these are o~ the p-channel enhancem~nt mod~ typeJ but the circuit may al~o be constructed uslng 11 other types o~ MOSFET8J lncludlng depletion mode p-ohannel 12 devices, and n-channel devices o~ either the enhancement 13 or depletion variety.
14 The complementary input 3ignals ~N and ~rN, which are applied to nodes A and B, respectively, can be 16 provided by an external oscillator. Although there are 17 num~rou3 pos~lble arrangements for generatlng these com-18 plem~ntary slgnals, lt is assumed rOr purpose Or illustratlon ~-`
19 in FIa. 3 that a generator~ not shown, produces a ¢lock signal ~0. This i~ applied to the ~ driver 30, a con-21 ~entlonal bootstrap inverter, whi¢h produces ~ at node B.
22 ~ In addition, ~ i9 used to drive another inverter, the ~ : :
23 driver 40, whlch produces 0IN for application to node A
24 As is ~hown, by way o~ example, MOSFETs Ql, ~2, and Q3, 25 and capacltor Cl ~orm the bootstrap lnverter whlch is~the 26 driver 30. -:~
27 In additlon to logically inverting 00 to create -~
28 ~ , this driver circuit also establishq~ the two level~
29 of the ~ pulse train. In general~ these levels are referred to a~ high and low. For p-ohannel MOSP$T circuits, V8S~
,. . . ..
'". ".
Alvarez 1 4:1L6~LS ~ -1 de~in~d a~ the mo~t posltlve voltage level supplled to 2 the chip, 19 the low level; and hereln 0 volts has been 3 arbltrarily chosen a~ this low or reference level~ The 4 negatlve dc supply voltage de3i~nated -VDD 18 the hlgh 5 level, In conformit~ with the~e de~lnltions, and the designa-6 tions used in FI~. 2, negatlve voltage~ great~r than threshold 7 are herein de~l~nated -V and referred to a~ high voltages and 8 voltages approaching VSs (de~lgnated ground) are re~erred to 9 a~ low voltages. Accordlngly, hlgher or increa~lng voltag~
mean those of lncreaslng magnltud~ ln negative dlre~tlonO -11 Where boot~trapping i~ employed -Y will, in most cases, be 12 the ~upply volta~e -VDD.
13 The other boot~trap inverter whlch form~ drlver 40 14 con~i~ts o~ MOS~ Q4~ Q5, and Q6 and capacltor C2. It fu~¢tlon~ identically to produce ~IN ~the complement of 16 ~ ) with similar levels Or -VDD and gro~nd. Ina~much 17 as drlver~ 30 and 40 operate in a conventional manner, 18 no ~urther dl~cusslon of their clrcuitry nor operation 19 1~ required.
Node B ls connected to one input oP a pus~/pull 21 ampllfier 41. This ampllfler consl~t~ Or a pull~up to 22 -VDD MOSFET Q99 a pull down to Ys5 MOSFET Q10, and ¢apacltor C3.
23 ~he drain~ource paths of MOSFETs Q9 and Q10 are serially con-24 nec~ed between a dc ~uppl~ voltage ~VDD and ground and the ~
capacitor C3 connect~ the intermedlate point~ node D~ to ~: :
26 the gate of MOS~ET Q9, node C. The gate of Q10 i~ cormected 27 to node B, and when the voltage at node B goes low ~ i8 28 zero ln FIG. 2A) the path to ground provlded by MOSFE~ Q10 29 is turned OFF.
Since the voltage at node A is the loglcal complement 31 o~ the voltage at node B, thls voltage at node A begins to ri se 32 when the node B voltage goes low, and the hlgh voltage at " ~
.,., .. ... ,, . ".
, : :, . . .. ....
Alvareæ
S
1 node A i tran~erred to node C under the control Or trans~er 2 gate 42. Thi~ gate 42 con~lst~ o~ a ~ingle MOSFET Q7, who~e 3 draln-source path conneots nodes A and C. m u~ the hlgh 4 voltage node A will be tran~ferred to node C i~ MOS~ Q7 1~ ON. The ~tate Or the M~SFET Q7 is, in turn, determlned 6 ~y ~he ~oltage applied to lts gate rrom ~en~ing circuit 43 7 as will be descrlbed hereinarter.
8 Assumi~g that Q7 i8 turn~d ON, the vol~age at 9 node C will ~tart to rlse, and ~ince node C ls the gate o~ pull~up M06Fh~ Q9, Qg wlll turn ON9 causing the voltage 11 at node D to rl~e toward -VDD. Th~ lar~e capacl~ance on 12 point D, however, cau~es it to charge much more 810wly ~ .
13 than point C, and, thu9, a~ the voltage at poln~ D ri~es, 14 it boo~t3 up the voltage at node C through capacitor C3 :;.
~o a level much greater than the ~upply voltage -VDD.
16 ~he volkage at point D i9 the ~ir~t output phase ~1~ Thu~, 17 when the voltage at node A i~ high and ~imultaneously the 18 gate 42 i~ oonductlng the voltage r~Om node A to the amplifier 19 ~tage 41, (as determined by the output of the sen~lng clrcuit 43), .
a 01 pul~e will be produced at node D, the output o~ the ~ -21 ampli~ier 41. ~- ~
22 The other part o~ the oircuit, consl~tlng o~ : :
2~ a transrer gate 32 (M~SFET Q8)D an ampli~ier 31 (pull-up 24 -MOSF~T Qll, pull-down MOSPET Q12 and capacitor C43, and a ae~ing cirGuit 33J is a duplioate o~ the part consist-26 ing o~ the element~ 42, 41 and 43, and lt produces 02 at 27 node F ln the same way that 01 is produced at node D. ~!
28 Thu~ a 02 pulse will appear whenever the voltage at nod2 B
29 rises and 1~ gated by trans~er gate 32 in response to a :~
reedback slgnal from sensing circuit 33.
~ ,, , . , ~,, - . . . . .
. ., :
.
Alvarez 1 -~L~4~6~S
1 The operation described above ~or producing ~1 and 2 assumes ~hat transfer gates 42 and 32 are ON. If the gates ~2 3 and 32 are 0~, their respectlve amplifi2rs 41 and 31 are OFF
4 and an OFF ampli~ier produces no output pulse. Of course, g~tes 42 and 32 are never ON concurrently. When it is ON, 6 MOSFET Q7 (gate 42) turns M~SFET Q9 of the ampli~ier 41 ON and 7 OFF in accordance with the voltage at node A; but MOSFET Q9 is - -8 never ON concurrently wlth MOSFET Q10, whlch discharges (or 9 turns OFF) the ampll~ier 41 when it is ON. There~ore, no dc power is dissipated when the ou~put o~ the amplifier 41 is 11 being prevented. MoSFETs Q8, Qll, and Q12 operate similarly 12 ~or the amplifier 31 in responss to the voltage at node ~
13 MOSFET Q7, which is gate 42, is ON only when the 14 complement 0~ 02 is generated by sensing circuit 43 and ~ed ~ -back to the gate of Q7~ The primary ~unction o~ the circuit 43 16 is to delay the ~eedback signal ~rom the output of the 17 ampli~ier 31 to the gate 42 by a flxed amount and ln addition, 18 a logical inversion. A suitable con~iguration o~ the sensing ~ ;
}9 clrcuit 43 there~ore consists o~ three series-connected boot~
strap inverters, but the use o~ bootstrap stages is a matter -~ ~
. ~, .
21 of design cholce and is purely optionàl. MOSFETs Q22J Q23, ;
22 and Q2~, along with capacitor C8, ~orm the ~irst inver~er stage~
23 MOSFET9 Q25, Q26, and Q27 and capaoitor C9 ~orm the second 24 inverter stage; and M~SFETs Q28, Q29J and Q30 and capacitor C10 form the last lnverter stageO Each inver~er is the same and 26 there~ore only a description of the first stage will be pre~
27 sented as a representative example. In this ~irsk inverterJ
28 the drain-source path o~ the inpuk or pullwdown MOSFET Q24 is 29 connected between ground and the inverter~s output node G~ The load MOSFET Q23 has its drain-source path in series with the dc 31 -~DD voltage suppl~ and node G, and capacitor C8 connects node G
32 to the gate o~ MOSFET 230 The drain-source path o~ isolating Alvarez 1 ~4~S
1 MOSFET 22 connect~ the gate of MOSFET 23 and the voltage 2 supply, and :Lt~ gate connection to the same supply insures 3 that it is permanently ON.
4 The clock phase ~ is produced at the output (node F) o~ ampli~ier 31. If the 02 signal is hlgh it ~:.
6 will cause node G to be grounded through M~SFET Q24 whlch 7 i3 turned ON by the high state at node F ( its gate), If 8 02 is low, it will cause node G to go high slnce the path 9 from nod0 G to ground will be opened and node G wlll be charged by the bootstrapped MOSFET Q23. Thus, the voltage 11 at node G wlll be a logical inversion of the voltage at~ -12 node F.
13 The seGond and third lnverter stages operate 14 in the same manner and the slgna~ at node ~ ls, in turn, inYerted to produce lts complement at node H, and thls 16 1~ inverted by the last stage to produce its complement 17 at node I. This ~ignal, whlch i~ desi8nat~d ~Sl and is 18 the logical lnverqion o~ the signal ~2 at node F, ls fed 19 back to the gate o~ the MOSFET Q7.
However9 0Sl is delayed by the sensing circuit 43 . .
21 and its specl~ic aharaoteristics such as rise and ~all ~2 times are ar~ected by the parameters o~ the circult 43.
23 In particular, the time t2 1 ls controlled by the delay 24 ln the resdback path ~rom node F to gate 42, and the size ( len~th o~ the channel ) o~ the load MOSFET Q23 is the prin-~6 cipal element a~ecting the delay ~ince an inverter~s speed 27 o~ outpuk tran~ition from a re~erence state to a high state 28 ~s lnvers~ly related to the channel length of the load ~ `
29 MaSFET. It is noted that i~ only spaclng between clock phases i~ required, a ~ingle inverter will ~u~ice ~or 31 khe senslng circuit 43 . However, a series connectlon o~
- `~
~ Alvarez 1 11~)416~5 1 any odd number of stages will provide an inverted output, and 2 using at least three stages offers advantages over the single 3 stage arrangement. ;
4 For example, increasing the delay time t2 1 (increasing the length of MOSFET Q23) slows the rise time trl of 0Sl and 6 hence 01~ and since it is desirable for the rise time to be 7 as fast as possible for a given delay, additional inverter stages 8 provide means for obtaining independent control of the rise time. - . -g Where three inverter stages are used, as shown, the load MOSFET Q23 can be used to establish delay, and the third stage load MOSFET Q29 11 can be used to establish rise time trl. The specific delay and 12 rise characteristics desired will, of course, determine the 13 specific sizes required and the techniques for making this 14 determination for a specific circuit are well known to those skilled in the art of MOSFET circuit design.
16 The sensing circuit 33 is identical to the sensing 17 circuit 43. MOSFETs Q13, Q14, and Q15, along with capacitor C5, 18 form its first stage; MOSFETs Q16, Q17, and Q18 and capacitor C6 19 form the second stage; and MOSFETs Ql9, Q20, and Q21 and capacitor C7 form the last stage. Accordingly, its parameters 21 may be selected to control the delay time tl 2 (basically the 22 size of MOSFET Q14) and rise time tr2 (basically the size of 23 MOSFET Q20) as in the case of the sensing circuit 43. These 24 size selections may, of course, be different than those made for the sensing circuit 43 and thus the delay between 01 and 26 02 (tl 2) can be made different from the delay between 02 and 27 01 (t2 1) Similarly, the rise times for 01 and ~2 may be 28 individually selected. ~;
29 The fall times of the output clock phases 01 and 02 are not essentially affected by the feedback signal; they are 31 functions of the input signals applied to Alvare z 1 nodea A and B, and o~ the 91ze of the pull-down MOSFET~ o~ the 2 ampli~lers, such a~ MOSFETs Q10 and Q12, respectivelyt 3 ko which nodes A and B are dire~tly connected.
4 Utllizing the circ~it o~ FIG. 3~ a complete set Or controls, there~ore, exists ~or spacing and shaplng ~ -6 the 01 and ~2 clock pul~es. Of course i~ ~haplng is not 7 desired, the ~ensing circuits can be reduced to a 3ingle 8 inverter rOr provlding onl~ the desired separation, In -`
9 summary~ the transrer gate (such as 423 will not be turned ONJ and hence a pulse associated with its clock phase (~
11 will not be produced, until the other clock phase (~2) ha3 12 gone low and a speci~ied delay (t2_1) has passed.
13 If the circuit o~ FIGo 3 i9 adJusted so that ~ either tl_2 or t2_1 is large9 and the other very ~mall, an addltional clo~k pha3e can be generated ln the gap between 16 the pulses Or the principal clock pha3es ~1 and ~, FI~. 4 17 illustrates a schematic diagram o~ a circuit whlch ~enerate3 18 a third clock pha~e between khe end Or the ~1 clock pha~e 19 pul~ and the be~inning of the ~2 clock phase pul~e~ and is there~ore de~ignated ~12~ This circult is appended ?1 to the clrcuit o~ FIG. 3 and will produce the 012 clock 22 pulse, as sh~wn in ~I~. 5, i~ the tl2 interval is larger 2~ than the pulse width Or 012 and the t2_1 interval is shorter 24 than the total delay td 0~ the FIa. 4 circuit~
The dc supply voltage -VDD and the ~l and 26 output of FIG. 3 are connected as indicatedO The 01 and 27 02 clo¢k phase~ are applied to a conventional book3trap 28 N~R-gate 51, shown as con~istll~ o~ t~o individual pull~
29 doNn or input MOSFETs Q33 and ~34, whose ~ource-draln pa~hs are connected in parallel between gro~nd and a common node J, 31 and a load MOSFET Q32 whose source-draln path i~ connected 32 between ~upply voltage -V~D and this node J; the gate voltage . ~ . . . . . .
.. ... . . .
Alvarez 1 ~ 4~6~5 1 of the load MOSFET Q32 is provided by MOSFET Q31, which is biased 2 to be permanently ON and by the bootstrap effect of capacitor Cll 3 which connects the node J to the gate. The 01 clock phase is 4 applied to the gate of MOSFET Q33 and the 02 clock phase is connected to the gate of MOSFET Q34. Since a high input to 6 either MOSFET Q33 or MOSFET Q34 will cause the voltage at node J :
7 to go to ground, the gate circuit 51 detects when 01 and 02 are 8 both simultaneously OFF, and only in this event does a high 9 voltage (-VDD~ appear at node J.
A bootstrap inverter 52 consists of MOSFETs ~35, Q36, 11 Q37 and capacitor C12. It is identical in structure and func-12 tion to the inverters in FIG. 3 and it produces at node K the 13 logical complement of the voltage at node J. ~ence when both 14 01 and ~2 are OFF (that is, no pulse exists) the voltage at node K will be low. The complementary voltages at nodes J and K
16 correspond to the voltages at nodes A and B in FIG. 3, and the 17 012 intermediate clock phase is produced by a push-pull amplifier 54 18 substantially as are the primary clock phases described herein-19 before. The voltage at node K is passed by transfer gate 53 (shown as MOSFET Q38 which is biased permanently ON) to one 21 input of the amplifier 54 and the complementary voltage at node J
22 is coupled directly to the other input of the amplifier 54. The 23 amplifier 54 (MOSFETs Q39 and Q40 and capacitor C13) corresponds 24 in structure and function to amplifiers 41 and 31 and except for the input to the gate of MOSFET Q38, gate 53 is similar to gates 42 26 and 32.
27 Of course, the delay tl 2' between the 01 and 02 clock 28 phases can be made small and the delay, t2 1' between the 02 and 29 01 can be made large by appropriate adjustment of the parameters in FIG. 3. This would produce a clock phase 021 between the 31 end of the 02 clock . ~ . , ' .
Alvareæ 1 9..~4~L6~
l phase and the beginnlng o~ the ~l clock phase. In additlon, 2 1~ neither tl_2 nor t2_l were short, the circuit of ~IG. 4 3 would produce an intermediate clock phase which contains 4 pulses in the two gaps between the ~l and ~2 primary clock 5 phases.
6 The gate 53 in FIG. 4 could also be controlled 7 by a delayed ~eedback signal and thus the paclng between 8 ~he preceding prlmary clock phase, such as ~l~ and the 9 lntermediate clock phase, such as ~12, would be adJustable.
In addltion, i~ appropriate logic and feedback wer~ pro-ll vided, the 01 and ~ primary clock phases could be used 12 to generate two intermediate clock phases with ind~pendent 13 spacing o~ these intermediate clock phases wlthin kh~ gaps 14 between the pulses ~ 01 and ~2 and between the pulses of 02 and ~l~ respectlvely. Theoretlcally~ it is possible 16 to generate an~ number of intermediate and subintermediate 17 clo¢k phaseis lf adequate spa¢ing is provided between ad~a-18 ce~t pul~es of preexisting clock phases. In all cases, of 19~ course~ the spacing would have to be greater than the pul~e width o~ the pulse being inserted.
21 In all cases it is to be understood that the ~22 a~ove de~cribed arran~e~nts are merely illustrative o~
?3 a small number Or the man~ possible applications o~ the -24 princlples o~ the present invention. Numerous and varied other~arrangements in accordance with these principles ~;
26 may readily be devised by those skilled in the ~rt with-27 out d~parting rrom the spirlt and scope o~ the in~entionO
, ~' ''. :' .
., -17- ~
.. . , ,, .. , , - .. . . :,. ~ -
and the dela~ed output from the sensing circuit is cross-16 coupled to control the transfer gate associated with the 17 other output phase. By ~udicious selection o~ the parameters 18 o~ the sensing circuits, the time and speed of "turn-ON" ~or 19 the transfer gate can be controlled. Accordingly, the time between one phase and the other can be controlledO Where 21 two sen~ing circuits are used the separation between the 22 pulses of ~he ~wo clock phasss, as well as the shape of 23 each pulse, can be selectedO `
2~ The dou~le coupling to each amplifier in con~unction with th transfer gates avoids the power dissipation common in 26 the prlor art, since the ampli~iers are normally OFF and the 27 ¢ross-coupled gate control is used to turn the ampli~ier ON
28 only when the clock phase is to be produced, 29 The multiple phase clock generator can be embodied using any approprlate ~abrication technique~ In addition 31 the trans~er gates, double-coupled ampli~iers and sensing 32 circults can be provided by numerous current configurations.
. .. ~ .
~ O 4 ~ ~ 5 As an example clrcuits using metal-o~lde-~emlconductor-~ield-errect translstor~, hereina~ter re~erred to as MOSFETs, is shown. In one particular embodiment, the ~enslng olrcuit~
consl~t o~ a ~erle~ Or bootstrap lnverters; each tran~rer gat0 1~ ~lmply a ~lngle MOSF~l wlth a cro~s-coupled ~eed-back ~lgnal applied ~rom the other sensing circult to it~
gate3 and the push/pull ampll~ler~ are boot~trap "lnverter~
with the direct coupled input applied to the gate o~ the pull-down MOSFET and the lnput ~rom the trans~er gate being applled to the gate Or the load or pull-up MOSFET, ~ ;
Since the spacing between the pulse~ o~ the two :-.
clock phase~ can be controlled, the s0paration between them can be made large enough ~or the insertlon o~ an addi-tional third clock phase with its pulses occurrlng durlng the time both of the two prlmary phase~ are OFF; i.e., between pul~es. The generation o~ a thLrd clock phase can be provided simply by the addltion Or a NOR-gate to detect when the first and second phases are OFF, an inYerter to generate the complement o~ the NOR-gate output~ and a 2~ push/pull amplifier to produce the thlrd clock phase inter-mediate 'co the ~ir~t two~, Wlth approprlate cirouitry, spacing ~or a rourth~ th, sixth, etc. clock phase can ~ :
be provided, and thus, theoreticallyD the space bet~een pulse~ o~ any two clock phases can be ~illed wlth the pulse~
of a~other additlonal clock phaseO
In accordance with one aspect of the present invention there is provided a multiple-phase clock generator circuit for providing at least two clock phases, each consisting of an individual pulse train comprising:
-~A ~ - 5 ~
.... . .... . . . . .. .
~0~ ~6 ~ S
means for produclng a ~irst lnput pulse train at a ~irst node and a second input pulse tr~in at a second node, the first and second input pulse trains being complemen~ary;
rirst amplifier means for produclng one o~ the clock phases;
first connection means for coupling the first and ~econd nodes to the first amplifier means;
the first amplifier means being turned on to start a pulse of the one clock phase when a pulse from the ~irst lo input pulse train is coupled to the first amplifier means, and the first amplifier mean~ being turned o~f to end the pulse of the one clock phase when a pul~e from the second input pulse train is coupled to the first amplifier means;
second ampll~ier means ~or producing another o~ the clock phases;
second connection means for coupling the first and second nodes to the second amplifier means;
the second amplifier means being turned on to start a pulse of the other clock phase when a pulse from the second ~nput pulse train is coupled to the second ampli~ier meansJ and the second amplifier means being turned o~f to end the pulse o~ the other clock phase when a pulse from the first input pulse traln i~ coupled to the second amplifier means;
feedback means ~or producing from the other clock phase at the output o~ the second ampli~ier means, a first con-trol pulse train whose pulses are delayed by a fir~k ;~
selected time from the end of the corresponding pulses of the other clock phase; and said first connection means including means responsive `
to the control pulse train for coupling the first input pulse ' .
5 a -~ - , . . .
, ~0416~5;
train at the fi~st node to the first ~mplifier means only ~uring the occurrence o~ the pulse of the first control pulse train;
whereby a p~lse of the one clock phase will begin only the ~irst preselected time a~ter a pulse of the other clock phase has ended.
In accordance with another aspect of the present invention there is provided a multiple phase clock. ~-generator circuit for producing at le~st two spaced apart ;
0 clock phases comprising:
means for generating ~n input pulse train and a complementary pulse train which is a logical complement of the input pulse train;
a first amplifier and a second amplifier, each having two inputs and each producing one of the clock phases at its output;
first conductive means for directly coupling the ~ ~
complementary pulse train to one input of the first amplifier; ~ .
second conductive means for directly coupling the input ;~ ~.
pulse train to one input of the second amplifier; `~
first gatlng means for applying the input pulse train to .
the second input of the first amplifier in response to a first control signal; . :~
second gating means for applying the complementary pulse .`~
.
train to a second input of the second amplifer in response to a second control slgnal; i.
first feedback means for monitoring the output of the first ~ :
amplifier and producing the second control signal to which the .
second gating means responds, said first feedback means includ~
ing means for delaying the output of the first amplifier; and second feedback means for monitoring the output of the second amplifier and providing the first control signal to which ' . ' f~ ~ - Sb -~ . . . .. . . . . . . . .
~L~4~L~;1S
the first gating means responds, said second feedback means including means for delaying the output of the second amplifier;
whereby specified spacings are provided between the pulses of one of the clock phases and the pulses of the other of the clock phases.
BRIEF DESCRIPTION OF THE DRAWINGS
In drawings which illustrate embodiments of the invention:
FIG. 1 is a block diagram illustrative of a two phase clock circuit in accordance with the present invention.
FIG. 2 iS a timing diagram illustrative of the :`
operation of the circuit of FIG. 1. ~
' ::
'', . .-i ~ - 5c -. , , . .. . .
. . . .. . ~., . . . ~
f Alvareæ 1 ~ `
1~416~S
1 FI~. 3 i~ a ~chem~tic diagram o~ a multiple pha~e 2 clock clrcult in accordance wlth the pre~ent inventlon, 3 FIG. 4 1~ a schematic diagram ~howlng an intermediate 4 clock pha~e circuit suitable ~or u~e with the two phase clock circult o~ FI~. 30 6 FI~, 5 1~ a timlng diagram helpful in describing 7 the operation o~ the circult of FI~. 4.
9 The block diagram o~ FI~. 1 illustrates the baslc elemen~ Or a two-p~as~ clock circult which provide~ ~wo ~ .
11 independently controllable clock phases 01 and 0~ ~or applica- j :
12 tion to ~eparate l~ad~ 14 and 24, re3pecti~ely, ~hown, ~or 13 example~ as capa¢itive l~ads. An o~lllator 10 produce~ :
14 two output~ ~N and ~IN whlch are ¢omplementary pul~e tralns as ~hown in FIG. 2A. One output o~ the osclllator 10~ ~ -16 ~ , 1~ directly coupled to an lnput Al_l o~ a rlr~t 17 ampli~ier 11. Thl~ lnput provide~ a path to dls¢harge 18 the output, 01. ~ the ~irst ampllrler 11 to a low or reference : :
lg~ level (no pulee; ~hown a~ ~round in the timing dla~ram o~
FIa. 2F) whenever this input i~ at a high level9 (pul~e 21 pre~ent; ~V ~n the timing diagram or FI~. 2C~. The out-22 put, 01> ~ the first ampli~ler 11 is allowed to rl~e to 23 the high level only wh~n there exist~ a hlgh level enable 24 puls~ at the other input Al-2 to ampli~ier 11 (~ee FI~. 2B), ~ Thl~ hl~h level at the A1N2 input i8 produced by the AND
26 trans~er gate 12 only when itY inputs (the output ~SI from 27 a rirst delay circuit 13 and the other output, 0IN~ ~
28 osclllator 10) are high. Hence the ~l clock pulse i8 turned 29 oN (pulse begin~) when a pulse o~ the 0IN output ~rom os¢lllator 10 i8 passed to the ampli~ier 11 in respon~e 31 to a pulse ~rom circuit 13.
.. .. ..
, -, . . .. .
. , ~ , - .
Alvarez 1 1 The ~irst d~lay clrcuit 13 i8 part Or a ~eedback 2 pakh ~rom the output o~ a second ampllrler 21 to the trans-3 ~er gate 12. The lnput to the first delay circult 13 i~
4 thuæ the output clock signal 02 and thi~ i~ delayed9 and loglcally ln~erted to produce a control output ~Sl- ThU50 6 a de~ined interval after ~2 goe~ low (ground), the ~Sl 7 control ~lgnal exhiblt~ a high level pulse whlchj when 8 ooincldent with the high level pul~e o~ the other comple-9 mentary pul~e kraln ~IN at khe output of the o~cillator 10 cau~es AND tran~er gate 12 to produce the enable pulse at 11 the input Al-2 of the ~lr~t ampll~ier ll o The amount o~
12 the delay and in addltlon, the ri~e tlme o~ the control 13 signal 0Sl therefore determine the turn-on characteri~tl¢s 14 o~ the output clock pha~e 01~ and the~e characteristlcs can be adJu~ted by choosing approprl.ate parameters within 16 the delay circuit 13. The ~l clock pha~e turns O~F (pul~e 17 end~) in respon~e to a change in the level Or the ~N out- :
18 put ~rom o~cillator 10 (and hence an equiYalent change in : l9 the ~tate o~ the output ~
Th~ ~econd hal~ Or khe clrcuit lncludes identical 21 elemsnt~ and works ln the same ~ er to produce the other 22 clock phase 02~ The oscillator outputs 0IN and ~ are, 23 o~ cour3e~ connected in reverse order to the second ampli~ier 21 ~ -24 and the gate 22; the feedback to the second delay circult 23 i~
the clock pul~e ~l ~rom the output o~ the first ampli~ ll, 26 ~ ln~tead o~ khe clock pha~e 02~ and the control output 0S2 is 27 applied to gate 22. The 0IN ~ignal applied to one lnput A2 28 o~ the ampli~ler 21 (FIa. 2D) provides a path to dl~charge ~ ~
29 clock ~ignal 02 to the low level (no pulse shown a~ ground - :
in FI~. 2~) whenever 0IN 13 hlgh. The delayed output Or .
Alvarez 1 ~ 0~ ,5 the delay ¢lrcult 23 provldes a high level pulse (J2ls2 in 2 FIa~o 2I) a rlxed interval a~ clo~k pha~e 02 ~FIG, 2~) 3 ~oe~ low. The coincidence Or a hlgh 0S2 ~ignal and a high 4 ~ ~lgnal applied to the AND tran~f`er gate 22 produce~ a 5 hlgh level pul~e at the lnput A2-2 c~ the amplirier 21, 6 q~h~9 in turn, cause~ a hlgh state o~ output cloc~ si~snal 02 7 at the ampll~ier output~ The characteri~tics (delay and 8 rise tl~ae ) of the control sign~l ~2 are, o~ cour~e, adJu~t-9 able by varlatlon o~ the parameter~ within the delay circuit 230 Thu~ a ~ pul~e ~-V in FI~. 2G~ is produced 11 only when ~ ls hlgh and coincldentally 01 ha~ been low 12 ~or a de~lned delay time, deslgnated tl_2o SimilarlyJ 01 13 can e~hiblt a pul~e (-V in FIG. 2F) only when ~IN i9 high 14 and aolncidentally ~2 (the other output clock) ha~ been ~ :
15 low for a derined delay time~ deslgn~.ted t2_1~ which may 16 be dir~erent from tl_2. Accordln~ly, the pul~e~ o~ the ~ ~ .
17 two output clock signals ~ and 02 c~nnot overlap in tlme 18 and ~helr spacing can b~ indlv~dua~ly controll~d by parameter 19 variation~ especially in the delay circuit~ 13 and 23.
~ .. . .
20 ~ In FI~S~ 2H and 2I the de~ignationa trl and tr2 " ~
21 repre~ent, re~pectively, the rise time ~ 0$1~ and the : ~ :
rl~e ~ti~e ~ 0'S2~ S~nce 0'Sl and ~S2~ the output~ Or the 23 delay circuits 13 and 239 re~pectively, trigger th~ rise 24 o~ the ampli~ler output~ the parameters of the delay circuits 13 and 23 control the ri~e time~ o~ the clock signals 01 and 02J and 26 the ri~e tlm~ ~ 01 and 02 are dependent upon trl and tr2, 27 respeotively. The ~all time~ ~ 0'1 and 02 are controlled 28 by the lnput clock ~ignal ~IN and its complement ~ and 29 by the parameter~ o~ power ampll~ier~ lI and 21 respe¢tlvely.
l~he delay between the end o~ a 0'2 pul~e (when 31 ~2 reaohes ground in FI~. 2~) and the beginnlng o~ a 01 32 pulse (~hen 01~ ~tarts to go toward -V in FIG. 2~ design~ted ~. . . , . . - ..
.. , ,, . ~', : . , . :
. . .
; . . . , Alvare z S
t2_1, and the delay between th~ rall of ~1 and the rlse ~ ~2 is deslgnated t1~2J as shown in FI~. 2~ and lndlcated 3 hereinberore.
4 Whlle the multiple pha~e clock circult can be 5 embodi2d uslng numerous alternatlve technologle includ-6 ing vacuum tube~3 bipolar tran~istors, etc., FI~. 3 illustrates 7 an embodlmenk o~ a two-phase cir¢uit u~lng MCS~ETs or field-8 errect translstors o~ the metal-oxlde-semlconductor type.
9 It 1~ as~um~d that these are o~ the p-channel enhancem~nt mod~ typeJ but the circuit may al~o be constructed uslng 11 other types o~ MOSFET8J lncludlng depletion mode p-ohannel 12 devices, and n-channel devices o~ either the enhancement 13 or depletion variety.
14 The complementary input 3ignals ~N and ~rN, which are applied to nodes A and B, respectively, can be 16 provided by an external oscillator. Although there are 17 num~rou3 pos~lble arrangements for generatlng these com-18 plem~ntary slgnals, lt is assumed rOr purpose Or illustratlon ~-`
19 in FIa. 3 that a generator~ not shown, produces a ¢lock signal ~0. This i~ applied to the ~ driver 30, a con-21 ~entlonal bootstrap inverter, whi¢h produces ~ at node B.
22 ~ In addition, ~ i9 used to drive another inverter, the ~ : :
23 driver 40, whlch produces 0IN for application to node A
24 As is ~hown, by way o~ example, MOSFETs Ql, ~2, and Q3, 25 and capacltor Cl ~orm the bootstrap lnverter whlch is~the 26 driver 30. -:~
27 In additlon to logically inverting 00 to create -~
28 ~ , this driver circuit also establishq~ the two level~
29 of the ~ pulse train. In general~ these levels are referred to a~ high and low. For p-ohannel MOSP$T circuits, V8S~
,. . . ..
'". ".
Alvarez 1 4:1L6~LS ~ -1 de~in~d a~ the mo~t posltlve voltage level supplled to 2 the chip, 19 the low level; and hereln 0 volts has been 3 arbltrarily chosen a~ this low or reference level~ The 4 negatlve dc supply voltage de3i~nated -VDD 18 the hlgh 5 level, In conformit~ with the~e de~lnltions, and the designa-6 tions used in FI~. 2, negatlve voltage~ great~r than threshold 7 are herein de~l~nated -V and referred to a~ high voltages and 8 voltages approaching VSs (de~lgnated ground) are re~erred to 9 a~ low voltages. Accordlngly, hlgher or increa~lng voltag~
mean those of lncreaslng magnltud~ ln negative dlre~tlonO -11 Where boot~trapping i~ employed -Y will, in most cases, be 12 the ~upply volta~e -VDD.
13 The other boot~trap inverter whlch form~ drlver 40 14 con~i~ts o~ MOS~ Q4~ Q5, and Q6 and capacltor C2. It fu~¢tlon~ identically to produce ~IN ~the complement of 16 ~ ) with similar levels Or -VDD and gro~nd. Ina~much 17 as drlver~ 30 and 40 operate in a conventional manner, 18 no ~urther dl~cusslon of their clrcuitry nor operation 19 1~ required.
Node B ls connected to one input oP a pus~/pull 21 ampllfier 41. This ampllfler consl~t~ Or a pull~up to 22 -VDD MOSFET Q99 a pull down to Ys5 MOSFET Q10, and ¢apacltor C3.
23 ~he drain~ource paths of MOSFETs Q9 and Q10 are serially con-24 nec~ed between a dc ~uppl~ voltage ~VDD and ground and the ~
capacitor C3 connect~ the intermedlate point~ node D~ to ~: :
26 the gate of MOS~ET Q9, node C. The gate of Q10 i~ cormected 27 to node B, and when the voltage at node B goes low ~ i8 28 zero ln FIG. 2A) the path to ground provlded by MOSFE~ Q10 29 is turned OFF.
Since the voltage at node A is the loglcal complement 31 o~ the voltage at node B, thls voltage at node A begins to ri se 32 when the node B voltage goes low, and the hlgh voltage at " ~
.,., .. ... ,, . ".
, : :, . . .. ....
Alvareæ
S
1 node A i tran~erred to node C under the control Or trans~er 2 gate 42. Thi~ gate 42 con~lst~ o~ a ~ingle MOSFET Q7, who~e 3 draln-source path conneots nodes A and C. m u~ the hlgh 4 voltage node A will be tran~ferred to node C i~ MOS~ Q7 1~ ON. The ~tate Or the M~SFET Q7 is, in turn, determlned 6 ~y ~he ~oltage applied to lts gate rrom ~en~ing circuit 43 7 as will be descrlbed hereinarter.
8 Assumi~g that Q7 i8 turn~d ON, the vol~age at 9 node C will ~tart to rlse, and ~ince node C ls the gate o~ pull~up M06Fh~ Q9, Qg wlll turn ON9 causing the voltage 11 at node D to rl~e toward -VDD. Th~ lar~e capacl~ance on 12 point D, however, cau~es it to charge much more 810wly ~ .
13 than point C, and, thu9, a~ the voltage at poln~ D ri~es, 14 it boo~t3 up the voltage at node C through capacitor C3 :;.
~o a level much greater than the ~upply voltage -VDD.
16 ~he volkage at point D i9 the ~ir~t output phase ~1~ Thu~, 17 when the voltage at node A i~ high and ~imultaneously the 18 gate 42 i~ oonductlng the voltage r~Om node A to the amplifier 19 ~tage 41, (as determined by the output of the sen~lng clrcuit 43), .
a 01 pul~e will be produced at node D, the output o~ the ~ -21 ampli~ier 41. ~- ~
22 The other part o~ the oircuit, consl~tlng o~ : :
2~ a transrer gate 32 (M~SFET Q8)D an ampli~ier 31 (pull-up 24 -MOSF~T Qll, pull-down MOSPET Q12 and capacitor C43, and a ae~ing cirGuit 33J is a duplioate o~ the part consist-26 ing o~ the element~ 42, 41 and 43, and lt produces 02 at 27 node F ln the same way that 01 is produced at node D. ~!
28 Thu~ a 02 pulse will appear whenever the voltage at nod2 B
29 rises and 1~ gated by trans~er gate 32 in response to a :~
reedback slgnal from sensing circuit 33.
~ ,, , . , ~,, - . . . . .
. ., :
.
Alvarez 1 -~L~4~6~S
1 The operation described above ~or producing ~1 and 2 assumes ~hat transfer gates 42 and 32 are ON. If the gates ~2 3 and 32 are 0~, their respectlve amplifi2rs 41 and 31 are OFF
4 and an OFF ampli~ier produces no output pulse. Of course, g~tes 42 and 32 are never ON concurrently. When it is ON, 6 MOSFET Q7 (gate 42) turns M~SFET Q9 of the ampli~ier 41 ON and 7 OFF in accordance with the voltage at node A; but MOSFET Q9 is - -8 never ON concurrently wlth MOSFET Q10, whlch discharges (or 9 turns OFF) the ampll~ier 41 when it is ON. There~ore, no dc power is dissipated when the ou~put o~ the amplifier 41 is 11 being prevented. MoSFETs Q8, Qll, and Q12 operate similarly 12 ~or the amplifier 31 in responss to the voltage at node ~
13 MOSFET Q7, which is gate 42, is ON only when the 14 complement 0~ 02 is generated by sensing circuit 43 and ~ed ~ -back to the gate of Q7~ The primary ~unction o~ the circuit 43 16 is to delay the ~eedback signal ~rom the output of the 17 ampli~ier 31 to the gate 42 by a flxed amount and ln addition, 18 a logical inversion. A suitable con~iguration o~ the sensing ~ ;
}9 clrcuit 43 there~ore consists o~ three series-connected boot~
strap inverters, but the use o~ bootstrap stages is a matter -~ ~
. ~, .
21 of design cholce and is purely optionàl. MOSFETs Q22J Q23, ;
22 and Q2~, along with capacitor C8, ~orm the ~irst inver~er stage~
23 MOSFET9 Q25, Q26, and Q27 and capaoitor C9 ~orm the second 24 inverter stage; and M~SFETs Q28, Q29J and Q30 and capacitor C10 form the last lnverter stageO Each inver~er is the same and 26 there~ore only a description of the first stage will be pre~
27 sented as a representative example. In this ~irsk inverterJ
28 the drain-source path o~ the inpuk or pullwdown MOSFET Q24 is 29 connected between ground and the inverter~s output node G~ The load MOSFET Q23 has its drain-source path in series with the dc 31 -~DD voltage suppl~ and node G, and capacitor C8 connects node G
32 to the gate o~ MOSFET 230 The drain-source path o~ isolating Alvarez 1 ~4~S
1 MOSFET 22 connect~ the gate of MOSFET 23 and the voltage 2 supply, and :Lt~ gate connection to the same supply insures 3 that it is permanently ON.
4 The clock phase ~ is produced at the output (node F) o~ ampli~ier 31. If the 02 signal is hlgh it ~:.
6 will cause node G to be grounded through M~SFET Q24 whlch 7 i3 turned ON by the high state at node F ( its gate), If 8 02 is low, it will cause node G to go high slnce the path 9 from nod0 G to ground will be opened and node G wlll be charged by the bootstrapped MOSFET Q23. Thus, the voltage 11 at node G wlll be a logical inversion of the voltage at~ -12 node F.
13 The seGond and third lnverter stages operate 14 in the same manner and the slgna~ at node ~ ls, in turn, inYerted to produce lts complement at node H, and thls 16 1~ inverted by the last stage to produce its complement 17 at node I. This ~ignal, whlch i~ desi8nat~d ~Sl and is 18 the logical lnverqion o~ the signal ~2 at node F, ls fed 19 back to the gate o~ the MOSFET Q7.
However9 0Sl is delayed by the sensing circuit 43 . .
21 and its specl~ic aharaoteristics such as rise and ~all ~2 times are ar~ected by the parameters o~ the circult 43.
23 In particular, the time t2 1 ls controlled by the delay 24 ln the resdback path ~rom node F to gate 42, and the size ( len~th o~ the channel ) o~ the load MOSFET Q23 is the prin-~6 cipal element a~ecting the delay ~ince an inverter~s speed 27 o~ outpuk tran~ition from a re~erence state to a high state 28 ~s lnvers~ly related to the channel length of the load ~ `
29 MaSFET. It is noted that i~ only spaclng between clock phases i~ required, a ~ingle inverter will ~u~ice ~or 31 khe senslng circuit 43 . However, a series connectlon o~
- `~
~ Alvarez 1 11~)416~5 1 any odd number of stages will provide an inverted output, and 2 using at least three stages offers advantages over the single 3 stage arrangement. ;
4 For example, increasing the delay time t2 1 (increasing the length of MOSFET Q23) slows the rise time trl of 0Sl and 6 hence 01~ and since it is desirable for the rise time to be 7 as fast as possible for a given delay, additional inverter stages 8 provide means for obtaining independent control of the rise time. - . -g Where three inverter stages are used, as shown, the load MOSFET Q23 can be used to establish delay, and the third stage load MOSFET Q29 11 can be used to establish rise time trl. The specific delay and 12 rise characteristics desired will, of course, determine the 13 specific sizes required and the techniques for making this 14 determination for a specific circuit are well known to those skilled in the art of MOSFET circuit design.
16 The sensing circuit 33 is identical to the sensing 17 circuit 43. MOSFETs Q13, Q14, and Q15, along with capacitor C5, 18 form its first stage; MOSFETs Q16, Q17, and Q18 and capacitor C6 19 form the second stage; and MOSFETs Ql9, Q20, and Q21 and capacitor C7 form the last stage. Accordingly, its parameters 21 may be selected to control the delay time tl 2 (basically the 22 size of MOSFET Q14) and rise time tr2 (basically the size of 23 MOSFET Q20) as in the case of the sensing circuit 43. These 24 size selections may, of course, be different than those made for the sensing circuit 43 and thus the delay between 01 and 26 02 (tl 2) can be made different from the delay between 02 and 27 01 (t2 1) Similarly, the rise times for 01 and ~2 may be 28 individually selected. ~;
29 The fall times of the output clock phases 01 and 02 are not essentially affected by the feedback signal; they are 31 functions of the input signals applied to Alvare z 1 nodea A and B, and o~ the 91ze of the pull-down MOSFET~ o~ the 2 ampli~lers, such a~ MOSFETs Q10 and Q12, respectivelyt 3 ko which nodes A and B are dire~tly connected.
4 Utllizing the circ~it o~ FIG. 3~ a complete set Or controls, there~ore, exists ~or spacing and shaplng ~ -6 the 01 and ~2 clock pul~es. Of course i~ ~haplng is not 7 desired, the ~ensing circuits can be reduced to a 3ingle 8 inverter rOr provlding onl~ the desired separation, In -`
9 summary~ the transrer gate (such as 423 will not be turned ONJ and hence a pulse associated with its clock phase (~
11 will not be produced, until the other clock phase (~2) ha3 12 gone low and a speci~ied delay (t2_1) has passed.
13 If the circuit o~ FIGo 3 i9 adJusted so that ~ either tl_2 or t2_1 is large9 and the other very ~mall, an addltional clo~k pha3e can be generated ln the gap between 16 the pulses Or the principal clock pha3es ~1 and ~, FI~. 4 17 illustrates a schematic diagram o~ a circuit whlch ~enerate3 18 a third clock pha~e between khe end Or the ~1 clock pha~e 19 pul~ and the be~inning of the ~2 clock phase pul~e~ and is there~ore de~ignated ~12~ This circult is appended ?1 to the clrcuit o~ FIG. 3 and will produce the 012 clock 22 pulse, as sh~wn in ~I~. 5, i~ the tl2 interval is larger 2~ than the pulse width Or 012 and the t2_1 interval is shorter 24 than the total delay td 0~ the FIa. 4 circuit~
The dc supply voltage -VDD and the ~l and 26 output of FIG. 3 are connected as indicatedO The 01 and 27 02 clo¢k phase~ are applied to a conventional book3trap 28 N~R-gate 51, shown as con~istll~ o~ t~o individual pull~
29 doNn or input MOSFETs Q33 and ~34, whose ~ource-draln pa~hs are connected in parallel between gro~nd and a common node J, 31 and a load MOSFET Q32 whose source-draln path i~ connected 32 between ~upply voltage -V~D and this node J; the gate voltage . ~ . . . . . .
.. ... . . .
Alvarez 1 ~ 4~6~5 1 of the load MOSFET Q32 is provided by MOSFET Q31, which is biased 2 to be permanently ON and by the bootstrap effect of capacitor Cll 3 which connects the node J to the gate. The 01 clock phase is 4 applied to the gate of MOSFET Q33 and the 02 clock phase is connected to the gate of MOSFET Q34. Since a high input to 6 either MOSFET Q33 or MOSFET Q34 will cause the voltage at node J :
7 to go to ground, the gate circuit 51 detects when 01 and 02 are 8 both simultaneously OFF, and only in this event does a high 9 voltage (-VDD~ appear at node J.
A bootstrap inverter 52 consists of MOSFETs ~35, Q36, 11 Q37 and capacitor C12. It is identical in structure and func-12 tion to the inverters in FIG. 3 and it produces at node K the 13 logical complement of the voltage at node J. ~ence when both 14 01 and ~2 are OFF (that is, no pulse exists) the voltage at node K will be low. The complementary voltages at nodes J and K
16 correspond to the voltages at nodes A and B in FIG. 3, and the 17 012 intermediate clock phase is produced by a push-pull amplifier 54 18 substantially as are the primary clock phases described herein-19 before. The voltage at node K is passed by transfer gate 53 (shown as MOSFET Q38 which is biased permanently ON) to one 21 input of the amplifier 54 and the complementary voltage at node J
22 is coupled directly to the other input of the amplifier 54. The 23 amplifier 54 (MOSFETs Q39 and Q40 and capacitor C13) corresponds 24 in structure and function to amplifiers 41 and 31 and except for the input to the gate of MOSFET Q38, gate 53 is similar to gates 42 26 and 32.
27 Of course, the delay tl 2' between the 01 and 02 clock 28 phases can be made small and the delay, t2 1' between the 02 and 29 01 can be made large by appropriate adjustment of the parameters in FIG. 3. This would produce a clock phase 021 between the 31 end of the 02 clock . ~ . , ' .
Alvareæ 1 9..~4~L6~
l phase and the beginnlng o~ the ~l clock phase. In additlon, 2 1~ neither tl_2 nor t2_l were short, the circuit of ~IG. 4 3 would produce an intermediate clock phase which contains 4 pulses in the two gaps between the ~l and ~2 primary clock 5 phases.
6 The gate 53 in FIG. 4 could also be controlled 7 by a delayed ~eedback signal and thus the paclng between 8 ~he preceding prlmary clock phase, such as ~l~ and the 9 lntermediate clock phase, such as ~12, would be adJustable.
In addltion, i~ appropriate logic and feedback wer~ pro-ll vided, the 01 and ~ primary clock phases could be used 12 to generate two intermediate clock phases with ind~pendent 13 spacing o~ these intermediate clock phases wlthin kh~ gaps 14 between the pulses ~ 01 and ~2 and between the pulses of 02 and ~l~ respectlvely. Theoretlcally~ it is possible 16 to generate an~ number of intermediate and subintermediate 17 clo¢k phaseis lf adequate spa¢ing is provided between ad~a-18 ce~t pul~es of preexisting clock phases. In all cases, of 19~ course~ the spacing would have to be greater than the pul~e width o~ the pulse being inserted.
21 In all cases it is to be understood that the ~22 a~ove de~cribed arran~e~nts are merely illustrative o~
?3 a small number Or the man~ possible applications o~ the -24 princlples o~ the present invention. Numerous and varied other~arrangements in accordance with these principles ~;
26 may readily be devised by those skilled in the ~rt with-27 out d~parting rrom the spirlt and scope o~ the in~entionO
, ~' ''. :' .
., -17- ~
.. . , ,, .. , , - .. . . :,. ~ -
Claims (18)
1. A multiple-phase clock generator circuit for providing at least two clock phases, each consisting of an individual pulse train comprising:
means for producing a first input pulse train at a first node and a second input pulse train at a second node, the first and second input pulse trains being complementary;
first amplifier means for producing one of the clock phases;
first connection means for coupling the first and second nodes to the first amplifier means;
the first amplifier means being turned on to start a pulse of the one clock phase when a pulse from the first input pulse train is coupled to the first amplifier means, and the first amplifier means being turned of to end the pulse of the one clock phase when a pulse from the second input pulse train is coupled to the first amplifier means;
second amplifier means for producing another of the clock phases;
second connection means for coupling the first and second nodes to the second amplifier means;
the second amplifier means being turned on to start a pulse of the other clock phase when a pulse from the second input pulse train is coupled to the second amplifier means, and the second amplifier means being turned off to end the pulse of the other clock phase when a pulse from the first input pulse train is coupled to the second amplifier means;
feedback means for producing from the other clock phase at the output of the second amplifier means, a first con-trol pulse train whose pulses are delayed by a first selected time from the end of the corresponding pulses of the other clock phase; and said first connection means including means responsive to the control pulse train for coupling the first input pulse train at the first node to the first amplifier means only dur-ing the occurrence of the pulse of the first control pulse train;
whereby a pulse of the one clock phase will begin only the first preselected time after a pulse of the other clock phase has ended.
means for producing a first input pulse train at a first node and a second input pulse train at a second node, the first and second input pulse trains being complementary;
first amplifier means for producing one of the clock phases;
first connection means for coupling the first and second nodes to the first amplifier means;
the first amplifier means being turned on to start a pulse of the one clock phase when a pulse from the first input pulse train is coupled to the first amplifier means, and the first amplifier means being turned of to end the pulse of the one clock phase when a pulse from the second input pulse train is coupled to the first amplifier means;
second amplifier means for producing another of the clock phases;
second connection means for coupling the first and second nodes to the second amplifier means;
the second amplifier means being turned on to start a pulse of the other clock phase when a pulse from the second input pulse train is coupled to the second amplifier means, and the second amplifier means being turned off to end the pulse of the other clock phase when a pulse from the first input pulse train is coupled to the second amplifier means;
feedback means for producing from the other clock phase at the output of the second amplifier means, a first con-trol pulse train whose pulses are delayed by a first selected time from the end of the corresponding pulses of the other clock phase; and said first connection means including means responsive to the control pulse train for coupling the first input pulse train at the first node to the first amplifier means only dur-ing the occurrence of the pulse of the first control pulse train;
whereby a pulse of the one clock phase will begin only the first preselected time after a pulse of the other clock phase has ended.
2. A multiple-phase clock generator circuit as claimed in claim 1 further comprising second feedback means for producing from the one clock phase at the output of the first amplifier means a second control pulse train whose pulses are delayed by a second selected time from the end of the corresponding pulses of the one clock phase; and said second connecting means including means responsive to the second control pulse train for coupling the second input pulse train at the second node to the second amplifier means only during the occurrence of a pulse of the second control pulse train;
whereby a pulse of the other clock phase will begin only the second preselected time after a pulse of the one clock phase has ended.
whereby a pulse of the other clock phase will begin only the second preselected time after a pulse of the one clock phase has ended.
3. A multiple-phase clock generator circuit as claimed in claim 2 wherein the first and second selected times in the first and second feedback means are different from one another.
4. A multiple-phase clock generator circuit as claimed in claim 1 further comprising an auxiliary amplifier means for producing a third clock phase pulse train, the pulses of the third clock phase occurring only during the intervals between the end of a pulse of one of the clock phases and the beginning of the pulse of the other of the clock phases.
5. A multiple-phase clock generator circuit as claimed in claim 1 wherein the feedback means includes an odd number of inverter stages as the means for providing the first selected time delay.
6. A multiple-phase clock generator circuit as claimed in claim 5 wherein the feedback means includes a series connec-tion of at least three inverter stages and the parameters of the inverter stages are chosen to provide the first selected time delay and also a selected rise time of the first control pulse train.
7. A multiple-phase clock generator circuit as claimed in claim 1 wherein the first amplifier means is a push/pull amplifier having first and second inputs, the first node being connected to the first input and the second node being connected to the second input.
8. A multiple-phase clock generator circuit as claimed in claim 7 wherein the first connection means includes a trans-istor switch having two controlled electrodes, one controlled electrode being connected to the first node and the other con-trolled electrode being connected to the first input of the first amplifier means and a control electrode connected to the feedback means.
9. A multiple-phase clock generator circuit as claimed in claim 8 wherein the transistor switch means is a field-effect transistor of the metal-oxide-semiconductor type having its gate electrode connected to the feedback means and its drain-source path connected between the first node and the first input of the first amplifier means.
10. A multiple phase clock generator circuit for producing at least two clock phases of the type having:
an oscillator source means, having first and second nodes, for producing complementary pulse trains at said first and second nodes, respectively;
first and second amplifier means for producing one of said clock phases at the output of each said amplifier means, the clock phases being pulse trains, the pulses of each being pro-duced at the output of the respective amplifier means in response to an enabling indication applied to its input;
first coupling means for connecting said first node to said first amplifier means, a specified level of the pulse train at the first node being coupled as the enabling indication to the first amplifier means;
said first coupling means including first feedback means connected to the output of the second amplifier means to dis-able the coupling of the enabling indication to the first amplifier means in response to a specified level of the clock phase at the output of the second amplifier means;
characterized in that:
the first coupling means further includes a direct and permanent connection between the second node and the first amplifier means, said direct connection providing a discharge path from the output of the first amplifier means in response to a specified level of the pulse train at the second node; and the first feedback means includes adjustable means for delaying the feedback signal from the output of the second amplifier means so that the coupling of the enabling indication to the first amplifier means is possible only a first selected time interval after the clock phase at the output of the second amplifier means goes from a first specified level to a second specified level;
whereby a defined time separation is provided between a pulse of one of the clock phases at the output of the second amplifier means and a succeeding pulse of the other clock phase at the output of the first amplifier means.
an oscillator source means, having first and second nodes, for producing complementary pulse trains at said first and second nodes, respectively;
first and second amplifier means for producing one of said clock phases at the output of each said amplifier means, the clock phases being pulse trains, the pulses of each being pro-duced at the output of the respective amplifier means in response to an enabling indication applied to its input;
first coupling means for connecting said first node to said first amplifier means, a specified level of the pulse train at the first node being coupled as the enabling indication to the first amplifier means;
said first coupling means including first feedback means connected to the output of the second amplifier means to dis-able the coupling of the enabling indication to the first amplifier means in response to a specified level of the clock phase at the output of the second amplifier means;
characterized in that:
the first coupling means further includes a direct and permanent connection between the second node and the first amplifier means, said direct connection providing a discharge path from the output of the first amplifier means in response to a specified level of the pulse train at the second node; and the first feedback means includes adjustable means for delaying the feedback signal from the output of the second amplifier means so that the coupling of the enabling indication to the first amplifier means is possible only a first selected time interval after the clock phase at the output of the second amplifier means goes from a first specified level to a second specified level;
whereby a defined time separation is provided between a pulse of one of the clock phases at the output of the second amplifier means and a succeeding pulse of the other clock phase at the output of the first amplifier means.
11. A multiple phase clock generator circuit as claimed in claim 10 further comprising, second coupling means connecting said second node to said second amplifier means, a specified level of the pulse train at the second node being coupled as the enabling indication to the second amplifier means;
second feedback means for disabling the coupling of the enabling indication to the second amplifier means in response to a specified level of the clock phase at the output of the first amplifier means; and the second feedback means including adjustable means for delaying the feedback signal from the output of the first amplifier means so that the coupling of the enabling indication to the second amplifier means is possible only a second selected time interval after the clock phase of the output of the first amplifier means goes from a first specified level to a second specified level.
second feedback means for disabling the coupling of the enabling indication to the second amplifier means in response to a specified level of the clock phase at the output of the first amplifier means; and the second feedback means including adjustable means for delaying the feedback signal from the output of the first amplifier means so that the coupling of the enabling indication to the second amplifier means is possible only a second selected time interval after the clock phase of the output of the first amplifier means goes from a first specified level to a second specified level.
12. A multiple phase clock generator circuit as claimed in claim 11, wherein the first and second amplifiers are push/pull amplifiers having first and second inputs;
the first coupling means includes a transistor switch for disabling the coupling of the enabling indication to the first amplifier means; and the second coupling means includes a transistor switch for disabling the coupling of the enabling indication to the second amplifier means;
the transistor switch of the first coupling means having two controlled electrodes, one being connected to the first node and the other being connected to the first input of the first amplifier, and a control electrode connected to the first feedback means;
the transistor switch of the second coupling means having two controlled electrodes, one being connected to the second node and the other being connected to the first input of the second amplifier, and a control electrode connected to the second feedback means.
the first coupling means includes a transistor switch for disabling the coupling of the enabling indication to the first amplifier means; and the second coupling means includes a transistor switch for disabling the coupling of the enabling indication to the second amplifier means;
the transistor switch of the first coupling means having two controlled electrodes, one being connected to the first node and the other being connected to the first input of the first amplifier, and a control electrode connected to the first feedback means;
the transistor switch of the second coupling means having two controlled electrodes, one being connected to the second node and the other being connected to the first input of the second amplifier, and a control electrode connected to the second feedback means.
13. A multiple phase clock generator circuit as claimed in claim 11 wherein the first and second selected time intervals are different from one another.
14. A multiple phase clock generator circuit as claimed in claim 10 further comprising an auxiliary amplifier means for producing a third clock phase pulse train, the pulses of the third clock phase occurring only during the intervals between the end of the pulse of one of the clock phases and the begin-ning of the pulse of the other of the clock phases.
15. A multiple phase clock generator circuit as claimed in claim 10 wherein the first feedback means includes an odd num-ber of inverter stages.
16. A multiple phase clock generator circuit as claimed in claim 10 wherein the direct connection to the first amplifier means causes the first amplifier means to turn OFF, and wherein the disablable coupling to the first amplifier means causes the first amplifier means to turn ON.
17. A multiple phase clock generator circuit for producing at least two spaced apart clock phases comprising:
means for generating an input pulse train and a complementary pulse train which is a logical complement of the input pulse train;
a first amplifier and a second amplifier, each having two inputs and each producing one of the clock phases at its output;
first conductive means for directly coupling the complementary pulse train to one input of the first amplifier;
second conductive means for directly coupling the input pulse train to one input of the second amplifier;
first gating means for applying the input pulse train to the second input of the first amplifier in response to a first control signal;
second gating means for applying the complementary pulse train to a second input of the second amplifer in response to a second control signal;
first feedback means for monitoring the output of the first amplifier and producing the second control signal to which the second gating means responds, said first feedback means includ-ing means for delaying the output of the first amplifier; and second feedback means for monitoring the output of the second amplifier and providing the first control signal to which the first gating means responds, said second feedback means including means for delaying the output of the second amplifier;
whereby specified spacings are provided between the pulses of one of the clock phases and the pulses of the other of the clock phases.
means for generating an input pulse train and a complementary pulse train which is a logical complement of the input pulse train;
a first amplifier and a second amplifier, each having two inputs and each producing one of the clock phases at its output;
first conductive means for directly coupling the complementary pulse train to one input of the first amplifier;
second conductive means for directly coupling the input pulse train to one input of the second amplifier;
first gating means for applying the input pulse train to the second input of the first amplifier in response to a first control signal;
second gating means for applying the complementary pulse train to a second input of the second amplifer in response to a second control signal;
first feedback means for monitoring the output of the first amplifier and producing the second control signal to which the second gating means responds, said first feedback means includ-ing means for delaying the output of the first amplifier; and second feedback means for monitoring the output of the second amplifier and providing the first control signal to which the first gating means responds, said second feedback means including means for delaying the output of the second amplifier;
whereby specified spacings are provided between the pulses of one of the clock phases and the pulses of the other of the clock phases.
18. A multiple phase clock generator as claimed in claim 17 further including means responsive to the two clock phases for producing an intermediate clock phase in the time between the end of the pulse of one of the clock phases and the beginning of the pulse of the other of the clock phases, said intermediate clock phase producing means including means for monitoring when the pulses of both the one and the other clock phases are off, and means operative only when the one and the other clock pulses are off for producing a third clock phase intermediate to the two clock phases.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/579,759 US3961269A (en) | 1975-05-22 | 1975-05-22 | Multiple phase clock generator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1041615A true CA1041615A (en) | 1978-10-31 |
Family
ID=24318243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA249,019A Expired CA1041615A (en) | 1975-05-22 | 1976-03-29 | Multiple phase clock generator |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US3961269A (en) |
| JP (1) | JPS51147162A (en) |
| CA (1) | CA1041615A (en) |
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| DE2553517C3 (en) * | 1975-11-28 | 1978-12-07 | Ibm Deutschland Gmbh, 7000 Stuttgart | Delay circuit with field effect transistors |
| JPS53106552A (en) * | 1977-02-28 | 1978-09-16 | Toshiba Corp | Waveform shaping circuit |
| DE2713319C2 (en) * | 1977-03-25 | 1983-08-18 | Siemens AG, 1000 Berlin und 8000 München | Clock generator for digital semiconductor circuits |
| US4140927A (en) * | 1977-04-04 | 1979-02-20 | Teletype Corporation | Non-overlapping clock generator |
| DE2837855C2 (en) * | 1978-08-30 | 1984-03-29 | Siemens AG, 1000 Berlin und 8000 München | Pulse converter for clock supply of digital semiconductor circuits |
| JPS5787620A (en) * | 1980-11-20 | 1982-06-01 | Fujitsu Ltd | Clock generating circuit |
| EP0055073B1 (en) * | 1980-12-22 | 1985-07-10 | British Telecommunications | Improvements in or relating to electronic clock generators |
| US4456837A (en) * | 1981-10-15 | 1984-06-26 | Rca Corporation | Circuitry for generating non-overlapping pulse trains |
| US4433252A (en) * | 1982-01-18 | 1984-02-21 | International Business Machines Corporation | Input signal responsive pulse generating and biasing circuit for integrated circuits |
| IT1210945B (en) * | 1982-10-22 | 1989-09-29 | Ates Componenti Elettron | INTERFACE CIRCUIT FOR GENERATORS OF SYNCHRONISM SIGNALS WITH TWO OVERLAPPED PHASES. |
| JPS59121697A (en) * | 1982-12-27 | 1984-07-13 | Toshiba Corp | Shift register |
| EP0262412A1 (en) * | 1986-09-01 | 1988-04-06 | Siemens Aktiengesellschaft | Load-adapted CMOS clock generator |
| DE3708499A1 (en) * | 1987-03-16 | 1988-10-20 | Sgs Halbleiterbauelemente Gmbh | DIGITAL PRACTICAL DRIVER CIRCUIT |
| US5133064A (en) | 1987-04-27 | 1992-07-21 | Hitachi, Ltd. | Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices |
| JPH01149516A (en) * | 1987-12-04 | 1989-06-12 | Mitsubishi Electric Corp | Clock generating circuit |
| US4816700A (en) * | 1987-12-16 | 1989-03-28 | Intel Corporation | Two-phase non-overlapping clock generator |
| US5053639A (en) * | 1989-06-16 | 1991-10-01 | Ncr Corporation | Symmetrical clock generator and method |
| US4965471A (en) * | 1989-06-26 | 1990-10-23 | Eastman Kodak Company | BI-CMOS clock driver with reduced crossover current |
| US4943787A (en) | 1989-09-05 | 1990-07-24 | Motorola, Inc. | Digital time base generator with adjustable delay between two outputs |
| US5638542A (en) * | 1993-12-29 | 1997-06-10 | Intel Corporation | Low power non-overlap two phase complementary clock unit using synchronous delay line |
| US6239627B1 (en) * | 1995-01-03 | 2001-05-29 | Via-Cyrix, Inc. | Clock multiplier using nonoverlapping clock pulses for waveform generation |
| US6246278B1 (en) | 1995-12-22 | 2001-06-12 | Lsi Logic Corporation | High speed single phase to dual phase clock divider |
| DE19548629C1 (en) * | 1995-12-23 | 1997-07-24 | Itt Ind Gmbh Deutsche | Complementary clock system |
| US6104414A (en) * | 1997-03-12 | 2000-08-15 | Cybex Computer Products Corporation | Video distribution hub |
| US6385745B1 (en) * | 1997-06-30 | 2002-05-07 | Cypress Semiconductor Corp. | Phase independent receiver and/or decoder |
| US6052011A (en) * | 1997-11-10 | 2000-04-18 | Tritech Microelectronics, Ltd. | Fractional period delay circuit |
| US6175928B1 (en) * | 1997-12-31 | 2001-01-16 | Intel Corporation | Reducing timing variance of signals from an electronic device |
| US6037821A (en) * | 1998-05-28 | 2000-03-14 | General Electric Company | Digital programmable clock generator with improved accuracy |
| US6037809A (en) * | 1998-06-02 | 2000-03-14 | General Electric Company | Apparatus and method for a high frequency clocked comparator and apparatus for multi-phase programmable clock generator |
| US6031401A (en) * | 1998-06-08 | 2000-02-29 | Tritech Microelectronics, Ltd. | Clock waveform synthesizer |
| AU4496600A (en) * | 1999-04-30 | 2000-11-17 | Lockheed Martin Corporation | Method and apparatus for a single event upset (seu) tolerant clock splitter |
| US7612595B2 (en) * | 2006-09-19 | 2009-11-03 | Melexis Tessenderlo Nv | Sequence independent non-overlapping digital signal generator with programmable delay |
| TWI514770B (en) * | 2014-03-10 | 2015-12-21 | Realtek Semiconductor Corp | DC voltage generation circuit and pulse generation circuit thereof |
| US10613575B1 (en) * | 2019-05-03 | 2020-04-07 | Realtek Semiconductor Corp. | Method and apparatus for generating high-speed quadrature clock |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3292100A (en) * | 1966-01-04 | 1966-12-13 | Gen Electric | Pulse generator with multiple phasedisplaced outputs |
| US3441751A (en) * | 1966-10-04 | 1969-04-29 | Rca Corp | Two phase clock pulse generator employing delay line having input-output means and characteristic impedance termination means at each end |
| US3590280A (en) * | 1969-11-18 | 1971-06-29 | Westinghouse Electric Corp | Variable multiphase clock system |
| US3668436A (en) * | 1969-12-15 | 1972-06-06 | Computer Design Corp | Circuit apparatus for supplying first and second trains of mutually exclusive clock pulses |
| US3648181A (en) * | 1970-10-22 | 1972-03-07 | Spacetac Inc | Pulse generating circuit for producing pulses of amplitude which is a multiple of the amplitude of the source voltage |
| US3740660A (en) * | 1971-05-27 | 1973-06-19 | North American Rockwell | Multiple phase clock generator circuit with control circuit |
| US3735277A (en) * | 1971-05-27 | 1973-05-22 | North American Rockwell | Multiple phase clock generator circuit |
-
1975
- 1975-05-22 US US05/579,759 patent/US3961269A/en not_active Expired - Lifetime
-
1976
- 1976-03-29 CA CA249,019A patent/CA1041615A/en not_active Expired
- 1976-05-20 JP JP51057336A patent/JPS51147162A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US3961269A (en) | 1976-06-01 |
| JPS51147162A (en) | 1976-12-17 |
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