CA1047610A - High density logic array - Google Patents
High density logic arrayInfo
- Publication number
- CA1047610A CA1047610A CA238,824A CA238824A CA1047610A CA 1047610 A CA1047610 A CA 1047610A CA 238824 A CA238824 A CA 238824A CA 1047610 A CA1047610 A CA 1047610A
- Authority
- CA
- Canada
- Prior art keywords
- array
- input
- lines
- product term
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
Abstract
HIGH DENSITY LOGIC ARRAY
ABSTRACT
This specification describes arrays for performing logic functions. In these arrays, input variables can be fed to either or both ends of input lines. When input variables are fed to both ends of a line, the line is broken to separate logic performed on the variables fed to one end from the logic performed on the variables fed to the other end.
The arrays are compounded. Two arrays are arranged on opposite sides of a third array and the output signals from the two arrays function as input variables to the third array. Input lines in the third array can also be broken to separate array logic functions performed in the third array on variables fed to the opposite ends of such lines.
ABSTRACT
This specification describes arrays for performing logic functions. In these arrays, input variables can be fed to either or both ends of input lines. When input variables are fed to both ends of a line, the line is broken to separate logic performed on the variables fed to one end from the logic performed on the variables fed to the other end.
The arrays are compounded. Two arrays are arranged on opposite sides of a third array and the output signals from the two arrays function as input variables to the third array. Input lines in the third array can also be broken to separate array logic functions performed in the third array on variables fed to the opposite ends of such lines.
Description
16 B~CKGROUND OF T~IE INVENTION
17 The present invention relates to arrays for per~orm-18 in~ loyic functions and more particularly it is related 19 to increasing the number of logic fu,nctions performed in an array without increasing the size of the array.
21 The performing of logic in matr:ices of identical 22 circuit elements e~ch located at a unique intersection of 23 .an input and output line in a grid of intersecting input 24 and output lines is well known. It is also well known that the standardization of logic circuit layouts stemming 26 from the use of logic matrices or arrays results in the 27 simplification and acceleration of the design and manu-28 facturing of monolithic chips containing logic performing ,.
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17 The present invention relates to arrays for per~orm-18 in~ loyic functions and more particularly it is related 19 to increasing the number of logic fu,nctions performed in an array without increasing the size of the array.
21 The performing of logic in matr:ices of identical 22 circuit elements e~ch located at a unique intersection of 23 .an input and output line in a grid of intersecting input 24 and output lines is well known. It is also well known that the standardization of logic circuit layouts stemming 26 from the use of logic matrices or arrays results in the 27 simplification and acceleration of the design and manu-28 facturing of monolithic chips containing logic performing ,.
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2 has been limited. A major cause in this limited use has been
3 that only a small percentage of the intersections in an array ; 4 turn out to be usable in performing logic functions. This S percentage o~ useful intersections in the arrays results in 6 iner~icient use of the surface area of the monolithic chips 7 on which the arrays are fabricated. It turns out, that for 8 most applications, the design and manufacturing efficiencies 9 of logic arrays are outweighed economically by their inefficient use of chip area and it is less expensive to spend additlonal ll time and effoxt to design and manufacture logic chips with 12 highly customized layouts that are less orderly than logic 13 arrays but perform for more logic functions in a given area 14 of a monolithic chip.
The small percentage of usable logic circuits in a 16 logic array is a result of the orderliness of the array.
17 Once input and output lines are used to perform a given 18 logic Eunction they cannot be used in performing other 19 unrelated logic functions without hopelessly unbalancing the logic. As a ~esult, large areas of the array contain 21 intersections of input and output lines that are barren 22 of usable circuits.
23 A number of schemes have been devised to reduce the 24 sparseness of the loglc on logic array chips. One such ~scheme is to use~a plurality of decoders to feed input 26 varlables to the input lines of a single array allowing ~27 a number of very powerful loglc functions to be efficiently `, :.
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The small percentage of usable logic circuits in a 16 logic array is a result of the orderliness of the array.
17 Once input and output lines are used to perform a given 18 logic Eunction they cannot be used in performing other 19 unrelated logic functions without hopelessly unbalancing the logic. As a ~esult, large areas of the array contain 21 intersections of input and output lines that are barren 22 of usable circuits.
23 A number of schemes have been devised to reduce the 24 sparseness of the loglc on logic array chips. One such ~scheme is to use~a plurality of decoders to feed input 26 varlables to the input lines of a single array allowing ~27 a number of very powerful loglc functions to be efficiently `, :.
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,`'': ' ',' . ' ' 1 performed in a sinyle array. Another scheme used to reduce 2 sparseness involves using compound arrangement of arrays 3 called programmable array logic chips (PLA's). These involve
4 feeding -the output of a first array called a product term ; 5 yenerator, or an AND array, to a second array called the 6 sum of a product term gene~rator, or an OR array, so as to 7 increase the number of functions that can be performed without geometrically increasing the number of array inter-g sections needed to perform those functions. While these modifications increase the number of useful logic circuits 11 that can be placed in an array logic chip, they do not 12 solve the problem of the unusable portions of the input 13 and output lines that is discussecl above.
1~ TIIF INV~NTION
lS In accordance with the present invention, the size of 16 the unusable portions of the input and output lines is 17 reduced. This is accomplished by feediny input variables 18 to either or both ends of the input lines. When input 19 variables are fed to both ends of an input lina the input line is segmented to separate the logic functions performed 21 on input variables fed to one end from lo~ic functions per-22 formed on input variables fed to the other. This arrangement 23 cuts in half the length of the output lines needed to per-24 form logic on a given number of input ~ariables. The -reduction in length of these output lines is compounded in 26 the preferred embodiment of the present invention by 27 splitting the AND array of a PLA into two and arranging 2~ the two halves on opposite sides of the OR array of the 29 PLA. The OR array then receives outputs from both halves KI9-74-01~ -3-. . . - , :.
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1 of the split AND array on opposite ends o~ its input lines.
2 Input lines in both the AND and OR arrays are then segmented 3 in the manner described above to separate different logic 4 functions being performed on the same line.
s Therefore, it is an ob~ect of the present invention to 6 increase the amount of logic that can be performed ~y a 7 loyic array circuit chip of a given size~
8 Another object o~ the present invent:ion is to reduce 9 the size of se~ments of the array that cannot be used to perform usable logic functions.
11 A further object of the invention is to provide array 12 logic that is more adaptable to the use of performing dif-13 ferent logic functions.
]~ E DRAWINGS
'I'hese and other o~jects, fecltures an(l advantacJes oE the 16 invention will be apparent from the following more particular 17 description of the preferred em~odiments of the invention of 18 which:
19 FIGURE 1 is a schematic representation of a layout for a programmed logic array chip incorporating the present 21 invention;
22 E'IGURE 2 is a chart o~ the logic functions that can be 23 performed on any two input variables in the programmed logic 24 array chip of Fig. l; ~ :
FIGUR~ 3 is a plan view showing in more detail the 2S layout o~ the AND array in Fig. l;
27 FIGURE 4 is a sectional view taken along line 4-4 in 28 Fig. 3;
29 FIGURE 5 is a sectional view taken through a via hole in '.
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1 an ~rray nlo(lule laye~d out in accordance with the schematic 2 o~ ri~. 1;
3 FIGURE 6 is an electrical schematic of an alternate 4 layout scheme Eor the AND array in Fig. l;
FIGURE 7 is a plan view of the layout for the schematic 6 of Fig. 6;
7 FIGURE 8 is a sectional view taken along line 8-8 in 8 Fig. 7;
9 FIGUR~S 9 and 10 are more detailed plan views of the sys-tem of rails shown in Fig. l; and 11 FIGURE 11 is a section taken along line 11-11 in 12 Fig. 9.
- .
14 Referring now to Fig. 1, two AND arrays 10 ancl 12 are 15 located on opposite sides of an OR array 14, Each oE the AND ; ;~
16 arrays 10 and 12 is connected to a plurality of two bit input 17 decoders 16 located on both sides of the AND arrays. ~hese 18 decoders 16 pxovide four output combinations of two input 1~ vari.lbles. 'l~he decoders 16 receive input variables on input linea 18 and reed each one oE its four output com~inations 21 oE two variables to a different input line 20 in the arrays 22 10 and 12. Because each input line 20 is connected to two 23 different decoders 16 it can receive two diEferent combinations 24 of two variables.
Arranged orthogonally with respect to the input lines 20 26 are a plurality of parallel output lines 22 that form a grid 27 with the input lines. Located at intersections oE the 28 input and output lines 20 and 22 are logic performing devices ''.
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r 1 24 that will perform a logical operation, in this case an 2 AND operation, on data placed on the input lines 20 and 3 provide the resultant on the output lines 22.
4 The output lines 22 of the AND arrays 10 and 12 are connected to the input lines 26 for the OR array 14 posi-6 tioned between the two AND arrays. These input lines 26 7 intersect the output lines 28 of the OR array. Located 8 at these intersections are logic producing elements 29 that 9 perform an OR function with respect to the signals received from the ~ND arrays and provide the resultant on the OlltpUt 11 lines 28. The output lines 28 supply set and reset inputs 12 to a plurality o~ JK latches 30 which are joined in shift . . . .
13 re~ister fashion so that data cannot only be pLaced in 14 each latch 30 from the OR array but can also be placed onto line 32 from some external source and shifted from one latch, 16 to another.
17 As can be seen, logical functions can be performed on 18 the inputs to the two bit decoders in the two bit decoders 16, 19 the AND arrays 10 and 12, the OR array 14 and the JK latches 30. The different logical functions that can be performed 21 in the ~ND arrays 10 and 12 on any two inputs to the decoders 22 16 are shown in Fig. 2. The headings on the column oE this 23 graph show the four possible outputs of any one of the two 24 bit decoders 16 that receives a signal, a, on one of its inputs and a signal, b, on the other input. The legends 26 on each row indicates the logical function that will be 27 provided on an output line when the outputs of the decoder 28 marked with a binary "1" in that row are ANDED together , .
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1 by couplincJ the proper input lines 20 to that output line 2 22 with lo~ic per~ornling elemen-ts 29. r~rEorming lo~Jic 3 operations using arrays and two bit decoders in this manner 4 is well known and can be found in Weinberger U.S. Patent No.
3,761,902, issued Sept. 25/73 and commonly assigned herewith.
6 In accorclance with the present invention, the :Loyical 7 functions are more dens~ly arranged on array logic chips 8 than possible in -the prior art. This is accomplishe~ ~y '3 arrangin~ ~ecoders 16 on bo~h sides of ~he AND arrays 10 ]0 an~ 12 and se(3montin~ the input lines 20 and 28 in the ANI) 11 and O~ arrays -to separate the func-tions performed on the 12 different inputs to the same line. ~s can be seen in Fig. 1, 13 the function performed in the first row of AND array 10 is 14 the Exclusive OR function of the two signals coming in Erom the decoder 16a in the upper left hand side of the AND array.
16 It is fed into the first JK 30a which receives the resultant 17 sic3nal on both its set and reset inputs preventing the JK
18 from latching thereby providing an unla-tched output signal.
19 A number o~ other functions are performed in this array 10 involving the output signals from decoders on both the right 21 and left hand side. When they involve the same input lines, 22 they are separated by breaks in the input lines from functions 23 being performed on the right hand side. A dotted line 36 24 down through these breaks indicates the separation of arrays 10 and 12 into portions performing functions in-26 volving the input variables to the left hand decoders and 27 .in those involving input variables to the right hand decoders.
28 Similarly the lower array is divided by a dotted line 36 , ' '~
~0~6~() 1 along the breaks in the input lines. However, you will 2 note that the input lines 20 are not always broken. They 3 continue completely across the array such as lines 20a and 4 20b do when they are involved in performing functions on inputs to either but not both the left or the right decoders.
6 Some times it is desirable that functions fed to opposite .. . .
7 ends of the same input line 20c be ANDED. This is accom-8 plished within terminal boxes 31 at each end of the AND
9 arrays 10 and 12 by providing a connection 34 between two output lines 20a and 22b to which the input line 20b is 11 coupled by logic performing elements 24a and b.
12 Like in the AND arrays, the input lines 26 of the OR
13 array are broken to separate functions performed on input 14 variables received from the top AND ~rray 10 from ~unctions per~ormed on in~)ut variables recei~ed ~rom the bottom ~ND
16 array 12a. Dotted line 38 has been placed through the O~ ;
17 array to show how the space in the OR array is divided up `-~
18 between that performing inputs from the top and those per-19 forming logical functions from inputs on the bottom AND
array. It should be noted that line 28a extends all the 21 way through the OR array so that it performs a logical 22 function on input variables supplied to both the top and 23 bottom arrays. This may be desired in some cases.
24 By examininy the dotted lines 36 and 38, you can see 25 that the use of the arrays is more intense than it would `
26 be if all the inputs were on one side of the array. First 27 of all with all the inputs on one side, there would not be 28 double use of input lines. In other words, portions of . ~ . ; .
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1 input lines not used to perform functions involving one 2 set of input variables could not be used to perform functions 3 involving another. Also if the decoders were all placed on 4 one side of the line and the two AND arrays were added together, the length of the output lines would have to be 6 extended considerably and larger portions of these output 7 lines would be unusable. For instance, output line 22d 8 involved in line performing an Exclusive OR of inputs a 9 and b to the first decoder 16a would be four times as long if all twelve decoders 16 of the two AND arrays 10 and 12 11 were placed on one side of a single array and therefore 12 would have four times as much unusable area of the chip 13 arranged along it than is in the arrangement shown in Fig. 1.
14 In the same way, division of the OR array decreases the amount of unused area on the chips.
16 The maximum extent of the improvement can be analyzed 17 in the following manner. Assume that a PLA having X inputs, 1~ Y outputs and N product terms is n~eded. The following 19 wouId be a comparison of the size of the arrays needed in accordance with the prior art and the present invention.
21Prior Art Present Invention 22 2XN N AND ARRAY(S) : ' ' .: ~
242XN+~N XN ~ YN TOTAL
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:~ 1 if the input/output ratio was one e~ x=Yr the present .: .
2 invention results in the following array size reductions :
4 OR 2 Improvement Factor 6 Further improvement is possible if the output lines 28 7 of the OR array were not required to intersect all product 8 terms. For example, if the hori~ontal output lines 28 shown 9 in Fig. 1 were terminated at the midpoint of the array and outputted on both sides of the array 14 the array sizes 11 would be; : ~:
12 Prior Art Present Invention 13 2~N XN AND ARRAY
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16 again i:E the input to output ra-tio were one 18 OR 4 Improvement Factor This indicates that for a unity I/O ratio the improvement 21 factor of.between 3 and 4 can be obtained by using the 22 present invention. While a complete division of the OR
23 array 14 may cause problems, a division of the OR array 24 into Y/2 lines feeding completely through (as shown~ and 25 Y/2 lines terminating at the midpoint is viewed as pre- ..
26 senting no difficulty in impleménting the logical personality..
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L76~3 1 Figures 3 and 4 show how the AND arrays 10 and 12 can 2 be fabricated in FET technology using a combination of yate 3 and metal personalization of the array. A number of diffusion stripes 40 and 42 are made into the substrate 44 for the array.
These diffusions 40 and 42 are the source and sink diffusions 6 for FET's which are the logic performing elements 24 of the 7 array. In addition the diffusions 40 serve as the output 8 lines 22 of the array. The input lines 20 of the array are 9 metal stripes arranged at right angles to the diffusions 40 and 42 on top of thin and thick layers 48 and 50 of oxide 11 that decouple the lines. Whenever a logic function is to 12 be performed at the intersection a gate metalization 52 13 is placed over a set of diffusions 40 and 42 on the thin 14 metal oxide layer 48 and under one of the metal stripes.
Where there is no logic function to be performed at the 16 intersection of a particular input line and output line no l7 such g~lt~ et~lization pattern i5 placed between the stripes 19 As can be seen from Figs. 3 and 4, breaks 52 occur in the metal stripes between functions performed on one 21 side of the stripes and functions performed on the other 22 side of the skripes. Thus, it is quite apparent with this 23 technique that the manufacturing steps of all the chips 24 would be the same until the point of laying out the gates and metalization. The chip can then be personalized to 26 perform the desired logic functions by adding the metal 27 gates where the logic function is to be performed at an 28 intersection and providing ~or breaks in the line whe:re 29 functions are performed on opposite ends of the same line.
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1 In the completed chip, each metal line 46 becomes 2 the input to an FET logic circuit in which the gate 3 metalization 52 is the gate of an FET having a source 4 connected by diffusion stripe 40 through gated FETs to some positive voltage +V and connected to ground by 6 diffusion stripe 42. The gated FETs are periodically 7 rendered conductive by a clock pulse to charge the 8 ~iEfusion stripcs, 40 positive. Durin~3 alterna-te perio(ls 9 the outputs of decoders lG are yated onto th~ metal stripes 48. When a signal is received from the decoders 16 on 11 metal stripes 48 it biases each FET connected thereto ~;
12 conductive for providing a path to ground changing the ~`
13 voltage on the diffusion stripe 40 or output line 22 from 14 ~V to ground. Since the outputs of the decoders are the negative of the inputs to the decoders a logical AND
~, 16 function is performed in the arrays 10 and 12 on the outputs 17 Oe the decoders.
18 The OR array 14 is quite similar to the AND array 19 e~cept the OR array is arranged with the metal stripes i 20 vertically and the diffusion stripes horizontally.
21 Furthermore, the output of the AND array is positive 22 with respect to the input of the decoders so that a NOR
23 ~unction is performed by elements 29 in the OR array on 24 the outputs of the AND arrays. The output of the OR array -~
., .; ., .. :
is inverted in the latches 30 so that an OR function is 26 performed on the outputs of the AND array in the OR array : ::
j 27 and the latches. The outputs of the latches are gated on 28 while the diffusions of the AND array are being charged.
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:' ~ ''' . '" ~' ,' ~ ' : ' ' ':.~ '. ':, ' . -:' . ' , 1 Unlike the dif~usions in the ~ND array, the diffusions 40 2 in the OR arra~ are continuously charged.
3 I'o make the connection between the AND arrays and the 4 OR arrays, one of the metal stripes 56 in the OR array connects to one of the diffusions 40 in the AND array by 6 way of a metalized via hole 54 through the oxide layers 7 48 and 50.
8 While a gate-metal personalization is desirable in 9 most cases, there are situations in which it is desirable to have circuit arrangement in which logic can be changed 11 by a purely metal personalization process. Such an arrange-12 ment is shown in Fig. 6. In the embodiment of Fig. 6 each 13 of the intersections of input and output lines 20 is popu-14 lated by an FET 24 for performing logic. Whether the FET
is Eunctioning or not depends on how its yate is connected.
16 If the FET 24 is not being used its gate is grounded to hold 17 the FET biased off. If the FET 24 is being used to perform 18 logic, its gate is connected to one of the input lines 22 19 to allow the F~T to be rendered conducting or non conducting by the pulses placed on the input line 20. ~s shown in Fiys.
21 7 and a, each F¢T is provided with a gate and metal connections 22 58 are selectively made Erom the gates 52 to the me-tal stripes 23 46 or to a diffusion stripes 42 through a via connection 10 ;~
24 in one processing step. It should be understood that the invention is not limited to either one of the above 26 personalization techniques and can be applied equally as ;
27 well to a number o-f technologies. In particular, it can 28 be applied to bi-polar technology instead of the described 29 FET technology.
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As described in commonly assigned U.S. Patent No. 3,936,812 which issued on February 3, 1976 and entitled "Segmented Parallel Rail Paths For Input/Output Signals", filed on even date herewith, the connections to the inputs and outputs of the arrays can be personalized in accordance with the functions to be performed in the array. To this end, a plurality of vertical rails 62 are provided on the chip on each side of the arrays 10, 12 and 14. Arranged orthogonally with respect to these rails 62 are the inputs 18 to the decoder 16, the outputs 66 of the JK's and the inputs 68, the off chip drivers 66. As shown in FIGURES 7, 10 and 11 the input lines 18 and 68 and the output lines 67 are metallized patterns on the surface of the oxidation layer 48-50 of the chip. The rails 62 are each made up of alternating metal portions 70 on top of the oxidation layer 48-50 and diffused por-tions 72 in the substrate 44 of the chip. These are joined by metalllzed via holes 74 that pass through the oxidation layer 48-50. The diffused portions 72 are located opposite the off chips drivers 66, the decoders 16 and the latches 30 so that the lines to the drivers, latches and decoders can pass over the diffused portions of certain oF the rails 62 and be connected -~
to metallized portions of other of the rails. The rails are segmented by openings 76 in the metal portions 70 to electrically isolate two or more different signals contained on the same rail on electrically isolated segments of the sarne rail. For instance, suppose JK 30a is to be connected to the off chip driver 66a, the metal lines 67 and 68 are connected to opposing metal por-tions 70a and 70b of the same rail 62a. The metal lines ' ;
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1 67 and 68 pass over the diffused portions 72 of the other 2 rails 62 so they do not short the rails together. Furthermore, 3 the metallized portions 70a and 70b of ra:il 62a both contain 4 an opening to isolate the segment of rail 62a containing the connection between the JK 30a and the off chip driver 66a 6 from the remainder of the rail 52a so that the remainder 7 of the rail can be used to carry other signals to the array such as ~he connection b~tween JK 30b and -the input -to two-bi-t ~ ~eco~er 16~. t~ should be noted that the inputs to the decoders 16 are positive and the outputs of the JK are also 11 positive so the outputs of the JK 30a can be directly con-12 nected back to the decoders 16b permitting sequential logic 13 to be performed with the arrays 10, 12, 14 and JK's 30 14 without the use of off chip connections between the JK's and the decoders. Connected across the top of the chip and 16 the bottom oE th~ chip are~a number of pads 74a which l7 ~un~tion oxclusivcly as illpUt pads ~or in~ut signals onto lf3 thc ciliE) to bc Fed to the inputs of the clecoders 16. They 19 are connected to the rails 62 by a nletalization pattern determined by the functions to be performed on the chips.
21 The pads 74a along the side of the chip may be used either 22 as output pads or input pads. If they are used as output 23 pads they are connected by metal personalization 76 to one 24 of the off chip drivers 66. If they are used as input pads along with pads on the bottom and top of the array are con-26 nected by personalization directly to the rails 62.
27 Above we have described one embodiment of the invention.
28 As can be seen, it permits alternate uses for various ele-29 ments in the array logic chip. In this way it is similar . . .~ , . .
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1 to a virtual memory which from the outside appears to have 2 a larger capacity -than it actually does. The reason for 3 this is that like in the memory the actua:L capacit~ is used very ine~Lriciently so that the lines and terminals can be assigned duplicate use so long as those uses do not 6 conflict.
7 In order tv make the understanding of the present 8 invention easi.er, the illustrated PLA was limited in size 9 and number of associated circuits. In fact, sub6tantially larger arrays are anticipated. For instance, two ~ND
11 arrays having 48 inputs and each being served by 24 de-12 coders would be more reasonable than the illustrated ~ND .:
13 arrays. In the same way an OR array havin~ 112 output.s 1~ :eeccl:ing 56 ~K's would also be more in the order o:E what 1.5 actually would be :Eound on one o:E these chi.ps.
16 While the invention has been particularly shown and 17 described with reference to a preferred embodiment thereof, 18 it will be understood by those skilled in the art that the 19 above and other changes in form and details may be made therein without departing from the spirit and scope of 21 the invention.
22 What is claimed is:
' ' ' -KI9-74~018 -16-;
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1~ TIIF INV~NTION
lS In accordance with the present invention, the size of 16 the unusable portions of the input and output lines is 17 reduced. This is accomplished by feediny input variables 18 to either or both ends of the input lines. When input 19 variables are fed to both ends of an input lina the input line is segmented to separate the logic functions performed 21 on input variables fed to one end from lo~ic functions per-22 formed on input variables fed to the other. This arrangement 23 cuts in half the length of the output lines needed to per-24 form logic on a given number of input ~ariables. The -reduction in length of these output lines is compounded in 26 the preferred embodiment of the present invention by 27 splitting the AND array of a PLA into two and arranging 2~ the two halves on opposite sides of the OR array of the 29 PLA. The OR array then receives outputs from both halves KI9-74-01~ -3-. . . - , :.
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1 of the split AND array on opposite ends o~ its input lines.
2 Input lines in both the AND and OR arrays are then segmented 3 in the manner described above to separate different logic 4 functions being performed on the same line.
s Therefore, it is an ob~ect of the present invention to 6 increase the amount of logic that can be performed ~y a 7 loyic array circuit chip of a given size~
8 Another object o~ the present invent:ion is to reduce 9 the size of se~ments of the array that cannot be used to perform usable logic functions.
11 A further object of the invention is to provide array 12 logic that is more adaptable to the use of performing dif-13 ferent logic functions.
]~ E DRAWINGS
'I'hese and other o~jects, fecltures an(l advantacJes oE the 16 invention will be apparent from the following more particular 17 description of the preferred em~odiments of the invention of 18 which:
19 FIGURE 1 is a schematic representation of a layout for a programmed logic array chip incorporating the present 21 invention;
22 E'IGURE 2 is a chart o~ the logic functions that can be 23 performed on any two input variables in the programmed logic 24 array chip of Fig. l; ~ :
FIGUR~ 3 is a plan view showing in more detail the 2S layout o~ the AND array in Fig. l;
27 FIGURE 4 is a sectional view taken along line 4-4 in 28 Fig. 3;
29 FIGURE 5 is a sectional view taken through a via hole in '.
, 7~
1 an ~rray nlo(lule laye~d out in accordance with the schematic 2 o~ ri~. 1;
3 FIGURE 6 is an electrical schematic of an alternate 4 layout scheme Eor the AND array in Fig. l;
FIGURE 7 is a plan view of the layout for the schematic 6 of Fig. 6;
7 FIGURE 8 is a sectional view taken along line 8-8 in 8 Fig. 7;
9 FIGUR~S 9 and 10 are more detailed plan views of the sys-tem of rails shown in Fig. l; and 11 FIGURE 11 is a section taken along line 11-11 in 12 Fig. 9.
- .
14 Referring now to Fig. 1, two AND arrays 10 ancl 12 are 15 located on opposite sides of an OR array 14, Each oE the AND ; ;~
16 arrays 10 and 12 is connected to a plurality of two bit input 17 decoders 16 located on both sides of the AND arrays. ~hese 18 decoders 16 pxovide four output combinations of two input 1~ vari.lbles. 'l~he decoders 16 receive input variables on input linea 18 and reed each one oE its four output com~inations 21 oE two variables to a different input line 20 in the arrays 22 10 and 12. Because each input line 20 is connected to two 23 different decoders 16 it can receive two diEferent combinations 24 of two variables.
Arranged orthogonally with respect to the input lines 20 26 are a plurality of parallel output lines 22 that form a grid 27 with the input lines. Located at intersections oE the 28 input and output lines 20 and 22 are logic performing devices ''.
~ KI9-74-018 -5-.' .
- - ; - . : . I ~ .
r 1 24 that will perform a logical operation, in this case an 2 AND operation, on data placed on the input lines 20 and 3 provide the resultant on the output lines 22.
4 The output lines 22 of the AND arrays 10 and 12 are connected to the input lines 26 for the OR array 14 posi-6 tioned between the two AND arrays. These input lines 26 7 intersect the output lines 28 of the OR array. Located 8 at these intersections are logic producing elements 29 that 9 perform an OR function with respect to the signals received from the ~ND arrays and provide the resultant on the OlltpUt 11 lines 28. The output lines 28 supply set and reset inputs 12 to a plurality o~ JK latches 30 which are joined in shift . . . .
13 re~ister fashion so that data cannot only be pLaced in 14 each latch 30 from the OR array but can also be placed onto line 32 from some external source and shifted from one latch, 16 to another.
17 As can be seen, logical functions can be performed on 18 the inputs to the two bit decoders in the two bit decoders 16, 19 the AND arrays 10 and 12, the OR array 14 and the JK latches 30. The different logical functions that can be performed 21 in the ~ND arrays 10 and 12 on any two inputs to the decoders 22 16 are shown in Fig. 2. The headings on the column oE this 23 graph show the four possible outputs of any one of the two 24 bit decoders 16 that receives a signal, a, on one of its inputs and a signal, b, on the other input. The legends 26 on each row indicates the logical function that will be 27 provided on an output line when the outputs of the decoder 28 marked with a binary "1" in that row are ANDED together , .
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1 by couplincJ the proper input lines 20 to that output line 2 22 with lo~ic per~ornling elemen-ts 29. r~rEorming lo~Jic 3 operations using arrays and two bit decoders in this manner 4 is well known and can be found in Weinberger U.S. Patent No.
3,761,902, issued Sept. 25/73 and commonly assigned herewith.
6 In accorclance with the present invention, the :Loyical 7 functions are more dens~ly arranged on array logic chips 8 than possible in -the prior art. This is accomplishe~ ~y '3 arrangin~ ~ecoders 16 on bo~h sides of ~he AND arrays 10 ]0 an~ 12 and se(3montin~ the input lines 20 and 28 in the ANI) 11 and O~ arrays -to separate the func-tions performed on the 12 different inputs to the same line. ~s can be seen in Fig. 1, 13 the function performed in the first row of AND array 10 is 14 the Exclusive OR function of the two signals coming in Erom the decoder 16a in the upper left hand side of the AND array.
16 It is fed into the first JK 30a which receives the resultant 17 sic3nal on both its set and reset inputs preventing the JK
18 from latching thereby providing an unla-tched output signal.
19 A number o~ other functions are performed in this array 10 involving the output signals from decoders on both the right 21 and left hand side. When they involve the same input lines, 22 they are separated by breaks in the input lines from functions 23 being performed on the right hand side. A dotted line 36 24 down through these breaks indicates the separation of arrays 10 and 12 into portions performing functions in-26 volving the input variables to the left hand decoders and 27 .in those involving input variables to the right hand decoders.
28 Similarly the lower array is divided by a dotted line 36 , ' '~
~0~6~() 1 along the breaks in the input lines. However, you will 2 note that the input lines 20 are not always broken. They 3 continue completely across the array such as lines 20a and 4 20b do when they are involved in performing functions on inputs to either but not both the left or the right decoders.
6 Some times it is desirable that functions fed to opposite .. . .
7 ends of the same input line 20c be ANDED. This is accom-8 plished within terminal boxes 31 at each end of the AND
9 arrays 10 and 12 by providing a connection 34 between two output lines 20a and 22b to which the input line 20b is 11 coupled by logic performing elements 24a and b.
12 Like in the AND arrays, the input lines 26 of the OR
13 array are broken to separate functions performed on input 14 variables received from the top AND ~rray 10 from ~unctions per~ormed on in~)ut variables recei~ed ~rom the bottom ~ND
16 array 12a. Dotted line 38 has been placed through the O~ ;
17 array to show how the space in the OR array is divided up `-~
18 between that performing inputs from the top and those per-19 forming logical functions from inputs on the bottom AND
array. It should be noted that line 28a extends all the 21 way through the OR array so that it performs a logical 22 function on input variables supplied to both the top and 23 bottom arrays. This may be desired in some cases.
24 By examininy the dotted lines 36 and 38, you can see 25 that the use of the arrays is more intense than it would `
26 be if all the inputs were on one side of the array. First 27 of all with all the inputs on one side, there would not be 28 double use of input lines. In other words, portions of . ~ . ; .
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1 input lines not used to perform functions involving one 2 set of input variables could not be used to perform functions 3 involving another. Also if the decoders were all placed on 4 one side of the line and the two AND arrays were added together, the length of the output lines would have to be 6 extended considerably and larger portions of these output 7 lines would be unusable. For instance, output line 22d 8 involved in line performing an Exclusive OR of inputs a 9 and b to the first decoder 16a would be four times as long if all twelve decoders 16 of the two AND arrays 10 and 12 11 were placed on one side of a single array and therefore 12 would have four times as much unusable area of the chip 13 arranged along it than is in the arrangement shown in Fig. 1.
14 In the same way, division of the OR array decreases the amount of unused area on the chips.
16 The maximum extent of the improvement can be analyzed 17 in the following manner. Assume that a PLA having X inputs, 1~ Y outputs and N product terms is n~eded. The following 19 wouId be a comparison of the size of the arrays needed in accordance with the prior art and the present invention.
21Prior Art Present Invention 22 2XN N AND ARRAY(S) : ' ' .: ~
242XN+~N XN ~ YN TOTAL
KI9-74-018 ~ -9-: :
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:~ 1 if the input/output ratio was one e~ x=Yr the present .: .
2 invention results in the following array size reductions :
4 OR 2 Improvement Factor 6 Further improvement is possible if the output lines 28 7 of the OR array were not required to intersect all product 8 terms. For example, if the hori~ontal output lines 28 shown 9 in Fig. 1 were terminated at the midpoint of the array and outputted on both sides of the array 14 the array sizes 11 would be; : ~:
12 Prior Art Present Invention 13 2~N XN AND ARRAY
~ .
2XN+YN XN ~ YN TOTAL
16 again i:E the input to output ra-tio were one 18 OR 4 Improvement Factor This indicates that for a unity I/O ratio the improvement 21 factor of.between 3 and 4 can be obtained by using the 22 present invention. While a complete division of the OR
23 array 14 may cause problems, a division of the OR array 24 into Y/2 lines feeding completely through (as shown~ and 25 Y/2 lines terminating at the midpoint is viewed as pre- ..
26 senting no difficulty in impleménting the logical personality..
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KI9-74-018 -lO-. ~ , .
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L76~3 1 Figures 3 and 4 show how the AND arrays 10 and 12 can 2 be fabricated in FET technology using a combination of yate 3 and metal personalization of the array. A number of diffusion stripes 40 and 42 are made into the substrate 44 for the array.
These diffusions 40 and 42 are the source and sink diffusions 6 for FET's which are the logic performing elements 24 of the 7 array. In addition the diffusions 40 serve as the output 8 lines 22 of the array. The input lines 20 of the array are 9 metal stripes arranged at right angles to the diffusions 40 and 42 on top of thin and thick layers 48 and 50 of oxide 11 that decouple the lines. Whenever a logic function is to 12 be performed at the intersection a gate metalization 52 13 is placed over a set of diffusions 40 and 42 on the thin 14 metal oxide layer 48 and under one of the metal stripes.
Where there is no logic function to be performed at the 16 intersection of a particular input line and output line no l7 such g~lt~ et~lization pattern i5 placed between the stripes 19 As can be seen from Figs. 3 and 4, breaks 52 occur in the metal stripes between functions performed on one 21 side of the stripes and functions performed on the other 22 side of the skripes. Thus, it is quite apparent with this 23 technique that the manufacturing steps of all the chips 24 would be the same until the point of laying out the gates and metalization. The chip can then be personalized to 26 perform the desired logic functions by adding the metal 27 gates where the logic function is to be performed at an 28 intersection and providing ~or breaks in the line whe:re 29 functions are performed on opposite ends of the same line.
, KI9-74-018 ~11--.
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1 In the completed chip, each metal line 46 becomes 2 the input to an FET logic circuit in which the gate 3 metalization 52 is the gate of an FET having a source 4 connected by diffusion stripe 40 through gated FETs to some positive voltage +V and connected to ground by 6 diffusion stripe 42. The gated FETs are periodically 7 rendered conductive by a clock pulse to charge the 8 ~iEfusion stripcs, 40 positive. Durin~3 alterna-te perio(ls 9 the outputs of decoders lG are yated onto th~ metal stripes 48. When a signal is received from the decoders 16 on 11 metal stripes 48 it biases each FET connected thereto ~;
12 conductive for providing a path to ground changing the ~`
13 voltage on the diffusion stripe 40 or output line 22 from 14 ~V to ground. Since the outputs of the decoders are the negative of the inputs to the decoders a logical AND
~, 16 function is performed in the arrays 10 and 12 on the outputs 17 Oe the decoders.
18 The OR array 14 is quite similar to the AND array 19 e~cept the OR array is arranged with the metal stripes i 20 vertically and the diffusion stripes horizontally.
21 Furthermore, the output of the AND array is positive 22 with respect to the input of the decoders so that a NOR
23 ~unction is performed by elements 29 in the OR array on 24 the outputs of the AND arrays. The output of the OR array -~
., .; ., .. :
is inverted in the latches 30 so that an OR function is 26 performed on the outputs of the AND array in the OR array : ::
j 27 and the latches. The outputs of the latches are gated on 28 while the diffusions of the AND array are being charged.
, j~ KI9-74-018 -12-.:
:' ~ ''' . '" ~' ,' ~ ' : ' ' ':.~ '. ':, ' . -:' . ' , 1 Unlike the dif~usions in the ~ND array, the diffusions 40 2 in the OR arra~ are continuously charged.
3 I'o make the connection between the AND arrays and the 4 OR arrays, one of the metal stripes 56 in the OR array connects to one of the diffusions 40 in the AND array by 6 way of a metalized via hole 54 through the oxide layers 7 48 and 50.
8 While a gate-metal personalization is desirable in 9 most cases, there are situations in which it is desirable to have circuit arrangement in which logic can be changed 11 by a purely metal personalization process. Such an arrange-12 ment is shown in Fig. 6. In the embodiment of Fig. 6 each 13 of the intersections of input and output lines 20 is popu-14 lated by an FET 24 for performing logic. Whether the FET
is Eunctioning or not depends on how its yate is connected.
16 If the FET 24 is not being used its gate is grounded to hold 17 the FET biased off. If the FET 24 is being used to perform 18 logic, its gate is connected to one of the input lines 22 19 to allow the F~T to be rendered conducting or non conducting by the pulses placed on the input line 20. ~s shown in Fiys.
21 7 and a, each F¢T is provided with a gate and metal connections 22 58 are selectively made Erom the gates 52 to the me-tal stripes 23 46 or to a diffusion stripes 42 through a via connection 10 ;~
24 in one processing step. It should be understood that the invention is not limited to either one of the above 26 personalization techniques and can be applied equally as ;
27 well to a number o-f technologies. In particular, it can 28 be applied to bi-polar technology instead of the described 29 FET technology.
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As described in commonly assigned U.S. Patent No. 3,936,812 which issued on February 3, 1976 and entitled "Segmented Parallel Rail Paths For Input/Output Signals", filed on even date herewith, the connections to the inputs and outputs of the arrays can be personalized in accordance with the functions to be performed in the array. To this end, a plurality of vertical rails 62 are provided on the chip on each side of the arrays 10, 12 and 14. Arranged orthogonally with respect to these rails 62 are the inputs 18 to the decoder 16, the outputs 66 of the JK's and the inputs 68, the off chip drivers 66. As shown in FIGURES 7, 10 and 11 the input lines 18 and 68 and the output lines 67 are metallized patterns on the surface of the oxidation layer 48-50 of the chip. The rails 62 are each made up of alternating metal portions 70 on top of the oxidation layer 48-50 and diffused por-tions 72 in the substrate 44 of the chip. These are joined by metalllzed via holes 74 that pass through the oxidation layer 48-50. The diffused portions 72 are located opposite the off chips drivers 66, the decoders 16 and the latches 30 so that the lines to the drivers, latches and decoders can pass over the diffused portions of certain oF the rails 62 and be connected -~
to metallized portions of other of the rails. The rails are segmented by openings 76 in the metal portions 70 to electrically isolate two or more different signals contained on the same rail on electrically isolated segments of the sarne rail. For instance, suppose JK 30a is to be connected to the off chip driver 66a, the metal lines 67 and 68 are connected to opposing metal por-tions 70a and 70b of the same rail 62a. The metal lines ' ;
, 7~
1 67 and 68 pass over the diffused portions 72 of the other 2 rails 62 so they do not short the rails together. Furthermore, 3 the metallized portions 70a and 70b of ra:il 62a both contain 4 an opening to isolate the segment of rail 62a containing the connection between the JK 30a and the off chip driver 66a 6 from the remainder of the rail 52a so that the remainder 7 of the rail can be used to carry other signals to the array such as ~he connection b~tween JK 30b and -the input -to two-bi-t ~ ~eco~er 16~. t~ should be noted that the inputs to the decoders 16 are positive and the outputs of the JK are also 11 positive so the outputs of the JK 30a can be directly con-12 nected back to the decoders 16b permitting sequential logic 13 to be performed with the arrays 10, 12, 14 and JK's 30 14 without the use of off chip connections between the JK's and the decoders. Connected across the top of the chip and 16 the bottom oE th~ chip are~a number of pads 74a which l7 ~un~tion oxclusivcly as illpUt pads ~or in~ut signals onto lf3 thc ciliE) to bc Fed to the inputs of the clecoders 16. They 19 are connected to the rails 62 by a nletalization pattern determined by the functions to be performed on the chips.
21 The pads 74a along the side of the chip may be used either 22 as output pads or input pads. If they are used as output 23 pads they are connected by metal personalization 76 to one 24 of the off chip drivers 66. If they are used as input pads along with pads on the bottom and top of the array are con-26 nected by personalization directly to the rails 62.
27 Above we have described one embodiment of the invention.
28 As can be seen, it permits alternate uses for various ele-29 ments in the array logic chip. In this way it is similar . . .~ , . .
::
.. . . . .
1 to a virtual memory which from the outside appears to have 2 a larger capacity -than it actually does. The reason for 3 this is that like in the memory the actua:L capacit~ is used very ine~Lriciently so that the lines and terminals can be assigned duplicate use so long as those uses do not 6 conflict.
7 In order tv make the understanding of the present 8 invention easi.er, the illustrated PLA was limited in size 9 and number of associated circuits. In fact, sub6tantially larger arrays are anticipated. For instance, two ~ND
11 arrays having 48 inputs and each being served by 24 de-12 coders would be more reasonable than the illustrated ~ND .:
13 arrays. In the same way an OR array havin~ 112 output.s 1~ :eeccl:ing 56 ~K's would also be more in the order o:E what 1.5 actually would be :Eound on one o:E these chi.ps.
16 While the invention has been particularly shown and 17 described with reference to a preferred embodiment thereof, 18 it will be understood by those skilled in the art that the 19 above and other changes in form and details may be made therein without departing from the spirit and scope of 21 the invention.
22 What is claimed is:
' ' ' -KI9-74~018 -16-;
,
Claims (12)
1. In a logic performing arrangement including an array having a plurality of input lines intersected by a plurality of orthogonally oriented output lines with logical elements located at at least some of the intersections of the input and output lines so that logical functions are performed on interrogation signals placed on the input lines and the responses thereto placed on the output lines, the improvements comprising;
different interrogating means coupled to opposite ends of the same input lines so that two different interrogating signals can be placed on each of said same input lines; and input lines in the plurality of input lines which are split into two seg-ments to separate from one another on different segments of the same input line two different sets of logical elements coupled on the same input line so the two different interrogation signals each interrogate only one set of logical elements whereby the number of logic functions performed by the array can be increased without increasing the number of intersections of input and output lines.
different interrogating means coupled to opposite ends of the same input lines so that two different interrogating signals can be placed on each of said same input lines; and input lines in the plurality of input lines which are split into two seg-ments to separate from one another on different segments of the same input line two different sets of logical elements coupled on the same input line so the two different interrogation signals each interrogate only one set of logical elements whereby the number of logic functions performed by the array can be increased without increasing the number of intersections of input and output lines.
2. The logic performing arrangement of claim 1 wherein said interrogating means are different decoders coupled to opposite ends of the same input lines.
3. The logic performing arrangement of claim 2 wherein the different decoders each decode two input signals each and in response thereto place an interrogation signal on one of the input lines coupled thereto.
4. The logic performing arrangement of claim 1 wherein said array is a sum of product term generating array and said interrogating means is two product term generating arrays one positioned on each side of the sum of product term generating array with each product term generating array having one output line connected to one input line of the sum of product term gen-erating arrays.
5. The logic performing arrangement of claim 4 wherein at least one of said input lines in the sum of product term generating array is not split into two segments so that logic can be performed on outputs of both the product term generating arrays coupled to that line.
6. The logic performing arrangement of claim 1 wherein the splits that divide in the input lines into two segments occur at different points along the input line in different input lines.
7. The logic performing arrangement of claim 6 wherein one of plurality of said different interrogating means coupled to input lines of the array is not used and those input lines are not broken to separate logic perform-ing elements coupled to that line.
8. In a programmable logic array chip having a product term generating array made up of a plurality of input lines intersected by a plurality of output lines with logical elements located at the intersection of some of the input and output lines and with the input lines receiving interrogating signals from a plurality of decoders, and having a sum of product term gen-erating array made up of a plurality of input lines intersected by a plural-ity of output lines with logical elements located at the intersection of some of the input and output lines, and with the input lines of the sum of the product term generating array receiving on its input lines the outputs of the product term generating array made in response to the interrogations and which in turn supplies inputs to a string of latches on its output lines, the improvement comprising:
two of said separate product term generating arrays positioned on oppo-site sides of said sum of product term generating array with each of the input lines of the sum of product term generating array coupled to one of the output lines of the two separate product term generating arrays so that the sum of product term generating array receives signals from each of the two separate product term generating arrays.
two of said separate product term generating arrays positioned on oppo-site sides of said sum of product term generating array with each of the input lines of the sum of product term generating array coupled to one of the output lines of the two separate product term generating arrays so that the sum of product term generating array receives signals from each of the two separate product term generating arrays.
9. The programmable logic array of claim 8 wherein breaks occur in lines of the product term and sum of product term generating arrays at different points in different lines to separate logic functions performed in the arrays.
10. The programmable logic array chip of claim 8 in which at least one of the input lines of the sum of product term generating arrays are broken to separate functions performed in the sum of the product term generating array on the two signals fed to that input line by the product term generating arrays.
11. The programmable logic array of claim 10 where not all the input lines of the sum of product term generating array are broken so that logic func-tions can be performed which involve the output of the two product term generating arrays connected to the line.
12. The programmable logic array of claim 11 wherein different decoders in said plurality of decoders are connected to opposite ends of the same input lines in both the product term generating arrays; and input lines in the product term generating arrays are segmented at different points in different input lines to separate functions performed along the segmented input lines on interrogating signals from one of the decoders coupled to the segmented lines from those functions performed on input signals from the other of the decoders coupled to that one.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/537,219 US3987287A (en) | 1974-12-30 | 1974-12-30 | High density logic array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1047610A true CA1047610A (en) | 1979-01-30 |
Family
ID=24141731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA238,824A Expired CA1047610A (en) | 1974-12-30 | 1975-10-30 | High density logic array |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US3987287A (en) |
| JP (2) | JPS5851451B2 (en) |
| CA (1) | CA1047610A (en) |
| DE (1) | DE2556275C2 (en) |
| GB (1) | GB1473029A (en) |
| IT (1) | IT1050023B (en) |
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| US5552720A (en) * | 1994-12-01 | 1996-09-03 | Quicklogic Corporation | Method for simultaneous programming of multiple antifuses |
| US5744980A (en) * | 1996-02-16 | 1998-04-28 | Actel Corporation | Flexible, high-performance static RAM architecture for field-programmable gate arrays |
| US20050102476A1 (en) * | 2003-11-12 | 2005-05-12 | Infineon Technologies North America Corp. | Random access memory with optional column address strobe latency of one |
| US8661394B1 (en) | 2008-09-24 | 2014-02-25 | Iowa State University Research Foundation, Inc. | Depth-optimal mapping of logic chains in reconfigurable fabrics |
| US8438522B1 (en) | 2008-09-24 | 2013-05-07 | Iowa State University Research Foundation, Inc. | Logic element architecture for generic logic chains in programmable devices |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1101851A (en) * | 1965-01-20 | 1968-01-31 | Ncr Co | Generalized logic circuitry |
| US3699534A (en) * | 1970-12-15 | 1972-10-17 | Us Navy | Cellular arithmetic array |
| US3818252A (en) * | 1971-12-20 | 1974-06-18 | Hitachi Ltd | Universal logical integrated circuit |
| US3761902A (en) * | 1971-12-30 | 1973-09-25 | Ibm | Functional memory using multi-state associative cells |
| US3731073A (en) * | 1972-04-05 | 1973-05-01 | Bell Telephone Labor Inc | Programmable switching array |
| US3816725A (en) * | 1972-04-28 | 1974-06-11 | Gen Electric | Multiple level associative logic circuits |
| US3849638A (en) * | 1973-07-18 | 1974-11-19 | Gen Electric | Segmented associative logic circuits |
-
1974
- 1974-12-30 US US05/537,219 patent/US3987287A/en not_active Expired - Lifetime
-
1975
- 1975-09-16 GB GB3791875A patent/GB1473029A/en not_active Expired
- 1975-10-30 CA CA238,824A patent/CA1047610A/en not_active Expired
- 1975-12-09 IT IT30096/75A patent/IT1050023B/en active
- 1975-12-12 JP JP50147531A patent/JPS5851451B2/en not_active Expired
- 1975-12-13 DE DE2556275A patent/DE2556275C2/en not_active Expired
-
1980
- 1980-06-20 JP JP55082980A patent/JPS6053965B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6053965B2 (en) | 1985-11-28 |
| DE2556275A1 (en) | 1976-07-08 |
| IT1050023B (en) | 1981-03-10 |
| JPS5184538A (en) | 1976-07-23 |
| DE2556275C2 (en) | 1982-04-01 |
| JPS5851451B2 (en) | 1983-11-16 |
| JPS5623032A (en) | 1981-03-04 |
| GB1473029A (en) | 1977-05-11 |
| US3987287A (en) | 1976-10-19 |
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