CA1049167A

CA1049167A - Apparatus for image manipulation

Info

Publication number: CA1049167A
Application number: CA76252292A
Authority: CA
Inventors: Everett T. Eiselen
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 1975-05-12
Filing date: 1976-05-11
Publication date: 1979-02-20
Also published as: DE2620217A1; FR2311463B1; IT1067518B; US3976982A; ES220730Y; GB1537328A; JPS5711059B2; FR2311463A1; JPS51138332A; ES220730U

Abstract

AN APPARATUS FOR IMAGE MANIPULATION
Abstract of the Disclosure An image can be represented by an M x N array I (*,*) of image points, where each point I(i,j) over the ranges O?i?M and O?j?N is a value or set of values representing the color and intensity of an elemental portion of the image. A black/white image can be represented by assigning to each point I(i,j) a value of 1 or O. Thus, I(i,j) = 1 represents a black elemental image area, while I(i,j) = O
represents a white elemental area.
Image manipulation refers to that class of image processing opera-tions which sequentially process the points of a rectangular array I(0,0), I(0,1),... I(0,n-1), I(1,0),..., I(M-1, N-1) in such a way that the resulting points must be mapped into coordinate points of the array. The image processing operations satisfying this constraint include the blanking of an image area, the combining of two images, the changing of scale of an image by a rational amount, rotation by 90°, and the creation of a mirror image.
Image manipulations in the invention are performed upon black/white images by logically combining a base image stored in an accumulating memory with a sequence from another raster source subject to selective size and translation changes. Such processing is subject to two con-straints. First, the data must be in non-compressed form. Second, the processed data must not fall outside the memory space originally occupied by the base image in the memory. Optionally, the function of magnification/minification may be performed separately from the other image manipulations. This can be conveniently done by placing the magni/minifier between the external image source and a network, which network logically combines the serial information from the external source with the serially extracted base image information stored in the accumulating memory.

Description

Background of the Invention This invention relates to the manipulation of images formed by two-dimensional arrays of Boolean coded points and, more particularly, to the manipulation of such images by bit stream processing.
In the prior art, the nature of elec~ronic circuits has made it con-venient to represent visual information such as documents, drawings, and pictures, by a two-dimensional array. The visual information, or image, is typically divided into rows and columns of small units or elemental areas, termed "picture elements" or "pels". Each picture element is assigned a value representative of its intensity (darkness) and its color. In a formal sense an image may be considered an M x N
array I(*,*) of image points, wherein each point I(i,j) over the ranges 0~ i~ M and oc j~ N is a value or set of values representing the color and intensity of each pel. A black/white image is one in which l(i,j) is a Boolean coded value. Typically, I(i,j) = 1 represents a black pel, while I(i,j) = 0 represents a white pel.
Images are most com~only generated by scanning pictorial data such as 8 1/2 by 11 inch documents. Thereafter, the scanned pictorial data can be stored, viewed from a display, transmitted or printed.
As a result of this form of presentation, electronic circuits can handle these picture elements one-by-one, rather than trying to handle the whole picture at a time. Typical examples of this one-by-one or sequential processing are television and facsimile transmission.
Since most scanners and printers process an image from left-to-right and from top-to-bottom, an M x N array of image 9~67 1 points is normally serialized in standard "r~w major" sequence

2 I(o~o)~I(o~ (o~N~ o)~ N-l). The seriali-

3 zation for purposes of transmission and displa~ in such divérse

4 fields as facsimile and television have encouraaed the use of synonyms in the literature. For example, imaqe points consti-6 tuting a cluster of consecutive rows or col`umns are said to 7 form a "raster". Indeed, the term "raster operation" refers to 8 the sequential processinq of elements in consecutive array rows 9 or columns. In this specification, the terms "raster coded inormation" and "raster operations" are deemed svnonymous with 11 the terms "points in an imaae array" and the "serial processina 12 o~ such points in row major order".
13 There are many processes that can be performed on I4 serialized, raster coded imaqes. Foi examPle, qeometric distortion can be corrected, periodic noise can be removed, 16 and variations in light levels can be compensated. Such 17 processes have been used with great benefit on photoqraphs 18 from space probes. The notion of manipulation of an image 19 can be distinguished from the above processes, and may be de~ined by way of example as the set of operations which 21 expand, shrink, justapose, cut up, or mosaic portions 22 of an image. Such operations are familiar to viewers of 23 home television receivers and occur in the cr,mposinq rooms 24 of newpaper and magazines. It becomes desirable, therefore, to be able to electronically maniPulate arrav~ of diaital 26 points in much the same manner that home teIevision can 27 create special effects or that a comPosinq room can cut and 28 paste photographs~ These operations when performed by electronic 29 systems are referred to as "electronic cut-and-paste".
Operations on larqe arrays of points have been handled 31 by ordinary, general-purpose diaital computers. However, the , - ''''---1! ' :` ~' ' . , - " . ' .

1~91~7 1 cost per manipulation is hi~h due to the larqe number of 2 processing steps which a general purpose structure must 3 exercise for each and every picture element in an array.
4 Recognizing that even an 8 1/2 x 11 inch pa~e requires well S over 10 pels at 120 pel per inch resolution, then apparatus 6 which could save information handling steps would become 7 economically attractive.
8 The prior art yields no clue as to the set of operations 9 which may be performed upon an array field, an efficient processing architecture emphasizing simplified hardware, 11 the reduction of the number of operations required and the 12 avoidance of self-destruction of image information. What 13 is avallable in the prior art may be found, for example, in 14 Belleson, U.S. Patent, 3,697,67g. Belleson describes the use of an addressable memory as a buffer for assembling ~-16 image arrays which, in turn, can drive a raster output 17 device.
18 Summary of the Invention 19 It is accordingly an object of this invention to devise an image manipulating apparatus capable of blankinq an imaqe 21 area, combining two images, changing scale, translatlon, rota~lon, 22 and creation of a mirror image. It is another object to devise 23 an apparatus in which points of any manipulated ima~e are mappable 24 into unique points in the array without requirin~ interpolation.
Relatedly, such an apparatus should avoid the potential self-26 destruction of image informat~on occasioned by the translation, ' ~ SA975006 -4-.

, . . . ... . ,. . ' . .

. .

~ 1 rc,tation, or mirrorin~ of imaqes in place.
2 The foregoing objects are satisfied by an emkodiment 3 which manipulates black/white ima~es by bit stream processinq.
4 The apparatus includes an accumulating memory for storing a base imaqe, an external source of coded sequences, and a network 6 which logically com~ines the base imaqe with the coded sequences 7 from the external source for such operations as translati~n, 8 rotation, mirrorina and com~ininq of two imaaes. Other manipula-9 tive operations such as inversion merely reauire streamina the bits from the selected portion of the accumulating memory throuqh 11 the network, performing the indicated loaical operation, and 12 streaming the bits back to their same coordinate locations.
13 Parenthetically, the execution of translate, rotate, and mirror 14 operations by the loqical combininq of the serialized base imaqe with an external coded stream avoids the potential self-destruction 16 of those image points in the manipulated imaqe located at 17 coordinates overlappinq points in the base image.
18 The amount of information required to represent the 19 page of a business ietter as a black/white imaae at a resolution of 120 pels per inch is well over one million bits. Because of 21 the inherent two-dimensional redundancy of such as array, the 22 amount of information can be reduced by compression techniaues 23 to about one-tenth. Such redundancy reduction is used primarily 24 for transmission and storaqe, rather than for maniPulation.
Among the reasons advanced for the necessity to manipulate 26 images in their uncompressed form is the fact that uncompressed 27 data contains relational information amonq clusters of points, 28 which information is frequently lost when data is compressed, 29 and must be reinserted.
It is an aspect of the invention that the functic,n of 31 magnification/minification may be performed ser,arately from -r ~04~16t7 1 other image manipulations. Conveniently, this is done by 2 placing the magni/minifier between the external raster source 3 and the combining network. In this reaard, the alteration of 4 magnification attributable to an image is accomplished by whole integer replication of existinq imaae elements so that the 6 resulting image points will fall on raster points.
7 The accumulating memory, which stores the base ima~e, 8 includes means for selectively addressinq linear seauences g at any arbitrary starting aadress alon~ either of the array dimensions. Since serial bit stream processina is central 11 to the architecture, it is also desirable to include means 12 for extracting selectively addressed seauences from the memory 13 and for replacing information at the same or other address 14 locations at a continuous rate. In addition to the network ;
for logically combining serial information from the external 16 source and the accumulatinq memory, there are included means 17 for specifying the loqical function to be performed by the 1~ combining network and for desianatinq the addresses for both 19 extracting data from and for writinq the loaically combined sequences into the memory. The apParatus of the imrention 21 thus permits image manipulation to be reduced to a series 2~ of parameters. By this is meant a series of numbers which 23 can be conveniently supplied to the aPparatus controller by 24 a CPU or even an operator-driven keyboard.
Brief Description of the Drawinqs ~6 FIG 1 shows the system logic of the preferred embodiment.
2~ FIG 2 illustrates the translation function performed by 28 t~e accumulating memory.
29 FIG 3 sets forth the orientation function performed by 30 the accumulating memory.
31 FIG 4 defines the loqic combining network.

, : ' ' '',',' '.. ' ', '' ',.: , ~ .` . ,.. _ , . : ,, .: ,: : ', ' ' ' . . . . ' 1C3~9~;7 1 FIG 5 shows examples of enlarqinq and reducinq of scale 2 control 3 set forth in FIG 1.
3 FIG 6 depicts data path control.
4 FIG 7 shows examples of imaqe manipulation.
FIG 8 sets forth the detailed loqic of the accumulatinq ~
6 memory and address control 15.
7 FIG 9 sets forth the detailed loqic of loqic unit 11.
8 FIG 10 sets forth the detailed loaic of unity scale control 9 with connections for enlarqe and reduce features.
FIG 11 shows the detailed loqic of the enlarqer 7.
11 ' FIG 12 depicts the detailed loqic of reducer 9.
12 FIG 13 exhibits the detailed loqic of clockinq and 1 control network 21.
14 Description of the Preferred Embodiment Referring now to FIG 1, there is shown a system archi-16 tecture for the image manipulating apparatus.~ The M x N array 17 of image points, hereinafter termed the "base image" is stored 18 in accumulating memory 15. This memory may be of the bit 19 addressable type in order to facilitate the extraction of :
subarray geometries anywhere within the array field. In this 21 invention, the subarray geometry of interest is limited to 22 rectangles.
23 A logic combining unit 11 facilitates the execution 24 of logical operations upon one or more bit streams simultaneously ~5 applied thereto over paths 6 and 17. The out~ut from the 26 logical combining unit, also in bit serial form, i5 applied 27 in parallel to raster output sink 31 and accumulatinq memory 28 15 over path 13.
29 Raster input source 1 driving binary sequences over path 5 through scale control 3 is responsihle for the appearance 31 of the bit stream on path 6. A clockinq and control unit 21 3~ responsive to a set of parameters applied to it over path 33 SA974006 - ~7~ -.
.' . .~i ' . , ,., : ; ' : ' ' .

: . . . .

l regulates the activation/deactivation, synchronism~ and 2 addressing of the raster information stored in accumulatinq 3 memory 15.
4 The manipulations which the apparatus is capable of performing include translation, orientation, combination, 6 scale change, and input/out. Translation is taken to be the 7 extraction and placement of fields at specific locations in 8 the master array. Orientation inciudes both the placement 9 of image fields in the master array at any one of four ninety degree angle rotations and the forming of mirror images in either ll the horizontal or vertical. Combination refers to the merging 12 Of two image fields in any of 16 possible ways. The ability 13 to scale change means that the siæe of an image field can 14 be altered by an integer ratio. Lastly, input/output implies that image fields can be entered from a raster input source 16 or extracted and appl'ed to a raster output sink.
17 It is apparent by delimitinq the class of imaqes to 18 black/white images, there is a substantial reduction in the 19 amount of memory storage because only one bit per pel, rather than several bits per pel, is required -to encode each element.
21 Also~ the areas extracted from the array are limited to rectanq-22 ular subarray geometries. These rectanqular subarrays will 23 be referred to as "image fields". As is apparent, rectanqular 24 subarray geometry greatly simplifies the accessinq of the pels within the fields in view of the fact that the Cartesian 26 coordinates of the edges remain constant. In contrast to 27 the random access of the image field within the master array, 28 the pels are accessed sequentially within the subarray geometries.
29 Consecutive pels are called the "scan line". Also within the image fields, scan lines are accessed sequentially. This SA97~006 -8-: ... . . ... . ............. . . .......... . . . .
' " ', ''' , ' ,' '." ' ' ' . ' ' " ' ' ', :, ' '' " . ' ~' ' ' ~4gl~7 1 limitation permits pels to be addressed by incrementing simple 2 counters. Apparatus for performinq imaqe manipulation processes 3 a single field at a time, rather than processinq several fields 4 at once. This constraint avoids the requirement to multiplex the scan lines from several fields into a sinqle scan line for 6 the master array. The apparatus of the invention is also constrained 7 in that the pels from any manipulation process fall on raster 8 points, rather than permit-ting them to fall between raster points.
9 This mapping avoids the need for interpolation loqic. ~owever, this limit restricts any enlarqinq and reducing to inteqer ratios, 11 as well as requirina rotation to be in ninety deqree increments.
12 Referring now to FIG 2, taken toqether with FIG 1, there 13 is shown the translation func-tion performed by the accumulatinq 14 memory. In this regard, translation is controlled by the four parameters X, Y, dX, dY. The first picture element 16 of an incoming image field is placed at the starting coordinates 17 X,Y. The size of the image field as modified by the scale 18 control 3 is determined by the parameters dX and dY, where 19 dX gives the extent in the X direction of the imaqe field and the accumulating memory, and dY gives the extent in the 21 Y direction.
22 Referring now to FIG 3, there is shown the orientation 23 function performed by the accumulatinq memory. The orientation 24 is controlled by three parameters. These are, namely, F, sX, sY.
F designates the coordinate direction which is to he incremented 26 first as the sequential picture elements are received, thereby 27 specifying the coordinate along whlch the scan line will be.
28 The parameter sX gives the sign for incrementinq the X coordinate ~9 as either a plus or minus 1. The parameter sY performs the same function for the Y coordinate. FIG 3 illustrates how .' : ' ' . .:
.
,~ . .

3L~49~67 1 the result would appear in the accumulating memory if the 2 incoming image field contained the letter F. The sequence of 3 pels for the incoming image field are always treated as though 4 they were left-to-right, top-to-hottom. In matrix terminoloqy, this is defined as "row major" order". In FI~ 3, the 6 orientation change is relative to those scan directions 7 because there can be no absolute coordinates for the incomin~
8 image field. Its only reference is the picture element 9 sequence.
Referring now to FIG 4, there is shown the symbolic 11 definition of logic combining network. The loglc unit combines 12 two image fields, picture-element by picture-element. The 13 process used for the combination is specified by the Boolean 14 function parameter B since the two black/white fields are treated as two 2-valued data streams. In the preferred 16 embodiment, the combining process is performed by pure combi-17 natorial logic so that there are no timing considerations other 18 than those of insuring that the correspondinq pels from the 19 two images be presented at the same time to the network. As a result, the output is available later after some appropriate 21 circuit delay time. The output can be replaced in the accumulator 22 memory 15 or applied to output sink 31.
23 Output sink 31 preferably may consist of a presentation 24 device such as a raster printer or display. Also, the sin]c 2~ must be able to accept data with a rate faster than the maximum 26 data rate of the apparatus so as to tolerate variations in data 27 flow and avoid the need for internal buffering on any of the 28 major data paths 5, 6, 17, and 13.
29 Input source 1 contemplates raster scanners and raster generators of encoded alphanumeric and vector graphics data.

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1~4~67 l The input source l, similar to sink 31, must be operable 2 at a data rate greater than the maximum data rate of the 3 apparatus.
4 Scale control 3 changes the size of the incoming image.
The size can be enlarged, reduced or left the same. Because 6 of the constraint that any processed picture element must 7 fall on a pel position, enlarging or reducing is equivalent 8 to multiplication and division by integer values. Scale g control can be inserted in the output leg, such as in path 13 as an alternative to the input leg on path 5.
11 ~ Referring now to FIG 5, there are shown examples of 12 scale change. In enlarging~ one picture element is made into 13 many. Because it is impossible to create information that does 14 not exist in the original image, all of the resulting picture elements are given the same value as the original pel. In the 16 reducinq operation, several picture elements are logically 17 Combined to just one. Reduction is the process for discarding 18 information. Consequently, care must be exercised to preserve 19 as much useful information as possible.
In the scale control operations exemplified in FIG 5, 21 the control is responsive to parameters SC, R-l and R2. The 22 parameter SC determines whether the scan control enlarges, 23 reduces, or preser~es the existing size. In the instant 24 case, the scale change is constrainted to be the same in both the x and y directions. The parameter R-1 is one less 26 than the size ratio and is used wherever unity scale is not 27 preserved. The parameter R2 is the ratio of areas and is used 28 to determine when more than half of the picture elements are 29 black during reduction. It is not used for either enlaxging or unity scale.

~ , . . . .
, . . .

~L9~L67 .
l Both enlarging and reducing involve storing data. In enlarging~ data is stored as it comes into enlarqer 7 so that~
3 it can be replicated. In enlarging, data is read out fastèr 41 than it is read in. During the time when scan lines are being replicated, no data is being read in, causing thereby an interruption 6 in input data flow.
7 In the reducing operation, all of the scan lines that 8 will be reduced to a single scan line are read in before any 9 data is read out. Thus, the stor~ data is processed as the reduced scan line is produced, before any more data is read ll in causing thereby an interruption in input data flow.
12 Clocking and control element 21 sets up an operation 13 by initializing each of the units as, for example, input 14 source l, scale control 3, accumulating memory 15, logic unit ll, or output sink 31. It conditions the input and 16 output it required, and controls the data paths 5, 6, l7 17 and 13. Clocking and control thereupon gates the master 18 clock so as to allow the operation to proceed. ~ufficient -l9 intelligence is provided for clockinq and control to determine whether the pel clock during each scan line, 21 scan clock at the end of each scan line, or raw clock 22 ~hould be distributed to the elements involved in the 23 operation. Clocking and control also monitors the progress 24 of the operation and signals the completion to the instruction source interface when the operation is completed.
26 Referring now to FIG 6, there is shown examples of 27 data path control exercised by clocking and control element 28 21. Relatedly, the selection of images to be processed and 29 the data paths are determined by the parameters PC, IA, OA.
30 ~he parameters IA and nA are the inPut address and the output -31 address respectively. The two bits of the path control parameter 32 PC specify whether (~ontinued on next Pa~e) .
'' l the input or output have~ een selected. Since there are two 2 images processed by the logic unit, one must always be from , 3 the accumulating memory, while the other is from the input.
4 However, if the input is not selected, then that lea 6 o~
the logic unit is forced to 0. If the output 31 is selected, 6 then the image is not replaced in the accumulatina memory 15.
7 Referring again to FIG l, all of the parameters are 8 entered over path 33 into clockinq and control element 21.
9 The source of parameters may be either a computer or an operator-driven keyboard. Since the size of the imaae area, 11 as well as any reduction involved, affects the time it takes 12 to perform an operation, then the parameter source must be 13 prepared to supply parameters as needed. In the preferred 14 embodiment~ all of the parameters are presented in parallel Under the control of two timing lines.
16 The foregoing paragraphs have been directed to some 17 of the functinal aspects of the embodiment. The followin~ -18 paragraphs are directed to illustrate the operation of the ~l9 apparatus for raster image manipulation. Reference should be made to FIG 7 which illustrates an example of image manipulation.
21 The objective of the sequence is to take a page of text that 22 haS been previously converted to raster form and stored so as 23 to be available to the apparatus at input address 1. The page 24 of text consists of two columns where each row of text is represented by a short line in FIG 7. ~ portion of the left-26 hand column is to be extracted, rotated ninety degxees counter-27 clockwise and placed on the left-hand side of a new page. A
28 diagram that has previously been stored at input address 2 is 29 to be reduced by a factor of two, rotated ninety de~rees counter-clock wise and placed on the right-hand side of the new page.
31 For purposes of this example, it is desired that the diagram 32 WOuld look better switched right-for-left, so a mirror image 33 is created before it is placed on the pa~e. The size o~ the , ................................................. .. . .. ,_ .
.

l~gl~7 accumulating memory is assumed to be 1024 x 1320 picture 2 elements. The coordinates are given wlth increasinq X to the 3 right and increasing Y down the page. The accumulator memory 4 15 is cleared before the sequence starts. However, since the first step is a full load of the accumulator memory, its 6 initial status is not important. In this regard, FIG 7 shows 7 the accumulator memory before and after each operation. The 8 memory after one step is identical to the accumulator before g the next step.
The status of the source 1 and output 31 are shown when 11 theY are involved in the step. It should be noted that the value of each parameter required for a step is also listed.
12 Parameters which are not included are not used in the step.
13 Step 1: The accumulator is loaded (B=3~ from the 14 input (PC=01) address l(IA=l) in a raster image storage device (not shown). The input image is the same size as the accumulator 16 memory 15(dX=1024, dY=1320), so that no scale change is required 17 (SC=l). The loading starts in the upper left-hand corner (X=l, 18 Y=l) and proceeds in row major order (F=0,sX=0,sY=0).
Step 2: A portion of the left-hand column of text is extracted from the accumulator memory 15. The area involved 21 is shown in the dotted lines in the "before" accumulator memory 22 column. The process starts at (X=9o,Y=275j and covers the 23 area (dX=400,dY=840). The normal sequence is followed (F=0, 24 Sx=o sy=o) The area is extracted (B=5) and sent -to the output (PC=10) storage address 3(OA=3~ to temporarily hold 26 this intermediate result for use in step 4.
Step 3: The whole data memory 15 is cleared by settinq it equal to 0~B=0). No input or output is involved (PC=00~.
The process starts in the upper left-hand corner (X=l,Y=l) and continues for the full area of the accumulator memory : '-. : ' : .

1(dX=1024,dY=1320). In the normal sequence (F=0,sX=0,sY=0).
2 Although the process could have started in any corner and 3 have progressed in an appropriate sequence, the normal 4 sequence is chosen for convenience.
5Step 4: The partial column of text temporarily stored 6 in step 2 is now loaded (B=3) from input (PC=01) storage 7 address 3(IA=3). The size of this field is the same size 8as the one extracted (dX=840,dY=400). However, the coordinates 9 are reversed because it is rotated as it is placed in the accumulator memory 15. The rotation is achieved by scanning 11 along Y(F=l) in the negative Y direction (sY=l). Successive 12 scan lines are placed in increasing X positions (sX=0). The 13 partial column of text is placed in the proper location by 14starting at (X=100,Y=1190). The size is not changed during input (SC=l).
16Step 5: The diagram is loaded from the input (PC=01) 17 storage address 2 (IA=2). It is reduced to one-half size 18 (SC=0,R-l=l,R2=4) as it is loaded. For variety, it is decided 19 to logically OR (B=7) the incoming data with that existing in the accumulator memory. However, since that area of the 21 aceumulator memory is presently all zeros, the result is the 22 same as a replace (B=3). The incoming image is the same size 23 as the aeeumulator memory that is reduced by a factor of two 24 so that the size of the field in the accumulator memory is 25(dX=660,dY=512) where the reversal of coordinates is caused 26 by the rotation.
27Rotation requires that scanning take place along the 28 Y coordinate. Also, the mirror image is produced by scanning 29 to increasing Y(SY=0) whilç successive scan lines are placed in inereasing X positions (SX--0). Lastly, the appropriate 31starting loeation is X=100,Y=140.

.
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1~49167 1 Referri.r.q now to Fl~ 8, there i.s sho~Tn a detailed 2 logic diaaram of the accumulatinq mem~rv 15 and the a~s~ciat~d 3 address control. The parametric inputs F, Y, sY~X~sK are 4 supplied by control loaic element 21 over co].lective path 19 to corresponding y and x counters throuah appropriate control 6 logic activated by Pel and scan clocks from clockina and control 7 unit element 21. The accumulatina memory includes a random access 8 bit addressable memory 81 for storina d~ta seri~lly by bit 9 applied to it over path 13 and for sup~lying data serially by bit out over Path 17. The X and Y c~ordinates are a~plied 11 to address reqister 83 from the corres~onAina x and y counters 12 85 and 87. The counter~, themselve.s, are of the u~/d~wn ty~e ~ :
13 with synchronous loadin~. .
14 The memory is initialiæed by loadina X and Y values into counters 85 and 87, resPectively! Parameters ~, sX,sv 16 are held at a constant value all throuqh the o~erati~n. It . :~
17 should be observed that the pel clock activates memory timing 18 element 89, which element controls the read cycle durina. phase 19 1 of pel clock and the write cvcle during phase 4. The scan clock operates to ~ate approPriate parameter.~ from element 21 21 to eounters 85 and 87 for the purpose of either loadina, 22 incrementing or deerementina the reaister count.
;~3 After initialization, in res~onse to each pel ciock ~4 pulse received over path 91, memory 81 i.s fir.st read and then written into at the current addres.s c~ntained in reaister 26 83. Additionally, the eontents of reaisters 85 and 87 are ~7 changed as a function of the parameters in F,~sX, and .sY.
.

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, .
' 1~4gl67 1 If F=0 and sX=0, then the x count in reqister 85 is 2 incremented by phase 5 of the pel clock. If F=0 and sX=l, 3 then the x count is decremented by phase 5. Likewise, if 4 F=l and sY=0, then the y count in re~ister 87 is incremented by phase 5, while if F=l and sY=l, then the y count is decremented 6 by phase 5.
7 When a scan clock pulse is received over path 93, 8 then the registers 85 and 87 have their contents altered as 9 a function of F,sX and sY, as follows:
If F=0 and sY=0, then the x count is loaded in register 11 85 and the y count is incremented by phase 5. If F=0 and sY=l, 12 then the x count is loaded and the y count is decremented. If 13 F=l and sX=0, then the y count is loaded and the x count 14 incremented. Lastly, if F=l and sX=l, then the y count is loaded and the x count is decremented.
16 - Referring now to FIG 9, when taken together with FIG 4,-17 there is shown a logic unit 11 to which serial data from 18 the scale control element 3 is applied over path 6 and serial 19 data from the accumulator memory 15 is applied over path 17. The output of the lo~ic unit is applied to data path 2I 13.
22 Logic unit 11 can have its function configured by 23 the signals applied to the plurality of conductors B8, B4, 24 B2, and Bl shown as control path 23 runninq from clockin~
and control element 21.
26 For example, if the control leads B8, B4, B2, Bl are 27 coded as 0111, then the loqic unit represents a loqical 28 nOR". If the control leads are coded as 0110, then an exclusive 29 "OR" is set up, etc. Other control combinations include 0001 for a loqical "AND", 0011 for "replace", 0101 for "extract", 0000 31 for "set to 0", and 1111 "set to l's".

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10~9167 1 Referring now to Fl~,,S ln-12, thexe is sho~n the detailed 2 logic level embodiments of scale control eiement 3 of FIG 1., 3 Moxe particularly, FIG 10 sets forth the detailed lo~ic of 4) unity scale control with connections for enlar~e an~ reduce features. FIG 11 shows the detailed loaic of the enlarGer 7, 6 while FIG 12 depicts the detailed loqic of reducer 9. As 7 previously mentioned in discussion with FI~7 5 showin~ examples 8 of scale chan,ae, there are three Paramenter~s reaulatin~ scale 9 control operations. These parameters are, resPectively, SC, R-l and R2. The parameter SC determines whether the scan 11 control enlarqes, reduces or preserves the existin.a size.
12 Parameter R-l is one less than the size ratio and is used 13 whenever unity scale is not preserved. Lastlv, the parameter 14 R is the ratio of areas and is use~ to determine when more than half of the Picture elements are black durina reduction.
16 It is not used for either enlarainq or unity scale.
17' Parametric control is suPplied from clockinq and control 18unit 21 to scale control element 3 over path 25.
19Referring now to FIG 10, the lnput p,el clock from enlarger scale control of FIG 11 is suPplied to path 2 and 21 through an AND/QR cluster to raster inPut source 1 o~rer path 22 14. Other clockinq control inclu~es the pel clock on path 23 25 applied to latching element D. Since unity scale implies no 24 chan,q,e in the image, it amounts to a resynchronizina opportunity.
and a convenient connectinq point for the bit streams from 26enlarger 7 over path 12 and reducer 9 over path 10, all of the 27 foregoin~ beinq coupled to the loqic unit 11 via path 6.
28Referrin,q now to ~IG 11 there is shown enlaraer 7 ,' 29 responsive to raster input source over path 5 an~ aeneratina an output over path 12 which terminates in the unity scale - ~49~L67 1 element described in FIC7 10. Since parameter SG determines 2 whether to enlarqe or reduce, if selected, the enlaraer parameter 3 is re~ulated by R-l shown drivina a scan counter. As suqqested 4~ in enlarging, data must be read out on path 12 faster than it is read in on path 5. This derives from the fact that enlarqina 6 consists of replication of picture elements bv an inteqral number 7 of times. The input data is stored in temporary store so that 8 scan lines can be replicated an inteqral number of times. Durina 9 scan line replication, no input is taken into the enlarqer.
The enlarqer is enabled over ~ath 25 by the same AN~ qate loaic 11 that terminates the pel clock and the scan clock. A scan counter 12 and pel counter regulated by parameter ~-1 control the replication.
13 Referring now to FIG 12, there,is sho~7n the reduced scale 14 control 9. Scale reduction proceeds in two steps. First, R
scan lines are loaded into temporary store, one scan line at 16 a time. The loadin~ proceeds by reading the contents of the 17 memory into the temporary store data reqister. The input data 18 is inserted into the bit position determined by the scan count 19 dixected to the bit select. Then the modified temporary store data register is written into the temporary store. During 21 this period, the pel clock is inhibited. The pseudo pel clock 22 is used to count the pels in the reduced scan line by decrementina 23 DP in FIG 13~ The relation of input pels to reduced pels is 24 maintained by the pel count. At the end o~ each scan line, the pseudo scan clock is used to restore the counting of pels 26 in the reduced scan line by loading DP in FIG 13, but it does 27 not decrement DS in FIG 13 because the reduce element has not 28 yet produced the reduced scan line. This process is continued 29 until the scan count is decremented to zero.
The second step actually generates the reduced scan line.
-~

- . ~ , , " . . .
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.

l~y9 16 ~
1 Before each group of ~ pels-axe examined to determine whether 2 a black or white output pel should be produced, the black count 3 is loaded wi-th R2. Then, one pel from each of R scan lines is 4 read from the temporary store into the count register. In the count register each pel in sequence is shifted into the left-6 hand position where, if it is a black pel, it enables the black 7 count causing it to be decremented by 2. AEter R groups of R
8 pels have been examined, the contents of the blac]c count is 9 compared to zero. If the black count is less than zero, a black pel is placed on output pel line 10; if greater than zero, a 11 white pel is placed on output pel line 10; if equal to zero, 12 then a pel value opposite to the current pel value is placed on 13 output pel line 10. This process continues until a reduced scan 14 line is produced, at which time the counter DS in FIG 13 is deeremented. The above process is repeated until all scan lines 16 in the input image have been proeessed as indicated by counters 17 DS and DP, FIG 13, being decremented to zero.
18 State Decode Table for FIG 12 19 I = Initialize Ll = (mode = 00) & (pel count ~ 0) & (DP ~ 0) & raw clock 21 L2 = (mode = 00) & (pel eount = 0) & (DP ~ 0) & raw clock 22 L3 = (mode = 00) & (scan count ~ 0) & (DP = 0) & raw clock 23 L4 = (mode = 00) & (sean eount = 0) & (DP = 0) & raw clock 24 Rl = (mode = 01) & (scan count = 0) & (pel count = 0) & raw clock R2 = (mode = 10) & (scan count ~ 0) & raw clock 26 R3 = (mode = 10) & (scan count = 0) & (pel count ~ 0) & raw clock 27 R4 = (mode = 10) & pel clock 28 R5 - (mode = 01) & scan clock 29 Ll+L2 = (mode = 00) & (DP ~ 0) & raw clock L3~L4 - (mode = 00) & (DP = 0) & raw clock ' ~49~67 1 Referring now to FIG 13, there is exhibited the detailed 2 logic of clockinq and control network 21. Parameters F, dY, dX, 3 PC and SC are applied over paths 33. It is through this interface 4 that all parameters are entered. The other function of this element is that of providing clockinq and synchronizing signals 6 to be distributed to all elements in the system so that given 7 a master clock, submultiple frequencies of interest can be 8 derived and transmitted. Thus, raw clock is gated through 9 from the master clock while the pel clock, scan clock are derived submultiples and transmitted over paths 25 and 19.
11 Decode Table for FIG 13 . .
12 Select Input = (PC = 01+11) & (Start op.+op. Busy) 13 Select output = (PC + 10+11) & (Start Op.+Op. Busv) 14 Enable Reduce = ((PC=Ol+ll)&SC=01) & (Start Op.+Op. Busy) Enable Enlarge =((PC=Ol~ll)&SC=10) & (Start Op.+Op. Busy) 16 Enable Unity = ((PC=Ol+ll)&SC=00) & (Start op.+Op. Busy) 17 Clocking and control circuit 21 sets u~ the manipulation 1~ operation when signalled to do so. In terms of siqnal flow, it 19 selects the signal source and notes input ready when received.

It selects the sink and notes the output readv when received.

21 Clocking and control further initializes the accumulatin~ memory 22 15, the enlarger 7 and the reducer 9. In performinq the 23 operation, the clocking and control circuit sends the pel and 24 scan clock to those units involved.

It should be appreciated that the pel clock provides a 26 cycle for each pel read from the accumula-tinq memory 15. Many 27 events occur for each pel clock cycle. Thus, the pel clock 28 consists of five phases in order to allow for the circuit delays 29 involved in the events which occur in a sinqle pel clock cycle.

The pel clock is shown in the diagrams as thouqh it were a :104~167 1 single phase except the phase u~ed by various units, for example, 2 02 is shown at the pel clock input to the unit in FIGS 8, 11 and 3 12. Relatedly, the scan clock cycle occurs at the end of ~ each scan line. There is no data transfer. The scan can be along either the X or the Y direction in the accumulating 6 memory 15 depending upon which coordinate is sequenced first.
7 Since thexe is only a reinitilize function performed by the 8 scan clock, it can consist of a sinqle phase. Also, it should 9 be noted that a pel clock can be inhibited by the reduced function, if selected. When reducer 9 is selected and the 11 pel clock inhibited, then clocking and control network 21 12 sends "raw clock" to the reducer unless the conditions for 13 scan clock exist. In the latter case, scan clock is sent unless -14 scan clock is inhiblted in which case raw clock is aaain transmitted.
The assumption is that once conditions are present to initiate a 16 clock cycle, then all phases will be produced e~7en if the initiatin~
17 conditions cease in the middle of the cycle.
18 The foregoing has described the system of this invention 19 and has illustrated its concrete implementation. It is a matter of course that known circuits are selectively employed as the 21 circuits of the above described block diaarams by those skilled 22 in the art. It is needless to exemplify the detailed lo~ic~
23 Such circuits may be those shown, for example, in "Pulse, Digital, 24 and Switching Waveforms, Devices, and Circuits for their Generation ~25 and Processing", Sections 18, 9 and 10, bv Jacob Millman, Herbert 26 Taub, published by McGraw Hill Book Com~any.
27 It will be apparent that many modifications and variations 28 may be affected without departin~ from the scope of the novel 29 concepts of this invention.
What i5 claimed i8:

, . _

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. An apparatus for manipulating a two-dimensional array of Boolean coded points, comprising:
memory means for storing the array, said means including means for selectively addressing linear subarrays in one of two directions and at an arbitrary starting address along either of the array dimensions;
means for extracting the selectively addressed linear subarrays from the memory and for replacing information at the same or other sel-ectively addressed locations in the memory at a continuous rate;
a source of Boolean coded information;
means for logically combining in serial fashion the linear sub-arrays extracted from the memory means with serial information from the source; and control means for specifying the logical function performed by the combining means and for designating the addresses both for extracting data from the memory means and for writing the logically combined sequences into the memory means.

2. An apparatus for manipulating a two-dimensional array of Boolean coded points according to claim 1 wherein the apparatus further comprises:
means for altering the magnification attributable to Boolean coded information from the source by whole integer replication of existing array elements, said means being interposed between the source and the logical combining means.

3. An apparatus for manipulating a two-dimensional array of Boolean coded points according to claim 2, wherein the means for altering the magnification attributable to Boolean coded information from the source by whole integer replication of existing array elements includes means for replacing a predetermined cluster of Boolean coded points by a single Boolean value.