CA1056504A - Keyword detection in continuous speech using continuous asynchronous correlation - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A system for detecting one or more keywords in continuous speech is disclosed wherein a speech processor extracts a plurality of analog speech parameters from the input continuous speech, an STV
generator circuit selectively converts the plurality of analog speech parameters into digitized speech samples, an asynchronous correlation circuit continuously correlates sequences of the digitized speech samples with stored reference mask templates representative of sub-elements of one or more desired keywords in order to produce correlation data, and a decision function circuit is responsive to the correlation data for developing an occurrence decision output for each desired key-word that is detected.

Description

BACKGR~U~D OF TXE INVENTION
1. Field o~ the Invention This invention relates to speech recognition s~ste~s and particul~rly to a syste~ capable of recognizing keyNords in continuous speech. `

2. Description o~ the Prior Art Many speech recognition systems have been proposed ~or application in such ~ield~ RS data processing, communications and machine control in industry.
U. S. Patent ~os. 3,775,627 and 3,582~559 describe discr~te word recognition systems Nhich can only operate upon isolated utterances and will not function to detect keywords in continuous speech.
A word recognition system based on a sequence o~ phonetic event detections is disclosed in U. S Patent ~o. 3,588,363. ~his s~stem, while appllcable to discrete utterances, will not ~unction ~565(:~4 with continuous speech~ since the sound recognition network must be reset at the beginning o~ each word.
A limited vocabulary (fixed to two words) word recognition system is described in each of U. S. Patent ~os. 3,557~310 and

3,688,1~6. Neither o~ these systems will respond to a keyword in con~inuous speech.
A system ~or detecting ~ormants (poles in the vocal tract transfer function) in speech is disclosed in U. S. Patent ~o.
3~499~989. This system performs 3peech analysis but not utterance 1 0 classifiaatlon.
A system ~or classi~ring vowel sounds and making vowel/non-vowel decisions is described in U. S. Paten~ ~o. 3,428,748. This s~rstem, liXe the system o~ U. S. Patent No. 3,499,989, is a speech analyzer and is not capable of performing utterance classification.
U. S. Patent ~os. 3,129,287 and 3,742,1~3 describe limited vocabulary isolated word recognition systems which are unable to accomplish keyword recognition.
~ he system disclosed in U. S. Patenb ~o. 3,198,884 is oriented toward discrete di~3;it recognition. q~his system establishes 2 0 acoustic time reglstration via a segmentation procedure. Irhese segmentation procedures are subject to gross errors and are unsuitable for keyword recognition.
The system taught in U. S. Patent ~o 3,742~146 is directed to tne classi~ication o~ vowel sounds and has no provision for combining these events for keyword detection.
In the article of G. L. Clapper, entitled "Autcmatic ~ord Recognition'r~ found on pages 57-69 of IEl~ Spectrum, August 1971, a system is describ~d for recognizing discrete words. Since the system described in this article relies on word boundary information, keyword recognition by this qystem is impossible.

~565~)~

Asynchronous detection of keywords in continuous speech implies that no synchronization points are employed in the recognition process. Asynchronous detection is especially de~irable in the classification o~ continuous speech for two reasons. ~irst, the duration of a keyword in continuous speech i9 determined by the rate of speech and the stress glven to the keyword as part o~ the spoken message. Second, bhe position of the same phonetic elemonts acros~
an ensemble of dlf~erent utterances of the same keyword may not be linearly related. Thi9 second reason reduces the applicabllity o~
1 0 linear time normalization which has been ~ound useful in discrete word recognition.
Many of these prior art speech recognition systems, as well as other like systems, employ synchronization points in the recognition process. Conventional prior art procedures derive synchronization points with preclassification segmentation procedures. ~egmentation procedures possess two inherent disadvantages. First, performance degrades rapidly when noise is applied to the signal. Second, ccmputa-tional requirements are o~ten severe 3asing a key~ord spotting or detection system on a synchronous process ~hich is inherently noisey is ot an optimal procedure, since an omitted segmentation boundary could inhibit keyword recognition even with perfect recognition logicO
~ one of the above-described systems is capable of operating on continuous speech to detect one or more keywords.

~UMMoRY OF 1~ INVE~TION

Brief}y, a novel asynchronous detection system i~ pro~ided for detecting an unlimited number of keywords in continuous speech, which ~ystem does not require word isolation or segmentation In a preferred embodiment, a plurality oi' analog speech parameters are 3 extracted by a speech processor fr~ input continuous speech and ~o~6~04 selectively converted into digitized ti~e spectral matrix speech sample6 by an STV generator circuit, Sequences o~ the digitized speech samples are continuously correlated in an asynchronous correlation circuit with stored spectral reference mask templates corresponding to preselected keywords to be recognized in order to produce correlation data. This correlation data enables a decision function circuit to de~elop a decision output ~or each preselected keyword thab i9 detected.
It is therefore an ob~ect of this invention to provide a no~el asynchronous speech ~ecognition system, Another ob~ect of this inrention i5 to provide a system capable of recognizing keywords in continuous speech, A ~urther ob~ect of this invention is to provide a system for detecting keywords in continuous speech by utilizi~g a con~inuous asynchronous correlation operation, BRIEF DESCRIPTIO~ OF THE DRAWI~GS
These and other ob~ects, features and advantages oi the invention, as well a the invention itself~ will become more apparent to those skilled in the art in the light of the ~ollowipg detailed description taken in consideration with the acc~panying drawings 2 0 wherein like reference numerals indicate like or corresponding parts throughout the several views and wherein~

"` ` ~056S0~ ~

FIGURE 1 is a simplified block diagram of a preferred embodiment of the invention;
FIGU~E 2 is a block diagram of the speech processor of FIGUFE l;
FIGURE 3 is a block diagram of the S~V generator of FIGURE l;
FIGURE 4 illustrates waveforms use~ul in explaining the operation o~ the S~V generator clrcuit o~ FI~URE 3;
FI&URE 5 is a block diagram o~ the asynchronous correlation i O circuit o~ FIGURE l;
FIGURE 6 is a bloc~ diagram o~ the central control o~
FIGURE 5;
FIGURE 7 illustrates wave~orms useful in explaining the : operation of the central control of FIGURE 6;
FIGURE 8 is a block diagram of the mask unit of FIGURE
5; : - ~
F}GURE 9 illustrates the address locations of the mask storage memory circuit of FIGURES 5 and 8;
: : FIGURE 10 is a b}ock diagram of the RAM unit of FIGURE 5;

: 2 0 FIGUFE~ llA and llB illustrate the STV adaress locations in the RAM of FIGURES 5 and 10 during selected LQAD and RUN states;
FIGURE 12 illustrates dif~erent types o~ correlation operations : performed by same of the different con~igurations that could be utilized in the arithmetic pipeline unit o~ FIGURE 5:;
FIGURES 13A and 13B illustrate two di~ferent implementations for the comparison ~unction of FIGURES 5 and 12;
FIGUKES 14A, 14B and 14C illustrate three different imple-mentations for the threshold ~unction modifier of FIGURES 5 and 12;

~056504 FIGURES 15A and 15B illustrate two dif~erent implementations for the weighting ~unction modifier of FIGURES 5 and 12;
FIGURE 16 is a block diagram of the sum accumulator of PIGURES 5 and 1~;
FIGURE 17 illustrates the type #1 arithmetic pipeline unit 151 operation for a 16-word length mask X.
FqGURE 18 is a block dlagram o~ a ~irst part o~ the decision ~unction of FIGURE l;
FIGURE 19 i3 a block diagram of a second part of the decision 1 0 function o~ FIGURE l; and FIGURE 20 is a block diagram of an alternate second part of the decision function of FIGURE 1 which may be utilized in lieu of the structure of FIGURE 19.

DESCRIPTIO~ OF ~E PgEFER~ED EM~ODIME~

Re~erring now to the drawings, FIGURE 1 discloses a simplified block dlagram of a preferred embodiment of the invention for detecting one or more keywords in an input continuous speech. A speech processor 11, which is essentially a spectral anPlyzer, makes ~ analog s~ectral estim~tes of a continuous broadband speech input signal to develop 2 0 analog speech parameters Sl - S~ ln ~ channels. q~ese spectral estima~es can relate to the energy in 200 Hertz (Hz~ wide contiguous bandpasses. Each of the N channels of analog speech parameters are time division multiplexed and digitized by an STV generator 13 to develop ~-component spectral time vector (S~V) data every 10 milli-second (msec.) period.

lOS6504 This STV data from the STV generator 13 is stored in an asynchronous co~relation circuit 15, along with a preselected number of previously received STVs to form of sequence o~ STVs being stored~
Each time tha~ a new S~V is received, the oldest stored S~V is dis-carded ~rom the sequence. The sequence of stored STVs essen~ially forms a spectrogram with the ~requency components of each srv being dispo3ed along, for example, a vertlcal ~requency axis and the STV~
being disposed along a horizontal time axis in lQ msec increments.

With an S~V being taken every 10 msecJ a pattsrn de~elops which 1 0 forms the spectrogram.
The asynchronous correlation circuit 15 continuously per~orms an asynchronous correlation on the sequence of STVs being generated by the STV generator 13. ~o accomplish this continuous asynchronous correlation, the digitized incoming speech parameters in a se~uence of consecutive STVs are selectively matched or correlated in the correlation circuit 15 with internally stored reference mask templates or masks (in~icated in FIGURE 9). The stored masks are representative of subelements of the keyword utterance. Typically, these subelements are phoneme pairs ("dyads" or two phonetic events) and/or phoneme 2 0 trlplets ("triads" or three phonetic events). One dyad or triad would be stored in each mask. On the average, six masks would be required for the detection of A desired keyword by the system.
It should be noted that our English language has a phonetic alphabet which is made up o~ phonetic symbols which, in turng represent these phonetic events. There are about 44 phonetic events in the Engl~sh l~nguage. These phonetic events include, for example, vowel sounds (ee, uh, uu, er, ah, etc.), "~tops" which a person forms by closing his vocal tract in certain positions (t, k, g, b, etc.) and other consonent sounds.

~56504 The stored masks can be of ai~ferent lengths. Typically, they can vary from 1 to 16 STVs in length, with an average mask being about 10 STVs in length.

~ ach of the stored masks is periodically compared ~ith a correspondingly long sequence of consecutive S~Vs to identi~y or correlate the dyad and triad sound groups. ~he close~ess o~ the ldenti~ication or correlatlon between each mask and the corresponding ST~ sequence is indicated by a correlatlon score. In thi~ man~er, a mea~urement of keyword like~ihood ~or each of the desired keywords is'periodically computed.
~ he output correlation scorss between the stored masks and the parameterized speech or STVs are incorporated into output correlation data from the correlation circuit 15. This output correlation data i8 combined into an overall sim larity metric by a decision function circuit 17, which may be a computer or special purpose logic. ~hi similarity metric is in~ernally thresholded in the decision ~unction 17 to produce an occurrence decision output ~or each keyword that is detected. The decision function's c~mbina-tion of the correlation data takes into account the temporal sequence of ~he æubelements of the keyword a~ well as the variability in articulation rate.
A 3ystem timing gen~rator 19 supplie~, ~la internal caunt-down circuits (not shown), output clock pulse timing signals of one megahertz (1 M~z), one hundred kllohertz (100 KHz) and one hundred ~ertz (100 Ez), which are selectively supplied to the circuits of FIGURE 1 to enable them to perform their above-indicabed operations.
Ihe circuit components o~ FIGURE 1 will nGw be discussed in more ~056504 detail to more clearly explain the invention.

Referring now to FIGURE 2, a block diagram o~ the speech processor 11 of FIGURE 1 is illustrated. The continuous speech ~nput signal is gain-controlled by an automabic ga~n control (AGC) circuit 21 before being applied to a preemphasis circu~t 23. The preemphasls circuit 23 emphasi~es the ~requenay spectrum of the signal from the AGC circuit 21 by~ for exampl~) 6 decibels per octave before applylng the resultant preemphasized sienal to a spectrum analyzer 25.
~he spectrum analyzer 25 may c~mprise a filter bank of contiguous 200 Hæ bandpass filters (not shown) for separating the various frequency components in the preemphasized signal.

~ he various separated frequency camponents from the spectrum analyzer 25 are respectively detected through rectification by diodes 2~1 - 27K and filteriDg by low pass filters 291 - 29K
bPfore being applied to conventional logarithmic amplifiers 311 - 3 to develop the analog speech parameters Sl - SK. The outputs of preselected ones of the filters 291 - 29K may also be applied to a feature extractor 33 for the generation of linear and non-linear functions of these preselected filter outputs to develop the analog 2 ~ speech parameters SK+l - Sn. Any selected number and combination of the analog speech parameters from the logarithmic amplifiers 311 - 31K
and the feature extractor 33 may be utilized in subsequent signal processi~g. In any event, for purposes of the following descri~tion~
assum~ that the total number o~ analog speçch parameters to be processed is ~ and that ~ = 16. The spectral estimates or analog speech para-meters Sl - S16 (where ~ = 16) from the speech processor 11 are applied to the SFV generator 13 to develop an associated STV.

:1056504 Referring now to FIGURE 3, a block diagram o~ the STV
generator 13 is illustrated. ~he wave~orms of FIGURæ 4 will also be referred to in explaining the operation of the circuit 13 of FIGURE 3. The 100 Hz signal (waveform ~ rom the sy~tem timing generator 19 is differentiated and negative limited by a differen-tiator and negative limiter 43 to develop a start of load pulse ~SOL) illustrabed in waveform 45. The SOL pulse sets flip flop 47 to initiate the pulse gate ~9. Pulse gate 49 enables an A~D gate 51 to pass a preselected number of 100 KHz pulses frcm the system timing generator 1~ as a 100 KHz burst of 16 pulses illustrated by the waveform 53. This 100 K~z burst of pulses is dela~ed 5 micro-seconds ~sec) by a delay circuit 55 before being applied as a delayed 100 KHz burst of 16 pulses (wa~eform 57) to the count (C) input of counter 59 to initiabe its counting sequence, The output count of the counter 59 i9 applied to a c~mparator 61 where it is compared with an ~ count of 16. When the count of the counter 61 reaches 16, the comparator generates a load reset pulse 63 which is used to reset the counter 59 to a zero count and to reset the flip flop 47 to prevent any subsequent pulses from being passed through the AND gate 51 and being counted by the counter 59. ~he load reset pulse 63 is delayed 10 microseco~ds by a delay circuit 65 in order to generate an end of load pulse (EOL) 67. ~he SOL and EOL pulses are applied to a central control circuit 87 in FIGU~E 5, the operation of which will be subsequently explained.
The 100 KEz burst of pulses 53 frcm the A~D gate 51 is appli~d to the step input of an ~ or 16-channel multiplexer 69.
The multiplexer 69 steps up one position for each of the 16 pulses in the 100 K~z burst of pulses. The analog speech parameters ~1 ~
S16 frcm the speech processor 11 (FIGUKE 2) are applied in parallel 105650~

to the multlplexer 69. With each one of the sixteen 100 KHz burst of pulses being applied to its step input, the multiplexer 69 time division multiplexes the Sl - S16 input signals so that they are sequentially applied to an analog to digital converter (ADC) 73.
The multiplex~r also generates sample pulses 71 which are applied to the ADC 73 to enable the A M 73 to sequentlally digltize the sequentiall~ aligned Sl through S16 spectral estimate signal3. ~he 16 sequentially developed digitized spectral esbimates comprise one spectral time vector tS~V). A new STV or S~V data is developed every 0 10 msec. This 10 msec period is the interpulse period ~or the 100 Hz pulse ~rom the system timing generator 19. A~te~ a new srv i9 developed by the ADC ~3, the multiplexer 69 is reset to its initial step position -by the EOL pulse in preparation ~or the start of the next LOAD state.

` Each one of the digitized Sl ~ 516 spectral estimates is a binary word which may be, for example, 6 bits wide. It should be noted at this time th~at henceforth the term "word" Nill be used to define a binary word, while the term "keyword" will be used to de n ne a dicbionary word that is being sought ~or detection in the speech input.

2 0 The spectral estimate3 or analog speech parameters Sl through S16 are sequentially aligned because it takcs approximately lOJusec. for the ADC 73 to perform an analog to digital conversion per sample. ~herefore it takes approxi~ately 160 ~sec. for all 16 channels of serial~zed speech parameters Sl through S16 to be digitized. As stated before, the 16 seguentially developed digitized spectral estimates Sl - S16 comprise one spectral time vector (SIV).
Xence, in this description each S~Y i~ comprised o~ a serial sequence of 16 binary words, with each word being 6 bits ~ide. After each 1~56504 one of the spectral estimates Sl - S16 is digitized, the ADC 73 generates a data available signal 75 to indicate that the STV data is ready to be utilized.

Referring now to FIGURE 5, the S~V data ana data available signals from FIGURE 3 are respectively applied to a rand~m accecs memory (RAM) 81 and a RAM control 83 in RAM unit 85 (to be dlscussed later)~ while the SOL and EOL pulses ~rom the S~V generator 13 o~
FIGURE 3 are applied to the central control 87. ~he central conbrol 87 generates load and run gates which respectively control 1 0 the duration o~ LOAD and RUN states of operation. At this time, the block diagr~m o~ the central control 87 in FIGURE 6 and the waveforms of FIGURE 7 will be reierred to to more clearly explain the operation of the central control.

.
In FIGURE 6, the SOL pulse 45 (FIGURES 3, 4 and 7) sets a load flip flop 85 to start the IQAD state o~ operation by initiatlng a "1'1 state load gate 91 at its Q output. Approxlmately 160 micro-seconds later, the EOL pulse 67 (FIGURES 3, 4 and 7) resets the load flip ~lop 89 to terminate the load gate and hence end the LOAD state of operation. At the same time that the EOL pulse 2 resets the load ~lip ~lop 89, it sets a run flip ~lop 93 to start the RUN state of operation by initiating a "l" staté run gate 95 at its Q output. After approximately 7 milliseconds, a "1" state End 0~ FU~ (EOR) pulse or bit 97 is applied ~rom a mask unit 99 in FIGURE 5 to reset the run ~lip ~lop to terminate the run gate ~5, and hence end the RUM state of operation. The duration of the LOAD and RUW states of operation are respectively determined by the durations o~ the load and run gate slgnals 91 and 95. A new STV is generated during each LOAD state, while all correlations are made wlthin the RUN state. As indicated in the waveform 95 a~ter the termination of the run gate, there is approximately 2.84 milliseconds before the next SOL pulse 45. ~his time of 2.84 milli-seconds allows for an additional delay of up to 2.8~ ~illiseconds before the EOR pulse i9 applied to terminate the ~UN gate 95, should the system so require a longer RUN state operation.
~ he run g~te 95 and bhe 1 MHz clock puls08 are applied to inputs o~ an A~D gate 9~. In additlon, a b~nary "l" ~tate trainer c = and signal (from trainer 105 in FIGURE 5) is applied to an 1 0 lnvertin~ input of the AND gate 96. This "1" state trainer ccDmand signal is only applied to disable the AND gate 96 when the trainer 105 desires to store new mask data in the mask u~it 99 (FIGURE 5).
The operation o~ the trainer 105 and mask unlt 99 will be explained later in relation to FIGURE 8.
When no "1" state trainer c~mmand signal is applied to the AND gate ~ the AMD gate is no longer in a disabled condition. This allows the central control 87 to generate signals that enable the RAM unit o5 and mask unit 99 to simultaneously perform a READ operation.
~his READ operation only occurs when a run ~ate signal, but no trainer 2 ~ c~mmand signal, is applied to the A~D gate 96. When the run gate signal 95 is applied to the AND gate 96 duri~g a READ operation, the run gate signal enables the AMD gate 96 to pass 1 MHz clock pulses as "count"
pulses ~hese "count" p~ es are also delayed for about 100 nano-seconds (nsec~ by a delay circult 98 to develop "read" pulses. ~hese count and read pulses are applied to both of the RAM and mask units 85 and 99 (EIGURES 8 and 10) to enable them to si~ultaneously read out their corresponding contents to perform correlation~ (to be discussed later) It can therefore be seen that the central control 87 is prevented irom generating count and read pulses whenever the A~D

~056S04 gate 96 is disabled by the appllcation o~ the "1" state trainer command signal to its inverting input.
Referring back to FIGURE 5, the count and read pulses fram the central control 87 are respectively applied to a mask memory control lOl and a mask storage memory 103 in the maak unlt 99 to enable the mask memory control 101 to control the READ/WRI~E
operations of the mask storage memory 103. ~he mask atorage memory 103 may be a core memory with word address locatlons starting at locatlon D and continuing sequentiall~ u~til the end of the last 1 0 stored word. Also associated with the mask unit 99 is the trainer 105~ which may be a logic circuit or a computer. The trainer 105 trains or controls the mask unit 99 to store any desired dyads and/
or triads which may comprlse one or more desired keywords. To more clearly explain the operation of the mask unit 99~ re~erence will now be made to ~IGURE 8.
In FIGURE 8, whenever the trainer 105 desires new data to be written into the mask storage memory lO3, it sends a "1'l state trainer command signal to a selector switch 107 in the mask memor~
control 101, as well as to the in~erting input of the previously 2 discussed AND gate 96 (FIGURE 6). As stated before, the inversion of the "l" state tralner command signal disables the A~D gate 96, At the same time the "1" state trainer ccmmand signal causes the selector switch 107 to only allow trainer addresses to pass through a "write" input of the s~itch 107 to the mask storage memory 103.
3ach "WRI~E" command from the trainer 105 enables the mask storage memory 103 to allow mask data ~rom the trainer 105 to be written into the mask storage memory 103 at the associated trainer address~

_ 14 -1~5650~

When no "1" state trainer command is applied to the selector switch 107 (and to the AMD gate 96 of FIGURE 6), internally generated addresses in the mask memory control lOl are passed through a "read"
input oi the selector switch lO~ to the mask storage memory 103 for a READ operation. rrhis READ operation can only occur when no "1"
state trainer c~mmand signal is being applied to the selector switch 10~ (and AND gate 95 in ~IGUFE 6). During a READ operabion, read and count pulses from the c~ntral control 87 (FIGURE 6) are res-pecti~el~ applied to the mask storage memory 103 and to the "count"
1 ~ inpùt o~ a counter 109. Each time that a count pulse ls counted by the counter 1~ an internal address is generated which passes through the "read" inpu~ o~ the selector switch 107 to the mask storage memory 103 as a "read" address. The read pulses, which as explained in relation to FIGURE 6 are 100 nsec. delayed count pulses, enable the mask storage memory 103 to sequentially read out its contents auring the RU~ state. It should be noted that due to thi~ 100 nsec delay between associated count and read pulses~ each of the internal addresses ~rom khe counter 109 is in a stabilized condition before the read pulse~ command the ma~k storage memory 103 to sequentiaIly read out iks contenks.
Each time that a read pulse is applied to the mask storage memory 103~ an eighteen-bit word, stored at the address location being internally addressed b~ the counter lO9 at that time, is read out of the mask storage memory 103.
~ his elghteen-bit word can be sequentially comprised o~
6 bits of am~litude in~ormation ri, 5 bits of threshold information ai, 5 bits of w~ighting information wi, a first l-bit signal and a second l-bit signal. The ~irst l-bit signal changes ~rom a blnary "O" state to a blnar~ "l" state "End of Mask" (EOM) 5ignal at the .

_ 15 -~056504 end of each of the masks being road out o~ the mask storage memory 103 durin~ a gU~ state The second l-bit signal changes from a bin~ry "O"
state signal to a binary "1" state "End of Run" (EOR) signal aPter all of the masks have been read out of the mask storage memory 103 during a RU~ state. This EOR signal is used to reæet the counter 109 and, as mentioned be~ore, to reset the flip ~lop 93 (FIGURE 6) to terminate the run gate and ~UN state. The counter 10~ i3 reset to assure that the internal address from the counter 109 will be at O at the start of the next RUN stabe.
i As indicated in FIGURES 5 and 8, the mask storage memory 103 ha~ the capability of storing 8192 eighteen_bit words, This storage ability of the mask storage memory 103 is illustrated in FIGURE 9.
More specifically~ PIGURE 9 illustrates various exemplary address locations o~ the mask storage memory 103. It wiIl be recalled that the stored masks can be of different lengths and that they can vary ~rom 1 to 16 STVs in length. It should be further recalled that each STV was stated to beg fcr example, 16 words in length wlth each word being 6 bits wide. As a result, the masks can vary fr~m 16 words in length to 256 words in length, with one dyad or triad being 2 stored in each mask of the mask storage memory 103.
In the generation of each of the masks indicated in FIGURE 9 to be stored in the memory 103, a skilled person having a reasonable command of acoustic phonetics defines the length of each mask by looking at trainlng spectrograms so that he can train the sy~tem of the in~ention by co~tro}li~g the operatlon of the trainer 105 of FIGURE 5.
In some cases multiple masks per dyad or triad will be used ~ because of free variation and interspeaker effect. In the generation of multiple masks, that skilled person examines spectrograms to find 3 3 perhaps 10 mask samples of a dyad or triad and typically groups them into, for exampla, three mask subgroup6 to span the free variation and interspeaker effects ~or that dyad or triad.

- 16 _ lOS6S04 ~ ree variatlon may be defined as the utterance of different phonetic representations or sounds conveying the same semantic information.
More specifically there is an ideal way of saying something. Each person has a free variation of speaking from the ideal way. ~his free variation can be caused by dialect, prosody (an emotional utterance by the speaker) or sentence stress. Three types of free varlation which may occur are the substitution o~ one sound ~or another ("da" or "th~" for "the"), the omission of a syllable ("pat" instead o~ "part") and the insertion of a sQund in a key~ord (adding "uh" to the end of "park"). Inter-1 0 speaker effect or variation may be defined as occurring when theutterance of the same sound by different speakers results in different characteristic resonances for that same phonetlc event.
After grouping the above-noted 10 mask samples into three mask subgroups, corresponding ccmponents in the masks in each of the three mask subgroups are then a~eraged to form a single mask for that dyad or triad in that subgroup. The three multiple masks for a dyad - or triad are then serially stored in the memory 103 in contiguous locations and would be subsequently processed in parallel.
It should be recalled that there are approxlmately 44 2 dif~erent sounds or phonetic events in the English language and that the recognition system of this invention is based upon dyads and/or triads where a dyad is two phonetic events and a triad is three phonetlc events. ~herefore, there could be approximately 1936 different dyads and/or triaas. However, if 500 to 700 dyads and/or triads ~ere utilized in this system, probably well over 90~0 of the keywords in a standard English dictionary could be recognized.
With one dyad or triad being stored in each mask of the mask storage memory 103, the system of this invention could have an unlimited vocabulary if enough masks were used and the syste~ were implemented large enough to ccmpute a decision output for each of the deslred key-words. The invention thus has the capability of unlimited vocabulary ~056504 recognition in continuous speech. However, the system could also be utilized for limited vocabulary recognition in such exemplary appli-cations as: baggage routing; zip code usage; remote data entry over a telephone, such as for sales orders; voice augmented word recognition to control the operation o~ machinery in a factory or the internal operation of an airplane; and selected word spotting, or a presorting of speech by setting the system to recognize a limited number o~ key-words of intereqt in communications broadcasts In a limited vocabulary recognition utllization, the masks in the mask storage memory 103 could be grouped to~ether in sequence to define the keyword or keywords to be recognized, but this is not absolutely necessary. It should be under-stood that the difference between these capabilities of unlimited and limited vocabulary recognitLon lies only in the amount of duplication of equipment~implemented into the system.
SLnce, as previously stated during the discussion of FIGURE 8, each word in the mask storage memory 103 can be re:d out in l ~sec due to the application of the 1 MXz count and read pulses, it would tak: 8192 ~sec or 8.192 msec to read out :11 of the words in the memory 103 if the memory 103 were filled. Xowever, only approxi-:~ :
2 0 mately 7000 eighteen-bit words are shown in FYGURE 9 as being stored in the memory 103, with the memory 103 havlng the capability of storing an additional 1192 eighteen-bit words in the remaining 1.192 msec If the operatLon of th~ system so requires.
M masks are :hown in FIGURE 9 as being stored in the memory 103. ~he word length of :ach mask i9 shown airectly below the mask number while the address locations of the words in each mask are indicated by the associated range of numbers. For ex mple, mask 2 is 128 eighteen-bit words in length, with these words being located in address locations 257 through 384, (biDQry address locations of 3 ooooloooooool through 0000110000000). ~he "1" state EOM signal is contained in the word (000000000~00000010) ~ollowing each of the masks to indicate the end of that mask. For example, the binary word 000000000000000010 containing the "1~' state EOM signal can be found at address location 385 (binary address location 0000110000001) which follows the end of mask 2. ~he "1" state EOR signal i9 contained in the word (000000000000000001) contalned in address location 7000 (binary address location 1101101011000) following the EOM signal that ~ollows the last mask (mask M) stored in the memory 1030 It will be recalled that this EOR signal is used ln FIGURE 6 to reset the run ~lip flop 93 to termlnate bhe run gate, and in FIGURE 8 to reset the counter 109.
Returning now to FIGURE 5, as stated before STV data and data available signals from the ADC 73 (FIGURE 3) are respectively applied to the RAM 81 and RAM control 83 in the RAM unit 85. In addition, the EOL signal from the delay circuit 65 (FIGURE 3), the EOM signals from the mask storage memory 103, and the load gate signal and count pulses from the central contro]. 87 are applied to the RAM
control 83, while the read pulses from the central control 87 are applied to the RAM 81. To more completely e~plain the operation of 2 0 the RAM unit 85, FIGURES 10, llA and llB will now be referred to.
The RAM 81 ln FIGURE 10 (and FIGURE 5) corresponds to a spectrogram, with the frequency components in the STVs stored therein being vertically disposed along a vertical ~requency axis and ad~acent one~ of the sequence of stored STYs being separated by 10 msec of time from each other along an orthogonal time axls. Every 10 msec a new 5TV is stored in the RAM 81. By this means a pattern starts developing which forms the spectrogram. The RAM 81 may be solid state and have a word length that is panel-selectable between 1 and 1024 locations. In operation, the RAM 81 must have a word-storage length at least as long 3 ~ as that of the longest mask stored in the mask storage memory 103.

~ 19 _ `~ 1 3ach of the masks, as shcwn in FIGURE 9, ust have a word length equal to some intsgral multiple of 16 words, since a mask can be between 1 through 16 ~IVs in length and each STV includes 16 digiti~ed spectral eStimRtes or words in length. Since the longest mask shown in FIGURE 9 (mask 1) is 256 word~ lon~, or the equivalent o~ 16 S~Vs long, let us hence~orth assume that the selected word length of the RAM 81 is such that the RA~ 81 stores 256 ~ords or 16 STYs a~ any given time.

The address locations for the 16 STVs stored in the RAM 81 1 0 dùring various LOAD and gUN states are illustrated in FIGURES llA
and llB. MO~ULO or rollover addressing is utilized for the RAM 81.
The address locations ~or the 256 words stored in the RAM 81 range from O through 255. Since 255 is the highest num~ered address ; location, the addressing is called MO~ULO 255 addressl~g. In MO~ULO 255 addressing, the RAM 81 operationally resembles a circle when it is addre~sed, as indicated in ~I~URES llA and lIB. In either o~ ~he LCAD or RU~ states, when address location 255 is reached, the next addresses in that operational state start with O and increase in the direction indicated by the arrow in FIGURE llA
2 ~ or llR.

~056504 FI~URE llA illustrates STVs 1 through 16, with srv 1 being stored in load address locations 0-15, S~V 2 being stored in load address locations 16-31, S~V 3 belng stored in load address locatlons 32_47, ... and STV 16 being stored in load address locations 240_255, In ~IGURE llA, S~V 1 i~ the oldest S~V 3ince it wa8 stored ~irst, whlle STV 16 i8 the newest S~Y since it WRS
stored last. During the slxteenth LOAD state the 16 digitized spactral estimates, or fre~uency component words, in STV 16 were sequentlally stored ln load address Iocations 240-255. ~he first i O digitized spectral estimate in SI~ 16 was written into load address location 240 at the start of the sixteenth LOAD state and the last or sixteenth digitized spectral estimate in STV 16 was written into load address location 255 at the end of the sixteenth ~OAD state.
:
Since the RAM 81 stores 256 words in 256 address locations, a synchronous load counter 1?1, which supplies load addresses to the RAM during the 10AD state, must likewise have 256 address counts or load addresses. Theae 256 address counts range from O (00000000) through 255 (11111111). Assume? for purposes of this discussion, that the last count or load address of the s~nchronous counter 121 2 0 was 255, as illustrated in FIGURE llA at the end of the sixteenth LQAD state. ~his 255~count is compared with a fixed number WM in a ~05650~
comparator 123. ~he comparator 123 can be a set of A~D gates. The number WM is panel-selected to be equal to the last or largest load address required of the load counter 121, which is 255 in the present discussion. When the count o~ the counter 121 beccmes egual to WM, or 255~ the comparator 123 develops and applies a "1" state ~ignal to the "reset" input of the counter 1~1. The synchronous counter 121 operates such that, whenever a "1" state sienal is applied to its reset input, the next data available signal 75 (FIGUR~ 4) applied from the ADC 73 ln FIGURE 3 to its "count" input wlll qause the load counter 121 to reset to a zero address count (00000000).
During the next or, for example, seventeenth IOAD state, the load signal 91 (FIGURE 7) is applied frcm the load flip flop 89 (FIGURE 6) to a selector switch 125 to enable the RAM control 83 to operate in the LOAD state. During this seventeenth LOAD 5tate, the 16 data available pulses 75 from the ADC 73 (~IGURE 3)t that occur during the generation of STV 17, are applied to the "count" input of the load counter 121. Since it was previously stated that at the end o~
the sixteenth LOAD state the count of the counter 121 ~as at 255, the first data available pulse during the next or seventeenth LOAD
2 0 state resets the counter 121 to a zero count, as illustrated in URE llB at the start of the seventeenth LQAD state. Each one of the remaini~g 15 data avallable pulses causes the counter 121 to change lts output load address bg a count of 1. During the seventeenth LOAD state~ the counter 121 therefore develops load addresses of 0, 1~ 2 ... 15. During the application of the seventeenth LOAD signal to the selector switch 125~ the 16 load addresses from the counter 121 are sequentially passed through a "load" input of the selector switch 1?5 to the RAM 81.

lQ56504 Each of the 16 data available pulses occurring during each LCAD state i9 delayed approximataly 100 nanoseconds (nsec) by a delay circuit 127 before being applied as a "write" command signal to the RAM 8L Conseguently, each of the load addresses iB in a stabilized condition before the "write" signals command the RAM 81 to write in the 16 digitized spectral estimates in the ~TV being applied to the input o~ the RAM 81. It should be recalled that each o~ these digltlzed spectral estimate~ i8 a word 6 bits wide.
Durlng the seventeenth LO~D state the 16 spectral estimates 1 ~ in S~V 17 are sequentially wrltten into the load address locations 0-15 o~ the RAM 81, as illustrated in FI~URE llB. The first spectral estimate in S~V 17 is written into load address location 0, and the last spectral estimate in STV 17 is written into load address location 15. In comparing FIGURES llA and llB it can be seen that at the end of the seventeenth LOAD state, STV 17 has been written into the load address locations 0-15 that were formerly occupied by STV 1, which was the oldest stored STV at the end of the sixteenth LOAD state, while STVs 2-16 remain in the address locations that they occupied at the end o~ the sixteenth LOAD state. During the eighteenth LOAD
2 a state (not ~llustrated) STV 2 ~nll be discarded while S~V 18 is being written into load address locations 16-31. It can therefore be seen that every 10 msec. a new SIV i6 stored in the RAM 81, while the oldest STV is being discarded. As a result, at any given time the RAM 81 holds 0.16 seconds or 160 msec of digitized spectral estimates or time samples of parame~erized continuous ~peech.

_ 23 -" ~056509L
As explained in relation to FIGURE 6, the generation of the EOL pulse (FIGURE 3) terminates the load signal 91 to terminate the LOAD state and initiates the run signal 95 to start the RU~ state.
The ~OL pulse also passes through an OR gate 1~9 to the "load" input of a run counter 131. The run counter 131 i9 a preset counter which is enabled by the EOL pul3e to load in~ or appl~ bo iba "output", the current preset address. The current preset address may be defined as the last load address that is being applied ~rom the lo~d counter 121 to the "preset address input" o~ the counter 131 at the bime that the EOL pulse i9 being generated. This preset address appears at the "output" o~ the run counter 131 before the counter 131 starts counting durlng the ~ollowing RUN s~ate When the load signal 91 is terminated by the EOL pulse at the completion of a IOAD state, the RAM control 83 starts operating in the RUN state. If no "1" state trainer command signal is generated by the trainer 105, as previously discussed in relation to FIGURE 6, read and count pulses from the central control 87 (FIGURE 6) are respectively applied to the RAM 81 and to the "count" lnput of the run counter 131.
~ he first 1 MHz count pulse that occurs durlng the RU~
state causes the outp~t run address count of the run counter 131 to increment by a count of one (1) As a result, the first run address that appears at the "outputi' of the counter 131 at the start of the RUM state is one count greater than the current preset address (or last load address in the prior LOAD state). For example, as illustrated in FIGURE llA, the last load addre~s count at the end of the 16th LOAD state is 255. During the 16th RUN state, the run address from the counter 131 starts with a run address count that is one greater than the last load address of 255 namely zero (0~. Each _ 2~ -' I !, ~, ~()5~;504 of the subsequent 1 M~z count pulses, that occur within the period of time that a mask is being read out of the memory, causes the counter 131 to increment its output run address count by an additional count Qf one (1).
Each run address count from the run counter 131 is compared in a comparator 133 with the number ~M~ ~hich ln this illustration is equal to 255. I~ the run address count doe~ not reach 255 before the end of a mask is reached~ an EOM pulse or stgnal associated with that mask is passed through the OR gate 1~9 to enable the counter 131 to 1 0 load into its "output" the current preset address. By this means the run addresses that sequentially occur when the following mask is being read out start with an address count that is one (1) greater than the current preset address and increment upward until the end of that following mask. On the other hand, whenever the run address count of the counter 131 reaches 255 be~ore the end of a mask, the comparator 133 generates and pa~ses a "1" state signal to the "reset"
input of the run counter 131. ~his '1" state signal enables the counter 131 to be reset to a zero (O) address count by the next 1 MEz ccunt pu}se that occurs. In this manner the run counter 131 2 o can count up from its current preset address to a count of 255, then continue counting from zero (O) upward to the end of a mask, at which time an EOM pulse is generated As indicated above, at the end o~ each mask that is read out of the mask storage memory 103 (FIGURE 8) an EOM pulse is passed through the OR gate 129 to the "load" input of the run counter 131.
Each EOM pulse operates, as did the EOL pulse at the end of the previous LOAD state, to enable the counter 131 to appl~ the preset address to its "output" before the start of the reading out of the next mask.

The first 1 MHz count pulse, that occurs during the time that the next mask in that same RUN state is being read out, causes the run addres~ count to again be one (1) greater than the current preset address. During any given RUN state, the preset address remains the same for each mask beinB read out. During the following RUN state, the preset address ~or that ~ollowln~ RUN state di~ers ~rom that o~ the former RUN state by a count of 16. For exampleJ
as shown in FIGURES llA and llB~ the preset address (or last load address) at the end o~ the 16th LOAD state, and henoe during the 1 0 16th RUN state, is 255, while the preset address immediately be~ore and during the 17th RUN state is 15. In a like manner~ the preset addresses ~or the 18th, l9th and 20th RUN states (not shown) would be 31, 47 and 63, respectively.
It can be seen from the above description o~ the operation o~ the run counter 131 that, during any given RUN state, the prior EOL pulse loads the current preset address into the counter 131 ~or the first mask being read out during that given RUN state, and the EOM pulses respectively load the current preset address into the counter 131 ~or the sub~e~uent ma6ks being read out o~ the memory 2 0 103 during that given RUN state. As a result, at the start o~ any given RU~ state and at the beginning of each mask being read out during that RUN state, the proper preset address is loaded into the run counter 131. ~his assures that the RAM 81 ~ill be properly addressed when a ne~ mask is being read out o~ the mask storage memory 103 during any given RUN state. In this manner, proper timing can be obtained in the correlation ~f each of the masks in the memory 103 with the STVs stored in the RA~ 81.

- - 26 _ 105650~

The reason for starting the run addresses (during the RU~
state) at a count one greater than the last load address in the prior LOAD state is that the sequence of STVs to be correlated ~ith each stored mask starts ~rom the oldest S~V and proceeds toward the newest STV. It has been previously indlcated that, in relation to ~IGUR~ llA, ST~ 16 is the newest STV that is stored in the RAM 81 after the six-teenth LOAD state and that STV 16 is located in RAM load address locations 240_255. Therefore, durlng the slxteenth RUN state, the run addresses ~or each mask start at 0 and sequentially increase i ~ upward until the end o~ that mask~ a~ter which time the run addresses ~or the ~ollowin~ mask start at 0 and sequentially increase upward until the end of that ~ollowing mask, etc. In a like manner, as indicated in FIGURE llB, during the seventeenth RU~ state~ the run addresses i~or each mask start at 16, which is one more than the last load address of 15 that occurred at the end of the seventeenth LOAD
state, and increase upward to the end of that mask9 etc.
During a RUN state the run addresses from the run counter 131 are applied through a "run" input of the selector switch 125 to the RAM 81, since no load signal is being applied to the switch 125 2 0 during the RUN state.
It will again be recalled that the read pulse being applled to the RAM 81 are lCO nsec-delayed count pulses. As a result, the run addre~ses occurring during a RUN state are in a stabili~ed con-dition before the read signals or pulses command the RAM 81 to sequentially read out words equal in number to the number of words contained in the mask being read out of the mask storage memory 103 at that time.

~0~;6504 ~ Sach time that a run address and a read pulse are applied to the RAM 81 during the RU~ state, a 6-bit wide word is read out of the RAM 81. The 6-bit words that are read out of the RAM 81 during a RUll state are designated as the xi signal.
Referrin~s back to ~ 5, it will be recalled that the RAM 81 is updated during the LOAD state portion of each 10 msec period by storing the ne~est Sq~ while discardi~g the oldest S~V.
Also, during the RU~ state portlon of each 10 msec period~ all of the word components ln each mask ln the mask storage memory 103 10 (FIWPES 8 and 5) are correlated with corresponding word components stored ln the RAD~ 81, by ccmputing a sequence of correlation functions on a component by component basis and summing all of the correlation functions to develop a correlation data signal for each mask. ~o achieve this correlation, as indicated in ~1~ 5, the xi signal from the RAM 81, along with the ri~ wi~ EOM and EOR signals from the mask storage memory 103, are applied to an arithmetic pipeline unit 151, which will now be more fully discussed.
The arithmetic pipeline unit 151 performs a series of mathematical operations in correlating the xi signal with the output 2 of the mask storage memory 103. The pipeline unit 151 is composed of four sequentlal arithmetic functions, each of which may be separated by a holding register frcrn the adjacent arithmetic ~unction. More specifically, the arithmetic pipeline unit 151 is comprised of a comparison function circuit 153, holding registers 155, 159 and 163, threshold and weighting function modi~iers 157 and 161, and a sum accumulator 165. I~he holding re3isters 155, 159 and 163 are con-~entional circuits well known in the art. Xowe~er, there are different ways in which the comparison function circuit 153 and threshold and ~7eighting function modifiers 157 and 161 can be ~056504 implemented, depending upon the type of correlation being utilized in the arithmetic pipeline unit 1510 The various implementatlons of the circuits 153, 157 and 161, as well as the implementation of the sum sccumulator 165, will be discussed later. At this time only a generalized discusslon of the operation of the circuits of the arithmetic pipeline unit 151 will be given.
At each 1 MHz "read" pulse time auring the gUN state, a 6-blt word xi is read out o~ the RAM 81 and the eighteen-bit word (co~prlsed of the 6-bit word ri~ the 5-bit word ~i~ the 5-bit word 1 0 wi~ the l-bit EOM and the l-bit EOR) is read out of the mask storage memory 103 The x~ and ri words are utilized by the comparison function 153 to generate a ci word. This ci word may vary up to 12 bits in width, depending upon the type of correlation operation being performed by the arithmetic pipeline unit 151. The cl, ~i and wi words and EOM
and EOR bits are clocked into and temporarily stored in the holding register 155 during each 1 MHz clock pulse period.
The ci and 6i words from the holding register 155 are selectively utilized by the threshold function modifier 157 to generate a ti word, which may vary up to 1~ bits in width, depending 2 0 upon the type of correlation operation being performed by the pipeline unit 151 The ti word fr~m the function modifier 157, and the ~i word and EOM and EOR bits from the holding register 155 are clocked into and temporarily stored in the holding register 159 during each 1 MHz clock pulse period.
~ he ti and wi words ~rom the holding register 159 are selectively utilized by the ~eighting function modifier 161 to deYelQp ~ rd~ ~ey up ts ~7~ bits in wldth, depe~ding upon the type of correlation operation being per~ormed by the pipe-line unit 151. The mi word from the function modifier 161 and the 1056S0~

EOM and EOR bits from the holding register 159 are clocked into and temporarily stnred in the holding register 163 during each 1 MXz clock pulse period.
At èach 1 M~z clock pulse time during the run gate, the data in a new mi word i9 applied to the sum accumulator 165 and added to ~hat has been previously accumulated. Each new data sum is an 18-bit correlation data word d, which is developed ~s an output of the arithmetic pipeline unit 151. At the end of each of the masks being read out o~ the mask storage memory 103, a "1" state EOM
1 0 signal from the holding reeister 163 is applied throu~h a 100 nsec delay circuit 167 to the sum accumulator 165 to clear the accumulator 165 for the start of the next mask.
Individual correlation operations between the reference mask templates (read out of the memory 103) and the digitized para-meterized continuous speech (read out of the RAM 81) are computed u~ing a discriminant function. The arithmetic pipeline unit y 1 could be implemented to perform any one o~ man~ different types of discriminant functions or correlation operations. A different dis-criminant function, and its associated mathematical operations, are mathematically depicted in FIGURE 12 for each of five exemplary types R arithmetic pipeline units 151. These five types of dis-criminant functions are:
TYPE DISCRIMI~A~ FU~CTIO~
#l Threshold Distance Function ~ Unweighted Absolute Value Distance Function #3 Weighted Absolute Value Distance Function ~ Euclidean Di~tance Squared Function #5 Dot Product of Two Vectors ~unction o 30 -~05650~
For the purpose of the following discusslon in relationto FIGURES 12 and 5, let ri refer to the components o~ a given mask expressed as vectors and xi re~er to the corresponding components o~ digitized parameterized speech being compared.
The metric for measuring degree o~ match between two vectors ri and xi h~ving weight vector wi and threshold vector ~i canJ in general, be expressed as:

a = ~, wiFi i=l 1 0 where Fi = F~ri~ Xi~

n = number of components or words in the given mask and i = 1, 2 ... , n.
~ere the ~ectors-are:
ri = ri~ r2~ rn Xi = Xl~ X2~ Xn i = wl, ~2~ ' Wn ~ i 91' ~2' ' ~n In addition, independence is assumed betNeen ccmponents.
The discriminant function for the solution of d in the 2 0 above general equatlon, or in FIGURE 12, may or may not employ thresholds (~i)' and the weight (wi) asslgned to each dimension may be unity. For example,~as seen in FIGURE l~, the unweighted absolute value distance ~unction c~ type ~ employs only vectors xi and rl, where ~i ¦Xi ~ r¦ and wi = 1 "` 1()56~0~

Llkewise, the Euclidean distance squared function of type ~4 is implemented using Fi = (Xi ~ ri) ~ where wi - 1.
and the dot product of two vectors function oP type #5 is implemented using Fi = xiri, where wi = 1.

On the other hand, the weighted absolute value di3tance function of type #3 employs the vectors xi~ ri and ~i even though Fl = ¦Xi - ri I

a And the threshold distance function of type #l employs all of the vectors xi, ri~ ~i and wi, wherein Fi = F( ¦ xi - r~

The minimum value of d in the equation d ~ wiF
.
or at the output o~ the sum accumulator 165 corresponds to the closest match ln the correlation of xi and ri.

As shown in FIGUKE 1~, for most comparison functions ci, - the relationship between xi and ri can be expressed in terms ci =
¦xi - rl¦ , as shown in type numbers 1 through 4. B~ introducing 2 a this di~ferent expression in place of xi and ri the independence function is modi~ied significantly. The previously stated assumption o~ independence between individual components o~ xi and ri is no longer required. The new assumption is that ¦ xi - r~¦ ~where i = 1, 2 ... n) be independent. The former assumption is wiaely employed in pattern recognition even though it is obvlously not -~ 10565V4 -valid. With the new assumption, however~ a greater degree of validity exists. Assumed is only that interfeature noise is independen~.
The comparison ~unctions 153 ~or type numbers 1 through 4 each have the property of requiring that the di~erential ¦xi - ri¦
be small ~or a good match, and only a ~ew large di~ferentials can cause a poor metric.
A modification in the threshold function modl~ier 157 to the camparison ~unction o~ type #l llmits the extent bo which a single component may degrade the matah metric. Such a limit usually employs a threshold and i5 illustrated in the threshold distance function o~ type ~1.
To more speci~ically describe the fi~e above-noted exemplary types of arithmetic pipellne units 151, reference will again be made to FIGURE 12J as well as to two types of ccmparison functions 153 illustrated in FIGURES 13A and 13B, three types of threshold function modi~lers 157 illustrated in FIGURES l~A, 14B
and 14C, two types of weighting ~unction modiflers 161 illustrated 1~ ~IGURES 15A and 15B, and the sum accumulator 165 illustrated in ~IGURE 16 2 0 In type #1, the "threshold distance function" operation may be defined as the sum o~ the 1 weighted ~wi) absolute values o~ the di~erences between corresponding ccmponents o~ the quantities Xi and ri, where the differences are less than the preselected threshold value o~ the quantity ~i and where i = 1, 2 0 . n. This ~irst function may be expressed as:

lT {,Xl - rL~

~05656)4 ~here i = 1, 2, ... n and n = the number o~ words in a given mask.
It can be seen in this type #1 function that both the thresholds l and weights wi are used.

In the explanation of the threshold distanae ~unction operation of arithmetic pipeline unit type ~1~ the specific com-parison ~unction circult 153A of FIGURE 13A, the speci~ic threshold function modifier 157A of FIGURE 14A and the speciflc weighting function modi~ier 161A of FIGURE 15A, a8 well as the sum accumulator 165 of FIGURE 16, wlll now be referred to.

0 The comparison function circuit 153A of FIGURE 13A
develops ci, or the absolute values of the difference between corresponding camponents o~ the two numbers or quantities xi and ri. More specifically, the 6-bit xi signal i8 directly applied to a c~mbiner circuit 201~ while the 6-bit ri signal is complemented by logical inverters or ~AND gates 203-208 before being applied to the combiner 201. ~o enable the combiner 201 to develop a 2's complemen~ arithmetic output, a binar~ "1" is also applied to the combiner 201 to be added to the complemented ri signal. ~he xi, 2 ri-and "1" signals are summed in the combiner 20I ta develop an output signal o~ 6 blts, ~hich 6 bits are respect~ively applied to associated first inputs of exclusive-OR gates 211-216. A carryout bit ~rom the c~biner 201 is logically inverted by NAND gate 219 before being applied to second inputs of the exclusive-OR gates 211_216. A "1" state carryout from the combiner 201 is inverted by the ~AND gate 219 to cause the exclusive-OR gates 211-216 to act as repeaters of the associated bits applied to their first inputs.

_ 34 -Conversel~r, a "O" state carryout from the combiner 201 is inverted by the ~D gate 219 to cause the exclusive-OR gates 211-216 to act as inverters of the associated bits applied to their first inputs.

The 6-bit output of the excluslve-OR ~tes 211~216 is æummed in a second combiner circult 221 with a second 6-bit number comprised of flve "O" bibs and the one bit output of ~9~1D gate 219.
As a result, this second 6-bit number is either 000000 (zero) or 000001 (one)~ dependlng upon whether the carryout bit is a binary "1" or binary "O". A "O" state carry-in bi-t (or no carry-in) i8 il O used by the combiner 221 in summir~g its two 6-bit inputs together.
~he output of the combiner 221 is a 6-bit word ci, which is equal to the absolute value of the dif~erence between each of the corres-ponding components of xi and ri.

To illustrate the 2's ccmplement arithmetic operation of the comparison ~unction 153A of FIGI~ 13A, first assume that Xi = 5 ~or 000101) and ri = 3 (or 000011) at one instant of time.
In this case, the additlon of 000001 (or 1) to 111100 ~the complement of ri, or ri) deve}ops 111101 (~ + 1); the ~um of 000101 (xi) and 111101 (ri + lj i~ the combiner 201 is 000010 2 0 (or 2) with a carryout of 1; and the inversion of the 1 carryout by the ~ilD gate 219 causes the exclusive-OR eates 211-216 to repeat their 000010 inputs at their outputs a~ causes 000000 to be added in the combiner 221 to the 000010 output of the gates 211-216 to develop a 6-bit ci output of 000010 (or 2) at that time.

~05~S04 ~ ow assume that xi = 3 (or 000011) and ri = 5 (or OOQ101).
In this second case, the addition of 000001 (or 1) to 111010 (ri) develops 111011 (ri + 1); the sum of 000011 (xi) and 111011 (ri ~ 1) in the combiner 201 is 111110 with a carryout of 0; and the ~nversion of the O carryout by the ~AND gate 219 causes the exclu~ive-OR gatea 211~216 to invert their 111110 inputs to develop the signal 000001 and cau~es 000001 to be added in the combiner 221 to the signal 000001 to develop a 6_bit ci output o~ 000010 (or 2).

The comparison function circuit 157A of FIGURE 13A has the 1 0 property of requiring that ci, or the differential ¦xi - ri¦ be small for a good match between xi and ri, and only a fe~ large differentials ~ can cause a poor match.
.~ The ci output fro.m the comparison function 153A o~ FIGURE
: : 13A is compared in amplitude with the threshold signal 9i in the .
; threshold function modifier 15~A that is illustrated in FIGURE 14A.
~he threshold function modifier 157A comprises a comparator 225 which develops a l-bit binary "1" state tl signal (ti = 1) when-ever the amplitude of ci is greater than the threshold ai.
Whene~er ci is equal to or less than the threshold ~i~ a binary 2 0 o state ti signal (ti = ) is developed.

~056504 As illustrated in the specific weighting fun~tion modifier 161A of FIGURE 15A, the ti output from the threshold function modi~ier 157A of FIGURE 14A is multiplied b~ the 5-bit weighting information w in a multiplier 229 to develop a 5-bit mi output word. ~he mi output word from the multiplier 229 is applied to the sum accumulator 165 o~
FIGURE 16.
In FIGURE 16~ the run gate ~rom FIGURE 6 enables an AND
gate 233 durlng the RUN state to pass 1 MHz clock pulses through a 100 nsec. delay circuit 235 to the "clock" input of a shift register 1 0 237. It will be recalled (as shown in FIGURE 5) that at each 1 MHz clock pulse time a new mi word i9 stored in holdlng register 163 and applied to the sum accumulator 165. Each mi word from the holding register 163 is summed in a combiner circuit 239 with what has been previously accumulated, and is now at the output o~ the shift register 237, to develop a new sum. After each new sum has stabilized, a 100 nsec-delayed 1 MHz clock pulse from the delay circuit 235 clocks that new sum into the shift register 237 The register 237 maintains at its output a running sum or total of the mi words pre~iously ge~erated 2 as a given mask is being read out of the mask storage memory 103 (FIGURE 5). ~his running sum or total of mi words at the output of the shi~t register is d, where n d = ~ mi' i~l and i = 1~ 2 ... n9 and n = the number of words in a given mask.
~herefore, it can be seen that each time a new mi signal i8 applied to the sum accumulator 165, it is added in the combiner 239 to what has been previously accumulated in the register 237 for the associated - 37 ~

~S6504 mask a~d developed as a new d value at the output of the su~ accumulator 165, At the end of each mask a~ EOM bit ~r~m the holding regi~ter 163 is pas3ed through a 500 nsec. delay circuit 241 to t~e "clear"
input of the shi~t re6ister 237. Thi3 delayed EOM bit clears all of the Q outputs (not 3h~wn) of th~ register 237 to binary ~to" states 30 that the re~ister 23~ will be in a cleared conditio~ at the start of the next mask.
~ he accumul~biDg operat~on or the 9um accu~ulator 165 will .
naw be described i~ relation to mask 2. A~ sho~ in FIGUEE 9, mask 2 i9 8 Sr~s lon3 and coDtains 128 wQrd~ in those 8 SF~s. As a result, a total o~ 128 mi word~ will be generated as mask 2 is being se~uen_ tially read out o~ the mask storage memory 103. There~ore~ the shift register 237 ca~ store the sum of thoso 1~8 mi words before a delayed 30M signal from the delay circuit 241 clear~ the shi~t register for the subsequent mi word rom mask 3. In the abo~e exam~le, if the sum of 90 mi words is stored in the register 237, the 91st mi word is summed with that sum, and, upon being clocked again, the register 2y stores the sum oi~ tho e 91 mi word~, It can t~ereiore be seen that a ~ew d output, or running total o~ mi words, i~ generated every 1O m~ec in response to the applicatlon of each new mi word to the co~biner 239. Each of these d outpu~s can be, for example, an 18-bit word~ For maæk 2 a total o~ 1?8 d words or outputs ~ill be ~enerated by the register 237 durlng each RU~ 3ta~e. ~ouever, as will be shown later, only the largest or last one o~ these 1~8 d words (d2) will be subsequently used as the mask 2 correlatlon da~a ~ignal.

_ 38 -105650~
Referring back to FIGURE 1?, in type ~2 the "unweighted absolute value distance funct~on" may be deiined as the sum of the i absolute values of the di~ferences between corresponding ccmponents of the quantities xi and ri, where i = 1, 2 ... n. This second ~unction may be expressed as:

n d = ~ ¦xi rl ¦, i 2l where i - 1, 2 .~. n and n = the number o~ words in a given mask. ~
It can be seen in this type ~2 iunction that the weighting word~ wi are ~ach egual to unity and that the threshold ~i is not 1 B u9ed~
In the implementation of the unweighted absolute value distance function o~ arithmetic pipeline unit type #2, the speci~ic comparison iunction 153A of FIGURE 13A, the specii~c threshold iunction modiiier 157C of ~IGU~ C,~ the speci~ic weighting ~unction modifier 161B o~ FIGt~æ 15B and the sum accumulator 165 oi FIGU~E 16 can be utilized. The c~arison iunction 153A o~ FIG~RE 13A and the sum accumulator 165 of FIG~lRE 16 have been previously discussed.
FIGtJRE 14C indicates that the threshold Iunction modiîier 157C is a straight lead 245. As a result, the threshold ~ is not utilized in 2 0 the threshold function modifier 157C of` FIG[~E 14C and ti = Ci The weighti~g function modifler 161B of FIGURE 15B illustrates a straight lead 247 to show that the weight wi. assigned to each component or dimension of the signal ti is unity. Therefore mi =
ti = Ci and each of the mi and ti words is a 6-bit word, since each value o~ ci ls a 6-bit word.

_ 39 -1~)565~)4 For the specific implementation of the type #2 unweighted absolute value distance function, the arithmetic pipellne unit 151 of FIGURE 5 can be simplified by deleting the holding register 155, 159 and 163 and the threshold and weighting function modifiers 157 and 161, and by applying the ci word (from tho comparison function 153A
of FIGURE 13A) and the EOM bit (from the mask storage memory 103) directly to the sum accumulator 165~ and also by respectively appl~i~g the EOM and EOR bits (from the mask storaee memory 103) to the r~m~ining places indicated in FIGURE 5.

1 0 Referring back to FIGUR~ in type #3 the "weighted absolute value dlstance functlon" may be defined as the sum of the i weighted (wi) absolube values o~ the differences between corres-ponding components of the ~uantities xi and ri, where i = 1, 2 ... n.
Ihis third function may be expressed as:

d = h Ni ¦ Xi ~ ri ¦ ~
=

where i = 1, 2 ... n and n = the number of words in a given mask.
It can be seen in this type #3 function that the threshold words ai are not utilized.

In the implementation of the weighted absolute distance 2 0 function of arithmetic plpeline unit type #3~ the speciiic comparison function 153A of EIGURE 13A, the speclfic threshold function modifier 157C o~ FI&URE 14C, the specific weighting function modifier 161A of FIGURE 15A and the sum accumulator 165 of FIGURE 16 can be utilized.
All o~ these circuits have been previously discussed and therefore require no further discussion. However, as inaicated in FIGUR~ 12, the bit lengths for the ci, ti, mi and d words in type #3 are 6, 6, 11 and 18, respectively. It should be noted that type #3 differs _ 1~o -~L05650~

from type ~1 in that no threshold a ls employed. As a result, for specifically implementing this type #3, the arithmetic pipeline unit 151 of FIGURE 5 can be simpllfied by deleting the threshold ~unction modifier 157 and the holding register 159, and by applying the ci and Wi words ~rom the holding register 155 directly to the weighting function modifier 161 (since ti = Ci and wi = wi) and the EOM and EOR
words ~rom the holding register 155 directl~ to the holding regi~ter 163.
Referring back to FIGURE 12S in type ~4 the "Euclldean di3tance squared function" may be de~ined as the sum of the squares of the 1 1 0 differences between corresponding components of the quantities xi and ri, where i = 1, 2 ... n. This fourth function may be expressed as:

~ 2 d = ~ (xi - ri) where i = 1, 2 ... n and n = the number of words in a given mask.
It can be seen that in this type #4 function each of the weighting words wi are egual to unity and that no threshold ~i words are utili7ed.
In the implementation of the Euclidean distance squared function of arithmetic pipel~ne unit type #4, the speclfic comparison function 153A of FIGURE 13A, the specific threshold function modifier 2 ~ 157B of FIGURE 14B, the specific weighting ~unction modifier 161B of FIGURE 15B and the sum accumulator 165 of FIGURE 16 can be utilized.
Only the threshold function modifier 157B of FIGURE 14B will now be discussed in detail, slnce the remaining ones of the above-identified circuits have been previously discussed.

The threshold function modifier 157B oY FIGURE 14B co~prises a s~uaring or multiplier circuit 249 which, while not utilizing the threshold ~i~ squares the 6-bit ci input by multiplying it by itsel~

_ 41 -~056504 to develop a 12-bit ti output which is equal to ci ci or ci . As indicated in FIGURE 12, the bit }engths for the mi and d words in type #4 are 12 and 18, respectively.
For the specific implementation of the type ~4 Euclidean distance squared function, the arithmetic pipeline unlt 151 of FIGUF~
5 can be simplified by deleting the weighting function modifier 161 and holding register 163, by directly apply$n~ the ti word and EOM
bit from the holding register 159 direcbly to the sum accumulator 165, and by also applying the ~OM and EOR blts from the holding register 159 to the remaining places indicated in FIGURE 5.
Referrlng back to FIGURE 1~ in type #5, the "dot product of two vectors function" may be deflned as the sum of the i products of corresponding components of the quantitles xi and ri where i = 1, 2 ... n. This fifth function may be expressed as:

i I

where i = 1,;2 ... n and n = the number of words in a given masX.
It can be seen in this type #5 function that the welghtlng words wi are each equal to unity and that none of the threshold words ~i are used 2 o In the implementation of the dot product of two vectors function of arithmetic pipeline unit type #5, the specific comparlson functlon 153B of FIG~RE 13B, the speciflc threshold function modifier 157C of EIGURE 14C, the speci~ic weighting function modifier 161B of FIGURE 15B and the sum accumulator 165 o~ FIGURE 16 can be utilized.
Only the comparison function 153B of ~IGURE 13B will be discussed in detail~ since the rest of the above-identified circuits ha~e been previously discussed.

_ 42 -The comparison function 153B o~ FIGURE 13~ camprises a multiplier 251 which multiplies corresponding components of the xi and ri words together to develop a 12-blt ci word. ~ere ci is equal to the product xi ri. As indicated in FIGURE 12, the bit lengths for each of the ti, mi and d words in type #5 are 12, 12 and 18 respectively.
For the speci~ic implementabidn of the type #5 dot product of two vectors function, the arithmetic pipeLine unit 151 of FIGU~E 5 can be simplified by deleting the holdlng registers 155, 159 and 163 and the throshold and weightin~ ~unction modifiers 157 and 161, and 1 0 b~ applying the ci word (from the compari~on function 153B of FIGURE 13B) and the EOM bit (fram the mask storage memory 103) directly to the sum accu~ulator 165,-and also by respectlvely applying the EOM and EOR bits (from the mask storage memory 103) to the remainlng places indicated in FIGURE 5.
~ he correlation operation bf the arithmetic pipeline unit 151 will no~ be further analyzed. More specifically, the correlation operation of the type #l unit 151 (FIGURE 1~) in con~unction with~
for example, a 16-word len~th mask X wil1 be analyzed by referring ; to FIGURE 17, since that type #1 unit utilizes both thresholds ~i 2 0 and weights wi. However, it should be noted that, from the informa-given, a similar analyæis can be readily made by those skilled in the art ~or the~other types of arithmetic pipeline units 151 (FIGURE 12).
Assu~e, as shown in FIGU$-E 17, that x1, ri- ~i and wi develop their respectively indicated values during the 16 consecutive periods of 1 MHz count pulses~(from the central control 87) for the 16-word length mask X. In this 16 word length mask, i = 1, 2 .., 16.
It can be seen that each o~ the ci words (from the comparison function 153A of FIGURE 13A) i~ equal to the absolute value o~ the differences - ~3 -~05~50~

between the corresponding xi and ri words. Whenever the values of these ci words exceed the corresponding threshold values ~i' the ti words (from the threshold function modifier 157A of FIGURE 14A) are equal to a value of one (1). For all other values of ci and ~i~ the ~alues of ths ti words are zero (O). The multlplications of corresponding values of the ti and wi words de~elop the mi words (from the weighting function modi~ier 161A of FIGU~E l5A). Whenever a ti word i3 equal to one (1) the assoclated re~ulting mi word is equal in valle to the associated weighting word wi. Whenever ~ ti 1 0 word is equal to zero (O), the associated resulting mi word is equal to zero (O). The su~mation or running total of the value of the previously Rccumulated mi words with the value o~ the newest mi word is shown, with the final sum at the output of the sum accumulator 165`of FIGURE 16 having a value of 31 during the final or sixteenth count pulse period for mask X. It is this final sum of 31 that is the output correlation data signal dx for mask X.
Referring back to FIGURE 5, the d's from the sum accumulator 165 in the aritk~etic pipeline unit 151 are appl~ed via a compoæite line 301 to the "data in" input of a first-ln, first-out (FIFO) 2 0 data storage circuit 303. The FIFO data storage circuit 303 can be comprised of an array of eighteen parallel_operated FIFO shift registers (not sh~wn), each of which can be of the type manufactured by Fairchild and have the Fairchild part number A7K3341191. Each FIFO shift register in the circuit 303 has 'idata in", "strobe in" and "strobe out" inputs and a "data out" output.
The 18 bits in each of the d's developed by the sum accumulator 165 are appl1ed to respective "data in" inputs of the eighteen FIFO shift registers in the circuit 303. All of the eighteen "strobe in" inputs are connected together for commonly receiving each EOM bit from the _ ~4 -~056S04 holdi~g register 163. ~y this means each EOM blt enables the eighteen FIFO shift registers to accept only the 18 bits in the last d word developed before the EOM bit is received. It can therefore be seen that only the 18 bits in one d word are respectively shifted into the circuit 303 for each mask that i be~ng read out of the mask storage memory 103. ~he d word that i9 stored in the cir-cuit 303 for each mask is the largest and hence last accumulated sum developed in the sum accumulator 165 befoxe the accumulator 165 i9 cleared by the delayed EOM bit from the delay circuit 167. ~he array 10 of FIFO shlft reglsters ln the circuit 303 internally shlfts ln parallel the 18 bits in each received d word d~n to the flrst empty locatlon. This enables the circuit 303 to sequentlally store a d word ~or each of the masks belng read out of the mask storage memory 103 during the RUN state.
As will shortly be explained ln more detail in relation to FIGURES 18 and I9~ the EOR (end-of-run) bit ~rom the holding register 163 is applied to the decislon ~unction 17. In response to each EOR
bit, the decision function 17 generates a serlal se~uence of ~ O
output strobe pulses. All of the "strobe out" outputs of the circuit 2 0 303 are connected together for commonly receiving each of the Fl~O
output strobe pulses. In this manner each of the se~uence of FIFO
output strobe pulses cammands all of the eighteen FIFO shift registers to collectively read out an associated 18-bit correlatlon data word d for an associated mask that had previously been read out of the mask storage memory 103. Since9 as indicated in FIGURE 9, there are M different masks stored ln the mask storage memory 103, there are M different correlation data words (dl, d2 ... dm) that are sequentially read out of the FIFO circuit 303.
The sequence of correlation data words are a~plied to the decision 1056S~4 functlon 17. The operation of the decision functlon 17 will now be more fully explained by re~erring to FIGURES 18 and 19 FIGURE 18 dlscloses a first portion of the decision function 17. In operation, the ~OR bit ~rom the holding regiRter 163 (~IGURE 5) sets a flip flop 311 to cause its Q output to change to a "1" state signal. This "1" state signal enables an AND gate 313 to pass 100 KEæ clock pulses (fr~m the system tlming generator 19 of ~IGURE 1) to the "count" lnput of a counter 315 and bo a 100 n~ec delay circuit 317.
1 0 Each of the 100 KHz pulses from the AND gate 313 i8 counted by the counter 315 to de~elop and apply an address caunt to the "address" input of a demultiplexer 319. Each of the 100 KXz pulses that is being counted by the counter 315 is also delayed 100 nsec by the delay circuit 317 to develop a FIFO output Rtrobe pulse.
Therefore, the output of the delay circuit 317 is the sequence of FIFO output strobe pulses which enable the FIFO data storage circuit 303 (FIGURE 5) to sequentiall~ read out and apply the 18-bit wide FIFO correlation data signals dl - dm to the demultiplexer 319.
Each addre6s count from the counter 315 is in a stabilized 2 0 condition before the associated one of the dl - dm data signals is applied to the demultiplexer 319 The FIFO output strobe pulses from the delay circuit 317 are also applied to the demultiplexer 319.
~he demultlplexer 319 may be a set of electronic switches which are sequentially addressed by the addresses fram the counter 315 to con~ert the serially-de~eloped dl - dm input data signals into parallel dl - dm output~. At the same time~ the demultiplexer 319 con~erts the serial sequence of FIFO output strobe pulses fr~m the delay circuit 317 into parallel output strobe signals~ strobe strobem.

~6 -~S65~4 Each output address count from the co~mter 315 is applied to one input of a comparator 321. ~he number M, which is equal to the number o~ masks stored in the mask storage memory 103 (FIGURE 5) is applied to a second input o~ the c~mparator 321. When the address count ~rom the counter 315 is equal to the number M, the comparator 321 develops an enable pulse which resets the ~lip flop 311 to prevsnt any more 100 KHz pulses from being passed by the AND gate 313. ~he enable pulse also resets the counter 315 to a zero (O) count. The ~lip ~lop 311 ~nd counter 315 remain in their reset aonditions untll 1 0 the ~ollowin~ EOR bit enables new FIFO correlation data signals to be demultiplexed. ~he mask correlation data signals dl - dm, the strobel _ strobe signals and the enable pulse are applied to a second portion o~ the decision ~unction 17, which is illustrated in FIGURE 19.
In FIGURE 19 the second part o~ the decision function 17 is shown ~or a ~our-ma~k case, where M = ~. However it should be realized that the implementation shown could readily be expanded to, for example, a 27-mask case (where M = 27). To correlate more than 27 masks within one sampling period~ a preselected number of the 2 o asynchronous correlation circuits 15 (~IGURF 5) could be operated in parallel to simultaneously produce a similar number o~ parallel streams of output correlation data. HoNever, i~ only one asynchronous correlation circuit 15 were used (as illustrated in FIGURE l), more than 27 masks could be correlated ~ithin one sampling period by basically decreasing the time required for each mask correlation within the chosen sampling period. In this latter case~ to expand the system o~ the invention to, ~or example, at least a 500-mask case, the following modi~ications could be made: present state-o~-the-art~ faster ~emories could be used ~or the RAM al and mask - ~7 -~56504 storage memory 103; the word-storage capacity of the mask storage memory 103 could be expanded to, for example, 131,072 words; a 10 MHz clock (instead o~ the illustrated 1 M~z clock) could be used to read out the words from the RAM 81 and memory 103 and to perform the other timing operations in the sy~tem; and a sampling time o~
20 msec (instead of 10 msec) could be used in the system by utili~lng a sampling ~requency o~ 50 Hz instead o* the illustrQted 100 X~). 0~ course, a combination o~ these two cases could also be used to increase the number of mask correlations within a 1 0 sampling perlod. Ib can therefore be seen that, by any of the above recited means, the system o~ the invention could be readily implemented to uæe any other desired number of masks.
It will be recalled that the words in each mask in the mask storage memory 103 are continuously compared with associated STVs, or digitized speech, stored in the RAM 81 (FIG~RE 5); that a correlation data signal d is the sum of these comparisons for an associated mask; that a correlation data signal (dl - dm) is gen-erated ~or each o~ the masks 1 - M in the memory 103; and that the relative amplitude o~ each of these dl - d signals represents a ~:: 2 0 measurement of the closene~s or re~emblance between the associated mask in the memory 103 and the speech stored in the RAM 81.
As described previously, the masks in the mask storage memory 103 (FIGURE 5) each represent a dyad or triad phonetic sound, Assume, for the ~our mask case illustrated in FIGURE 19, that the keyword "Los Angeles" is desired to be detected. Phonetically the keyword "Los Angeles" can be broken down to the sound groups "Los", "An" "ge" and "les". For purposes of the ~ollowing aiscussion, let the masks 1-4 respectively represent the sound groups "~os", "An", "ge" and "les".

- 48 _ ~056S(~4 During each 10 msec period new mask correlation data sienals dl, d2, d3 and d4 are generated and respectively applied by way of composite lines to buffer registers 331, 333 and 335 and to a combiner circuit 337. Every 10 msec the strobes 1-3 enable `- the registers 331, 333 and 335 to respectively shift in and store the newest values of dl~ d2 and d3. ~he buffer registers 331, 333 and 335 can each comprise 18 parallel shl~t registers (not shown) with each shift register containing 128 sequentially coupled flip flops (not shown). ~here~ore, each of the buffer registers 331, 333 and 335 can contain 128 consecutlve different values for the associated a at any given time~ For example, the buffer register 331 contains 128 consecutive valu~s of the mask 1 correlation signal dl. ~ince a different value of dl is generated every 10 msec, the register 331 (as well as each of the registers 333 and 335) is 1280 msec long.
- Associated with the buffer registers 331, 333 and 335 are windows of observation which are respectively time-positioned with respect to each other within the associated registers 331~
333 and 335 according to the relative times of occurrence of the : 2 0 phonetic sounds in the desired keyword, which in this example is "Los Angeles". For example, since the sound "Los" occurs before the sound "An", bhe window in the register 331 is located to the right of the window in the register 333. In a like manner, since the sound "An" occ~rs before the sound '1ge", the wind~w in the register 333 is located to the right of the window in the register 335. Since the sound 'lles" occurs last in the word "Los Angeles", it is applied directly to the ccmbiner 337.

~OS6504 Each of the windows o~ observation in the registers 331, 333 and 335 may be between 30 and 200 msec in length. The length or time duration of a w~ndow of observation is basically determined by the amount of variations in the rate o~ ipeech for the a~sociated dyad or triad. ~he more varlations in the rate of speech, the longer the window. On the other hand~ the boundaries of a window (or clo~e-ness of the windows to each other) are determined fro~ the tralning set o$ utterances. One boundary of the window ls determined by the closest ln time that the mask and the followin~ ad~acent mask are ever observed together, while the other boundary is determined by the ~urtherest away ln time that they are ever observed apart.
In determlning the length and boundaries of the wlndotts of observation for a desired keyword, the person who trains the trainer 105 (FIGURE 5) examines all of the training data to be used and statistically measures the ranges of each of the time ~ariances or variations of the associated masks with respect to each other.
Each window is derived from the training data by obser~ing the range or extremes of the varlations in time of the rates o~ speech for the associated dyad or triad ~ound in each desired keyword and adding 2 0 an additlonal 20~ of the range to each end. Each window is thus the empirical range o~ these variation~ expanded to permit limited addltional deviation found in the training data.
Each of the windows in FIGURE 19 are referenced to the last mask. As seen in FIGURE 19 for the four mask case, each of the windows for the buffer registers 331, 333 and 335 are referenced to mask 4 or more specifically to the current mask 4 correlation data signal d4. ~he further a~tay the windo~t in a buffer register is frcm the current d4 value ~or the last mask (mask 4), the wider the windott of observat10n. For example, in the buffer register 3319 the window between masks 1 and 4 is the widest, because it is furtherest away in time fram the current d4 value. On the other hand, in the buffer register 335, the window between masks 3 and 4 is the narrowest, because it is closest in time ~rom the current d4 value.
~ he windows in the buf~er registers 331, 333 and 335 are stationary as the correlation values dl - d3 are bein~ shifted through the buffers ~he various d values (of dl~ d2 and d3) contained in the wi~dows o~ the bu~er reglaters 331~ 333 and 335 are respectively applied to maximum or peak detectors 339, 341 and 343. Each peak detector detects the maximum d value within lts associated window.
The best match between a mask and the spectrographic signal stored in the RAM 81 is indicated by this peak value, which indlcates a close correlation between that mask with its associated part o~ a desired keyword. As indicated be~ore, the proper width and positioning of the windows with respect to each other enables the proper peaks for the associated components of a desired keyword to be s~multaneously developed when that desired keyword is present. The current value of d4~ along with the maxi~um values of dl, d2 and d3 that are developed within their respective windows are summed together in the 2 0 combiner clrcult 337 to develop a final declsion ~unctlon signal.
It can be seen that ln this illustration the final decision function signal is the summation o~ the present correlation value for the last mask (mask 4) and the maximum values, looking back in time, contained in the windoRs of the previous masks. Every 10 msec a new value of the final decision function is compu~ed.
The amplitude of each final decision function signal is indicative as to whether or not a desired keyword is co~tained in the speech being analyzed. To determine whether or not the desired key~ord is present, each final decision function signal, and a 3 0 decision threshold signal 0, are applied to a threshold gate 345.
The decision threRhold signal ~ is empirically derived in tralning ., 1C~56504 the trainer 105 (FIGUFE 5). Upon the application of the ena~le signal from the comparator 321 (~IGUFE 18), the threshold gate 345 develops a decisio~ output signal. ~he decision output is a "1" state signal whenever the final decision function signal is larger than the decision threshold ~, and a "0" state output otherwise. Every 10 msec a new value of decision output is computed by comparing a newly developed final decislon ~unction with the decision threshold ~. A "1" state decision output ~rom the threshold gate 345 indlcates that the correlation values of the speech input and the masks that make up that keyword have been detected in the right order and with the proper peak values, and that there~ore the desired keyword has been detected. ~his "1" state decision output could be utilized by an output circuit ~not shown) to ring a bell, turn a light on~ enable so~e control equipment to perform s~me preselected function~ such as the initiation or termination of the operation of scme other equipment (not show~). Due to the locations and widths of the windows in the circuit of FIGURE 19, the mask correlations can be combined in a manner that allows for a wide variation in rateæ of 2 0 speech.
It should be noted that the circuit of FIGURE lg can just detect one given keyword. Where additional ke~ords are desired to be detected, an additional circuit similar to that shown in FIGURE 19 is required for each additional keyword to be detected.
In this event the proper ones o~ the correlation data s~gnals dl - dm would have to be utilized with each additional keyword to be selected, with one buffer register being associated with all but the last mask o~ the mask group associated with any glven Xeyword, and with the windows in the buffer registers being properly positioned and having ; ~ O the proper widths. ~y continuously combining the mask correlation ~0S6504 data from the demultiplexer 319 (FIGURE 18) in a selective manner, as indicated above, any given number of keywords could be detected by the resultant system.
Where, for example, three multiple masks are used because o~ free variation and interspeaker e~fect (discussed previously) each o~ the three masks could be correlated in series (or even in parallel) with the output of the RAM 81. The correlation data ~ignals from these three multiple mask~ could then be simultaneou~ly applied to a maximum or peak detector (not sh~wn) simi~lar to the peak detectors 339, 341 1 0 and 3~3, with the maximum mask correlation value d of the three being applied as, for example, one of the d's to the circuitry of FIGURE 19.
~y using multiple masks, the system of the in~ention is not only able to accept a large number of d~fferent spea~ers but also able to accept broad free variation in the phonetic transcription of the keyword being detected.
FIGURE 20 discloses a block diagram o~ an alternate second part o~ the decision function 17 of FIGUR3 1 which may be utilized in lieu of the structure of ~IGURE 19. The circuit illustrated in FIGUFE 20, like that in FIGURE 19, deals with an exemplary four-mask 2 0 case. It should be obvlous that the circuit of FIGURE 20 could readily be expanded to utilize more masks in conformance with the teaching herein presented. Also the circuit of ~IGURE 20J like that of FIGURE 19, only has the capability of detecting one keyword.
To enable the system of the in~ention to have the capability of detecting any gi~en number o~ keywords, a correspondi~g number of - circuits similar to FIGURE 20 would have to be implemented into the system.

:1056504 It will be recalled that in the circuit of FIGURE 19, the windows of the buffer registers 331, 333 and 335 were referenced to the current mask correlation data (d4) that was derived fram the last mask (mask 4 in the illustrated example). In the circuit of FIGURE 20 each window is referenced to the correlation d~ta developed ~rom the following ad~acent mask rather than to that of the l~st ma~k.
In FIGURE 20 the mask 1 correlation data signals dl are consecutively strobed into a bu~fer register 351 every lO msec by the associated strobe 1 sienals. ~he register 351 has a window of 1 0 observation which substantially encompasses the whole storage capacity of the register 351. E~ery 10 msec a max~um detector 353 selects the peak dl value frcm the window of observation of the register 351.
Each peak dl output from the maximum detector 353 is su~med with an associated mask 2 correlation data signal d2 in a combiner circuit 355 to develop a first declsion ~unction signal for masks 1 and 2. Every lO msec a new first decision function is developed.
Consecutively developed first decision function slgnals from the combiner 355 are strobed into a buffer register 357 by associated strobe 2 ignals. Like register 351, the register 357 has a window - 2 0 of observation which sub~tantially encompasses the whole storage capacity of the register 357. Every 10 msec a maximum detector 359 selects the peak value of the first decision function signals stored within the window of ob~ervation in the register 357. Each peak first decision function from the maximum detector 359 is summed with an associated mask 3 correlation data signal d3 in a combiner circuit 361 to develop a second decision function signal for masks 19 2 and 3. E~ery 10 msec a new second decision function is developed.

:

.

~OS650~

Consecutively developed second decision function signals from the combiner 361 are strobed into a buffer register 363 by associated strobe 3 signals. Like registers 351 and 357, the buf~er register 363 has a window of observation which substantially encom-passes the whole storage capacity of the register 363. It can there-fore be seen that, while the registers 351, 357 and 363 of FICTURE 20 are similar to the registers 331, 333 and 335 o~ FIGURE 19, they a~e much shorter in length or storage capacity than the register6 of ~IGURE 19.
Every 10 msec a maximum detector 365 selects the peak value o~ the second decision function signals stored within the window of observation in the register 363. Each Feak second decision functlon from the maximum detector 365 is summed with an associated mask 4 correlation data signal d4 in a cambiner circuit 367 to develop a third decision function signal for masks 1, 2, 3 and 4. Since onl~
a four-mask case is illustrated in FIGURE 20, this third decision function signal is the final decision function signal. It can therefore be seen that the circuit o~ FIGURE 20 locates the maximum a discriminant value or decision fu,nction over the time window between two adjacent masks and adds this value to the discriminant function of the follcwing mask, etc. In this manner the ~inal decision function is sequentially accumulated in the circuit o~ FIGUR~ 20, rather than at the end llke in FIGURE 19.
The final decision ~unction ~rom the combiner 367 is compared with the empirically-derived decision threshold ~ in a threshold gate 369 to develop a decision output signal each time that the enable signal from the comparator 321 is applied to the gate 369. A "1" state decision output indicates that a preselected - 3 ~ keyword has occurred or been detected, while a "0" state decision output lndica~es the converse. A 'tl" state decisio~ output ~ig~al _ . . .
ca~ be used to periorm any of the ~unctions speci~ied in regard to FIGURE
19. As me~ioned before, whenever additional ~eyword~ are de3ired to be detected by the system, a~ addition circuit oi FIGURE 20 would be required to ba implemented i~to the system for each additio~al keyword.
Since the implemontation o~ PIGUg~ 20 re~erences each oi the windows in the bu~r re3i9t~r3 3519 357 ~nd 363 with respect to t,he ~ollowing ad~acent mQsk, rather than to ~he la9t mask as ls done in FIGURE 19, the implementatio~ o~ FIGURE 20 o~fers se~eral adva~tages 1 0 o~è~ the implementatio~ shown 1~ FIGURE 19, First, each oi the buf~ers 351, 357 and 363 i~ FIGUR~ 20 are relati~ely short 1~ le~gth, si~ce eQch winaow substantially encompasses the entire qtorag2 capacity oi the associated regi~ter. On the cther hand~ the circuit o~ FIGURE 19 requires a relati~ely l~rge storage capacity ior each oi the register~ 331, 333 and 335, slnce each ~inaow .
only utiliz23 a relati~ely small part of the storage capacity of itS
8930ciated one Oe the- reglsters 331, 333 and 335. In other words, less buffer storage capacity iq required in ~IGURE 20 than in FIGURE l9, 31nce the storage requlred in FIGURE 20 is o~ly the maximum occurrence time 2 ~ between adJacent ma~ks, ra~her than the msx1mum time between the first and last ma~ks oi PIGURE 19. ~herefore, a smaller ~maunt of hardware i~ Deeded ~or the cixcuit of FIGURE 20 than that oi FI w ~æ l9.

_ 56 _ ~056504 Second, the windows of the registers in FIGUKE 20 are each of the same length and narr~wer than those of the registers of FIGURE l9.
In FIGURE l9 the windows have to be made }onger and longer as the registers are referenced further and further away from the last mask. As shown in PIGURE l9, the register 331 required a longer window than the register 333 which in turn required a longqr window than the register 335. Thiæ iæ due to the fact that the variance of time occurrence i3 greater the more distant in time a window is from the correlation data ~rom the last mask. In ~IGUgE 20~ the variation within a word is measured, whereas in FIGURE 19 1 ~ the variation all across the word ls measured. The variation of mask l with respect to mask 2 is much less than the variation of mask l with reapect to the laat mask. Consequently, the circuit of FIGURE 20 can accept the same range o~ words as that of FIGURE l9, but with much narrower windows.
Third, the circuit of FIGURE 20 is more accurate than that of FIGURE l9 since the windows in FIGURE 20 are narrower than those in FIGURE l9 Ihe windows of PI~URE l9 muat be longer to capture the required information. The wider that a window ia, the more values are stored within. Consequently, there is ~ore chance of a false 2 a keyword detection occurring by picking the wrong value. Conversely, by utilizing smaller windows in FIGURE 20, more accurately describing the temporal relationshipa within the keyword utterance~ the false alarm probability is reduced.
The in~ention thus pro~ides a system for asynchronously detecting one or more keywordæ in continuous speech wherein the input speech is changed into a plurality of analog speech parameters by a speech processor, the speech parameters are selectively converted into digitized speech samples or STVs by an STV generator, sequences 3 o of the digltized speech samples are continuously correlated in an asynchronous correlation circuit with subelemen~s of one or more ~ 57 ~

~05650~

desired keywords in order to de~elop correlatlon data, and the correlation data selectively enables a decislon functlon circuit to develop a preselected decision output signal for each preselected key~ord that is detected.
While the salient features of the inventlon have been lllustrated and descrlbedJ lt should be readlly apparent to those skilled in the art that many changes and modification~ can be made ln the system o~ the lnvention presented without departing fr~m the spirit and scope of the inventlon. For example, the system of FIGURE 1 could be implemented with different logic circuits and timing signals~ operated with serial data instead of parallel data or vice-versa~ and/or modified, as previously described, to utilize any selected number of masks in either a limited or unlimited key-word detectlon operation. It is therefore intended to cover all such changes and modifications of the invention that fall within the spirit and scope of the in~ention as set forth in th~ appended claim~.

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Claims (29)

What is claimed is:

1. A system for detecting one or more keywords in continuous speech, said system comprising:
processor means responsive to a continuous speech signal for continuously developing a plurality of speech parameters therefrom;
generator means responsive to the plurality of speech parameters for periodically generating digitized speech samples therefrom;
correlation means responsive to predetermined sequences of the digitized speech samples for producing a plurality of correlation data signals; and a decision means for each desired keyword, each of said decision means being responsive to associated ones of the correlation data signals for developing an occurrence decision output whenever an associated keyword has been detected.

2. The system of Claim 1 wherein said processor means comprises:
input means for separating the continuous speech signal into a plurality of preselected frequency components; and parameter means responsive to the plurality of preselected frequency components for developing the plurality of speech parameters.

3. The system of Claim 2 wherein said parameter means comprises:
first means responsive to the plurality of preselected frequency components for producing a plurality of associated detected signals; and second means responsive to the plurality of associated detected signals for developing the plurality of speech parameters.

4. The system of Claim 2 wherein said generator means comprises:
means responsive to the plurality of speech parameters for developing time division multiplexed speech parameters; and conversion means for developing the digitized speech samples in response to the time division multiplexed speech parameters.

5. The system of Claim 4 wherein said correlation means comprises:
first memory means for storing the digitized speech samples during a first mode of operation and for sequentially reading out sequences of digitized speech samples during a second mode of operation;
second memory means for storing preselected digitized information units respectively representative of subelements of at least one preselected keyword and for sequentially reading out the stored information units during the second mode of operation;
and means for sequentially correlating each of the stored information units during the second mode of operation with a corresponding sequence of digitized speech samples to develop a corresponding correlation data signal for each stored information unit, the amplitude of each said correlation data signal being indicative of the closeness of match between its associated stored unit and the corresponding sequence of digitized speech samples.

6. The system of Claim 5 wherein each said decision means comprises:
a plurality of storage means for storing respective sequences of predetermined ones of the correlation data signals, each of said storage means having an associated window encompassing a preselected sequence of previously stored correlation data signals associated with that said storage means;
a plurality of maximum detectors respectively coupled to said windows of said plurality of storage means for respectively developing the peak values of signals within said windows;
a combiner for combining another predetermined one of the correla-tion data signals with the peak values of signals from said plurality of maximum detectors to develop a final decision function; and a threshold gate for developing an occurrence decision output whenever the amplitude of the final decision function exceeds that of a decision threshold signal, said occurrence decision output being indicative of the detection of the keyword associated with said decision means.

7. The system of Claim 4 wherein each said decision means comprises:
a plurality of storage means for storing respective sequences of predetermined-ones of the correlation data signals, each of said storage means having an associated window encompassing a preselected sequence of previously stored correlation data signals associated with that said storage means;
a plurality of maximum detectors respectively coupled to said windows of said plurality of storage means for respectively developing the peak values of signals within said windows;
a combiner for combining another predetermined one of the correla-tion data signals with the peak values of signals from said plurality of maximum detectors to develop a final decision function; and a threshold gate for developing an occurrence decision output whenever the amplitude of the final decision function exceeds that of a decision threshold signal, said occurrence decision output being indicative of the detection of the keyword associated with said decision means.

8. The system of Claim 4 wherein said decision means comprises:
a preselected number N of sequentially coupled signal units, each of said signal units comprising:
a storage circuit for storing a sequence of signals, said storage circuit having a window substan-tially encompassing its total signal storage capacity;
a maximum detector coupled to said window of said storage circuit for detecting the peak value of the signals stored within said window; and a combiner for developing a summed output signal by summing the peak value from said maximum detector with a preselected one of the correlation data signals; and a threshold gate, the first one of said sequentially coupled signal units storing a sequence of a first preselected one of the correlation data signals, a sequence of the summed output signals of each said combiner in the first N-1 combiners being applied to and stored in said storage circuit in the following one of said signal units, a sequence of the summed output signals of the Nth one of said combiners being applied to said threshold gate, said threshold gate generating an occurrence decision output whenever the amplitude of a summed output signal from the Nth one of said combiners exceeds that of a decision thres-hold signal, said occurrence decision output being indicative of the detection of the keyword associated with said decision means.

9. The system of Claim 8 wherein said correlation means comprises:
first memory means for storing the digitized speech samples during a first mode of operation and for sequentially reading out sequences of digitized speech samples during a second mode of operation;
second memory means for storing preselected digitized information units respectively representative of subelements of at least one preselected keyword and for sequentially reading out the stored information units during the second mode of operation;
and means for sequentially correlating each of the stored information units during the second mode of operation with a corresponding sequence of digitized speech samples to develop a corresponding correlation data signal for each stored information unit, the amplitude of each said correlation data signal being indicative of the closeness of match between its associated stored unit and the corresponding sequence of digitized speech samples.

10. The system of Claim 2 wherein said correlation means comprises:
first memory means for storing the digitized speech samples during a first mode of operation and for sequentially reading out sequences of digitized speech samples during a second mode of operation;
second memory means for storing preselected digitized information units respectively representative of subelements of at least one preselected keyword and for sequentially reading out the stored information units during the second mode of operation;
and means for sequentially correlating each of the stored information units during the second mode of operation with a corresponding sequence of digitized speech samples to develop a corresponding correlation data signal for each stored information unit, the amplitude of each said correlation data signal being indicative of the closeness of match between its associated stored unit and the corresponding sequence of digitized speech samples.

11. The system of Claim 10 wherein each said decision means comprises:
a plurality of storage means for storing respective sequences of predetermined ones of the correlation data signals, each of said storage means having an associated window encompassing a preselected sequence of previously stored correlation data signals associated with that said storage means;
a plurality of maximum detectors respectively coupled to said windows of said plurality of storage means for respectively developing the peak values of signals within said windows;
a combiner for combining another predetermined one of the correla-tion data signals with the peak values of signals from said plurality of maximum detectors to develop a final decision function; and a threshold gate for developing an occurrence decision output whenever the amplitude of the final decision function exceeds that of a decision threshold signal, said occurrence decision output being indicative of the detection of the keyword associated with said decision means.

12. The system of Claim 10 wherein said decision means comprises:
a preselected number N of sequentially coupled signal units, each of said signal units comprising:
a storage circuit for storing 2 sequence of signals, said storage circuit having a window substan-tially encompassing its total signal storage capacity;
a maximum detector coupled to said window of said storage circuit for detecting the peak value of the signals stored within said window; and a combiner for developing an output signal by combining the peak value from said maximum detector with a preselected one of the correlation data signals; and a threshold gate, the first one of said sequentially coupled signal units storing a sequence of a first preselected one of the correlation data signals, a sequence of the output signals of each said combiner in the first N-1 combiners being applied to and stored in said storage circuit in the following one of said signal units, a sequence of the output signals of the Nth one of said combiners being applied to said threshold gate, said threshold gate generating an occurrence decision output whenever the amplitude of an output signal from the Nth one of said combiners exceeds that of a decision thres-hold signal, said occurrence decision output being indicative of the detection of the keyword associated with said decision means.

13. The system of Claim 2 wherein each said decision means comprises:
a plurality of storage means for storing respective sequences of predetermined-ones of the correlation data signals, each of said storage means having an associated window encompassing a preselected sequence of previously stored correlation data signals associated with that said storage means;
a plurality of maximum detectors respectively coupled to said windows of said plurality of storage means for respectively developing the peak values of signals within said windows;
a combiner for combining another predetermined one of the correla-tion data signals with the peak values of signals from said plurality of maximum detectors to develop a final decision function; and a threshold gate for developing an occurrence decision output whenever the amplitude of the final decision function exceeds that of a decision threshold signal, said occurrence decision output being indicative of the detection of the keyword associated with said decision means.

14. The system of Claim 2 wherein said decision means comprises:
a preselected number N of sequentially coupled signal units, each of said signal units comprising:
a storage circuit for storing a sequence of signals, said storage circuit having a window substan-tially encompassing its total signal storage capacity;
a maximum detector coupled to said window of said storage circuit for detecting the peak value of the signals stored within said window; and a combiner for developing an output signal by combining the peak value from said maximum detector with a preselected one of the correlation data signals; and a threshold gate, the first one of said sequentially coupled signal units storing a sequence of a first preselected one of the correlation data signals, a sequence of the output signals of each said combiner in the first N-1 combiners being applied to and stored in said storage circuit in the following one of said signal units, a sequence of the output signals of the Nth one of said combiners being applied to said threshold gate, said threshold gate generating an occurrence decision output whenever the amplitude of an output signal from the Nth one of said combiners exceeds that of a decision thres-hold signal, said occurrence decision output being indicative of the detection of the keyword associated with said decision means.

15. The system of Claim 1 wherein said generator means comprises:
means responsive to the plurality of analog speech parameters for developing time division multiplexed analog speech parameters; and conversion means for developing the digitized speech samples in response to the time division multiplexed analog speech parameters.

16. The system of Claim 15 wherein each said decision means comprises:
a plurality of storage means for storing respective sequences of predetermined ones of the correlation data signals, each of said storage means having an associated window encompassing a preselected sequence of previously stored correlation data signals associated with that said storage means;
a plurality of maximum detectors respectively coupled to said windows of said plurality of storage means for respectively developing the peak values of signals within said windows;
a combiner for combining another predetermined one of the correla-ion data signals with the peak values of signals from said plurality of maximum detectors to develop a final decision function; and a threshold gate for developing an occurrence decision output whenever the amplitude of the final decision function exceeds that of a decision threshold signal, said occurrence of the keyword associated with said decision means.

17. The system of Claim 15 wherein said decision means comprises:
a preselected number N of sequentially coupled signal units, each of said signal units comprising:
a storage circuit for storing a sequence of signals, said storage circuit having a window substan-tialiy encompassing its total signal storage capacity;
a maximum detector coupled to said window of said storage circuit for detecting the peak value of the signals stored within said window; and a combiner for developing an output signal by combining the peak value from said maximum detector with a preselected one of the correlation data signals; and a threshold gate, the first one of said sequentially coupled signal units storing a sequence of a first preselected one of the correlation data signals, a sequence of the output signals of each said combiner in the first N-1 combiners being applied to and stored in said storage circuit in the following one of said signal units, a sequence of the output signals of the Nth one of said combiners being applied to said threshold gate, said threshold gate generating an occurrence decision output whenever the amplitude of an output signal from the Nth one of said combiners exceeds that of a decision thres-hold signal, said occurrence decision output being indicative of the detection of the keyword associated with said decision means.

18. The system of Claim 15 wherein said correlation means comprises:
first memory means for storing the digitized speech samples during a first mode of operation and for sequentially reading out sequences of digitized speech samples during a second mode of operation;
second memory means for storing preselected digitized informa-tion units respectively representative of subelements of at least one preselected keyword and for sequentially reading out the stored information units during the second mode of operation, and means for sequentially correlating each of the stored information units during the second mode of operation with a corresponding sequence of digitized speech samples to develop a corresponding correlation data signal for each stored information unit, the amplitude of each said correlation data signal being indicative of the closeness of match between its associated stored unit and the corresponding sequence of digitized speech samples.

19. The system of Claim 18 wherein each said decision means comprises:
a plurality of storage means for storing respective sequences of predetermined ones of the correlation data singals, each of said storage means having an associated window encompassing a preselected sequence of previously stored correlation data signals associated with that said storage means;
a plurality of maximum detectors respectively coupled to said windows of said plurality of storage means for respectively developing the peak values of signals within said windows;
a combiner for combining another predetermined one of the correla-tion data signals with the peak values of signals from said plurality of maximum detectors to develop a final decision function; and a threshold gate for developing an occurrence decision output whenever the amplitude of the final decision function exceeds that of a decision threshold signal, said occurrence decision output being indicative of the detection of the keyword associated with said decision means.

20. The system of Claim 18 wherein said decision means comprises:
a preselected number N of sequentially coupled signal units, each of said signal units comprising:
a storage circuit for storing a sequence of signals, said storage circuit having a window substan-tially encompassing its total signal storage capacity;
a maximum detector coupled to said window of said storage circuit for detecting the peak value of the signals stored within said window; and a combiner for developing an output signal by combining the peak value from said maximum detector with a preselected one of the correlation data signals; and a threshold gate, the first one of said sequentially coupled signal units storing a sequence of a first preselected one of the correlation data signals, a sequence of the output signals of each said combiner in the first N-1 combiners being applied to and stored in said storage circuit is the following one of said signal units, 2 sequence of the output signals of the Nth one of said combiners being applied to said threshold gate, said threshold gate generating an occurrence decision output whenever the amplitude of an output signal from the Nth one of said combiners exceeds that of a decision thres-hold signal, said occurrence decision output being indicative of the detection of the keyword associated with said decision means.

21. The system of Claim 1 wherein said correlation means comprises:
first memory means for storing the digitized speech samples during a first mode of operation and for sequentially reading out sequences of digitized speech samples during a second mode of operation;
second memory means for storing preselected digitized information units respectively representative of subelements of at least one preselected keyword and for sequentially reading out the stored information units during the second mode of operation;
and means for sequentially correlating each of the stored information units during the second mode of operation with a corresponding sequence of digitized speech samples to develop a corresponding correlation data signal for each stored information unit, the amplitude of each said correlation data signal being indicative of the closeness of match between its associated stored unit and the corresponding sequence of digitized speech samples.

22. The system of Claim 21 wherein each said decision means comprises:
a plurality of storage means for storing respective sequences of predetermined- ones of the correlation data signals, each of said storage means having an associated window encompassing a preselected sequence of previously stored correlation data signals associated with that said storage means;
a plurality of maximum detectors respectively coupled to said windows of said plurality of storage means for respectively developing the peak values of signals within said windows;
a combiner for combining another predetermined one of the correla-tion data signals with the peak values of signals from said plurality of maximum detectors to develop a final decision function; and a threshold gate for developing an occurrence decision output whenever the amplitude of the final decision function exceeds that of a decision threshold signal, said occurrence decision output being indicative of the detection of the keyword associated with said decision means.

23. The system of Claim 21 wherein said decision means comprises:
a preselected number N of sequentially coupled signal units, each of said signal units comprising:
a storage circuit for storing s sequence of signals, said storage circuit having a window substan-tially encompassing its total signal storage capacity;
a maximum detector coupled to said window of said storage circuit for detecting the peak value of the signals stored within said window; and a combiner for developing an output signal by combining the peak value from said maximum detector with a preselected one of the correlation data signals; and a threshold gate, the first one of said sequentially coupled signal units storing a sequence of a first preselected one of the correlation data signals, a sequence of the output signals of each said combiner in the first N-1 combiners being applied to and stored in said storage circuit in the following one of said signal units, a sequence of the output signals of the Nth one of said combiners being applied to said threshold gate, said threshold gate generating an occurrence decision output whenever the amplitude of an output signal from the Nth one of said combiners exceeds that of a decision thres-hold signal, said occurrence decision output being indicative of the detection of the keyboard associated with said decision means.

24. The system of Claim 1 wherein each said decision means comprises:
a plurality of storage means for storing respective sequences of predetermined ones of the correlation data signals, each of said storage means having an associated window encompassing a preselected sequence of previously stored correlation data signals associated with that said storage means;
a plurality of maximum detectors respectively coupled to said windows of said plurality of storage means for respectively developing the peak values of signals within said windows;
a combiner for combining another predetermined one of the correla-tion data signals with the peak values of signals from said plurality of maximum detectors to develop a final decision function; and a threshold gate for developing an occurrence decision output whenever the amplitude of the final decision function exceeds that of a decision threshold signal, said occurrence decision output being indicative of the detection of the keyword associated with said decision means.

25. The system of Claim 1 wherein said decision means comprises:
a preselected number N of sequentially coupled signal units, each of said signal units comprising:
a storage circuit for storing a sequence of signals, said storage circuit having a widow substan-tially encompassing its total signal storage capacity;
a maximum detector coupled to said window of said storage circuit for detecting the peak value of the signals stored within said window; and a combiner for developing an output signal by combining the peak value from said maximum detector with a preselected one of the correlation data signals; and a threshold gate, the first one of said sequentially coupled signal units storing a sequence of a first preselected one of the correlation data signals, a sequence of the output signals of each said combiner in the first N-1 combiners being applied to and stored in said storage circuit in the following one of said signal limits, a sequence of the output signals of the Nth one of said combiners being applied to said threshold gate, said threshold gate generating an occurrence decision output whenever the amplitude of an output signal from the Nth one of said combiners exceeds that of a decision thres-hold signal, said occurrence decision output being indicative of the detection of the keyword associated with aid decision means.

26. A system for detecting one or more keywords in continuous speech, said system comprising:
input means for separating an input continuous speech signal into a plurality of frequency components;
parameter means for developing a plurality of analog speech parameters in response to the plurality of frequency components;
generator means for periodically generating digitized speech samples of the plurality of analog speech parameters;
first memory means for storing sequences of the periodically generated digitized speech samples;
second memory means for storing preselected digitized information units respectively representative of subelements of at least one preselected keyword;
means for correlating each of the stored information units with a corresponding sequence of digitized speech samples during a read mode of operation to develop a corresponding correlation data signal for each stored information unit;
and a decision means for each desired keyword, each of said decision means being responsive to associated ones of the correlation data signals for developing an occurrence decision output whenever an associated keyword is detected.

27. The system of Claim 26 wherein each said decision means comprises:
a plurality of storage means for storing respective sequences of predetermined ones of the correlation data signals, each of said storage means having an associated window encompassing a preselected sequence of previously stored correlation data signals associated with that said storage means;
a plurality of maximum detectors respectively coupled to said windows of said plurality of storage means for respectively developing the peak values of signals within said windows;
a combiner for combining another predetermined one of the correla-tion data signals with the peak values of signals from said plurality of maximum detectors to develop a final decision function; and a threshold gate for developing an occurrence decision output whenever the amplitude of the final decision function exceeds that of a decision threshold signal, said occurrence decision output being indicative of the detection of the keyword associated with said decision means.

28. The system of Claim 26 wherein said decision means comprises:
a preselected number N of sequentially coupled signal units, each of said signal units comprising:
a storage circuit for storing a sequence of signals, said storage circuit having a window substan-tially encompassing its total signal storage capacity;
a maximum detector coupled to said window of said storage circuit for detecting the peak value of the signals stored within said window; and a combiner for developing an output signal by combining the peak value from said maximum detector with a preselected one of the correlation data signals; and a threshold gate, the first one of said sequentially coupled signal units storing a sequence of a first preselected one of the correlation data signals, a sequence of the output signals of each said combiner in the first N-1 combiners being applied to and stored in said storage circuit in the following one of said signal units, a sequence of the output signals of the Nth one of said combiners being applied to said threshold gate, said threshold gate generating an occurrence decision output whenever the amplitude of an output signal from the Nth one of said combiners exceeds that of a decision thres-hold signal, said occurrence decision output being indicative of the detection of the keyword associated with said decision means.

29. A system for detecting one or more keywords in continuous speech, said system comprising:
first means responsive to a continuous speech signal for periodically generating a plurality of digitized speech parameters therefrom;
correlation means responsive to predetermined sequences of the digitized speech samples for producing a plurality of correlation data signals; and a decision means for each desired keyword, each of said decision means being responsive to associated ones of the correlation data signals for developing an occurrence decision output whenever an associated keyword has been detected.