CA1067208A - Insulated gate field-effect transistor read-only memory array - Google Patents

Insulated gate field-effect transistor read-only memory array

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Publication number
CA1067208A
CA1067208A CA307,472A CA307472A CA1067208A CA 1067208 A CA1067208 A CA 1067208A CA 307472 A CA307472 A CA 307472A CA 1067208 A CA1067208 A CA 1067208A
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Canada
Prior art keywords
potential
source
igfet
drain
signal
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Expired
Application number
CA307,472A
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French (fr)
Inventor
Antony G. Bell
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Fairchild Semiconductor Corp
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Fairchild Camera and Instrument Corp
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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0491Virtual ground arrays
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

ABSTRACT OF THE DISCLOSURE
An array of read-only memory cells is formed from a plurality of insulated gate field-effect transistors.
Information may be programmed into individual transistors within the array by application of selected potentials to the connecting lines of the array. An individual cell is programmed by causing some of the electrons flowing between the source and drain to acquire sufficient energy to be injected into and trapped in the insulating material separating the channel from the gate electrode. The trapped electrons cause a change in the current-voltage characteristics of the transistor, which may be detected during reading of the memory cell most easily by reversing the polarity of the source and the drain Embodiments of such an array are shown and may be utilized as a ROM, PROM or EPROM.

Description

~o67Z~8 BACKGROUND OF THE INVENTION
1. Pield of the Invention This invention relates to read-only memories, program-mable read-only memories, and erasable programmable read-only memories, and in particular to read-only memories fabricated from insulated gate field-effect transistors in which information is stored by the phenomena of hot electron trapping.
2. Prior Art A random access memory ~hereinafter RAM) is an array of latches, each with a unique address, having an addressing structure which is common for both reading and writing. Data stored in most typesof ~M~s ~s~olatile because it is stored only as long as power is supplied to the RAM. A read-only memory Chereinafter ROM) is a circuit in which information is stored in a fixed, nonvolatile manner; that is, the stored informa-tion remains even when power is not supplied to the circuit.
By convention, a ROM is a circuit in which information is stored by alterations made during fabrication or processing of the semiconductor wafer, while a programmable read-only memory (hereinafter PROM) is one in which the information is stored after the device is fabricated and packaged. Erasable programmable read-only memories (hereinafter EPROM's) are PROM's which can be completely erased and reprogr = ed.
EPROM's typically have been fabricated from arrays of MOS
transistors.
Electrically programmable ROM's fabricated using insulated gate field-effect transistors (hereinafter IGFET) have typically been of two different types. One type of elec-trically programmable ROM is the metal nitride oxide semi-conductor structure (hereinafter MNOS). Such structures rely on ¦ F-1347 I
10672~8 1 charge tunneling phenomena and have been described in numerous 2 publications. See, for example, "IEEE Transactions on Electron
3 Devices", May 1977, Volume ED24, Number 5. (A special issue
4 on nonvolatile semiconductor memories.) A typical MNOS structure is shown in Fig. 1. Such a 6 structure utilizes a very thin layer of insulating material, 7 typically silicon dioxide, to separate a silicon nitride 8 region and a gate electrode from the channel of the device.
9 MNOS devices are programmed by applying a positive potential to the gate electrode while holding the source, drain, and 11 substrate regions at a lower potential. This causes electrons 12 in the ~ubstrate and channel regions to "tunnel" vertically 13 through the oxide layer and lodge in the nitride layer.
14 For the electrons to tunnel through the oxide, the oxide layer must be Very thin, typically on the order of 20 16 to 30 angstroms. In addition, the electric field in the 17 gate insulating region must be very high for efficient 18 tunneling. The high electric field requires the use of high 19 voltages and a relatively thin nitride layer, typically on the order of 500 angstroms.
21 Accurate control of the thickness of the thin silicon --22 dioxide layer has proven difficult in a production environment, 23 as has control of the silicon nitride film properties.
24 Also, the high electric field required for tunneling can easily cause permanent damage to the memory.cells or to 26 peripheral circuitry, thereby reducing the yield of such 27 devices and increasing their costs. In addition, movement of _ 28 charge within the nitride and tunneling of the electrons 29 trapped in the nitride layer back through the thin oxide can change or destroy the information stored in the device, 10f~720~

ruining its e~fectiveness.
MNOS structures typically use expitaxial substrates and isolation diffusions to isolate each memory cell or groups of memory cells, depending upon the desired array organization, from surrounding cells or other peripheral circuitry. Because the tunneling effect is uniform across the full width of the gate electrode, the electrons trapped in the nitride will be almost uniformly distributed across the width of the silicon nitride layer. This results in electrically symmetrical device operation because device operation is not affected by source and drain terminal interchanges.
Another type of memory element used in forming electrically programmable ROM's is the field alterable MOS
transistor structure, also known as a floating gate structure (hereinafter FAMOS type). Such structures are well known.
See, for example, United States Patent 3,500,142 entitled FIEI,D EFFECT SEMICONDUCTOR APPARATUS WITH MEMORY INVOLVING
ENTRAPMENT OF CHARGE CARRIERS issued to D. Kahng and D. Frohman-Bentchkowsky, Applied PHysics Letters, Vol. 18, Page 332, 1971.
An example of a FAMOS type s ~ ture is shown in Figure 2.

FAMOS type structures utilize a charge injection phenomenon in which a control gate and drain electrodes are biased to cause electrons flowing between the source and drain to pass from the substrate and collect on the floating gate electrode.
The electrons' momentum from the source to the drain causes most of them to be injected onto the portion of the floating gate electrode nearest the drain. Because the floating gate electrode is conductive, the electrons spread out on the float-ing gate as they repel each other, thereby preserving electrical symmetr~ with respect to the source and drain terminals.

` ~06720~3 Un~ortunately, the FAMOS structure suffers from several disad~antages. A relatively thin layer of oxide or insulating material must be formed ~etween the floating gate electrode and the control electrode. This requires carefully controlled manufacturing processes resulting in lower yields and higher costs. Additionally, programming the FAMOS struc-ture requires relatively high voltages, for example, on the order of 25 to 30 volts. Such high voltages can cause ex-cessive parasitic conduction and/or rupture of the thin films formed elsewhere on the wafer. Further, the high voltages required increase the complexity of the structure of the device because the source and drain must be formed with care-fully controlled concentration profiles to ensure pn junction breakdown at the desired high voltages.
It has been discovered, and observed to be a limita-tion in I~FET design, that under appropriate biasing conditions electrons flowing between the source and drain of an IGFET can acquire sufficient energy to be injected into the insulating material between the gate electrode and the channel. Some of the injected electrons are trapped in the insulating materi-al near the drain, causing a change in the current-voltage characteristics of the IGFET, and creating an electrically asymmetrical structure sensitive to source/drain terminal interchanges. This effect is discussed in an article en-titled "N-Channel IGFET Design Limitations Due to Hot Electron Trapping", by S.A. Abbas and R.C. Dockerty, and published in the IEDM Proceedings, Washington, D.C., 1975. Abbas and Dockerty explain that the electrons flowing between the source and drain of an IGFET may under certain conditions undergo randomizing scattering motions which cause them to - 4 .

1 E-l347 ~067Z08 1 move toward the interface between the silicon substrate and 2 ¦overlying silicon dioxide layer. Some fraction of the 3 ¦electrons arriving at this interface have sufficient energy 4 ¦to be injected into the insulating material and trapped to cause a change in the operating characteristics of the 6 ¦part_cular transistor. Abbas and Dockerty observe that the 7 ¦change in operating characteristics is most evident when the 8 ¦transistor is operated in a reverse mode, that is, with the source and drain interchanged.

11 ¦SUMMARY OF THE INVENTION
lZ Applicant has discovered that the phenomenon of hot 13 electron trapping may be utilized to fabricate improved arrays 14 of IGFET memory cells. One cell of such an array may be 15 Ifabricated with well known MOS technology and may be programmed 16 electrically by applying suitable potentials to its source, 17 ¦drain and gate electrodes. By biasing the IGFET into its 18 pinch-off region, hot electrons are generated which are 19 injected, rather than tunneled, from the channel into the gate insulating material where they are trapped. The trapped 21 electrons cause a shift in the current-voltage characteristics 22 of the IGFET which is greatest if the IGFET is programmed in 23 one mode and-operated in the opposite mode, that is, with the 24 ¦source and drain terminals reversed. The change in current-25 ¦voltage characteristics of individual cells can be representative 26 ¦of information. _ 27 One cell of applicant's array may be fabricated simply 28 according to well known MOS fabrication processes. Because 29 ¦the memory cell is simple in design, it occupies a relatively small amount of wafer surface area, allowing large dense arrays.

Also, unlike prior-art MNOS- and FAMOS-type devices, no particularly thin regions of insulating material are required. This allows higher yields, lower ~ost and greater reliability.
Applicant has discovered that the memory cells may be arranged in a variety of arrays to create ROM's, PROM's and EPROM's. In one embodiment of the invention, a plurality of IGFET's each have a source connected to a single common line, a gate connected to one of a plurality of x lines and a drain connected to one of a plurality of y lines. By application of appropriate signals to ~he common line and the x and y lines, information may be stored in any desired IGFET and later retrieved.
In another embodiment, a plurality of IGFET's each have a gate connected to one of a plurality of i lines, a source connected to one of a plurality of j lines and a drain connected to one of a plurality of k lines.
By application of suitable signals to the i, j and k lines, information may be stored in and later retrieved from any desired cell.
Thus, according to one broad aspect of the present invention, there is provided a random-access semiconductor memory array comprising: a common line; a plurality of x lines; a plurality of y lines; a plurality of semiconductor memory cells, each being coupled to at least one of the x lines and one of the y lines and the common line, wherein each semiconductor memory cell comprises an insulated gate field-effect transistor (IGFET) which includes: a substrate of p conductivity type; spaced apart source and drain regions formed in the substrate, each of opposite conductivity to the substrate; a gate insulating region formed on the substrate between the source and the drain, the gate insulating region including means for trapping charge; an electrically conductive gate electrode formed on the gate insulat-ing region between the source and the drain; means for defining a state in the IGFET by applying a first signal to the gate electrode, a second signal to the source, and a third signal to the drain, wherein the potential of each of the first and second signals is greater than the potential of the third signal, to introduce charge nonuniformly into the gate insulating region predominantly toward the source region, and store charge nonuniformly ~ ~ -6-,.~, ,, ~--- , -106720~3 in the gate insulating region in the means for trapping charge predominant-ly toward the source region; means for detecting the state defined in the IGFET by applying a fourth signal to the gate electrode, a fifth signal to the source, and a sixth signal to the drain, wherein the potential of each of the fourth and sixth signals is greater than the potential of the fifth signal; and the application of electrical signals to the common, the x and the y lines, controls the means for defining a state in the IGFET.
According to another broad aspect of the invention, there is provided a method of programming a random-access semiconductor memory array having a common line, a plurality m of x lines, a plurality n of y lines and a plura;ity of IGFET's wherein each IGFET is connected to one x line and one y line, transistor T b being connected to line a and line b, where 0 ~a_<m and 0 ~b_<n, wherein each IGFET includes: a substrate of p conduc-tivity type; spaced-apart source and drain regions formed in the substrate, each of opposite conductivity to the substrate; a gate insulating region formed on the substrate between the source and the drain; an electrically conductive gate electrode formed on the gate insulating region between the source and the drain; and means for defining a state in the IGFET by apply-ing a first signal to the gate electrode, a second signal to the source, and a third signal to the drain, wherein the potential of each of the first and second signals is greater than the potential of the third signal, to introduce charge nonuniformly into the gate insulating region predominantly toward the source region, and store charge nonuniformly in the gate insulat-ing region in the means for trapping charge predominantly toward the source region; means for detecting the state defined in the IGFET by applying a fourth signal to the gate electrode, a fifth signal to the source, and a sixth signal to the drain, wherein the potential of each of the fourth and sixth signals is greater than the potential of the fifth signal; and tran-sistor Tab is programmed by the following steps: applying a first potential to the com~on line, the x lines and the y lines, applying a second potential to the common line, applying a third potential to all y lines except line b, applying a fourth potential to line a to activate the means for defining a ~ -6a-, J--~

~067208 state in the IGFET.
The invention will now be described in greater detail with reference to the accompanying drawings, in which:
Fig. 1 is a cross-sectional view of a prior-art MNOS structure;
Fig. 2 is a cross-sectional view of a prior-art FAMOS type struc-ture;
Fig. 3 is a cross-sectional view of an IGFET depicting schematic-ally that electrons flowing between the source and the drain may gain sufficient energy to be injected into and -6b-1 ~067~20~

1 ¦ trapped in the gate insu~ating material;
2 ¦ Fig. 4 is a graph showing how the current-voltage 3 ¦ characteristics of the IGFET may be altered by hot electron 4 ¦ trapping;
5 ¦ Fig. 5 is a schematic diagram of a single IGFET showing
6 ¦ the potentials applied to its source, drain, and gate for
7 ¦ both programming and operating the IGFET;
8 ¦ Figs. 6a through 6d depict one method for forming the
9 ¦structure shown in Fig. 6e.
10 ¦ Fig. 6e is a simplified cross-sectional view showing
11 ¦one embodiment of an IGFET memory cell with source, gate,
12 ¦and drain electrodes; and
13 ¦ Fig. 7 is a schematic diagram of an array of memory
14 ¦cells of the type shown in Fig. 5 or Fig. 6e;
15 ¦ Fig. 8 is a schematic diagram of another array of
16 ¦memory cells of the type shown in Fig. 5 or Fig. 6e.
17 l
18 DETAILED DESCRIPTION
19 Fig. 1 is a cross-sectional view of an MNOS structure
20 of the prior art. In this structure a very thin layer of
21 oxide, on the order of 20 to 30 angstroms thick, is formed
22 over the channel region of the transistor and beneath the
23 gate electrode. Typically, a 500 angstrom thick region of
24 silicon nitride is formed on the upper surface of the very
25 thin oxide. To isolate the MNOS cell from any others formed
26 on the same substrate a pn junction as shown in Fig. 1 must _
27 surround the memory cells. The disadvantages of this structure
28 have already been discussed.
29 Fig. 2 is a cross-sectional view of a FAMOS type prior-
30 art structure. In the FAMOS type structure, a floating - ~ F-1347 ~067201~3 1 ¦ gate, that is, a thin conductive region isolated from both 2 ¦ the channel and the control gate electrode, is used to store 3 ¦ a charge which later may be sensed. The disadvantages of ¦ the FAMOS structures have already been discussed. _ 5 ¦ Fig. 3 is a simplified cross-sectional view of an 6 ¦ IGFET. The transistor includes a substrate 12, a source 7 ¦ region 15, a drain region 16, insulating layers 18 and 20, 8 ¦ and gate electrode 14. MOS transistors like that depicted ¦ in Fig. 3 are well known. Such transistors may be fabricated 10 ¦ utilizing a p conductivity type substrate 12, n type source 11 ¦region 15 and n type drain region 16. Insulating layers 18 12 and 20 may be any suitable material, but typically layer 18 13 ¦will be silicon dioxide and layer 20 will be silicon nitride.
14 Gate electrode 14 will be an electrically conductive material, for example, polycrystalline silicon or metal.
16 It has been discovered that by biasing the IGFET transistor 17 structure shown in Fig. 3 with a positive voltage on the 18 drain 16, a substantially equal or larger positive voltage, 19 typically pulsed, on the gate electrode 14, and a lesser 20 voltage, typically ground, on the source 15, that electrons 21 flowing between the source and drain can acquire a sufficient 22 energy to be injected into the gate insulating regions 18 23 and 20. Abbas and Dockerty, supra, report that the electrons 24 flowing between the source 15 and drain 16 may undergo 25 direction randomizing scatterings which cause some of them 26 to move in the direction of the interface between the silicon 27 dioxide layer 18 and substrate 12. Some of the electrons _ 28 moving in this direction will have sufficient energy to 29 travel from the silicon substrate 12 into the gate insulating 30 materials 18 and 20, where they are trapped. The effect is .

1 shown schematically in Figure 3 by the arrow and minus 2 signs, representing the path of an electron and the locations 3 of previously trapped electrons, respectively. The number 4 of electrons trapped will depend on numerous factors as elaborated by Abbas and Dockerty. Principal factors, however, 6 are the number of electrons injected, the number of sites 7 available for the trapping and their capture cross-section.
8 Silicon nitride 20 is known to have a much greater trapping 9 efficiency than silicon dioxide layer 18, and consequently most of the electrons being injected into the gate insulating 11 layers 18 and 20 will lodge in silicon nitride layer 20.
12 The,momentum of the electrons w~-ll cause most to be trapped 13 nearer drain 16 than source 15. Fig. 3 shows schematically 14 by the "-" signs that most electrons are trapped in layer 20 near drain 16.
16 The exact number of electrons which must be trapped is 17 not critical as long as the number is sufficient to allow 18 the difference between the programmed and unprogrammed 19 states to be detected electrically. Useful threshold voltage changes for programming can be created in periods on the 21 order of milliseconds with gate and drain voltages on the 22 order of 15 to 20 volts. Five volts is sufficient for 23 subsequent circuit operation.
24 The effect of the trapped electrons upon the operating characteristics of the IGFET is shown in Fig_ 4. The 26 current-voltage curve for the IGFET which has not been _ -27 programmed, that is, which has not had electrons injected 28 into its gate insulating regions 18 and 20, is designated in 29 Fig. 4 by the curve marked "initial unprogrammed." If after 30 programming the structure by injecting electrons into the ~67ZO~

1 gate insulator 18 and 20, the IGFET is operated in the same 2 direction as it was programmed, the relationship between 3 current and voltage will be shifted slightly to the right.
4 That is, a given voltage causes a slightly smaller current than for an unprogrammed device. This is shown in Fig. 4 by 6 the curve designated "normal mode after programming." The 7 shift in current-voltage characteristics after programming, 8 however, may be made most pronounced if the IGFET is operated 9 in the reverse mode, that is, with the source and drain polarities reversed. This effect is also shown in Fig. 4, 11 where the current-voltage relationship for the device after 12 programming when operated in a reverse condition is shown by 13 the curve designated "reverse mode after programming." By 14 operating the device in a reverse mode after programming, a substantially greater voltage is required to produce a given 16 current than in either the "initial unprogrammed" condition 17 or the "normal mode after programming" condition. It is 18 this substantial change in the current-voltage relationship 19 which may be used to change the "state" of selected transistors 20 within a memory to thereby store information for later 21 recall during "reading" of the memory.
22 A cross-sectional view of an IGFET programmed and 23 operated according-to one embodiment of applicants' invention 24 is shown in Fig. 5. Fig. 5 depicts an IGFET which includes 25 a gate electrode 14, a source region 15, a drain region 16, 26 and gate insulating regions 18 and 20. The source and drain _ 27 will be ~*e conductivity type, while the substrate is opposite 28 conductivity. A structure such as that depicted in Fig. 5 29 would form a single cell of a ROM, PROM, or EPROM. To 30 program the memory cell shown in Fig. 5, selected voltages 1¦ are applied to the source and gate electrode, while a lower 21 voltage is applied to the drain. The voltage applied to the
31 gate is pulsed in some embodiments. The applied voltages 4 ¦ cause electrons to flow from the drain 16 through the 5 ¦ channel 17 in substrate 12 and toward the source 15. In the 61 manner previously described, some of the electrons will be 7 1 injected into the gate insulating regions 18 and 20. If 8 ¦ region 18 is silicon dioxide and region 20 is silicon nitride, 9 ¦ then, because of the trapping characteristics of these two 10 ¦ materials, most of the electrons injected will be trapped in 11 ¦ silicon nitride region 20. Further, because the electrons 12 are flowing toward source 15, most will be trapped near that 13 ¦end of the silicon nitride layer 20. The information stored 14 ¦in the cell may be sensed by changing the polarity of the 15 ¦source and drain, that is, by biasing the drain 16 to a 16 higher voltage than the source 15, and then detecting the 17 ¦shift of current-voltage characteristics. It will be apparent 18 ¦to those skilled in the semiconductor arts that the cell may 19 be programmed by applying a higher voltage to the drain 16 20 ¦than the source 15, and then reversing this-for reading.
21 The determination of which region is the source and which is 22 the drain is a matter of convention.
23 At least two advantages result from programming the 24 cell in an opposite direction from that in which it is 25 ¦operated. If the cell were not programmed with a polarity 26 opposite to that of the normal reading operation, the threshold 27 ¦voltage shift would be small and difficult to sense. This _ 28 ¦is shown in Fig. 4 by the relative closeness of the curves 29 designated "initial unprogrammed" and "normal mode after 30 programming." Secondly, by avoiding reversal of the bias ; F-1347 1~672~)8 1 voltage, devices in the peripheral control circuitry for a 2 memory utilizing this invention do not suffer unwanted 3 changes in their operating characteristics.
4 Fig. 6e depicts a cross-section of one embodiment of a S single IGFET suitable for use as a ROM, PROM, or EPROM cell.
6 The structure shown in Fig. 6e, like the structures shown in 7 Figs. 3 and 5, includes a substrate 30, a channel 33, a 8 source 31, and a drain 32. Also shown are silicon dioxide 9 37 and silicon-nitride 38 gate insulating regions, gate electrode 41, and ohmic contact 42a to source 31, contact 11 42b to drain 32, and contact 42c to electrode 41. Because 12 the structure shown in Fig. 6e may be fabricated utilizing 13 conventional semiconductor processing techniques, its manner 14 of fabrication is only briefly discussed herein.
One method of fabricating the semiconductor structure 16 shown in Fig. 6e is shown in Figs. 6a through 6d. According 17 to this technique, an insulating region 46, for example, one 18 micron thick thermally-formed silicon dioxide, is formed on 19 the upper surface of a semiconductor substrate 30. In one embodiment substrate 30 is p conductivity type semiconductor 21 material of 5 ohms per centimeter resistivity. Utilizing 22 well-known photolithographic and etching techniques, the 23 thick insulating region is patterned. As shown in Fig. 6a, 24 a section of the insulating material 46 has been removed, leaving two smaller regions 46a and 46b of insulating material.
26 The region of substrate 30 between insulating regions 46a 27 and 46b is used to form one embodiment of the memoxy cell of _ 28 this invention. As shown in Fig. 6b, gate dielectric regions 29 37 and 38 are formed next. One technique for fabricating the gate dielectric is to form a layer of silicon dioxide 1 ¦ 37, on the upper surface of which is formed a layer of 2 ¦ silicon nitride 38, also typically about 350 angstroms 3 ¦ thick, which may be heat-treated for stabilization. Silicon 4 ¦ nitride layer 38 will retard or prevent the formation of further silicon dioxide 37 beneath it during subsequent 6 fabrication steps. A polycrystalline silicon layer 41, 7 typically about 5000 angstroms thick, is then deposited on 8 the upper surface of silicon nitride layer 38. Then by 9 forming a further layer of oxide (not shown) on the surface of the polycrystalline silicon and patterning the oxide 11 layer, a mask may be formed. Selected chemical etching 12 solutions may then be applied to remove undesired portions 13 of the polycrystalline silicon 41, silicon nitride 38, and 14 silicon dioxide 37. The resulting structure is shown in Fig. 6b, in which the gate insulating regions 37 and 38 and 16 the electrode 41 have been patterned to allow formation of 17 source 31 and drain 32 regions in two noncontiguous regions 18 of substrate 30.
19 As shown in Fig. 6c, n conductivity type impurities are then diffused, implanted or otherwise introduced into the 21 exposed portions of substrate 30 and polycrystalline silicon 22 layer 41. These n-type regions form source region 31 and 23 drain region 32. The impurities also cause polycrystalline 24 silicon 41 to become electrically conductive.
Next, as shown in Fig. 6d, a thick insulating layer 48, 26 typically silicon dioxide, which is generally phosphorus 27 doped and about one micron thick, is formed across the _ 28 surface of the semiconductor structure, and openings are 29 made by well-known semiconductor processing techniques to 30 allow ohmic connections to source 31, drain 32, and polycrystalline silicon electrode 41. Regions 48a, 48b, 48c and 48d of layer 48 are shown. Finally, a conductive film ~2, typically metal, is deposited to a typical thickness of one micron and defined on the surface of the structure to form regions 42a, 42b~ and 42c, to provide ohmic contact with source 31~ drain
32 and gate electrode 41~ respectively.
In another embodiment of this invention, a depletion-mode IGFET is formed by introducing an impurity of the same conductiYity as the source and the drain into the channel.
Depletion-mode IGFET~s may be programmed and sensed in the same manner as the enhancement-mode IGFET's already discussed;
however, the necessary voltages will differ.
In some embodiments the information stored in the memory cell of this invention may be removed or erased, thereby allowing the fabrication of EPROMIs. The information (presence or absence of trapped electrons) stored in the structure may be removed by removing the trapped electrons from the silicon nitride layer 20. The trapped electrons may be removed using any suitable technique, and one technique is to ground the gate electrode and apply a sufficient potential to the drain to cause avalanche breakdown. The ease with which the avalanche breakdown may be induced in the device may be increased by implanting, diffusing, or otherwise introducing a heavily-doped impurity of the same conductivity type as the substrate into the channel 33 between the source region 31 and the drain region 32, to create a selectively lower breakdown. The presence of this impurity also increases the electron injection efficiency - ¦ F-1347 1~67Z08 1 into the gate insulation, for example, silicon dioxide layer 2 37 and silicon nitride layer 38.
3 In another embodiment of this inventlon a selected 4 impurity is embedded in the gate insulating region to enhance the trapping capability of the gate insulating 6 region. Trapping sites may be added by increasing the 7 trapping density and/or capture cross-section of the gate 8 insulating region. This may be accomplished by adding an 9 impurity to the gate insulator such as polycrystalline silicon, molybdenum or some other material which is compatible 11 with subsequent process operations. The amount of impurity 12 added will not be sufficient to form a conductive film, for 13 example, as in a FAMOS type structure, but merely enough to 14 increase the density of traps in the insulating material to therefore enhance its trapping capability.
16 A schematic diagram of an array 70 of IGFET memory 17 cells of the type depicted in Figs. 5 and 6e is shown in 18 Fig. 7. Although Fig. 7 depicts an array 70 of four IGFET's, 19 the array can be expanded to any desired size of m rows and n columns, where m and n are positive integers.
21 In general, an array of arbitrary size arranged like 22 array 70 is programmed by applying electrical signals to (l) 23 a common line (not shown but-which connects the grounded 24 terminals of cells Tll, Tl2, Tln T2l' T22 -- T2n' 25 Tml, Tm2, ... Tmn, (2) the x lines, and (3) the y lines.
26 The electrical signals are usually applied in an order which _ 27 first prevents the inadvertent programming of the desired 28 cell and then programs the desired cell. The step which 29 prevents inadvertently programming undesired cells is referred 30 to herein as establishing a "safe" condition.

¦ F-1347 ., _ I . . ~0672108 , 1 ¦ Those skilled in the semiconductor arts will realize 2 ¦ that for any given memory array a plurality of methods of 3 ¦ establishing a "safe" condit~on may exist. For example, _ 4 array 70 is in a safe condition when both of the following 5 ¦ conditions do not exist simultaneously:
6 ¦ 1. The source and drain are at different potentials.
7 ¦ 2. The gate potential is equal to or higher than the 8 ¦ greater of the source of the drain potent'ial.
9 ¦ In some embodiments of the invention, however, brief 10 ¦periods of an unsafe condition may be permitted. For example, 11 ¦in certain embodiments of the memory cell shown in Fig. 6e 12 in which prolonged high voltages or numerous repeated pulses 13 must be applied to the gate electrode to program the cell, 14 an unsafe condition may exist for a suitably brief period lS without programming the cell.
16 One embodiment of the method of programming a cell in 17 an array arranged like array 70 comprises the following 18 steps:
19 1. Initialize all lines to a low or ground potential, thereby placing all cells in a safe condition.
21 2. Apply a high potential, for example, Ve, to the 22 common line connecting all the sources.
23 - 3. Apply a high potential, e.g., Ve, or let float all 24 nonselected y lines.
4. Apply a high potential, which may be a pulsed 26 signal, greater than or equal to that applied in step 2 to _ 27 the selected x lines.
28 The foregoing steps cause only the one cell connected 29 to the selected x and y lines within array 70 to be programmed.
30 The first step places all cells within the array 70 in a 1 ¦ safe condition, thereby preventing inadvertently programming 2 ¦ nonselected cells. The second step allows any cell within 3 ¦ the array to be programmed. The third step prevents programming 4 ¦ all of the transistors in the array except those connected 5 ¦ to the desired y line. (This step also permits the transistors 6 ¦ connected to the desired y line to be programmed depending 7 ¦ upon the potential applied to their respective gate electrodes.) 8 ¦ Finally, the application of the high potential to the selected 9 ¦ x line results in the programming of a single desired transistor, Txy, within the array 70. The foregoing procedure may be 11 utilized repeatedly to program any number of transistors in 12 an array 70 of arbitrary size.
13 To read information from a selected cell or transistor 14 within the array:
1. Apply a low ox ground potential to the sources of 16 all the transistors, and 17 2. Raise a single x line and a single y line to the 18 desired high potential.
19 These conditions cause a current to appear on the y line dependent upon the previous programming, which current may 21 be detected and interpreted as a logical zero or a logical 22 one.
23 Another embodiment of an array of IGFET's which may be 24 programmed and operated according to this invention is depicted in Figure 8. Figure 8 shows an array 80 of eight 26 IGFET's in what is sometimes referred to as a virtual ground _ 27 read-only memory arrangement.
28 The j lines shown in Figure 8 will be referred to as 29 the virtual ground lines because they are selectively grounded 30 or held at low potential when the memory array 80 is being ~ ~-1347 10672(~8 I . .

1 ¦ read. The k lines of array 80 are referred to as the sense 2 ¦ lines and, in the embodiment shown in Figure 8, alternate 3 ¦ with the j lines. The gates of the cells of array 80 are 4 ¦ connected to the i lines, while the sources and drains are 5 ¦ connected to the j and k lines, respectively.
6 ¦ In one embodiment of the method hereof, information may 7 ¦ be programmed into a transistor, for e~ample, C23, within an 8 ¦ array arranged like array 80 by the following steps:
9 ¦ l. Initialize all i, j and k lines to a low or ground 10 ¦ potential, thereby placing all cells in a safe condition.
11 ¦ 2. Apply a high potential, e.g., Ve, to the virtual 12 ¦ground line j connected to the desired cell, e.g., j2.
13 3. Let float, or apply a high potential, e.g., Ve, to 14 all j and k lines which are on the same side of the k line connected to the desired cell as is the j line selected in 16 ¦step 2, e.g., il and kl.
17 ¦ 4. Let float, or apply a low or ground potential, to 18 ¦all j and k lines which are on the same side of the j cone 19 connected to the desired cell as the k line connected to the 20 desired cell, e.g., j3.
21 -- 5. -Apply--a- high potential, which may be pulsed, at 22 least equal to that applied in step 2, e.g., Ve, to the i 23 line connected to the desired celll e.g., i2.
24 The high potential on i2 and j2 together with the 25 ground or low potential of line k2 causes electrons to be 26 ¦injected into the gate insulating region of cell C23, _ 27 thereby programming it in the manner already described 28 ¦herein.
291 The information stored within a single cell of array 80 301 may be retrieved or read in a similar fashion. One such ¦ F - 1 3 4 7 1 method comprises the following steps:
2 l. Initialize all i, j and k lines to a low or ground 3 potential.
4 2. Raise the i line connected to the desired cell to _ S a chosen high potential.
6 3. Allow all j and k lines on the side of the cell 71 opposite the j line connected to the cell to float.
81 4. Raise the selected sense line k to a chosen high 9 potential, e.g., Ve.
10¦ The information stored within the selected cell may be 11 ¦ sensed by detecting and interpreting the current on the 12 ¦selected sense line j as a logical one or zero.
13 Although the foregoing invention has been described in 14 ¦part in terms of particular conductivity types, embodiments 15 1or methods, it will be appreciated by those skilled in the 16 ¦semiconductor and circuit-design arts that different materials 17 ¦or methods of equivalent function, including opposite conductivity 2l¦t~ es, may be aubstituted for tho~e referred to hereir.

2276 ~ . ' _

Claims (18)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A random-access semiconductor memory array comprising:
a common line;
a plurality of x lines;
a plurality of y lines;
a plurality of semiconductor memory cells, each being coupled to at least one of the x lines and one of the y lines and the common line, wherein each semiconductor memory cell comprises an insulated gate field-effect transistor (IGFET) which includes:
a substrate of P conductivity type;
spaced apart source and drain regions formed in the substrate, each of opposite conductivity to the substrate;
a gate insulating region formed on the substrate between the source and the drain, the gate insulating region including means for trapping charge;
an electrically conductive gate electrode formed on the gate insulating region between the source and the drain;
means for defining a state in the IGFET by applying a first signal to the gate electrode, a second signal to the source, and a third signal to the drain, wherein the potential of each of the first and second signals is greater than the potential of the third signal, to introduce charge nonuniformly into the gate insulating region predominantly toward the source region, and store charge nonuniformly in the gate insulating region in the means for trapping charge predominantly toward the source region;
means for detecting the state defined in the IGFET by applying a fourth signal to the gate electrode, a fifth signal to the source, and a sixth signal to the drain, wherein the potential of each of the fourth and sixth signals is greater than the potential of the fifth signal; and the application of electrical signals to the common, the x and y lines, controls the means for defining a state in the IGFET.
2. Structure as in claim 1 wherein:
each IGFET includes a source, a drain and a gate;
one of the source and the drain of each IGFET is connected to one of the y lines;
the other of the source and the drain of each IGFET is connected to the common line; and the gate of each IGFET is connected to one of the x lines.
3. Structure as in claim 2 wherein:
the gate is polycrystalline silicon.
4. Structure as in claim 3 wherein a gate insulating region separates the gate from a substrate, and the gate insulating region is formed from a layer of silicon dioxide and a layer of silicon nitride disposed on the layer of silicon dioxide.
5. Structure as in claim 4 wherein the common line may be selectably coupled to a selected low potential.
6. A method of programming a random-access semiconductor memory array having a common line, a plurality m of x lines, a plurality n of y lines and a plurality of IGFET's wherein each IGFET is connected to one x line and one y line, transistor Tab being connected to line a and line b, where 0 < a ?m and 0<b?n, wherein each IGFET includes;
a substrate of p conductivity type;
spaced-apart source and drain regions formed in the substrate, each of opposite conductivity to the substrate;
a gate insulating region formed on the substrate between the source and the drain;
an electrically conductive gate electrode formed on the gate insulating region between the source and the drain; and means for defining a state in the IGFET by applying a first signal to the gate electrode, a second signal to the source, and a third signal to the drain, wherein the potential of each of the first and second signals is greater than the potential of the third signal, to introduce charge nonuniformly into the gate insulating region predominantly toward the source region, and store charge nonuniformly in the gate insulating region in the means for trapping charge predominantly toward the source region;
means for detecting the state defined in the IGFET by applying a fourth signal to the gate electrode, a fifth signal to the source, and a sixth signal to the drain, wherein the potential of each of the fourth and sixth signals is greater than the potential of the fifth signal; and transistor Tab is programmed by the following steps:
applying a first potential to the common line, the x lines and the y lines, applying a second potential to the common line, applying a third potential to all y lines except line b, applying a fourth potential to line a to activate the means for defining a state in the IGFET.
7. The method of claim 6 wherein the source of each IGFET is connected to the common line, the drain of each IGFET
is connected to one y line, and the gate of each IGFET is connected to one x line.
8. A method as in claim 7 wherein each of the second, third and fourth potentials is higher than the first potential.
9. A method as in claim 8 wherein the fourth potential is at least as high as each of the second and third potentials.
10. A method as in claim 9 wherein the fourth potential is a pulsed signal having a maximum potential greater than each of the second and third potentials.
11. A method as in claim 10 wherein the first potential is ground potential and the second and third potentials are equal.
12. A method as in claim 6 wherein information stored in transistor Tab is sensed by applying a low potential to the common line and all x and y lines and a high potential to the a and b lines.
13. A method of programming a random-access semiconductor memory array having a plurality r of i lines, a plurality s of j lines, a plurality t of k lines and a plurality of IGFET's wherein the gate of each IGFET is connected to one i line, the source of each IGFET is connected to one j line and the drain of each IGFET is connected to one k line, whereby transistor Tcde, connected to line c, line d and line e where 0<c?r, 0<d?s and 0<e?t, and each IGFET includes:
a substrate of p conductivity type;

spaced-apart source and drain regions formed in the substrate, each of opposite conductivity to the substrate;
a gate insulating region formed on the substrate between the source and the drain;
an electrically conductive gate electrode formed on the gate insulating region between the source and the drain;
means for defining a state in the IGFET by applying a first signal to the gate electrode, a second signal to the source, and a third signal to the drain, wherein the potential of each of the first and second signals is greater than the potential of the third signal, to introduce charge nonuniformly into the gate insulating region predominantly toward the source region, and store charge nonuniformly in the gate insulating region in the means for trapping charge predominantly toward the source region;
means for detecting the state defined in the IGFET by applying a fourth signal to the gate electrode, a fifth signal to the source, and a sixth signal to the drain, wherein the potential of each of the fourth and sixth signals is greater than the potential of the fifth signal; and transistor Tcde is programmed by the following steps:
applying a first potential to all i, j and k lines;
applying a second potential to line d;
applying a third potential to all j and k lines which are on the same side of line d as is line e;
applying a fourth potential to all j and k lines which are on the same side of line e as is line d; and applying a fifth potential to line c to thereby activate a means for defining a state in the IGFET.
14. A method as in claim 13 wherein each of the second, fourth and fifth potentials is greater than either of the first and third potentials.
15. A method as in claim 14 wherein the first and the third potentials are ground potential.
16. A method as in claim 13 wherein at least one of the third and the fourth potentials is achieved by allowing the lines to which they are applied to float.
17. A method as in claim 16 wherein the fifth potential is at least as high as each of the second and fourth potentials.
18. A method as in claim 17 wherein the fifth potential is a pulsed signal having a maximum potential greater than each of the second and the fourth potential.
CA307,472A 1977-09-16 1978-07-14 Insulated gate field-effect transistor read-only memory array Expired CA1067208A (en)

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GB2004414A (en) 1979-03-28
JPS5453929A (en) 1979-04-27
FR2403623B3 (en) 1980-12-26
DE2838937A1 (en) 1979-03-29
US4173791A (en) 1979-11-06
FR2403623A1 (en) 1979-04-13
GB2004414B (en) 1982-10-20

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