CA1069220A - Integrated circuit package - Google Patents

Integrated circuit package

Info

Publication number
CA1069220A
CA1069220A CA281,572A CA281572A CA1069220A CA 1069220 A CA1069220 A CA 1069220A CA 281572 A CA281572 A CA 281572A CA 1069220 A CA1069220 A CA 1069220A
Authority
CA
Canada
Prior art keywords
cavity
chip
frame
leads
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA281,572A
Other languages
French (fr)
Inventor
Dimitry G. Grabbe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TE Connectivity Corp
Original Assignee
Dimitry G. Grabbe
Amp Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dimitry G. Grabbe, Amp Incorporated filed Critical Dimitry G. Grabbe
Application granted granted Critical
Publication of CA1069220A publication Critical patent/CA1069220A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Abstract

ABSTRACT

An integrated circuit package comprises an electrically insulating material frame defining a cavity; an integrated circuit chip received in the cavity; conductive leads extend-ing from the chip through the frame for connection to external circuitry; a sealing material gel surrounding the chip in the cavity; and a closure member sealing the cavity, the closure member being fractionally engaged with the frame.

Description

:~)69Z~
This invention relates to an integrated circuit package, and to a method of manufacturing such a packaye.
Integrated circults are widely used these days in, for example, watches, calculators etc, and there is a need for a method by which such circuits in the form of so called chips can be packaged easily and in a fully automated manner. The packages produced should be hermetically sealed against the ingress of gases or moisture in order to prolong the life of - the circuit.
According to this invention there is provided a method ~- - of manufacturing an integrated circuit package, including the steps of mounting an integrated circuit chip in a cavity in a -frame of electrically insulating material, the chip being ele-ctrically connected to conductive leads extending from the cavity through the frame for connection to external circuitry;
filling the cavity around the chip with a sealing material gel; and press fitting a closure member into frictional engage-ment with the frame thereby to compress the sealing material ~ -and hermetically seal the cavity.
Also according to this invention there is provided an integrated circuit package comprising an electrically in~
sulating material frame defining a cavity; an integrated circuit chip received in the cavity; conductive leads extend~
.:.
ing from the chip through the frame for connection to external circuitry; a sealing material gel surrounding the chip in the~
~ cavity; and a closure~member sealing the cavity, the closure ¦~ member being frictionally engaged with the frame. ;~
I ~ This invention will-now be described by way of example~
with reference to the drawings, in which:-~igure 1 is a bloc~ diagram illustrating the method of :
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the invention;
Figure 2 is a plan view of a sheet of integrated circuit chips;
Figure 3 is a plan view of a lead spider assembly for use in mounting a chip;.
Figure 4 shows the spider assembly of Figure 3 with a chip mounted thereon:
Figure 5 is a plan vlew of a plurality of conductive leads having an insulating material frame moulded thereon;
.` 10 Figure 6 shows the frame of Figure 5 with the spider/ .
. . chip assembly of Figure 4 mounted thereon;
- Figure 7 is a view of the other side of the assembly of :
Figure 6;
Figures 8, 9 and 10 illustrate steps in the method of .
the invention by views on the line VIII - VIII in Figure i; :
.
Figure 11 is a perspective view of the conductive lead/
frame assembly of Figure 5 with a spider/chip assembly to be mounted thereon;
Figure 12 is a perspective view with part broken away, .:.
of the assembIed structure of Figure 11; :
Figure 13 is a sectional view of a first package , ~: .
.. according to the invention; and . Figure 14 i~s a sectional view of a second package according to the invention.
~, . .
~ 25 Referring to:Figure l,.conductive lead frames (~or :~'1 . .
;`~` example as shown in Figures 11 and 12) are taken fr~m a souxce ~ 1 thereof, and are supplied to a moulding station 2 at which ~ .
:.
, an electrically lnsulating material frame (for example as shown :, in Figures 11 and 12) is moulded on each thereof. 5pider~
. ~ :
;: 30 assemblies (for example as shown in Figure 3) are taken from a : .

:
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. ~ . :

~069ZZ0 source 3 thereof and supplied together with integrated circuit chips from a source 4 thereof, to a mounting station 5 at which a chip is mounted on each spider to form an arrangement as shown in Figure 4. The spider/chip assemblies are then supplied to a mounting station 6 at which one such assembly is mounted in the frame of each lead/frame assembly supplied from the moulding station 2, to provide an assembly as shown in Fi~ures 6 and 7. The lead/frame/spider/chip assembly is then passed to a first sealing station 7 at which a closure member is press fitted into the frame to close one side thereo~ (as shown in .:
Flgure 8), then on to a second sealing station 8 at which the cavity within the frame is filled with a gel type sealing mat~
erial such as a silicone gel (as shown in Figure 9), and finally on to a third sealing station 9 at which a second closure member is press fitted into the frame to close the open side thereof and at the same time to compress the sealing material gel there-by to ensure that the package thus produced is reliable her- -metically sealed (as shown in Figure 9). :.
The above described method according to the invention has the advantage that it can readily be carried out in fully automated manner, the press fitting of the closure members in-to the frame to be retained therein solely by frictional ~ .
engagement giving the added advantage that the closure members : can be made and fitted at the stations 7 and 9 each by one 1 25stroke of suitable automatic equipment. : :
- Refer.ring now to Figure 2, this shows a plurality of J~ ` integrated c.ircuit chips 10 each having a plurality of contact : : , pads 11 arou:nd its.periphery. Many methods of manufacturing such chips a.re well known, and therefore none will be described ::: :

in detail he.rein. ~ .. : ..
- :
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Figure 3 shows a spider assembly comprising a plurality of converging leads 12 carried by a sheet 13 of insulating material. The sheet 13 has a window 14 therein, and the leads 12 extend both over the window 14 and beyond the periphery of the sheet 13.
Fi.gure ~ shows the spider assembly of Figure 3 with a chip 10 as shown in Figure 2 mounted over the window 14 thereof;
with the pads 11 of the chip 10 connected as by heat or ultra-sonic energy to the inner ends of the leads 12. Such assemblies are produced at the mounting station 5 of Figure 1.
Figure 5 shows part of a lead frame assembly comprising a plurality of conductive leads 15 forming part of a complete lead frame as shown in Figure 11. A frame 16 o~ electrically insulating material is moulded in known manner on the lead frame with the leads 15 extending from within the frame 16 out through the frame 15. Superfluous parts of the lead frame are subsequently removed in known manner to electrically isolate the leads 15 from each other, the leads 15 then being retalned in position by the ~rame 16. The lead/frame assembly shown in ; 20 Figure 5 is produced at the mouldlng station 2 of Figure 1.
Figure 6 shows the assembly of Figure 5 with a spider/
chip assembly as sho~wn in Figure 4 mounted thereon, with the outer ends of the leads 12 of the spider connected to the lnner ends o~ the conductive leads 15, the chip 10 thus being received in the cavity 17 defined by the frame 16. The connections between the leads 12 and 15 can be made by known methods such as thermal compression bonding, the leads preferably being coated with a noble metal such as gold or silver.
, ~ Figure 7 shows~the reverse s.ide of the assambly shown in Figure 6, which ls produced at the mountlng statlon 6 of :- ,:
; ~ .,:
- .
~ 5 ~

~836 ~C~692ZO
Flgure 1.
Figure 8 in a section on the line VIII - VIII in Figure 7, and illustrates the step carried out at station 7 o~ Figure 1. An insulating material closure member 18 is press fitted into the cavity 17 in the frame 16 to be retained there-in by frictional engagement only closing one side of the cavity 17.
Figure 9 shows the assembly with the closure member 18 in place. At station 8 in Figure 1 the cavity 17 is substan-tially filled with a gel type sealing material 19 such as a - silicone gel with a low level of molecular cross-linking, whereafter a second closure member 18 is press fitted to close the open side of the cavity 17, this step being carried out at station 9 in Figure 1. During press ~itting of the second closure member 1~ the sealing material 19 is compressed and ~lows to ~ill all available spaces within the cavity 17 and between the edges of the closure members 1~ and the ~rame 16, thereby effectively hermetically sealing the package thus produced.
.
Figure 10 shows the thus produced completed pac~age in accordance with the invention.
Figure 11 illustrates the step càrried out at station 6 of~Figure 1. A spider carrying a chip 10 is shown, which has been stamped from a strip 20 prior to insertion into the cavity 17 o~ the lead/frame assembly.
Referring to Fi~uxes 12 and 13 also, the cavity 17 also contains a conductive ground plate 21 on which the chip ]0 is seated and which is connected by way of one of the leads 15 to the outside of the frame 16.
` 30 Figure 13 also shows the leads 15 bant around the frame ., ., .~ .;: ~ ,.

~ ~ 6 -~C~69;~;20 16 to provide contacts suitable for establishing connections to the completed sealed package.
Although in the above described method only one chip 10 is mounted in the cavity 17, it will be appreciated that if required two spider/chip assemblies can be mounted at station 6 of Figure 1 with the leads 12 of the two assemblies being connected to opposite sides of the leads 15 of the lead/
frame assembly. Closure and sealing of the cavity 17 is then effected as described above.
10 - Such a package is shown in Figure 14, which also shows -a ground plate between the two chips.
Although described as being of insulating material, the closure members 18 can otherwise be of conductive material, this being particularly advantageous for the lower closure member of the assembly shown in Figure 13.

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Claims (9)

THE EMBODIMENTS OF THE INVENTION FOR WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE AS FOLLOWS:
1. A method of manufacturing an integrated circuit package, including the steps of mounting an integrated circuit chip in a cavity in a frame of electrically insulating material, the chip being electrically connected to conductive leads extending from the cavity through the frame for connection to external circuitry; filling the cavity around the chip with a sealing material gel, and press fitting a closure member into frictional engagement with the frame thereby to compress the sealing material and hermetically seal the cavity.
2. A method as claimed in Claim 1, in which the cavity is initially open at each of two opposed faces, and including the step of press fitting a closure member into frictional engagement with the frame to close each of the two opposed faces of the cavity to compress the sealing material and hermeti-cally seal the cavity.
3. A method as claimed in Claim 1 or Claim 2, including the step of mounting the chip on a sider assembly comprising a plurality of converging leads carried by a sheet of insulating material prior to mounting the chip in the cavity, the chip being electrically connected to the leads of the spider assembly, and the leads of the spider assembly being electrically connected to the conductive leads extending into the cavity.
4. An integrated circuit package comprising an electrically insulating material frame defining a cavity; an integrated circuit chip received in the cavity; conductive leads extending from the chip through the frame for connec-tion to external circuitry; a sealing material gel surrounding the chip in the cavity; and a closure member sealing the cavity; the closure member being frictionally engaged with the frame.
5. A package as claimed in Claim 4, in which the cavity is closed as two opposed faces by frictionally engaged closure members.
6. A package as claimed in Claim 4, in which the chip is carried by a spider assembly comprising a plurality of converging leads carried by a sheet of insulating material, the chip being electrically connected to the leads of the spider assembly, and the leads of the spider assembly being elec-trically connected to the conductive leads extending through the frame.
7. A package as claimed in Claim 4, Claim 5, or Claim 6, including a conductive ground plate located in the cavity, on which ground plate the chip is seated, the ground plate being connected to a conductive lead extend-ing through the frame.
8. A package as claimed in Claim 4 including two chips mounted in the cavity.
9. A package as claimed in Claim 4 in which the sealing material is a silicone gel.
CA281,572A 1976-07-30 1977-06-28 Integrated circuit package Expired CA1069220A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/710,043 US4079511A (en) 1976-07-30 1976-07-30 Method for packaging hermetically sealed integrated circuit chips on lead frames

Publications (1)

Publication Number Publication Date
CA1069220A true CA1069220A (en) 1980-01-01

Family

ID=24852388

Family Applications (1)

Application Number Title Priority Date Filing Date
CA281,572A Expired CA1069220A (en) 1976-07-30 1977-06-28 Integrated circuit package

Country Status (12)

Country Link
US (1) US4079511A (en)
JP (2) JPS5317276A (en)
BE (1) BE857125A (en)
BR (1) BR7704965A (en)
CA (1) CA1069220A (en)
DE (1) DE2734439A1 (en)
ES (2) ES461133A1 (en)
FR (1) FR2360174A1 (en)
GB (1) GB1524776A (en)
IT (1) IT1080619B (en)
NL (1) NL7707424A (en)
SE (1) SE423846B (en)

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JPS5317276A (en) 1978-02-17
US4079511A (en) 1978-03-21
NL7707424A (en) 1978-02-01
SE423846B (en) 1982-06-07
GB1524776A (en) 1978-09-13
IT1080619B (en) 1985-05-16
DE2734439A1 (en) 1978-02-02
FR2360174B1 (en) 1983-01-21
DE2734439C2 (en) 1988-08-25
JPS6143851B2 (en) 1986-09-30
JPS6229908B2 (en) 1987-06-29
FR2360174A1 (en) 1978-02-24
ES461133A1 (en) 1978-06-01
BR7704965A (en) 1978-04-25
ES462978A1 (en) 1978-06-01
BE857125A (en) 1978-01-25
JPS60126850A (en) 1985-07-06
SE7708156L (en) 1978-01-31

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