CA1076230A - Associative electronic multiprocessor for real time multiple data processings - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A plurality of processor units are combined to provide an associative electronic real time multiprocessor, which can be constructed form relatively simple modules without the necessity for complex control systems. In the multiprocessor, the individual processor units operate in parallel, and data exchanges between the units are carried out in real time by units which control the exchanges by means of exchange parameters characterizing inter alia the processor units involved in an exchange and the memory locations involved in said units, the control units operating in time division according to priorities established by decision elements operating according to logical criteria which are functions of the exchange parameters. The processor units are divided into subsystems interlinked by transmitting and receiving interface circuits associated with each subsystem.

Description

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The present invention relates ~o a programmable~

modular, associative electronic system con~isting of ai gital microprocessors, and more paxticularly~ it refers to s~ructures and functional procedures abl~ to carry out sel~-~overning ~ata .
processing operations as well as intercommunication and associative data exchanye operations among the modular microprocessor~
constituting the system, in consequence, the system carries out a wide ranging searoh for the recognition of data and data groups of similar properties~
Processing systems of ~his kind are par~ioularly use~ul when complex processing operatio~s hav,e to be carried out in real time, ~uch complex operations being possibly split into parallel elementary operations organized in variable hierarchies of any desired structure, al~o when khe resul~s of such elementary operations require to be mutually correlated and as~ociated for subsequen~ proce~sing develop~en~s~
Processing opexations of this kind can be found, for instance, in controlling progresqive, fast and complex operation~, in traffic controlO and in data and pattern recognition, even o~ an approxima~e natureO
Various kinds o digital proces~oxs able to carry out ~hese operations are ~nown in ~he art, but ~hey are serially operating, ~o that processing times, even if reduced to the minimum, are ~till ~ong, thus giving rise to easibility and cost problem~
Recently parallel processing systems have been designed, makins use o~ a plurality of conventio~al pro~essor~. ~owever they need interconnections general1y involving comp~ex switohing d~vice~, ana in any event very complex and insufficiently modular ~ .

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systems, thus giving rise to considerable cost, maintenance and programming problems.
These and other disadvantages are overcome by the present invention, whicb allows an unlimite~ number of operation~
to be carried out at a rate higher than that of a conventional pr4ce~sor, and has a ~airly simpleD cheap, highly reliable and entirely modular struct~re~
It is a characteristic o the present invention khat it provides the possibility of recognizing a pluxality of aata in real time, regardless of their number ana structural complexity.
It is a further characteristic of the system of the present invention that it has great flexibility, because, whilst keeping its struc~ure unvaried, it allows any of a range of operation~, by adapting itself from an informakio~al, logistic, and temporal point of view.
Accordingly the invention provideæ a modular programmable associative ele~tronic system formed by digital proces~or units (microprocessors) comprising means able ~o car~y ou~ in real time dat~ exchanges between processor uniks ~orming the system, said means consisting primarily of units con~rolling said exchanges by ut~lizing ~uitable exchange parameters, which characterize the ex~hange modalities, the operating conditions of any processor unit requiring a data exchange, of a proce9sor unit transmitting the data, of a proce~sor unit r~ceiving the datar and the characteris~ic~ of the relative memory locations of ~hese parameters and of the data to be exchanged: ~aid control unit~ operati~g in time division, accoxding to an operative sequence established in r~al time on the basi~ o logic~l cri~eria whic~ are fun~tio~s 1~7~ 3~

of said exchange parameters; all said processor units forming ~he system operating in parallel for simultaneous data proc~ssing.
These ana other character~stics of the pre~ent invention will become ~learer ~rom the following de~cription of an exemplary preferred embodiment thereof, i~ conjunction with the annexed drawings, in which:
- Fig. 1 is a block diagram showing, in simplified form, the general structure of a system in accordance with the invention:
- Fig. 2 is a func~ional block diagram of ~he proc~ssor units denoted by the refere~ce U~ in ~ig. l;
- Fig. 3 is a functional block diagram of one of the data exchange control units denoted by refere~ce DEC in Fig. l;
- Fig. 4 is a flow chart showing the sequence of operations of t~e data exchange between the operative unit~ of the system.
Fig~ 1 shows the general structure of the processing sys~em, ~ormed by a pl~rality of micropro~e~sors grouped in~o sub-systems and ~y units controlling data exchange among the micro-proce~sors.
In the drawing three subsystem~ of miaropro~e~sors SSl, SS2, SS3 are ~hown by way O~ example, although ~he number o ~ubsy~kem8 can be as man~ as required by the par~icular type of pro~essing oparation to be caxrled out~ Every subsystem consists O~ a plurality O~ mi~roprocessors UA, that is UAll, UA12~ o~
UAln or subsystem SSl UA21, UA22,....~, UA2n for su~sys~em SS2;
UA31, UA32~.UA3n ~Dr subsystem SS3.
Units UA are self-governing and progxammable digital microprocessor~, éach~paving i~S own memoryO whose capacity can be expanded at will they are i~plemented using conventional ~ 2 30 structures and tec~niques with the exce~tio~ of some ~eatUres regarding the location and structure of certain ~ircuîts, re~erred to hereinaft~r as the "characterizin~ part" of the microproc~sor.
Said microprocessors are able to carry out, besides the usual conventional processing operations, ~n asso~iative search in the memory as will be explained in more detail with refer~nce to Fig. 2, References DECl, DEC2, DEC3 denote data exchange control units, able to coordinate the operations relative to the exchange of data among microprocessors ~A belonging either to the same sub~ystem, or to different subsy~tems. The structure of these particular units will be described in detail hereinafter with re~erence to Fi~ure 3.
Reference~ TRA1, TRA2, TRA3 denote interfa~e circuits for data transmission from one subsystem to another. References RECl, REC2, R~C3 denote corresponding receiving interface circuits.
The units shown in Figure 1 are mutually interconnected in the following wayO
Each uni~ U~ is able to communicate with any other unit of the same subsystem (UA, DEC, TR~, REC) through a gen~ral bidirectional co~lnec~io~ denoted by reference 1 in sub~ystem SSl, by ~ in subsystem SS2, by 3 in ~ubsystem SS3, Connections 1~ 2, 3 are the common buses ~or all the signals and data within ~he subsystems, The data to be exchanged, t~e timing and control signal~, as well as other signals having digital signi~icance~
w~ich hereinafter will be called "exchange parameters" and will have special tasks which ar~ further described hereinaf~er, are transmitted vn saîd buses~

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These signals are: the addrl3sses characterizirlg units UA directly conn~cted ~o the bus or indixectly connected through transmitting interface circuit T~A and receiving interface circuit ~EC, that at any particular time are controllad by unit DEC; memory addres~e for the memorie~ contained in these units ~;
in~ormation relative to the extent and rats of the exchange;
and f inally timing and control signals ,~ Every unit U~ can also communicate with other devices compxi~ed or not comprised in tha subsystem through suitable bidiri3ctional individual c:onnactions~, 10 In the drawing, refl3rencss 7, 8 deno . e these bidirectional connections to unit UAll.
Ints3rconnections among di~ferent subsystems are realized through the intarface circuits TR~ (transmitter~ and REC (receiver) which are, as already m~ntioned, interfac~ units betw~en two buse~ belonging to ~wo different sub~ystems, 9.9~ bu~es 1 and 2,

2 and 3. Each tran~mitting i~t~rface circuit T~ is connected with its as30ciated receiving interace circuit REC through a bidirectional conn~ction, in the drawing, reference 4 deno~es the connection TRAl - REC2, reference 5 denotes the colmaction 20 ~TR~2 - REC3, refererlce 6 denotes the connection betwaen TR~3 and a pos~ible furl:her circuit REC not shown in the drawing.
Tha names of thei two inter~ace circuits TRI~ and REC
~transmitter and receiver~ and the directiorl arrows on connections 4, 5, 6 xa}ate only to the exchange of significant data and do not relate to tho dixection of propagation of the control signals accompanying such a~ exchange 5 the cormsc1:ions are in e~fect bidirectional with respect to such signals .
InteFconn~ction operations ocrur as follows.

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At a certain time, one of the u~i~s UA, for instance UAll, on the basis of the information it pxocesse~ or any way contains, may request tha~ a second unit UA, ~or instance U~12, sends a certain 5~t of data to a third unit UA, for instance UA22.

Thus the following list of the units concerned i9 formed:

- a unlt UA requesting the exchange;
- a unit UA transmittlng the data to be exchanged7 - a uni~ U~ receiving the data to be exchanged~
The requesting unit may also be the transmitting unit or ~he re~eiving unit: in this ~ase the number of uni~s involved in the exchange will be two in~tead of three.
The requesting unit UAll sends all the in~truetions relative to the exchange to be carried out ~which will be described in detail hereinafter) to the associated unit DE~l through the bus l; unit DECl then assumes control of the transmitting circuit a~d of the receiving cîrcuit, obviously for the purpose of conducting the opera~ions involYed i~ the requested data exchange.
Once the exch~nge is over, the units UA which were involved hegin to operate again independently from one another, and unit DECl rev~rts to a quie~cent condition walting for further possibl~ re~ues~s ~or exchange.
Figure 2 schematically represents the unctional blocks o~ one o~ the digital proce~sors UA. Reference I~l deno~es a conventional line interface; reference CC ~enotes a circuit switching and controlling me~ory operations; reference ME denote~ ::
the memory; reference CGl denotes a general control and timing maans of the microproces~or, refexence ED denotes t~e data processing circuits.

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The memory control and switching circuit CC is controllea by the general control means CGl: it is designed for causing memory ME ~o be slaved to the data processing circuits ED when the mlcropro~essor has to carry out operations on the data stored in the memory; circuit CC may also cause memory ME to be slaved, through the line interface ILl and the bus 1, to control unit DEC (Fig. 13 when the microproeessor is concerned in data exchanges with other uni~s connected to bus 1.
Memory ME (Fig. 2) is able to receive from circuit CC:
~he write/read instruction, through connection 15; the read/write addresses through connection 16; and input data to be memorized, ~hrough co~nection 170 It supplies outgoing data to the circuit CC and to the data processing circuits ED, throug~ connection 14.
A connection 7 is provided ~or possible memory expansion.
General control mean5 CGl controls, ~hrough connection 31, the circuit CC controlling and addressing the memory, and places, through this circuit, line inter~ace ILl and ~us 1 in communication wi~h co~trol unit DEC (Fig. 1).
The set o data processing circuits E~ (Fig. 2) basically con~i3ts o~ computational circuits, registers and logic units, and i~ able to recei~e data coming ~rom memory ME through ~onnection 14; it is also able to supply circuit CC, ~hroush conne~tion 10, ~ith the data to ~e registered in memory ME, ana to supply circuit TCC, through a connection 11, with memo~y addresses rela~ive to said data. MoreoYer, ED is sla~ed to general control means CGl through ~onnection 32, and can exchange data with peripheral ex~ernal devices ~hrough the con~ction 8, co~eyi~g also the necessary ~ontrol signals.

;2303 From what has been said a~ove, the microprocessors will b~ seen to be, generally speaking, proce~sing devices of universal type. The characterization of these units for the particular processing operations necessary to the ~pecific task of the system is to be found in th~ da~a processing circuits ED, which will be described hereinafter in more detail.
The set of circuits BD comprises the circuits usually present in the proces~ing units of the ~onvent.ional micro-processors, including two multiplexers MXl and MX2, a logir a~d axithmetic unit U~, and an accumulating register R~. These parts of the clrcuits ED are conve~tional and can be designed according to criteria well known in the art. One such structure has been exemplified here; alternatives will be apparent to those skilled in the art.
The means charactexizing processor UA for the specific functions for whic~ it is designed inside the processing system - is the characterizing unit UC.
It may be formed by u~ilizing a number of logic gates .
occupying a well defined area of the integrated circuit in which uni~ UA is realized. q~he structure of UC is uncommitted inside a well defined zone of E~, to which another 20ne is correlated, also having uncommitted structure, usually the ~ :
control mean~ CGl~
A multipurpose structure consi~ting o~ a register RE, an arithmetical adder SA and a counting circuit C~ has been schematically represented in the drawing~
Di~fexent operations will b~ carried out by UC
a~cording to the type of microprogram it i~ programmed for ~.

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and according to the instructions received. ~he basic ~tructure can r~main unchanged, thus all~wing mass-production at cheaper C05~S.
Counting circuit CN counts instantaneously, that is within the propagation time of conv~n~ional semiconductor-logic-networks, the number of bits, present from time to time on an output 20 of the accumulating register RA, which present, as will become clearer from th~ following des~ription, the logic value "1".
The result o~ s~ch coun~ing is sent to the accumula~or regist~r con~isti~g of the arithmetical adder SA and of the register R~.
To check for parity among data sequence~ storea in memory ME, the arithmetic and logic unit UL per~orms "Bx~lusive-O~"
operation~; the bits having logic level "1" resulting from such operations are stored i~ register RA, are counted b~ c~unter C~, and axe accumulated in regi ter RF. The measurement stated above results from such operations.
The above m~ntioned operation~ are per~ormed by i~dividual microprocessor~ UA simultaneou~ly, ~n parallel and independen~ly owing to the presence, in each one of themJ of the timing mean~ contained in uni~ CGl; obv~ously, this independen~ operation takes place till one o~ said uni~s requires a data ex~hange operation in this event, limited. to such exchange operation~, timing of the operatio~ of the units UA
invoIved i~ the exchan~e is provid d by control unit D13C (~ig. 1), - which is int~ndledE ~or the purpose of data exchange c:ontrol .
Figure 3 sho~ws in schematic forra ~y fu~ctiorlal blocks ~ .

,. . . ,, : i. . . - .

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the control uni~ D~C ~igure 1)~ which i~ common, ~s already seen, ~o all microprocessors of the same subsystem, and has the task of coordinating intercommunication operation~ between microprocessors~
In Figure 3 9 the reference IL2 denotes a ~onventional line interfac0; refer~nce CG2 denotes a general control device of circuit DEC in which timlng means are included5 SD denotes an exc~ange register receiving, memorizing and transmitting data object of the exchange; GPS denote~ a circuit controlling exchange parameters, said circuit receiving, transmitting and processing parameters which make possible the passage of data either between two units U~ of the same subsystem SS, or be~ween ~wo unit~
belonging to ~wo different sub~ystems; in the latter ca~e, tbe passage of data take~ place t~roug~ tran~mi~ting interface circuit TRA (Figure 1) o~ subsystem SS to which the circuit DEC belongs, and the receiving inter~ace circuit REC belonging to the second subsystem~ ~ :
Circuit GPS (Figure 3) basically consists o three operating block~: a first accu~ulator ~B, which records certain exchange parameters, namely the addresse~ of the units UA concerned in the exchange and the number o~ data block~ to be exchanged;
; a second accumulator AM, recordlng certain other exchange ~;
parameters, namely memory addresses; a xegister RF processing - exchan~e parameter~ relating to the ~requency of the exchange and to end of-exchange code~. During the phase of request for an exchange from a unit UA, all the devices forming the exchange paramet~rs control circuit &PS receive from the reque~ting unit UA, through ~us lo line interface IL2 and line 65~ all - 10- , : , .

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the ins~ructions relating to the data exchange which is to be carried out; these devices memori~e the instruction~ under the control of circuit CG2. More paxticularly, accumulator AB, controlled and timed by circuit CG2 through line 51, receives from requesting unit UA the following exchange paramet~rs: the adaress of the requesting unit UA: the address of the transmitting unit UA; the address of the receiving unit UA and the num~er of data blocks to be exchanged. since a plurality of units Uh can simultaneously xequest the same unit DEC ~.o carry out a data exchange, priority criteria are e~tablished according to which the request originating first in time~ or originating in position nearer in space to unit DEC, is first to be satisfiea.
The accum~lator AB memorizes and groups the four received parameters (every priority ~evel generates a group);
each group will occupy a set of four locations of a memory contained in th~ accumulator itself. At the beginning o~ the data exchange sequence, following suitable instructions received from th~ control circuit CG2 through line 51, accumulator AB
gives at its output on line 61 three of the parametexs received, namely the addresses of the reque~ting unit U~, o~ the transmitting unit UA, of receiving unit UA; ~aid addres~es, ~hrough the l.ine interface lL2 and the bus 1, select the units UA involved in the exchange operation, and which uni~ DEC is expected to control.
During the data exchange se~uence, accumulator ~B decrease~ by 1 the contents of the ~emory location where it first memorized the nu~ber of data blocks to be exchangea. If a plurality of requests for an exchange have take~ place, and therefore more locations have been used, th~y will be subseguently decremente~

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as a result o~ the exchan~e sequence, a~ explained below. When the content of the memory loc~tion relating to the number of data blocks to be exchanged, has reached zero (i.e, the last block in program has been exchanged)~ the accumulator AB sends, throuyh the connec~ion 51, a monitoring signal ~o the control cireuit CG2, which conclude~ the data exchange operation~
The memory addresses accumulator AM~ controlled and timed by circuit CG2 through line 52, xeceives from the xequesting unit UA, as already mentioned, exchange parameters relating to it; the~e parameters are the address of the starting memory location of the transmitting unit UA and the address of the :
starting memory location of the receivin~ unit UA. A190 in this case, to be able to accept simultaneous re~uests for da~a exchange, priority criteria are established, as above mentioned, on the basis of which the various exchange operations are carried out acc~rding to a certain se~uence~
During the exc~ange parameters acq~isition se~uence, accumulator AM memori~es and groups the two received parameter3 ~every priority level gives rise to a group); each group will ~old a ~et of two locations of a m~mory contained in ~.he accumulator it5elf. ~:
At the beginning of the data axchanys sequence, accumulator AM, urther to sui~able instructions received from ~ontrol circuit CG2 on line 52, gives at the output on line 62 either the same addresse~ previou~ly received from the requestin~
unit UA, or ~he same duly incremented, or still others genera~ed ~y itself (as it will be explained hexeinaf~er).
~hrough interface IL2 and bus 1 said addresses sele~t, ;Z3~

in the units UA intexested in the exchange, memory positions from which the data which are the object of the exchan~e must be extracted or to which they must be transferred"
During data exchanye, accumulator ~M incremen~s also by 1 the conten~s of locations of its own memory carrying memory addresses of uni~s UA from whic~ data which are the object o~
the exchange are ex~racted or in which ~hey are recorded. This ; operation occurs automatically and in a similar way or each priority levelO
Acc~mulator AM is also expected to generate the address of the me~ory location of the requesting unit UA, which forms the starting location for obtaining the exchange parameters.
In correspondence with the acqui5ition of each one of the exchange parameters, AM generates an address incremented b~ 1 with respect to the ~tarting ad~ress.
Thi-~ address generation stops with the acquisition of exchange parameters occupying the final memory position~
The register RF for fre~uency an~ end of exchange parame~ers is ~o~trolled and timed by control cirauit C~2 ~0 through line 54, and receives from the requesting unit UA, as already mentioned, two exchange parame~ers, namely the exchange frequency and the end-of-exchange code. In this case, also t~ handle more simultaneous req~e~ts for data exchange, priority ~ criteria are establishea on the basi~ of which the various - exahange operation~ wilI be carried out according to a certain :: ~equence. In the e w hange parame~ers acquisition sequence~ the register RF memorizcs and groups the two received parameters (each priority level gives rise ~o a group); earh group will : -- 13 --~ ., . .. . : .

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occupy a set of two locations of a memory contained in the register itselfD During the da~a exchange sequence, on $he ba~is of the received "frequency of exchange" parameter register, RF
provides on line 54 to control circuit CG2 the i~struc~ions necessary for circuit CG2 to 3pace the various data ex~hange operations both with respect to one another ~on the basis of ~he various levels of priority)~ and wi~h respect ~o ~he autonomous processing cycles of units UA involved in the anti~ipate~ data exchanges. .. .
To poin~ out the meaning of "Bxchange frequency"
a certain data exchange wi~h priori~y Pi may be assumed as occurring every n autonomous processing cycles, for instance of a transmitting unit UA~ and another data exchange with priority ; Pj may be assumed as occurring every m autonomous processing cycle~ of ano~her transmitting unit. ~-Circuit C~2 controls the work of unit D~C ~y interspacing . ;
the operations relative to different exchanges o~ the variou~
proce~sing uni~s, so that none of them remains in a waiting position and therefore idle during some time intervals. Obviou~ly the unit DEC duly memorizes both data and status o~ the interrupted exchange; said memorization has therefore a temporary character, :
and lasts only the time during which DEC carries out another , exchange operation which has been interspersed, on the basis of a suitable reque~t, either according to it~ greater priority or to take into accou~t the different frequency of a~other data excha~ge.
The operation of the unit DEC can be considered as a time division operati~n, ~ontrolled by logical ~riteria, said , , . . .: . . ,. : .

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criteria being a func~ion of the exchange frequency and of the priorityO
It is therefore a type of time division operation different from those which are strictly and automatically sequential as commonly used in other te~hniques.
Finally, on the basis o~ con~rol signals sent by circuit CG2 through line 54, register RF gives at the output on line 64 the end-of~exchange code previously received, and sends it in ~he usual way to re~ue~ting, tran~mitting and receiving units U.A, so as to in~orm them ~ha~ a given data excha~ge sequence is completed~
Data ex~hange register SD is also contxolled and timed by general control circuit CG~ through line 46~ and having at a given time received from tran3mitting unit UA, through bus 1, line interface IL2 and conn~ction 65, a certain data block, :
it memorizes it in a suita~le memory which it contains th rein;
after a ~ime interval, de~ermined ~y con~rol signals sent to it ; by the control circuit CG2 again through line 46, it sendq the data bloc~ to receiving unit UA, through line 63, line interface IL2 and bu~ 1.
All the operating blocks of Figure~ 1, 2, 3 may be implemented in various ways~ but ~nce ~he ~unc~ions they must carry out are kn~wnO t~eir implementation is routine for the i cirauit de~igner skilled in the art.
The operation of the system of the invention will now be described with reference to the exchange of data, which is the main fu~ction distinguishing the system.
Unit~ UA (Figure 1) which need to exchange data, re~uest :: 15 -7&~230 access to a unit DEC by sending to it, directly if the exchange is to be carried out in the same subsystem, or through units TRA and REC if the exchange is to be carried out bekween different subsystems, particular signals on a common bus (1, 2 or 33.
The control circuit CG2 (Figure 3) of the unit DEC concerned chooses one of these units UA on the basis o~ ~he time and space priority criteria alxeady described ~time of r2~uest or position of the unit UA in a given subsyst~m); the chosen unit UA becomes the requesting unit. Unit DEC controls the sequence lo of exchange serving a certain number of groups of units UA
(as many as there are priority levels allowed for), and operates, :~
a~ already said, according to time division techniques controlled by logical cri~eria.
The circuit CG2 sends to the chosen requesting unit UA, a signal which is the request for an exchange, and starts an exchange parameters acquisition sequence. In reply, UA send~
to unit DEC, and therein to accumulator AB, its address, which .
AB memorize~ and senas back on the bus 1 towards UA, through line 61, interface IL2 and bus 1. Simultaneously AM, upon the instruction of CG2, send~ to the same unit UA through an analogous path, the address o~ the memory cell of ~ which contains the fir~ of ~he exchange para~eters UA must send to DEC to make the exchange po~sible. The re~uesting unit ~A then sends towards the same unit DEC the exchange parameters mentioned ~elow, which characterize a si~gle and well-defined exchange operation:
1) Its addres~ (re~uesting unit) sent at the co~mencemen~ of the sequence;
2) Addres~ o~ unit U~ fro~ which data to be exchanged mu t ~e - 16 - ~ .

.. . . . . . . . . .

~ ~ ~ 6 ~ 3 extracted (tran~mitting unit);

3) Address of unit UA which has to receive such data (receiving unit);

4) The number of data blocks to be exchanged,

5) The address o~ the starting memory location of transmitting unit UA (that is the address of the memory location of the first data block to be exchanga~);
: 6) The ad~ress of ~hç starting memo.ry location of receiving unit UA:
7) Exchange frequen~y;
8) End-of-exchange code configuration.
The parameters denoted by numbers 1), 2), 3), 4) are memoxized by the accumulator AB (Figure 3), the parameters denoted b~ references 5), 6) are memorize~ by accumulator AM; the parameters denvted by references ~), 8) are memorized by register RF.
Once the parameters are ac~uired by the exchange parameters control circuit CPS of the unit DEC, the unit DEC
a~sumes ~ontrol and tim~ng of the receiving a~d transmitting unit~ UA (wheth0r in the same subs~stem or in di~fe~ent 5ub-~ystems) the data exchange takes place block by block, at intervals determined by the ex~hange ~requency, ~rom the memory of the transmitting unit to the memory of the receiving unit, beginning with memory positions identified by addre~es referred to above under items 5~ and 6), ~or ~he number of blocks identiied ~y the parameter referred to above ~mder item 4).
The time intervals ~omprised between the transfer o~ a given blo~k and a subse~uent one can vary within a .

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wide range, during such intervals9 if suf~icient].y long, the receiving and transmitting units ~an operate autonomously and process the data they contain. Moreover during such time intervals, as already said, data exchanges can occur 'betwee~ units UA
having a priori~y di~ferent fro~ that of the exchange in progress.
The flow chart of Pigure 4 descxibes th~ sequence of operations of acqui~ition of exchange parameters and data exchang~, with re~pect to a certain priority level.
In a rest condition, uni~ DEC (Figuxe 3) presen~s the general con~rol circuit rG2 in a ~waiting" condition: in such a conditionD that circuit continuously ~earche~ for a pos~ible data transfer reque~t on any priority level, as denoted in Figure 4 under t~e reference PCS (Priority choice se~uence) wherein priorities PnO Pi, Pl satisfy relation Pn < Pi ~ Plo ; The acceptan~e, on the part of unit DEC, of a request for an ~xchange presen~ed by a unit UA, is memorized i~ the general control circuit CG2 while waiting for the related exchange parameters ac~uls i tio~ sequence to occur, during such a waiting period the requesting unit UA can carry out autonomous proce~sing operation~.
The exc~a~ge parametcrs ac~uisition se~ence (EPAS) is described in t~e drawing as related to priority level Pi, o~e aaquisition only o~ exchange parameters per level is allowed, then a data exchanye ~e~uence (DES) must follow. Only at the end o ~his operation may a subsequent ac~uisition sequence ~EPAS) take place for tha~ prioxity level.
co~aitions Alt A2, A3, A4, A5, A60 A7~ A8 deno~e the se~uential acq~lisition of the eigh~ excharlge parameters above-. .

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mention~d. Control circuit CG2 ~Figure 3) o unit DEC, which is conn~cted for the whole acquisition time to requesting unit UA, operates the above-mentionea se~uence.
The eight parameters are stored in eight further memory locations in re~uesting unit UA t said locations being addressed by ~he accumulator ~M, as already described~ The acquisition of parameters occurs under the control of the accumulator AB, which~ as already stated, addresses the re~uesting unit UA. The parameters are regarded as compl~tely acquired when they are stored in the memor~es of ac~umulators AB and AM
o~ regis~er RF.
~he data exchange sequenc0 (DES) (Figure 4~ i5 ~ubdivided into two characteri~tics sub~equence~; a sequence for the exchange of information blocks realized ~y steps Sl and S2 a~d a sequence ~or terminating the exchange realized ~y steps Fl, F2, F3.
Assuming at first that decision blocks RAl, ~A2, RS
: prese~t outp~s ao~, the ~irst o the two above-mentioned subsequences is reached rom condition A8 of the sequence EPAS;
steps Sl and S2 are consecutivaly carried out: until the decision block FB present~ an output "0", step~ Sl a~d S2 are repeated in a elosed cycleO
When, after a certain number of iterations, as will bs seen hereinafter, deci~ion block FB presents an output "1", the secona 0~ said s~bsequence~ is initiate~, whi~h consists of ~teps Fl, F2, T3, and flnally the rest condition~ -During ~tep Sl a particular block of data is transerred from transmitting unit UA ~Fig~ 1) to uni~ DEC; during step S2 ~ ~g ~

~L~71~Z3~
IFi~ure 4~ the same block o~ data is transerred from unit DEC
(Fig. 1) to receiving unit UA; such operations are controlled and timed by controlling circuit CG2 (Figure 3) of unit DEC and occur as previously descxibed,, The blocX of data undcr consideration will be sent from a location in memory ME (Fig~ 2~ of transmitting uni~ UA
to an analogou~ one in receivi~g u~it UA; addressing opera~ions o~ the receiving unit and of the transmitting unit occur by means of accumulator AB (FigO 3~ of unit D~C; addressing of locations in memory ME (Fig. 2~ of the two units UA occurs by means of accumulator ~M (Fig~ 3); the respective operations of incrementing addres~es for sub~equent blocks and locations occur al50 by means of accumulator AM, all as previously described with reference to unit DEC.
When all the exchanges have been carried out, the deci~ion element F8 (Fig. 4) will present an output "1", and the end-of-exchange sequence is reached.
During steps Fl~ F2, F3 the end-of-exchange code is sent to the reque9ting, transmitting and receiving units UA.
~hi5 txang~er iS controlled hy regi~ter R~ (Fig. 3) under command o~ the control aircuit CG2, as already described.
The deci~ion element RAl (Fig~ 4~ has the aim oE
allowing a quick return to the priority choice sequence (PCS) (i.e. the waiting condit~on) at the end o~ the exchange pa~ameters acquisition sequence (EPAS): this allows the carrying out of anot~er exchange parameters ac~uisition sequence with a pr~ority level different fxom ~he one for priority levPl Pi just considered, before beginning the data exchange sequence in respect of level Pi~
'~ '~ `' ~ - 20 ~

- ~'76~3~

the criterion upon which decision element RAl is activated is not predetermined, and can be altered from time to time according to the basis o~ the operations a subsystem is expected to perform from time to time. For instance, RAl can go to logical 1 if at the end of a parameter ac~uisition sequence with priority Pi there is waiting another request for exchange of data having greater priority than t~e one in progress~ It forms, bas~cally, the "control with logical criteria" of the time ~ivision operation, which has already been mentioned.
~he decision element R~2 is intended to allow a return of the priority choice sequence (PCS) at the end of an elementary data exchange sequence DESo The purposes o this can be maniold, a~ for instance, to acquire in the shortest possibl0 time parameters relative to a re~uest for exchange having priority greater than the exchange in progre~s~ Also the unc~ion o~
the decision element RA2 is subject to the same comments as those made in respect the function of the decision elemen~ RAl~
The decision element R~ has the aim of allowing the passage from an acquisition sequence EPAS having priority Pi to a data exchange sequence DES having priority P (i-l); through the analogous decision blocks placea in other exchan~e sequences (1.~o...n) i~ is possible to carry out more ~han one priority choice. In the drawing RR ti~l) denotes the output "1" 0~
block RR relative to priority level P(i + 1). . ~:
The comments made about the function of the decision element RAl are also valid in r~spect of the deci~ion element RR~
~ Decision element RS is suitably implemented to allow ~6~30 the passage from the end o~ an elementar~ aata exchange se~uence having priority level Pi to an elementary daka exchange having a different priority level. In the drawing RS (i ~ 1) denotes the ou~put "1" from element P~S relative to priority level P (i + 1) ~, The ~unction of the decision element RS is subject to the same co~ments as those made in respect of decision element RAl .
The decision elem nts R~ and RS in this way allow the interchange o~ data at di:eferent priority l~vels by making use of the time division ~echnique with respect to exchange frequencies.

Claims (10)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. In an electronic data-processing system, in com-bination:
a plurality of mutually independent miniprocessors with individually programmed operating cycles, each miniproces-sor including a data store containing a series o-E data blocks;
a control unit connected to all said miniprocessors and responsive to a request from an originating miniprocessor, designating a transmitting miniprocessor and a receiving mini-processor, for establishing an exchange miniprogram for the con-secutive transfer of a selected number of data blocks during res-pective transfer cycles from said transmitting miniprocessor to said receiving miniprocessor;
timing means in said control unit dividing each of said transfer cycles into a first phase and a second phase;
instruction-register means in said control unit for temporarily storing, during the execution of said exchange mini-program, the identities of said transmitting and receiving mini--processors together with information identifying the data block to be consecutively transferred;
a buffer register in said control unit responsive to signals from said timing means for temporarily storing a data block read out from said transmitting miniprocessor during said first phase of a transfer cycle and for forwarding the stored data block to the receiving miniprocessor during said second phase of the same transfer cycle; and interface circuitry controlled by said timing means and responsive to the contents of said instruction-register means for establishing a transfer path for incoming data blocks from said transmitting miniprocessor to said buffer register during said first phase and a transfer path for outgoing data blocks from said buffer register to said receiving miniproces-sor during said second phase.

2. The combination defined in claim 1, wherein said instruction-register means is divided into a plurality of stages for the concurrent storage of information relating to different exchange miniprograms performed in time-division mode under the control of said timing means.

3. The combination defined in claim 2, wherein said stages correspond to different priority levels assigned by said timing means to the respective exchange miniprograms, said time-division mode following an order to preference conforming to said priority levels.

4. The combination defined in claim 1, wherein said instruction-register means includes a first register for the storage of said selected number of data blocks included in said exchange miniprogram, said instruction-register means further including a second register for the storage of the addresses of locations in the data stores of said transmitting and receiving miniprocessors.

5. The combination defined in claim 4, wherein said addresses are consecutively numbered, said first register inclu-ding first accumulating means responsive to counting pulses from said timing means for decrementing the stored number of data blocks upon the completion of each transfer cycle of said mini-program, said second register including second accumulating means responsive to counting pulses from said timing means for incre-menting the stored addresses of said locations upon the comple-tion of each transfer cycle.

6. The combination defined in claim 5, wherein said instruction-register means further includes an additional regis-ter for the storage of instructions from said originating mini-processor relating to the timing of said transfer cycles, said additional register being operable to emit a termination signal to said originating, transmitting and receiving miniprocessors in response to a command generated by said first accumulating means upon reduction of said stored number of data blocks to zero.

7. In an electronic data-processing system, in com-bination:
a multiplicity of mutually independent miniprocessors with individually programmed operating cycles, said miniproces-sors being grouped in a plurality of subsystems and including each a data store containing a series of data blocks;
a control unit in each subsystem connected to all said miniprocessors and responsive to a request from an originating miniprocessor in its own subsystem, designating a transmitting miniprocessor and a receiving miniprocessor, for establishing an exchange miniprogram for the consecutive transfer of a selec-ted number of data blocks during respective transfer cycles from said transmitting miniprocessor to said receiving miniprocessor;
timing means in each control unit dividing each of said transfer cycles into a first phase and a second phase;
instruction-register means in each control unit for temporarily storing, during the execution of said exchange mini-program, the identitites of said originating, transmitting and receiving miniprocessors together with information identifying the data blocks to be consecutively transferred;
a buffer register in each control unit responsive to signals from said timing means for temporarily storing a data block read out from said transmitting miniprocessor during said first phase of a transfer cycle and for forwarding the stored data block to the receiving miniprocessor during said second phase of the same transfer cycle; and interface circuitry controlled by said timing means of each control unit and responsive to the contents of said instruction-register means thereof for establishing a transfer path for incoming data blocks from said transmitting miniproces-sor to said buffer register during said first phase and a transfer path for outgoing data blocks from said buffer register to said receiving miniprocessor during said second phase.

8. The combination defined in claim 7, wherein said instruction-register means is divided into a plurality of stages for the concurrent storage of information relating to different exchange miniprograms performed in time-division mode under the control of said timing means according to an order of preference based on different priority levels assigned by said timing means to the respective exchange miniprograms, said timing means being responsive to temporary unavailability of a miniprocessor invol-ved in a requested high-priority exchange miniprogram, for car-rying out at least part of a concurrently requested lower-prior-ity exchange miniprogram.

9. The combination defined in claim 7, wherein said interface circuitry means includes a transmitting interface and a receiving interface in each subsystem, a bus in each sub-system connected in parallel to said transmitting and receiving interfaces, said control unit and said miniprocessors thereof, and branch connections extending between transmitting and re-ceiving interfaces of different subsystems.

10. The combination defined in claim 9, wherein said branch connections interlink the transmitting and receiving interfaces of all subsystems in a closed circuit for one-way data transmission.