CA1081379A - Telephone transmission system - Google Patents
Telephone transmission systemInfo
- Publication number
- CA1081379A CA1081379A CA262,529A CA262529A CA1081379A CA 1081379 A CA1081379 A CA 1081379A CA 262529 A CA262529 A CA 262529A CA 1081379 A CA1081379 A CA 1081379A
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- Prior art keywords
- signal
- signals
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- analog
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J4/00—Combined time-division and frequency-division multiplex systems
- H04J4/005—Transmultiplexing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
Abstract
A TELEPHONE TRANSMISSION SYSTEM
Abstract of the Disclosure The invention relates to telephone transmission systems in which frequency multiplexing is carried out by digital processes. It consists in substituting to a computation step of an analytical signal a computation step of a much simpler complex signal. The ultimate signal obtained is not compatible with standard multiplexing apparatus, but may nevertheless be transmitted along ordinary channels.
Abstract of the Disclosure The invention relates to telephone transmission systems in which frequency multiplexing is carried out by digital processes. It consists in substituting to a computation step of an analytical signal a computation step of a much simpler complex signal. The ultimate signal obtained is not compatible with standard multiplexing apparatus, but may nevertheless be transmitted along ordinary channels.
Description
This invention rela~es to telephone transmission systems in which several multiplexed telephone channels are trans-mitted along one and the same line. ~ne invention also relates to the multiplexers and demultiplexers ~hich enable a system of this kind to be used in practice.
For transmitting several separate telephone channels along one and the same line, it is known that these channels may be frequency-converted, for example by single sideband modulation of a set of suitably staggered carriers by these channels. International standards define the various ~requency conversion levels used in these frequency multiplexes and one o~ them is, for example, the Secondary European Group which ~omprises 60 telephone c~annels of which the spectrum is inverted and which are staggered at intervals of 4 ~Hz between 3~2 and 552 kHz.
It is also known that these channels can be digitalised ! and that the binary words thus obtained can be multiplexed in time to obtain a succession of frames which are transmitted along a common line, thus forming a tlme-division multiplex.
~o These ~perations ~re also defined hy international standa,-ds whichJ in particular, define the European PCM Group whlch comprises 30 channels each digitalised with 8 bits at intervals o~ 125 ~ (i.e. at a frequency of 8000 Hz). These channels are multiplexed in a frame of 256 bits, the 16 additional bits corresponding to 2 zero channels and being reserved ~or synchronisation.
In the case of frequency multiplexing~ the various opera-tions of modulation, demodulation and filtration may be carried ; ' ., . , . .. _ , . . ~ .
.. ,_,. . . .. .. .... .....
, - ~'' ' ,' . ~ ' '' ~
-out digital methods applied to the telephone signals which are previously digitalised and the reconverted into analog form.
A method such as this is descri-bed in the article "SSB/FDM
Utilizing TDM Digital Filters" published by Carl F. KURTH in the journal "IEEE Transactions On Communication Technology", Vol. com-l9, No. 1, February 1971.
In order to improve the simplicity and performance of a system of the type in question, it is preferred, rather than copying the digital method from the analog method, to use a more synthetic method such as that described by Jacque DAGUET
and Maurice BELLANGER in French Patent No. 2,188.920 published on January 18, 1974, in the article "TDM-FDM Transmultiplexer:
Digital Polyphase and FFT" published in the journal "IEEE
Transactions on Communications", Vol. com-22, No. 9, September 1974, and in the article entitled "Maquette de faisabilité d'un - Transmultiplexeur Numérique" (Feasibility Model of a Digital Transmultiplexer) published in the journal "Cables et Trans-missions" No. 4, October 1974.
In the multiplexer described in these publications, the telephone signals, which are real signals, are applied to modulators which convert them into analytical signals compris~ng a component in phase and a component in quadrature.
These analytical signals are applied to a fast Fourier trans-form calculator acting as modulator. The signals issuing in parallel from this calculator pass through circuits acting as filters which enable the crosstalk between channels to be eliminated and are then applied in series to a digita-analog converter. It can be shown that the signal issuing from-this converter comprises at least one frequency multiplex of the ' : ~
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telephone channels whose spectrum is based on the zero ~requen-cy. In order to obtain the desired secondary group, 1t is sufficient to effect a frequency conversion, for example by sub~ecting an adequate carrier to lower single sideband modu-lation.
It is often necessary to convert time-division multiplexes into frequency multiplexes and vice versa, for example two ~0-channel PCM groups into one 60 channel secondary group, in particular for utilising existing trunk connections whic~ are only able to transmit analog signals. An apparatus which effects a conversion such as this is called a transmitting or receiving transmultiplexer, according to the circumstances, If an apparatus such as this is to deliver or use a signal identical with that of a secondary group, it is necessary to eliminate the amplitude compression e~fects used in PCM systems. This can only be done without difficulty ! by decoding the PCM signal into an analog signal. In this case, the analog signal obtained has to be linearly recoded in order to be able to use a digital multiplexer.
~n obJect of t~e present invention is to simplify the multiplexers to a considerable extent by accepting obtai-ning a signal which is not identical with that of a sec~ondary group. In this case, it is possible in particular directly to use the digital PCM signals in the digital multiplexer.
This simpllficatlon is of particular interest in cases where two ~0-channel PCM groups are converted into one 60 channel secondary group because a single apparatus receives a whole number of PCM and secondary groups.
813'79 Although the signal is not identical with that of a secondary group, it does have the same external characteristics and is comprised within the same frequency limits, which means that it is still possible to use existing analog connections without modification. the only limitation arises out of the need to use homologous equipment at each end.
If this limitation is accepted, the non-compatibility between the signals may be much further increased whilst remaining within the same frequency limits. To this end, complex signals obtained by simple calculation, rather than analytical signals, are formed in the apparatus according to the invention from real telephone signals and the anti- -crosstalk filtration function is eliminated after modulation which introduces into the spectrum an interchannel crosstalk which is eliminated at the receiving end by the action of the receiver homologous with the transmitter. The spectral distri-bution is thus entirely different from that of a normal secondary group.
~ In accordance with the present invention, it is provided :~ 20 an apparatus for multiplexing a set of n incoming signals arriv-ing respectively on n input telephone channels into an output frequency division muitiplex signal going out on an output chan-nel. The apparatus comprises:
means for procéssing the incoming signals, pr~viding every T ~s n complex signals St,n = ~ ft,k + ft+Ttk~ i~ t,k ft+T k~ and n conjugate compleY signals St n = 1 [(ft k + ft+T k) ~ i (ft k- ft+T k)]~ and delivering said signals St and St means for receiving the signals St n and St digitally computing every 2T ,us the Fourier Transform of order 2N x 2N(N
n) of the signals St n and St,n, and delivering the result of the computation as 2N real signals in parallel;
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means for serializing according to a given order and during an interval of 2T us the real signals, delivering a serial digital signal; and means for converting the serial digital signal into the output division frequency multiplex signal.
For a better understanding of the invention and to show how the same may be carried into effect, reference will be made to the ensuring description and to the attached figures among which :
Fig. 1 illustrates a transmitting transmultiplexer.
Fig. 2 illustrates one embodiment of the component TRA
of the transmultiplexer illustrated in fig. 1.
Fig. 3 illustrates one embodiment of the component PS of the transmultiplexer illustrated in Fig. 2.
Fig. 4 illustrates a receiving transmultiplexer.
Fig. 5 illustrates one embodiment of the component RY of the transmultiplexer illustrated in Fig. 4.
Fig. 6 illustrates one embodiment of the component SP of the transmultiplexer illustrated in Fig. 4.
Fig. 7 illustrates one embodiment of the component TAR
of the multiplexer illustrated in Fig. 4. -Fig. 8a and 8b illustrate flow diagrams of transmission systems.
'~ ' .
" 1081379 The transmitting transmultiplexer illustrated diagrammati-cally in Fig. 1 comprises two demultiplexers DX1 and DX2, a real-analytical converter TRA, a Fourier transform~r TFR, a seria-liser PS, a counter SY, a bistable circult D, a commutator TS, a digital-analog converter DA 2nd a modulator BLU.
The symbols used are used by way of example and are consistent with european telephone standards. The single arrows represent connections in which signals or channels circulate in series. The thick arrows represent connections in which channels circulate in parallel. The connections supporting service signals, and in particular clock signals, other than those required for understanding the invention, have not been shown. It is assumed that these signals, uhich have not been shown, are generated in each module according to requirements and with the correct phase.
; This transmultiplexer receives two standardised PCM
groups PCM~ and PCM2 each comprising ~2 telephone channels, of which two are suppressed for synchronisation, sampled at 8000 Hz and coded from 8 bits. Tnese ~2 channels are thus ~ultiplexed into fr~mes lastirg ~0OO = 125 ~s.
The beginning of each frame is marked by the ascending edge o~ a synchronisation signal T which is common to the two PCM
; groups which are therefore synchronous. This signal T is a square si~nal at 8000 Hz supplied by the telephone hardware which deliver PCM1 and PCM2.
The demultiplexers DX1 and DX2 enable the signals which arrive in series at their inputs to be obtained in parallel at their outputs by known techniques. To this end, there are ...... .... . ...... . .. . ...... ..... ...
~ .. .. . . .
used, for example, registers which are successively loaded with the words of a PCM frame as they arrive and which are then simultaneously read in parallel when the ~rame is complete.
The signal T synchronises this operation. Accordingly, the 60 samples of telephone signals ft k (k = 2, ..., 61) are obtained every 125 J~s at the outputs of DXl and DX2, the four synchro-nisation channels having been eliminated. The output registers of DX1 and DX2 enable these signals to be memorised during the arrival of the following frame. The range of variation of k~ is thus fixed for reasons which will be explained hereinafter.
In conventional systems, the real signal of each of the telephone channels is converted at this stage into an analytical signal. This necessitates the use of a calculation process involving a large number of successive samples of the same signal which in turn necessitates the use of extensi~e hardware.
In the transmultiplexer according to the invention, there is no need for compatibility with the signal of a secondary group, which enables a complex pseudo-analytical signal to be ~ormed by the following simple calculation process :
Given two successives samples of one and the same channel ~t k~ ft+T k~ the following two signals are initially formed :
at,k 2 (ft,k t+T,k) bt,k 2 (ft,k ft+T,k) The following con~ugated complex signals, where j = ur- 1, are 25 then formed from these two signals : St m = at k + j bt k ror m = k = 2, ..., 61 ; SXt m - at k ~ j bt k for m = 128-k = 67, ..., 126 . Since this calculation is made for the samples ft k and ft+T k~ the following calculations will be made for the samples ., .
.. ,, ., . . .,, ~...... ... . . . .
: - "- - , :
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108~3'79 ~t+2T k anf ft+~T k~ which corresponds to the band reduction by two obtained by passing from a real signal to an analytical signal. The amount of information contained in the two succes-sives samples reappears in one of the two complex signals St m or SXt m. me fact that these two con~ugated complex signals are present corresponds to a need for calculation in tha ~ollowing components.
We shall term "unit interval" this time interval 2T - 250~s during which the two successive samples ft k and ft+T k are processed. The square signal T1 of ~requency 4000 Hz, which enables this unit interval to be marked in the transrnulti-plexer, is obtained from T by division by 2 in the bistable circuit D.
These calculations are effected in the real-analytical converter TRA which is made up of 60 identical circuits enabling the 120 signals Sm and sX to be obtained.
Figure 2 diagrammatically illustrates one o~ these cir-cuits comprising a delay circuit 210, two gates 211 and 212, two inverters 21~ and 2?0, two memories 214 and 215, an adder 216, a substractor 217 and two multipliers 218 and 2lg~ The connections represent the paths of the words or synchronisation signals wlthout distinguishing whether the bits are in series or parallel.
The delay circuit 210 delivers ~rom the signal T1 a signal T2 which is in phase with the signal f~. m is signal T2 activates in particular the computation circuits 214 to 219 which comprise the necessary internal delays.
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,....... ..... ~ ... - -..
The gate 211 (an assembly of gates i~ the bits are in parallel) is open during the part corresponding to a state 1 of the signal T2 (i.e. 125 ~) and accordingly allows through the signal ft k which is stored in the memory 214.
The inverter 21~ inverts the signal T2 and applies the signal T~ thus obtained to the gate 212 which is thus opened during the zero part corresponding to a state 0 of T2 (i.e.
the following 125 rs) and then allows through the signal ft+T ~ which is stored in the memory 215.
The outputs of the memories 214 and 215 are applied to the adder 216 where the signal 2at k is obtained and to the substractor 217 where the signal 2bt k is obtained. me multipliers 21~ an~ 219 are multipliers by ~.5 which enable at k and bt k to be obtained-The inverter 220 enables the signal - bt k to be obtained t,k I Accordingly3 two sets of signals (at k~ bt k) and (at k~ ~ bt k) are thus available at the output of the circuit shown in Figure 2, representing the signals St m and SXt m' ~o because the comp'ex rotation is only a symbolic representakion and since the digital systems are only able to effect the computations on the components of complex numbers.
For the purposes of computation in the Fourier transformer TFR, the 120 complex signals St m issuing from TRA have to be completed by 8 identically zero complex signals so that the 128 signals thus obtained may be written in the form of the column vector :
: ' .
10813'~9 9 t, ~ ~; t,2 + ~ bt,2 ~
~ ~ 5 ~ D
~t,67 ~ ; ~t,6 J bt,61 St,12~ at,2 ~ bt,2 m ese 128 signals are processed in the Fourier transformer TFR which is a known apparatus which effects the matrix compu-tation : ~ = { w~ ~t. One example o~ embodiment of an apparatus such as this may be ~ound in French Patent n 69.45.6~4. ~ W~ is a square matrix ~f which the elements wn k have the value te ~ _ ) n-k = wn k , n and k varying . ~rom O to 127.
- , . . - ; . -- . . ..
108~3~7~
We shall now show, with reference to a less complex example, that on the one hand the vector xt is real and that on the other hand thls operation corresponds to the modulation of a series of carriers spaced at intervals o~ 4 kHz by the channel signals.
In the case Or three channels + 1 identically zero channel (i.e. for a matrix 8 x 8), the above formula is written by replacing, as is customary in the expression of ~ W ~, the element wn k by its coefficient n.k, taking into account that this coe~ricient is defined modulo 8 inclusive ~or negative values, and by deleting the index t which is the same throughout, ~xO~ O O O O O O O O ~ .--x1 1 2 ~ -4 -~ -2 -1 a1 + ~ b x2 2 4 6 0 -6 -4 -2 a2 + j b2 X3 = ~ 6 1 -4 -1 -6 -~ . ~ + J b3 4 4 ~4 ~4 X5 5 2 7 -4 -7 -6 -5 a~ - ; b~
X6 6 4 2 0 -2 -4 -6 a2 ~ ~ b2 x~ 0 7 6 5 4 -5 -6 -7 a1 - ~ b By forming, in accordance with the rules of matrix computation, the product o~ the lines of the matrix by the vector S, it is round that only terms Or the rorm [ w k (a + ; b) + w k (a - ~ b)~ are obtained. Now, wk and w are Or the ~orm (c + ~ d) and (c - ~ d) and, by develo-ping the above expression, a term o~ the form 2 (ac - db), where the imaginary terms have disappeared, is obtained.
,. , ' 108~3~3 This result emanates from the particular expression given to the vector ~ and, more particularly, ~rom the introduction of the zero channel corresponding to the indices m = 0 and m = 64, and from the symmetrical distribution about this index 64 of the terms Sm and SXm. We shall term a vector such as this an anti-symmetrical vector. It is pointed out that it implies that the matric is square with an even number of lines and hence columns = 2N.
Assuming now that only the channel 1 is not zero, the vector xt is thus given by :
xO -rwo (al + ~ bl) + w (al - j bl) XlWl ~ al + ; bl ) + w 1 ( al - ~ b X2W (al +; bl) + W 2(al - j bl) x3(al + j b1) + w (a1 - ~ b1) xt = x4 = w (a1 + j b1) + w (a1 - i bl) x5w5 (a1 + ~ b1) + w 5(a1 - ~ b1) ! X6W6 (a1 + ~ b1) + w ta1 ~ ~ b1) . 7 IL_ (al + j b1) + w (a1 - j bl) ~ l ~ww2-w3 . (a1 + ~ bl~ + ww_34 . (a1 - j b1) Z5 ~ ~ 5 = w1 t x (a1 ~ ~ b1) t + (w1 t) 1 x (a1 - ; b1) t-108137~
Since this operation ~akes place in 250~s, it can ~e seen that the terms of w1 t may be considered as the 8 successive analytical samples of one period of a sinusoidal signal of frequency -6 = 4000 Hz. In the case of the matric lZ8 x 128, there will be 128 successive samples of the same period.
These samples are multiplied by the analytical sample ~a1 + j b1) t of a voice signal of which the frequency is comprised within the telephone baseband of ~00 to ~400 Hz. -As already known, this multiplication operation is the trans-lation in digital form o~ a modulation operation in analog form. As has already been seen, the operation (w1 t) 1x (a1 - j b1) t enables a real signal to be obta~ned by adding these two terms. Accordingly, the terms of xt are the 8 successives real samples of one period of a sinusoidal signal of frequency 4000 Hz modulated by a voice signal, this modulated signal thus being sampled 8 x 4000 = ~2000 times per second.
In order to see the type of modulation obtained, it is ~0 sufficient to point out that w1 t and (a + ; b1) t both corres-pond to vectors rotating in the direct sense and that (w1 t) 1 and (a1 - ~ b1) both correspond to vectors rotating in the opposite sense. In the two cases, the rotational speeds are added together in the case of products which thus correspond to terms of higher frequency than the carrier. Accordingly, the modulation in question is an upper sideband modulation.
However, regularly repeated lobes are obtained on account of the modulation emanating from the sampling operationO
~Q8g379 The method of modulation in question is in ~act a conversion of Hartley~s modulation method.
By applying the same reasoning to channel 2 alone, the following result is obtained :
Xt = (w1 t) 2 x (a2 + j b2) t + (w1,t) ( 2 2 t where the terms of (w1 t) 2 may be considered as the 8 succes-sive analytical samples of two periods of a sinusoidal signal of which the frequency is thus 8000 Hz. Accordingly, the terms f Xt are the 8 successive real samples o~ two periods o~ a sinusoidal signal o~ frequency 8000 Hz which has been sub~ec-ted to upper single sideband modulation by a voice signal and which is sampled 32000 times per second.
This reasoning is general and may be applied by degrees.
When the three channels are active, the terms of xt may be considered as the 8 successive samples o~ a signal compri-sing the superpositlon of three carriers spaced at intervals of 4000 Hz and modulated by upper sideband modulation.
It ls pointed out that the spacing between the carriers is rixed by the sampling frequency of the voice signals because the u~lt interval ~s fixed ~ this frequency and corresponds to a whole number of periods of carriers for each channel, this number being increased by one between each channel. The sampling frequency of these carriers is fixed by the size of the matrix ~ w ~ in dependance upon the unit interval.
The result (modulation) thus obtalned, however, is only an approximation for the ~ollowing three reasons :
; - on the one hand, the sampling process required for the digital processing gives rise to the well-~nown advent of modula4ion lobes, i.e. upper intermodulation products, which 108~379 in turn g~ves rise both to interchannel cross~alk, due to the sampling of the voice signals at 8000 Hz, and to the repeti-tion of the spectrum o~ the total signal in accordance with the ~ultiples o~ the sampling frequency of the carriers ;
- on the other hand, the sample of the voice signal is fixed and is therefore constant throughout the duration o~ the successive samples o~ the carrier taken in the single intervalJ
whereas it should normally de~elop and have a dif~erent value for each sample of the carrier. Although Shannon's conditi~on is thus satis~ied, the spectrum is distorded in this way ;
- ~inally, the signal a + j b used is only a ~irst order approximation o~ an analytical signal, with the result that the lower sideband is not completely suppressed during the modulation operation, whence another source of crosstalk.
It is for these reasons in particular that the signal ~inally obtained is not identical with that of a secondary group.
Reverting to the transmultiplexer described above, it can be seen that, apart from the channel 0 which is taken as zero to obtain a vector St of adequate constitution, the three zero channels 1, 62 and 63 were also used. This means that the passage through TFR corresponds to the modulation of 60 carriers staggered at intervals of 4 kHz ~rom 8 kHz to 244 kHz by 60 voice channels numbered from 2 to 61. m ere are two reasons for inserting the three zero channels 1, 62 and 63 :
- on the one hand to obtain a number of channels equal to a power o~ 2, which is the case because !28 = 27. This enables the so-called Fast Fourier Trans~orm methods of computation, which are particularly advantageous, to be used in TFR ;
.~ . ... . ... .
1~)~379 - on the other hand to obtain the equivalent of the clearance channels by analog techniques which enables the subsequent filtration problems to be simplified.
Accordingly, 128 digital samples of a real signal sampled at a frequency of 128 x 250 1o_~ = 5~2,000 times per second are simultaneously obtained every 250~s at the output o~ the Fourier trans~ormer TFR.
m e serializer PS enables these samples to be brought back into series in the unit interval of 250 ~s. Figure ~ diagram-matically illustrates one embodiment o~ this serializer comprising a delay circuit ~1, an oscillator 32, a counter ~, a decoder 34, AND gates 3000 to ~127 and an OR gate 35.
~ he signal T1 is delayed in the delay circuit 31 so as to compensate (modulo 250 ~s) the delays due to the computations in TRA and ~l~. The signal T4 thus compensated in pha e synchronises the oscillator 32 which supplies a s~gnal at 512,000 Hz. This signal at 512,000 Hz causes the counter to rotate. The phase of this counter is maintained by the signal T4 which resets it to zero so that the backward count always begins with the state O at the beginnin~ of the unit interval. The counter 33 counts by 128 and its counts are decoded by the decoder 34 which has 128 outputs O to 127.
i These outputs are connected to the 128 AND-gates 3000 to 3127 whlch are thus opened one after the other during the unit interval of 250~s. m ese gates receive the signals xO to xl27 coming from TFR o~ which the output registers memorize the 128 real words of a unit interval for the duration of the following unit interval . m e OR-circuit collects the outputs of the AND gates and thus delivers the serial digital signal : 17 .
~081379 Xs composed of the serialized signals xO to x127.
It ls known that the Fast Fourier Transform algorithms ultimately give an output vector of which the components form a permutation o~ the natural order. It is Or advantage to bring these components back into the natural order by an adequate mixing of the connections between the outputs Or TFR and the inputs of PS. In the absence of this mixing, however, the signal would be completely incompatible in the sense that the modula-tion, which would remain grouped except for crosstalk about~the 10 carriers of the normalised fre~uency plane, would be completely distributed in the bandwidth. In other words, crosstalk would be complete. Although this is not troublesome,it would be absolu-tely essential to use a strictly homologous apparatus at the receiving end.
m e signal XS enters the commutator TS of which the function will be explained hereina~ter.
The output of the commutator TS is applied to the digital-analog converter DA which converts the digital signal xsinto an analog signal of which the spectrum extends from 0 to 256 ! 20 kHz and, in addition, is repeated every 215 kHz on account of the sampling~ In fact, the energy is low between 0 and 8 kHz and between 248 and 256 kHz because it only corresponds to the crosstalk, as seen earlier on9 the channels 0, 1~ 62 and 6~
bein~ zero. Since it is desired to obtain a signal of which the 25 bandwidth is that of a secondary group, i.e. 240 kHz, the frequencies of the signal issuing from the converter ~ are limited by adequately calculating the output filter thereof in such a way that is only allows through the 8-2~8 kHz band, ~` This facilities the work of the subsequent components, although ,........ .. . . ............... . . . .
:1~131379 it may also be carried out in them. An analog signal, named base-band is thus obtained.
In order to obtain the desired ~requency signal, it is now necessary to convert this base-band signal. This conversion is carried out in the modulator BLU which is an ordinary single sideband modulator and by which it is possible, for example by sub~ecting a carrier at 304 kHz to upper single sideband modulation, to obtain a signal ~.avin~ a spectrum comprised between ~12 and 552 kHz, i.e. occupying as required the bandwidth of a secondary group.
The digital processing at the receiving end imposes a condition of frame synchronisation and a condition of level equality between the transmitter and the receiver.
To this end, a constant signal REF is inserted at regular intervals into the signal XS applied to the converter DA
during one complete unit interval. This signal acts as phase ! reference and level reference ~or the receiver. For example, thls signal may be inserted every 8 seconds, in which case it is quite inaudible. It would also be possible to transmit two ~0 signals, one acting as phase reference and the other as level reference, The commutator TS shown diagrammatically in Figure 1, but produced ~or example with transistors, enables the input of the converter DA to be connected either to the output o~ the serializer PS or to a line to which the signal REF is permanen-tly applied. mis signal has a constant levelJ for example half of the scale of the converter DA.
Thls commutator is activated by a signal coming ~rom the counter S~ which counts ths sign~ls T1 backwards, for example .
~08~379 by ~2,000, which gives a control signal every eight seconds.
SY contains an internal delay circuit enabling the operatlonal interval of TS to be made to coincide with one complete unit interval.
The receiving transmultiplexer shown in Figure 4, comprises a demodulator DBLU, an attenuator AT, an analog-digital conver-ter AD, a synchronizer RY, a parallelizer SP, a Fourier trans_ former RTFR, an analog-real converter TAR and two multiplexers MXl and MX2. The following description is made in accordan¢e with the same conventions as those used by the transmitting transmultiplexer.
mis receiving transmultiplexer receives an analog frequen-cy signal GS transmitted by a transmitter homologous with the receiver. mis signal thus a¢cupies the ~12-552 kHz frequency band, m e demodulator DBLU, which is an ordinary single sideband demodulator, enables this signal to be converted in the 8-248 kHz band. It therefore delivers an analog signal which shall be termed base-band signal.
~0 This base-band signal i.c attenuated in the attenuator AT
of which the function will be described hereinafter and which delivers an attenuated signal AN. "
This slgnal AN is applied to the analog-digital converter AD. me analog-digital converter functions at a ~requen¢y of 512,000 times per seconds and supplies 128 digitalized samples Or the signal AN in series every 250 ~s. This serlal digital signal XS is thus the same as that of the same n~me in the transmitter.
10~37~
In order to ensure this equality of level and to maintain synchronisation, the signal XS and the signal AN are both applied to the synchronizer RY. The synchronizer RY analyses the cons-tant level signal present for 250~h~ every 8 s and delivers a correcting signal S which controls the attenuator AT so as to - obtain a correct level of the signal XS and a synchronization signal Tl homologous with that of the same name in the transmit-ter.
Figure 5 shows one embodiment of the synchronizer RY
comprising three diodes 511, 512 and 513, ~our resistors R1 to R4, a capacitor C, an amplifier 514J an analog subtractor. 515, a comparator 516J an oscillator 517, a digital subtractor 518, three analog summators 519~ 520 and 521J one analog inverter 522J two digital inverters 423 and 528, four analog gates 524 to 15 527 and a sample-and-hold circuit 529.
The signal AN is reotified by the diode 511 and the resis-tor R1. A strictly positive s~gnal AR is thus obtained. The ampli~ier 514 acts as a separator for applying this signal AR
to the dlodes 512 and 513. The diodes are connected head-to-tail and are biased by a constant voltage +REF across the resistors R2 and R~. The value of +REF is substantially equal to the normal positive value of the reference signal contained in the signal AN. m e diode 512 only allows values of AR above +REF
through whilst the diode 513 allows only values of AR below 25 +REF through. The signal at the anode of the diode 513 is thus subtracted from the signal at the cathode o~ the diode 512 in ; the subtractor 515. In shortl this is equivalent to ~ull-wave recti~ying the signal AR about the value of +~EF .
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10813~
The common mode at the inputs of the subtractor 515 disappears in this operation and the signal at the output o~ the subtrac-tor is thus permanently positive except for the duration of the reference signal where it is zero and during the transient passages of AN through the value +REF. This signal charges a circuit made of the resistor R4 and the capacitor C. The time constant of this circuit is below the duration o~ the re~erence signal so that when this reference signal is present in the signal AN, the circuit R4-C has time to discharge to zero.
However, this time constant is sufficient for the circuit R~-L
not to discharge during the transient passages o~ the signal AN through the value +REF.
The comparator circuit 516 compares the voltage present in the circuit R4-C with a value which, although very low, is suf~icient to allow fairly switching o~ the circuit 516 when the circuit R4-C is discharged. Under these conditions, the circuit 516 switches after the beginning of the re~erence signal and its output passes from a logic state 1 to a logic state 0. When the re~erence signal disppears, the voltage present ~.n the circuit R~-C increases again almost instantane-ous on account o~ the low output impedance of the subtractor 515 and the circuit 516 itself also reswitches on the ~ield.
The ascending edge of the output slgnal of the circuit 516 thus clearly marks the end of the reference signal and hence the beginning o~ the following unit interval.
This signal, coming from the comparator 516, enables the oscillator 517 to be synchronizedO The oscillator 517 supplies the signal Tl whlch is, for example, a square signal at 8000 Hz ~0813'7~
of which the transitions in the same directions thus have a period of 250 ~.
It is difficult to obtain adequate level precision in particular on account of the threshold of the diodes, to control the attenuator AT by this part of the circuit SY. In addition, the converter AD would be removed from the components subjected to the control.
Accordingly, the value of the digital signal XS is compared with the normal value of the reference signal by subtracting ~rom it this value NREF in the digital subtractor 5~8. The result of this operation is expressed in the form of a digital word comprising in parallel a sign bit SIG and bits MOD repre-senting the absolute value of the deviation The voltages representing the bits Or the signal MOD are then added together in the analog summator 519. A non-linearity is thus introduced although it does not affect the result because the system is pilot-controlled. The result o~ this sum is always positive and the analog inverter 522 is used to make the negative value available as well. The choice between this positive value and thls negative value is made by the sign bit SIG which, according to circumstances, opens one o~ the analog gates 524 and 525 either directly or by way of a signal obtained by inversion of SIG in the digital inverter 528. The outputs of these gates are collected by the analog summator 520 which thus delivers a positive or negative error voltage according to the direction of the deviation between x5 and NREF.
The value of this voltage is only ~orrect during the instants where the reference signal ~s present in xs. These ; instants are ldentified by a state O at the output of the
For transmitting several separate telephone channels along one and the same line, it is known that these channels may be frequency-converted, for example by single sideband modulation of a set of suitably staggered carriers by these channels. International standards define the various ~requency conversion levels used in these frequency multiplexes and one o~ them is, for example, the Secondary European Group which ~omprises 60 telephone c~annels of which the spectrum is inverted and which are staggered at intervals of 4 ~Hz between 3~2 and 552 kHz.
It is also known that these channels can be digitalised ! and that the binary words thus obtained can be multiplexed in time to obtain a succession of frames which are transmitted along a common line, thus forming a tlme-division multiplex.
~o These ~perations ~re also defined hy international standa,-ds whichJ in particular, define the European PCM Group whlch comprises 30 channels each digitalised with 8 bits at intervals o~ 125 ~ (i.e. at a frequency of 8000 Hz). These channels are multiplexed in a frame of 256 bits, the 16 additional bits corresponding to 2 zero channels and being reserved ~or synchronisation.
In the case of frequency multiplexing~ the various opera-tions of modulation, demodulation and filtration may be carried ; ' ., . , . .. _ , . . ~ .
.. ,_,. . . .. .. .... .....
, - ~'' ' ,' . ~ ' '' ~
-out digital methods applied to the telephone signals which are previously digitalised and the reconverted into analog form.
A method such as this is descri-bed in the article "SSB/FDM
Utilizing TDM Digital Filters" published by Carl F. KURTH in the journal "IEEE Transactions On Communication Technology", Vol. com-l9, No. 1, February 1971.
In order to improve the simplicity and performance of a system of the type in question, it is preferred, rather than copying the digital method from the analog method, to use a more synthetic method such as that described by Jacque DAGUET
and Maurice BELLANGER in French Patent No. 2,188.920 published on January 18, 1974, in the article "TDM-FDM Transmultiplexer:
Digital Polyphase and FFT" published in the journal "IEEE
Transactions on Communications", Vol. com-22, No. 9, September 1974, and in the article entitled "Maquette de faisabilité d'un - Transmultiplexeur Numérique" (Feasibility Model of a Digital Transmultiplexer) published in the journal "Cables et Trans-missions" No. 4, October 1974.
In the multiplexer described in these publications, the telephone signals, which are real signals, are applied to modulators which convert them into analytical signals compris~ng a component in phase and a component in quadrature.
These analytical signals are applied to a fast Fourier trans-form calculator acting as modulator. The signals issuing in parallel from this calculator pass through circuits acting as filters which enable the crosstalk between channels to be eliminated and are then applied in series to a digita-analog converter. It can be shown that the signal issuing from-this converter comprises at least one frequency multiplex of the ' : ~
. . .
.' ~ .
telephone channels whose spectrum is based on the zero ~requen-cy. In order to obtain the desired secondary group, 1t is sufficient to effect a frequency conversion, for example by sub~ecting an adequate carrier to lower single sideband modu-lation.
It is often necessary to convert time-division multiplexes into frequency multiplexes and vice versa, for example two ~0-channel PCM groups into one 60 channel secondary group, in particular for utilising existing trunk connections whic~ are only able to transmit analog signals. An apparatus which effects a conversion such as this is called a transmitting or receiving transmultiplexer, according to the circumstances, If an apparatus such as this is to deliver or use a signal identical with that of a secondary group, it is necessary to eliminate the amplitude compression e~fects used in PCM systems. This can only be done without difficulty ! by decoding the PCM signal into an analog signal. In this case, the analog signal obtained has to be linearly recoded in order to be able to use a digital multiplexer.
~n obJect of t~e present invention is to simplify the multiplexers to a considerable extent by accepting obtai-ning a signal which is not identical with that of a sec~ondary group. In this case, it is possible in particular directly to use the digital PCM signals in the digital multiplexer.
This simpllficatlon is of particular interest in cases where two ~0-channel PCM groups are converted into one 60 channel secondary group because a single apparatus receives a whole number of PCM and secondary groups.
813'79 Although the signal is not identical with that of a secondary group, it does have the same external characteristics and is comprised within the same frequency limits, which means that it is still possible to use existing analog connections without modification. the only limitation arises out of the need to use homologous equipment at each end.
If this limitation is accepted, the non-compatibility between the signals may be much further increased whilst remaining within the same frequency limits. To this end, complex signals obtained by simple calculation, rather than analytical signals, are formed in the apparatus according to the invention from real telephone signals and the anti- -crosstalk filtration function is eliminated after modulation which introduces into the spectrum an interchannel crosstalk which is eliminated at the receiving end by the action of the receiver homologous with the transmitter. The spectral distri-bution is thus entirely different from that of a normal secondary group.
~ In accordance with the present invention, it is provided :~ 20 an apparatus for multiplexing a set of n incoming signals arriv-ing respectively on n input telephone channels into an output frequency division muitiplex signal going out on an output chan-nel. The apparatus comprises:
means for procéssing the incoming signals, pr~viding every T ~s n complex signals St,n = ~ ft,k + ft+Ttk~ i~ t,k ft+T k~ and n conjugate compleY signals St n = 1 [(ft k + ft+T k) ~ i (ft k- ft+T k)]~ and delivering said signals St and St means for receiving the signals St n and St digitally computing every 2T ,us the Fourier Transform of order 2N x 2N(N
n) of the signals St n and St,n, and delivering the result of the computation as 2N real signals in parallel;
.~,,'', .
~' .
means for serializing according to a given order and during an interval of 2T us the real signals, delivering a serial digital signal; and means for converting the serial digital signal into the output division frequency multiplex signal.
For a better understanding of the invention and to show how the same may be carried into effect, reference will be made to the ensuring description and to the attached figures among which :
Fig. 1 illustrates a transmitting transmultiplexer.
Fig. 2 illustrates one embodiment of the component TRA
of the transmultiplexer illustrated in fig. 1.
Fig. 3 illustrates one embodiment of the component PS of the transmultiplexer illustrated in Fig. 2.
Fig. 4 illustrates a receiving transmultiplexer.
Fig. 5 illustrates one embodiment of the component RY of the transmultiplexer illustrated in Fig. 4.
Fig. 6 illustrates one embodiment of the component SP of the transmultiplexer illustrated in Fig. 4.
Fig. 7 illustrates one embodiment of the component TAR
of the multiplexer illustrated in Fig. 4. -Fig. 8a and 8b illustrate flow diagrams of transmission systems.
'~ ' .
" 1081379 The transmitting transmultiplexer illustrated diagrammati-cally in Fig. 1 comprises two demultiplexers DX1 and DX2, a real-analytical converter TRA, a Fourier transform~r TFR, a seria-liser PS, a counter SY, a bistable circult D, a commutator TS, a digital-analog converter DA 2nd a modulator BLU.
The symbols used are used by way of example and are consistent with european telephone standards. The single arrows represent connections in which signals or channels circulate in series. The thick arrows represent connections in which channels circulate in parallel. The connections supporting service signals, and in particular clock signals, other than those required for understanding the invention, have not been shown. It is assumed that these signals, uhich have not been shown, are generated in each module according to requirements and with the correct phase.
; This transmultiplexer receives two standardised PCM
groups PCM~ and PCM2 each comprising ~2 telephone channels, of which two are suppressed for synchronisation, sampled at 8000 Hz and coded from 8 bits. Tnese ~2 channels are thus ~ultiplexed into fr~mes lastirg ~0OO = 125 ~s.
The beginning of each frame is marked by the ascending edge o~ a synchronisation signal T which is common to the two PCM
; groups which are therefore synchronous. This signal T is a square si~nal at 8000 Hz supplied by the telephone hardware which deliver PCM1 and PCM2.
The demultiplexers DX1 and DX2 enable the signals which arrive in series at their inputs to be obtained in parallel at their outputs by known techniques. To this end, there are ...... .... . ...... . .. . ...... ..... ...
~ .. .. . . .
used, for example, registers which are successively loaded with the words of a PCM frame as they arrive and which are then simultaneously read in parallel when the ~rame is complete.
The signal T synchronises this operation. Accordingly, the 60 samples of telephone signals ft k (k = 2, ..., 61) are obtained every 125 J~s at the outputs of DXl and DX2, the four synchro-nisation channels having been eliminated. The output registers of DX1 and DX2 enable these signals to be memorised during the arrival of the following frame. The range of variation of k~ is thus fixed for reasons which will be explained hereinafter.
In conventional systems, the real signal of each of the telephone channels is converted at this stage into an analytical signal. This necessitates the use of a calculation process involving a large number of successive samples of the same signal which in turn necessitates the use of extensi~e hardware.
In the transmultiplexer according to the invention, there is no need for compatibility with the signal of a secondary group, which enables a complex pseudo-analytical signal to be ~ormed by the following simple calculation process :
Given two successives samples of one and the same channel ~t k~ ft+T k~ the following two signals are initially formed :
at,k 2 (ft,k t+T,k) bt,k 2 (ft,k ft+T,k) The following con~ugated complex signals, where j = ur- 1, are 25 then formed from these two signals : St m = at k + j bt k ror m = k = 2, ..., 61 ; SXt m - at k ~ j bt k for m = 128-k = 67, ..., 126 . Since this calculation is made for the samples ft k and ft+T k~ the following calculations will be made for the samples ., .
.. ,, ., . . .,, ~...... ... . . . .
: - "- - , :
. , ~ .
. . .
108~3'79 ~t+2T k anf ft+~T k~ which corresponds to the band reduction by two obtained by passing from a real signal to an analytical signal. The amount of information contained in the two succes-sives samples reappears in one of the two complex signals St m or SXt m. me fact that these two con~ugated complex signals are present corresponds to a need for calculation in tha ~ollowing components.
We shall term "unit interval" this time interval 2T - 250~s during which the two successive samples ft k and ft+T k are processed. The square signal T1 of ~requency 4000 Hz, which enables this unit interval to be marked in the transrnulti-plexer, is obtained from T by division by 2 in the bistable circuit D.
These calculations are effected in the real-analytical converter TRA which is made up of 60 identical circuits enabling the 120 signals Sm and sX to be obtained.
Figure 2 diagrammatically illustrates one o~ these cir-cuits comprising a delay circuit 210, two gates 211 and 212, two inverters 21~ and 2?0, two memories 214 and 215, an adder 216, a substractor 217 and two multipliers 218 and 2lg~ The connections represent the paths of the words or synchronisation signals wlthout distinguishing whether the bits are in series or parallel.
The delay circuit 210 delivers ~rom the signal T1 a signal T2 which is in phase with the signal f~. m is signal T2 activates in particular the computation circuits 214 to 219 which comprise the necessary internal delays.
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g ~ :
,....... ..... ~ ... - -..
The gate 211 (an assembly of gates i~ the bits are in parallel) is open during the part corresponding to a state 1 of the signal T2 (i.e. 125 ~) and accordingly allows through the signal ft k which is stored in the memory 214.
The inverter 21~ inverts the signal T2 and applies the signal T~ thus obtained to the gate 212 which is thus opened during the zero part corresponding to a state 0 of T2 (i.e.
the following 125 rs) and then allows through the signal ft+T ~ which is stored in the memory 215.
The outputs of the memories 214 and 215 are applied to the adder 216 where the signal 2at k is obtained and to the substractor 217 where the signal 2bt k is obtained. me multipliers 21~ an~ 219 are multipliers by ~.5 which enable at k and bt k to be obtained-The inverter 220 enables the signal - bt k to be obtained t,k I Accordingly3 two sets of signals (at k~ bt k) and (at k~ ~ bt k) are thus available at the output of the circuit shown in Figure 2, representing the signals St m and SXt m' ~o because the comp'ex rotation is only a symbolic representakion and since the digital systems are only able to effect the computations on the components of complex numbers.
For the purposes of computation in the Fourier transformer TFR, the 120 complex signals St m issuing from TRA have to be completed by 8 identically zero complex signals so that the 128 signals thus obtained may be written in the form of the column vector :
: ' .
10813'~9 9 t, ~ ~; t,2 + ~ bt,2 ~
~ ~ 5 ~ D
~t,67 ~ ; ~t,6 J bt,61 St,12~ at,2 ~ bt,2 m ese 128 signals are processed in the Fourier transformer TFR which is a known apparatus which effects the matrix compu-tation : ~ = { w~ ~t. One example o~ embodiment of an apparatus such as this may be ~ound in French Patent n 69.45.6~4. ~ W~ is a square matrix ~f which the elements wn k have the value te ~ _ ) n-k = wn k , n and k varying . ~rom O to 127.
- , . . - ; . -- . . ..
108~3~7~
We shall now show, with reference to a less complex example, that on the one hand the vector xt is real and that on the other hand thls operation corresponds to the modulation of a series of carriers spaced at intervals o~ 4 kHz by the channel signals.
In the case Or three channels + 1 identically zero channel (i.e. for a matrix 8 x 8), the above formula is written by replacing, as is customary in the expression of ~ W ~, the element wn k by its coefficient n.k, taking into account that this coe~ricient is defined modulo 8 inclusive ~or negative values, and by deleting the index t which is the same throughout, ~xO~ O O O O O O O O ~ .--x1 1 2 ~ -4 -~ -2 -1 a1 + ~ b x2 2 4 6 0 -6 -4 -2 a2 + j b2 X3 = ~ 6 1 -4 -1 -6 -~ . ~ + J b3 4 4 ~4 ~4 X5 5 2 7 -4 -7 -6 -5 a~ - ; b~
X6 6 4 2 0 -2 -4 -6 a2 ~ ~ b2 x~ 0 7 6 5 4 -5 -6 -7 a1 - ~ b By forming, in accordance with the rules of matrix computation, the product o~ the lines of the matrix by the vector S, it is round that only terms Or the rorm [ w k (a + ; b) + w k (a - ~ b)~ are obtained. Now, wk and w are Or the ~orm (c + ~ d) and (c - ~ d) and, by develo-ping the above expression, a term o~ the form 2 (ac - db), where the imaginary terms have disappeared, is obtained.
,. , ' 108~3~3 This result emanates from the particular expression given to the vector ~ and, more particularly, ~rom the introduction of the zero channel corresponding to the indices m = 0 and m = 64, and from the symmetrical distribution about this index 64 of the terms Sm and SXm. We shall term a vector such as this an anti-symmetrical vector. It is pointed out that it implies that the matric is square with an even number of lines and hence columns = 2N.
Assuming now that only the channel 1 is not zero, the vector xt is thus given by :
xO -rwo (al + ~ bl) + w (al - j bl) XlWl ~ al + ; bl ) + w 1 ( al - ~ b X2W (al +; bl) + W 2(al - j bl) x3(al + j b1) + w (a1 - ~ b1) xt = x4 = w (a1 + j b1) + w (a1 - i bl) x5w5 (a1 + ~ b1) + w 5(a1 - ~ b1) ! X6W6 (a1 + ~ b1) + w ta1 ~ ~ b1) . 7 IL_ (al + j b1) + w (a1 - j bl) ~ l ~ww2-w3 . (a1 + ~ bl~ + ww_34 . (a1 - j b1) Z5 ~ ~ 5 = w1 t x (a1 ~ ~ b1) t + (w1 t) 1 x (a1 - ; b1) t-108137~
Since this operation ~akes place in 250~s, it can ~e seen that the terms of w1 t may be considered as the 8 successive analytical samples of one period of a sinusoidal signal of frequency -6 = 4000 Hz. In the case of the matric lZ8 x 128, there will be 128 successive samples of the same period.
These samples are multiplied by the analytical sample ~a1 + j b1) t of a voice signal of which the frequency is comprised within the telephone baseband of ~00 to ~400 Hz. -As already known, this multiplication operation is the trans-lation in digital form o~ a modulation operation in analog form. As has already been seen, the operation (w1 t) 1x (a1 - j b1) t enables a real signal to be obta~ned by adding these two terms. Accordingly, the terms of xt are the 8 successives real samples of one period of a sinusoidal signal of frequency 4000 Hz modulated by a voice signal, this modulated signal thus being sampled 8 x 4000 = ~2000 times per second.
In order to see the type of modulation obtained, it is ~0 sufficient to point out that w1 t and (a + ; b1) t both corres-pond to vectors rotating in the direct sense and that (w1 t) 1 and (a1 - ~ b1) both correspond to vectors rotating in the opposite sense. In the two cases, the rotational speeds are added together in the case of products which thus correspond to terms of higher frequency than the carrier. Accordingly, the modulation in question is an upper sideband modulation.
However, regularly repeated lobes are obtained on account of the modulation emanating from the sampling operationO
~Q8g379 The method of modulation in question is in ~act a conversion of Hartley~s modulation method.
By applying the same reasoning to channel 2 alone, the following result is obtained :
Xt = (w1 t) 2 x (a2 + j b2) t + (w1,t) ( 2 2 t where the terms of (w1 t) 2 may be considered as the 8 succes-sive analytical samples of two periods of a sinusoidal signal of which the frequency is thus 8000 Hz. Accordingly, the terms f Xt are the 8 successive real samples o~ two periods o~ a sinusoidal signal o~ frequency 8000 Hz which has been sub~ec-ted to upper single sideband modulation by a voice signal and which is sampled 32000 times per second.
This reasoning is general and may be applied by degrees.
When the three channels are active, the terms of xt may be considered as the 8 successive samples o~ a signal compri-sing the superpositlon of three carriers spaced at intervals of 4000 Hz and modulated by upper sideband modulation.
It ls pointed out that the spacing between the carriers is rixed by the sampling frequency of the voice signals because the u~lt interval ~s fixed ~ this frequency and corresponds to a whole number of periods of carriers for each channel, this number being increased by one between each channel. The sampling frequency of these carriers is fixed by the size of the matrix ~ w ~ in dependance upon the unit interval.
The result (modulation) thus obtalned, however, is only an approximation for the ~ollowing three reasons :
; - on the one hand, the sampling process required for the digital processing gives rise to the well-~nown advent of modula4ion lobes, i.e. upper intermodulation products, which 108~379 in turn g~ves rise both to interchannel cross~alk, due to the sampling of the voice signals at 8000 Hz, and to the repeti-tion of the spectrum o~ the total signal in accordance with the ~ultiples o~ the sampling frequency of the carriers ;
- on the other hand, the sample of the voice signal is fixed and is therefore constant throughout the duration o~ the successive samples o~ the carrier taken in the single intervalJ
whereas it should normally de~elop and have a dif~erent value for each sample of the carrier. Although Shannon's conditi~on is thus satis~ied, the spectrum is distorded in this way ;
- ~inally, the signal a + j b used is only a ~irst order approximation o~ an analytical signal, with the result that the lower sideband is not completely suppressed during the modulation operation, whence another source of crosstalk.
It is for these reasons in particular that the signal ~inally obtained is not identical with that of a secondary group.
Reverting to the transmultiplexer described above, it can be seen that, apart from the channel 0 which is taken as zero to obtain a vector St of adequate constitution, the three zero channels 1, 62 and 63 were also used. This means that the passage through TFR corresponds to the modulation of 60 carriers staggered at intervals of 4 kHz ~rom 8 kHz to 244 kHz by 60 voice channels numbered from 2 to 61. m ere are two reasons for inserting the three zero channels 1, 62 and 63 :
- on the one hand to obtain a number of channels equal to a power o~ 2, which is the case because !28 = 27. This enables the so-called Fast Fourier Trans~orm methods of computation, which are particularly advantageous, to be used in TFR ;
.~ . ... . ... .
1~)~379 - on the other hand to obtain the equivalent of the clearance channels by analog techniques which enables the subsequent filtration problems to be simplified.
Accordingly, 128 digital samples of a real signal sampled at a frequency of 128 x 250 1o_~ = 5~2,000 times per second are simultaneously obtained every 250~s at the output o~ the Fourier trans~ormer TFR.
m e serializer PS enables these samples to be brought back into series in the unit interval of 250 ~s. Figure ~ diagram-matically illustrates one embodiment o~ this serializer comprising a delay circuit ~1, an oscillator 32, a counter ~, a decoder 34, AND gates 3000 to ~127 and an OR gate 35.
~ he signal T1 is delayed in the delay circuit 31 so as to compensate (modulo 250 ~s) the delays due to the computations in TRA and ~l~. The signal T4 thus compensated in pha e synchronises the oscillator 32 which supplies a s~gnal at 512,000 Hz. This signal at 512,000 Hz causes the counter to rotate. The phase of this counter is maintained by the signal T4 which resets it to zero so that the backward count always begins with the state O at the beginnin~ of the unit interval. The counter 33 counts by 128 and its counts are decoded by the decoder 34 which has 128 outputs O to 127.
i These outputs are connected to the 128 AND-gates 3000 to 3127 whlch are thus opened one after the other during the unit interval of 250~s. m ese gates receive the signals xO to xl27 coming from TFR o~ which the output registers memorize the 128 real words of a unit interval for the duration of the following unit interval . m e OR-circuit collects the outputs of the AND gates and thus delivers the serial digital signal : 17 .
~081379 Xs composed of the serialized signals xO to x127.
It ls known that the Fast Fourier Transform algorithms ultimately give an output vector of which the components form a permutation o~ the natural order. It is Or advantage to bring these components back into the natural order by an adequate mixing of the connections between the outputs Or TFR and the inputs of PS. In the absence of this mixing, however, the signal would be completely incompatible in the sense that the modula-tion, which would remain grouped except for crosstalk about~the 10 carriers of the normalised fre~uency plane, would be completely distributed in the bandwidth. In other words, crosstalk would be complete. Although this is not troublesome,it would be absolu-tely essential to use a strictly homologous apparatus at the receiving end.
m e signal XS enters the commutator TS of which the function will be explained hereina~ter.
The output of the commutator TS is applied to the digital-analog converter DA which converts the digital signal xsinto an analog signal of which the spectrum extends from 0 to 256 ! 20 kHz and, in addition, is repeated every 215 kHz on account of the sampling~ In fact, the energy is low between 0 and 8 kHz and between 248 and 256 kHz because it only corresponds to the crosstalk, as seen earlier on9 the channels 0, 1~ 62 and 6~
bein~ zero. Since it is desired to obtain a signal of which the 25 bandwidth is that of a secondary group, i.e. 240 kHz, the frequencies of the signal issuing from the converter ~ are limited by adequately calculating the output filter thereof in such a way that is only allows through the 8-2~8 kHz band, ~` This facilities the work of the subsequent components, although ,........ .. . . ............... . . . .
:1~131379 it may also be carried out in them. An analog signal, named base-band is thus obtained.
In order to obtain the desired ~requency signal, it is now necessary to convert this base-band signal. This conversion is carried out in the modulator BLU which is an ordinary single sideband modulator and by which it is possible, for example by sub~ecting a carrier at 304 kHz to upper single sideband modulation, to obtain a signal ~.avin~ a spectrum comprised between ~12 and 552 kHz, i.e. occupying as required the bandwidth of a secondary group.
The digital processing at the receiving end imposes a condition of frame synchronisation and a condition of level equality between the transmitter and the receiver.
To this end, a constant signal REF is inserted at regular intervals into the signal XS applied to the converter DA
during one complete unit interval. This signal acts as phase ! reference and level reference ~or the receiver. For example, thls signal may be inserted every 8 seconds, in which case it is quite inaudible. It would also be possible to transmit two ~0 signals, one acting as phase reference and the other as level reference, The commutator TS shown diagrammatically in Figure 1, but produced ~or example with transistors, enables the input of the converter DA to be connected either to the output o~ the serializer PS or to a line to which the signal REF is permanen-tly applied. mis signal has a constant levelJ for example half of the scale of the converter DA.
Thls commutator is activated by a signal coming ~rom the counter S~ which counts ths sign~ls T1 backwards, for example .
~08~379 by ~2,000, which gives a control signal every eight seconds.
SY contains an internal delay circuit enabling the operatlonal interval of TS to be made to coincide with one complete unit interval.
The receiving transmultiplexer shown in Figure 4, comprises a demodulator DBLU, an attenuator AT, an analog-digital conver-ter AD, a synchronizer RY, a parallelizer SP, a Fourier trans_ former RTFR, an analog-real converter TAR and two multiplexers MXl and MX2. The following description is made in accordan¢e with the same conventions as those used by the transmitting transmultiplexer.
mis receiving transmultiplexer receives an analog frequen-cy signal GS transmitted by a transmitter homologous with the receiver. mis signal thus a¢cupies the ~12-552 kHz frequency band, m e demodulator DBLU, which is an ordinary single sideband demodulator, enables this signal to be converted in the 8-248 kHz band. It therefore delivers an analog signal which shall be termed base-band signal.
~0 This base-band signal i.c attenuated in the attenuator AT
of which the function will be described hereinafter and which delivers an attenuated signal AN. "
This slgnal AN is applied to the analog-digital converter AD. me analog-digital converter functions at a ~requen¢y of 512,000 times per seconds and supplies 128 digitalized samples Or the signal AN in series every 250 ~s. This serlal digital signal XS is thus the same as that of the same n~me in the transmitter.
10~37~
In order to ensure this equality of level and to maintain synchronisation, the signal XS and the signal AN are both applied to the synchronizer RY. The synchronizer RY analyses the cons-tant level signal present for 250~h~ every 8 s and delivers a correcting signal S which controls the attenuator AT so as to - obtain a correct level of the signal XS and a synchronization signal Tl homologous with that of the same name in the transmit-ter.
Figure 5 shows one embodiment of the synchronizer RY
comprising three diodes 511, 512 and 513, ~our resistors R1 to R4, a capacitor C, an amplifier 514J an analog subtractor. 515, a comparator 516J an oscillator 517, a digital subtractor 518, three analog summators 519~ 520 and 521J one analog inverter 522J two digital inverters 423 and 528, four analog gates 524 to 15 527 and a sample-and-hold circuit 529.
The signal AN is reotified by the diode 511 and the resis-tor R1. A strictly positive s~gnal AR is thus obtained. The ampli~ier 514 acts as a separator for applying this signal AR
to the dlodes 512 and 513. The diodes are connected head-to-tail and are biased by a constant voltage +REF across the resistors R2 and R~. The value of +REF is substantially equal to the normal positive value of the reference signal contained in the signal AN. m e diode 512 only allows values of AR above +REF
through whilst the diode 513 allows only values of AR below 25 +REF through. The signal at the anode of the diode 513 is thus subtracted from the signal at the cathode o~ the diode 512 in ; the subtractor 515. In shortl this is equivalent to ~ull-wave recti~ying the signal AR about the value of +~EF .
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, . , : .
.
10813~
The common mode at the inputs of the subtractor 515 disappears in this operation and the signal at the output o~ the subtrac-tor is thus permanently positive except for the duration of the reference signal where it is zero and during the transient passages of AN through the value +REF. This signal charges a circuit made of the resistor R4 and the capacitor C. The time constant of this circuit is below the duration o~ the re~erence signal so that when this reference signal is present in the signal AN, the circuit R4-C has time to discharge to zero.
However, this time constant is sufficient for the circuit R~-L
not to discharge during the transient passages o~ the signal AN through the value +REF.
The comparator circuit 516 compares the voltage present in the circuit R4-C with a value which, although very low, is suf~icient to allow fairly switching o~ the circuit 516 when the circuit R4-C is discharged. Under these conditions, the circuit 516 switches after the beginning of the re~erence signal and its output passes from a logic state 1 to a logic state 0. When the re~erence signal disppears, the voltage present ~.n the circuit R~-C increases again almost instantane-ous on account o~ the low output impedance of the subtractor 515 and the circuit 516 itself also reswitches on the ~ield.
The ascending edge of the output slgnal of the circuit 516 thus clearly marks the end of the reference signal and hence the beginning o~ the following unit interval.
This signal, coming from the comparator 516, enables the oscillator 517 to be synchronizedO The oscillator 517 supplies the signal Tl whlch is, for example, a square signal at 8000 Hz ~0813'7~
of which the transitions in the same directions thus have a period of 250 ~.
It is difficult to obtain adequate level precision in particular on account of the threshold of the diodes, to control the attenuator AT by this part of the circuit SY. In addition, the converter AD would be removed from the components subjected to the control.
Accordingly, the value of the digital signal XS is compared with the normal value of the reference signal by subtracting ~rom it this value NREF in the digital subtractor 5~8. The result of this operation is expressed in the form of a digital word comprising in parallel a sign bit SIG and bits MOD repre-senting the absolute value of the deviation The voltages representing the bits Or the signal MOD are then added together in the analog summator 519. A non-linearity is thus introduced although it does not affect the result because the system is pilot-controlled. The result o~ this sum is always positive and the analog inverter 522 is used to make the negative value available as well. The choice between this positive value and thls negative value is made by the sign bit SIG which, according to circumstances, opens one o~ the analog gates 524 and 525 either directly or by way of a signal obtained by inversion of SIG in the digital inverter 528. The outputs of these gates are collected by the analog summator 520 which thus delivers a positive or negative error voltage according to the direction of the deviation between x5 and NREF.
The value of this voltage is only ~orrect during the instants where the reference signal ~s present in xs. These ; instants are ldentified by a state O at the output of the
2~
10813~9 comparator 516. The digital inverter 523 enables an opening signal for the analog gate 526 to be obtained from this zero voltage. The summator 521 then receives the error voltage and delivers the signal S which controls the attenuator AT.
The response of this looped system is fairly rapid so that, at the end of the re~erence signal, it is in equilibrium~
x5 being equal to NREF except for one bit. It is thus possible to obtain the required precision because, in acoordance with standard practive, the converter AD is coded with more bits than necessary so as to avoid the errors o~ truncation in the following apparatus.
When the state o~ the output o~ the circuit 516 changes at the end of the reference signal, this change of state controls the sample-and-hold circuit 529 which memorizes the 15 error voltage and applies it to the analog gate 527 for the eigh seconds preceding the ~ollowing reference signal. This gate is opened by the state 1 which is then present at the output of the circuit 516, whilst the gate 526 is closed by the state O present at the output of the inverter 52:~i. me error 20 signal thus memorized is then applied to the summator 521 which thus still delivers the same signal S as at the end of the reference signal.
The paralleliser SP thus receives in series 128 digitalised samples in 250 ,~s and presents these 128 samples in parallel to 25 the Fourier transformer RTFR every 250,-4s. Figure 6 diagramma_ tically illustrates one embodiment of this paralleliser which comprises an oscillator 62, a counter 6:~i, a decoder 64, gates 6000 to 6127 and memories 7000 to 7127.
"
- ~
.
Th~ signal Tl synchronises the oscillator 62 which delivers a signal at 512,000 Hz, This signal at 512,000 Hz causes the counter 6~ to rotate. m e phase of th~s coun~er is maintained by the signal T1 which resets it to zero so that the backward 5 count always begins with the state 0 at the beginning of the unit interv~l. The counter 63 counts by 128 and its states are decoded by the decoder 64 which comprises 128 outputs 0 to 127. These outputs are connected to the 128 AND gates 6000 to 6127 which are thus opened one after the other during 10 the unit interval o~ 250~4s. These gates all receive the same signals Xs coming from the converter AD. Accordingly, they successively allow through the samples xO to xl27, These samples are memorlzed in the memories 7000 to 7127. At the beginning o~ each unit interval, therefore, these memories 15 contain the 128 samples of the preceding unit interval. These 128 samples xt m thus form a column vector xt of which the t elements are xt 0 to xt 127. By virtue of the decoder 64, it is possible in particular to carry out mixing opposite to that used at the transmitting end in the case where this variant is ~0 used At the beginning of each unit interval, this column vector is transferred to the Fourier transformer ~TFR, i.e. at the beginning of each unit interval the contents of the 128 output memories of SP are transferred to the 128 input registers of 25 RTFR, mis transformer is identical with the transformer TFR
of ~he transmitter except for the ~act that the ~alues o~ the coefflcients W which it contains are those which make it possibl~ to effect the opposite transformation to that carried ~ 081379 out at the transmitting end and thus corresponding to the ope-ration St = [w] -1. xt.
Accordingly, RTFR delivers 128 complex signals St m every 250/~s such that St,m = Ct,k + j dt k for m = 2, .. " 61 t,m et,k j gt,k for m = 128-k = 67,..., 126 In principle, the signals corresponding to k = 0, 1, 62, 63 should be zero such that Ct k = et k and dt,k = gt,k-ln practice, this is not the case due in particular to the truncation of the spectrum at the transmitting end of the quan-tification signal in the analog-digital conversion and rounding-off errors in RTFR, Accordingly, the signals corresponding to k = 0, 1, 62j 6~, which represent the zero channels added at the transmitting end to form the vector ~ , are not used.
A mean value is formed from the imaginary parts of St m ! and St m and from the real parts of these signalsJ which gives :
at k = ~Z~ (Ct,k + et,k) bt k = 21 (dt k ~ gt k) '-~ The ini~ial PCM samples are thus obtained ~y m~ring the ~ollowing calculations :
ft k = at,k + bt,k ft+T k = at,k t,k These calculations are made in the analytical-real converter TAR which is made up of 60 identical circuits enabling the 60 signals Or the 60 non-zero PCM channels transmitted to be obtained.
Figure 7 diagrammatically illustrates one of these circuits which comprises two adders 711 and 712, two subtractors 71 .. ., , . . ~ , -, . , . . ~ .
.
~081379 713 and 714, two multipliers 715 and 716, one delay circuit 717, an inverter 718, two AND gates 719 and 720 and an OR gate 721.
The connections represent the path of the words or synchronisa-tion signals without distin~;uising whether ~he bits are in series or parallel.
mis circuit receives at its input the binary words representing the real parts and imaginary parts of the words St m and St m coming from RTFR. It also receives the synchro-nisation signal Tl which is a square signal with a period of 250~s composed of a positive part with a duration of 125,~s corresponding to a logic state 1, followed by a zero part with a duration of 125rS corresponding to a logic state 0.
The delay circuit 717 delivers from the signal Tl a si~nal T5 which is in phase with the signals St m. This signal T5 1~ activates in particular the calculation circuits 711 to 716 which comprise the internal delays required for their successive operation.
The adder 711 effects the operation Ct k + et k whilst the subtractor 71~ effects the operation dt k ~ (-gt k).
The adder 712 effects the operation (Ct k+ et k) +
(dt k + gt k) whilst the subtractor 714 effects the operation (Ct,k + et,k) ~ (dt,k + gt,k)-The multiplier 715 effects the operation r(Ct k et k) +
(dt k +gt k)~ x 0.5, whilst the multiplier 716 effects the operation [(Ct k + et,k) - (dt,k + gt,k)-l x 5-Accordingly, two successi~res words ft k and ft+T k f the PCM channel n.k are available at the output registers of the multipliers 715 and 716. These regis'cers are designed to retain these words, whilst presenting them to the output connections, until the followlng operation.
. .
' ,; ., 1(~8~379 The gate 719 (an assembly of gates if the bits are in parallel) is opened during the positive part of the signal T5 (i.e. 125~s) and therefore allows the word ft k through during the first half of the u ni t interval 2T.
The inverter 718 inverts the signal T5 and applies the signal T6 thus obtained to the gate 720 which is thus op;-~n during the zero part of the signal T5 (i,e. the following 125~s) and thus allows the word ft+T k through during the second half of the unit interval 2T.
The OR gate 721 collects the output of the AND gates 719 and 720 and thus delivers the successives words ft k of the PCM channel n, k.
Of the 60 outputs of the converter TRA, 30 are connected to the multipl~xer r~1 and the other 30 to the multiplexer MX2.
These multiplexers are synchronised by the signal Tl and enable the two frames PCM1 and PCM2, identical with those applied to the transmitter, to be reconsti~uted by known techniques, One interesting variant Or these apparatus consists in replacing, in the transmitter, the multiplexers DX1 and DX2 by 60 analog-digital converters serving 60 ordinary telephone channels ~nd in replacing, in t~e receiver, the multiplexers MXl and MX2 by 60 digital-analog converters serving 60 ordinary telephone channels.
Digital apparatus capable of performing the function of secondary group modulators and demodulators are obtained in this way. However, the analog signal used is not compatible with the ordinary apparatus, but is able to use the same transmission channels. However, this analog signal will be compatible if the analog-digital converters and digital-analog converters used '~
28 ~ ~
., appl~ the coding law standardised in telephone engineering wi~h that used in the transmultiplexers described above. It is thus possible to construct transmission systems by which it is possible for example to connect a conventional exchange with spatial switching of analog sigrals to an electronic standard with time-division switching of PCM signals. To this end, a transmitter according to the above variant and a receiving transmultiplexer such as described are used in the direction conventional exchange_~ electronic exchange, whereas a tra~s-mitting transmultiplexer such as described above and a rece~vercorresponding to the above variant are used in the opposite direction.
~ igure 8a is z block diagram of a link such as described above between a transmitting transmultiplexer ETMX and a recei-ving transmultiplexer RTMX, in which two groups PCMl and PCM2are transmitted from one secondary group GS.
! As shown in Figure 8b, the roles of the transmitter and the receiver may readiIy be reversed. In this case, the transmultiplexer RTMX will receive a secondary group GS, ~0 comp2t1ble or not, and will transm1t two groups PCM1 .~nd P~2 in line. If the secondary group GS is comFatible, i.e. if it emanates from standard telephone hardwar, which is possible because in the apparatus described the band width is the same and only the meaning of the signals differs, the PCM channels transmitted will not be compatible, i.e. although the signals conform to the PCM standards their meaning will be incoherent ~or a normal PCM decoder on account of crosstalk arising out of the same reasons as those for which the group GS is not compatible. m e transmultiplexer l-iTMX receiving the groups ., . , . . _ . . . . . .
.
, - 1~81379 PCMl and PCM2 will transmit a secondary group GS identical with the initial secondary group except for the quantification noise introduced by the analog-digital conversion.
The following documents have been quoted during the French prosecution:
- Journal FR "Cables et transmissions" volume 28, No. 4 Octobre 1974, article "Maquette de faisabilité d'un transmulti-plexeur numérique" by Roche et al - French patent FR 2 188 920 (T.R.T. ), published on January 18, 1974.
'~`
.
10813~9 comparator 516. The digital inverter 523 enables an opening signal for the analog gate 526 to be obtained from this zero voltage. The summator 521 then receives the error voltage and delivers the signal S which controls the attenuator AT.
The response of this looped system is fairly rapid so that, at the end of the re~erence signal, it is in equilibrium~
x5 being equal to NREF except for one bit. It is thus possible to obtain the required precision because, in acoordance with standard practive, the converter AD is coded with more bits than necessary so as to avoid the errors o~ truncation in the following apparatus.
When the state o~ the output o~ the circuit 516 changes at the end of the reference signal, this change of state controls the sample-and-hold circuit 529 which memorizes the 15 error voltage and applies it to the analog gate 527 for the eigh seconds preceding the ~ollowing reference signal. This gate is opened by the state 1 which is then present at the output of the circuit 516, whilst the gate 526 is closed by the state O present at the output of the inverter 52:~i. me error 20 signal thus memorized is then applied to the summator 521 which thus still delivers the same signal S as at the end of the reference signal.
The paralleliser SP thus receives in series 128 digitalised samples in 250 ,~s and presents these 128 samples in parallel to 25 the Fourier transformer RTFR every 250,-4s. Figure 6 diagramma_ tically illustrates one embodiment of this paralleliser which comprises an oscillator 62, a counter 6:~i, a decoder 64, gates 6000 to 6127 and memories 7000 to 7127.
"
- ~
.
Th~ signal Tl synchronises the oscillator 62 which delivers a signal at 512,000 Hz, This signal at 512,000 Hz causes the counter 6~ to rotate. m e phase of th~s coun~er is maintained by the signal T1 which resets it to zero so that the backward 5 count always begins with the state 0 at the beginning of the unit interv~l. The counter 63 counts by 128 and its states are decoded by the decoder 64 which comprises 128 outputs 0 to 127. These outputs are connected to the 128 AND gates 6000 to 6127 which are thus opened one after the other during 10 the unit interval o~ 250~4s. These gates all receive the same signals Xs coming from the converter AD. Accordingly, they successively allow through the samples xO to xl27, These samples are memorlzed in the memories 7000 to 7127. At the beginning o~ each unit interval, therefore, these memories 15 contain the 128 samples of the preceding unit interval. These 128 samples xt m thus form a column vector xt of which the t elements are xt 0 to xt 127. By virtue of the decoder 64, it is possible in particular to carry out mixing opposite to that used at the transmitting end in the case where this variant is ~0 used At the beginning of each unit interval, this column vector is transferred to the Fourier transformer ~TFR, i.e. at the beginning of each unit interval the contents of the 128 output memories of SP are transferred to the 128 input registers of 25 RTFR, mis transformer is identical with the transformer TFR
of ~he transmitter except for the ~act that the ~alues o~ the coefflcients W which it contains are those which make it possibl~ to effect the opposite transformation to that carried ~ 081379 out at the transmitting end and thus corresponding to the ope-ration St = [w] -1. xt.
Accordingly, RTFR delivers 128 complex signals St m every 250/~s such that St,m = Ct,k + j dt k for m = 2, .. " 61 t,m et,k j gt,k for m = 128-k = 67,..., 126 In principle, the signals corresponding to k = 0, 1, 62, 63 should be zero such that Ct k = et k and dt,k = gt,k-ln practice, this is not the case due in particular to the truncation of the spectrum at the transmitting end of the quan-tification signal in the analog-digital conversion and rounding-off errors in RTFR, Accordingly, the signals corresponding to k = 0, 1, 62j 6~, which represent the zero channels added at the transmitting end to form the vector ~ , are not used.
A mean value is formed from the imaginary parts of St m ! and St m and from the real parts of these signalsJ which gives :
at k = ~Z~ (Ct,k + et,k) bt k = 21 (dt k ~ gt k) '-~ The ini~ial PCM samples are thus obtained ~y m~ring the ~ollowing calculations :
ft k = at,k + bt,k ft+T k = at,k t,k These calculations are made in the analytical-real converter TAR which is made up of 60 identical circuits enabling the 60 signals Or the 60 non-zero PCM channels transmitted to be obtained.
Figure 7 diagrammatically illustrates one of these circuits which comprises two adders 711 and 712, two subtractors 71 .. ., , . . ~ , -, . , . . ~ .
.
~081379 713 and 714, two multipliers 715 and 716, one delay circuit 717, an inverter 718, two AND gates 719 and 720 and an OR gate 721.
The connections represent the path of the words or synchronisa-tion signals without distin~;uising whether ~he bits are in series or parallel.
mis circuit receives at its input the binary words representing the real parts and imaginary parts of the words St m and St m coming from RTFR. It also receives the synchro-nisation signal Tl which is a square signal with a period of 250~s composed of a positive part with a duration of 125,~s corresponding to a logic state 1, followed by a zero part with a duration of 125rS corresponding to a logic state 0.
The delay circuit 717 delivers from the signal Tl a si~nal T5 which is in phase with the signals St m. This signal T5 1~ activates in particular the calculation circuits 711 to 716 which comprise the internal delays required for their successive operation.
The adder 711 effects the operation Ct k + et k whilst the subtractor 71~ effects the operation dt k ~ (-gt k).
The adder 712 effects the operation (Ct k+ et k) +
(dt k + gt k) whilst the subtractor 714 effects the operation (Ct,k + et,k) ~ (dt,k + gt,k)-The multiplier 715 effects the operation r(Ct k et k) +
(dt k +gt k)~ x 0.5, whilst the multiplier 716 effects the operation [(Ct k + et,k) - (dt,k + gt,k)-l x 5-Accordingly, two successi~res words ft k and ft+T k f the PCM channel n.k are available at the output registers of the multipliers 715 and 716. These regis'cers are designed to retain these words, whilst presenting them to the output connections, until the followlng operation.
. .
' ,; ., 1(~8~379 The gate 719 (an assembly of gates if the bits are in parallel) is opened during the positive part of the signal T5 (i.e. 125~s) and therefore allows the word ft k through during the first half of the u ni t interval 2T.
The inverter 718 inverts the signal T5 and applies the signal T6 thus obtained to the gate 720 which is thus op;-~n during the zero part of the signal T5 (i,e. the following 125~s) and thus allows the word ft+T k through during the second half of the unit interval 2T.
The OR gate 721 collects the output of the AND gates 719 and 720 and thus delivers the successives words ft k of the PCM channel n, k.
Of the 60 outputs of the converter TRA, 30 are connected to the multipl~xer r~1 and the other 30 to the multiplexer MX2.
These multiplexers are synchronised by the signal Tl and enable the two frames PCM1 and PCM2, identical with those applied to the transmitter, to be reconsti~uted by known techniques, One interesting variant Or these apparatus consists in replacing, in the transmitter, the multiplexers DX1 and DX2 by 60 analog-digital converters serving 60 ordinary telephone channels ~nd in replacing, in t~e receiver, the multiplexers MXl and MX2 by 60 digital-analog converters serving 60 ordinary telephone channels.
Digital apparatus capable of performing the function of secondary group modulators and demodulators are obtained in this way. However, the analog signal used is not compatible with the ordinary apparatus, but is able to use the same transmission channels. However, this analog signal will be compatible if the analog-digital converters and digital-analog converters used '~
28 ~ ~
., appl~ the coding law standardised in telephone engineering wi~h that used in the transmultiplexers described above. It is thus possible to construct transmission systems by which it is possible for example to connect a conventional exchange with spatial switching of analog sigrals to an electronic standard with time-division switching of PCM signals. To this end, a transmitter according to the above variant and a receiving transmultiplexer such as described are used in the direction conventional exchange_~ electronic exchange, whereas a tra~s-mitting transmultiplexer such as described above and a rece~vercorresponding to the above variant are used in the opposite direction.
~ igure 8a is z block diagram of a link such as described above between a transmitting transmultiplexer ETMX and a recei-ving transmultiplexer RTMX, in which two groups PCMl and PCM2are transmitted from one secondary group GS.
! As shown in Figure 8b, the roles of the transmitter and the receiver may readiIy be reversed. In this case, the transmultiplexer RTMX will receive a secondary group GS, ~0 comp2t1ble or not, and will transm1t two groups PCM1 .~nd P~2 in line. If the secondary group GS is comFatible, i.e. if it emanates from standard telephone hardwar, which is possible because in the apparatus described the band width is the same and only the meaning of the signals differs, the PCM channels transmitted will not be compatible, i.e. although the signals conform to the PCM standards their meaning will be incoherent ~or a normal PCM decoder on account of crosstalk arising out of the same reasons as those for which the group GS is not compatible. m e transmultiplexer l-iTMX receiving the groups ., . , . . _ . . . . . .
.
, - 1~81379 PCMl and PCM2 will transmit a secondary group GS identical with the initial secondary group except for the quantification noise introduced by the analog-digital conversion.
The following documents have been quoted during the French prosecution:
- Journal FR "Cables et transmissions" volume 28, No. 4 Octobre 1974, article "Maquette de faisabilité d'un transmulti-plexeur numérique" by Roche et al - French patent FR 2 188 920 (T.R.T. ), published on January 18, 1974.
'~`
.
Claims (12)
1. An apparatus for multiplexing a set of n incoming signals arriving respectively on n input telephone channels into an output frequency division multiplex signal going out on an output channel, said apparatus comprising :
means for processing said incoming signals providing every T µs n complex signals St,n= ? [(ft,k + ft+T,k) + j (ft,k - ft+T,k)] and n conjugate complex signals S?,n = ? [(ft,k +
ft+T,K) - j (ft,k - ft+T,k)], and delivering said signals St,n and S?,n;
means for receiving said signals St,n and S?,n,, digitally computing every 2T µs the Fourier Transform of order 2N x 2N
(N?n) of said signals St,n and S?,n, and delivering the result of said computation as 2N real signals in parallel;
means for serializing according to a given order and during an interval fo 2T µs said real signals, delivering a serial digital; and means for converting said serial digital signal into said output division frequency multiplex signal.
means for processing said incoming signals providing every T µs n complex signals St,n= ? [(ft,k + ft+T,k) + j (ft,k - ft+T,k)] and n conjugate complex signals S?,n = ? [(ft,k +
ft+T,K) - j (ft,k - ft+T,k)], and delivering said signals St,n and S?,n;
means for receiving said signals St,n and S?,n,, digitally computing every 2T µs the Fourier Transform of order 2N x 2N
(N?n) of said signals St,n and S?,n, and delivering the result of said computation as 2N real signals in parallel;
means for serializing according to a given order and during an interval fo 2T µs said real signals, delivering a serial digital; and means for converting said serial digital signal into said output division frequency multiplex signal.
2. An apparatus as claimed in claim 1, further compris-ing means for periodically inserting in said serial digital signal a synchronisation signal with a calibrated level, a calibrated duration, and a fixed position in said serial digital signal.
3. An apparatus as claimed in claim 1, wherein said means for computing the Fourier Transform are designed for using a Fast Fourier Transform process, and said given order is a restored natural order; whereby cross-talk in said output channel is minimized.
4. An apparatus as claimed in claim 1, wherein said set of n incoming signals includes at least a sub-set of signals grouped in a PCM frame, said means for providing the signals ft,k comprise at least a PCM demultiplexer.
5. An apparatus as claimed in claim 1, wherein said converting means comprise a digital-analog converter for converting said serial digital signal into a base-band signal; and a signal side-band modulator for modulating said base-band signal and delivering said output signal.
6, An apparatus as claimed in claim 1, wherein, said incoming telephone channels being distinct analog channels, said means for providing the signals ft,k comprise at least one analog-digital converter.
7. An apparatus for demultiplexing an incoming frequency division multiplex signal arriving on an input channel into a set of n output signals going out respectively on n output telephone channels, said apparatus comprising:
means for converting said incoming frequency division multiplex signal into a serial digital signal; said serial digital signal comprising 2N real signal during 2 T µs;
means for parallelizing according to a given order said serial digital signal, delivering said 2N real signals in pa-rallel every 2T µs;
means for receiving said 2 N real signals, digitally computing every 2T µs the Inverse Fourier Transform of order 2N x 2N(N>n) of said 2N real signal in parallel, and delivering n complex signals St,n = Ct,k+j dt,k and n conjugate complex signals S?,n = et,k - j gt,k ; an means for receiving said signals St,n and S?,n, digitally computing every 2T µs n signals ft,k = ? [(Ct,k + et,k) + (dt,k + gt,k )] and n signals ft+T,k = ? [(Ct,k + et,k) - (dt,k+
gt,k )] and delivering successively said n signals ft,k in parallel and then said n signal ft+T,k in parallel; and means for distributing said signals ft,k and ft+T,k onto said output telephone channels.
means for converting said incoming frequency division multiplex signal into a serial digital signal; said serial digital signal comprising 2N real signal during 2 T µs;
means for parallelizing according to a given order said serial digital signal, delivering said 2N real signals in pa-rallel every 2T µs;
means for receiving said 2 N real signals, digitally computing every 2T µs the Inverse Fourier Transform of order 2N x 2N(N>n) of said 2N real signal in parallel, and delivering n complex signals St,n = Ct,k+j dt,k and n conjugate complex signals S?,n = et,k - j gt,k ; an means for receiving said signals St,n and S?,n, digitally computing every 2T µs n signals ft,k = ? [(Ct,k + et,k) + (dt,k + gt,k )] and n signals ft+T,k = ? [(Ct,k + et,k) - (dt,k+
gt,k )] and delivering successively said n signals ft,k in parallel and then said n signal ft+T,k in parallel; and means for distributing said signals ft,k and ft+T,k onto said output telephone channels.
8. An apparatus as claimed in claim 7, wherein said in-coming frequency division multiplex signal includes a synchroni-sation signal of calibrated level and of calibrated duration inserted periodically at a fixed time position; and further comprising regulating means incorporated into said converting means for correcting the level of said incoming frequency division multiplex signal; and means for analysing said calibrated level and said fixed time position, delivering a control signal to said regulating means and a timing signal for synchronizing said apparatus.
9. An apparatus as claimed in claim 7, wherein said means for computing the Inverse Fourier Transform are designed for using a Fast Fourier Transform process, and said given order is a scrambled order used in said Fast Fourier Transform process.
10. An apparatus as claimed in claim 7, wherein said set of n output signals includes at least a sub-set of signals grouped in a PCM frame, said distributing means comprise at least a PCM multiplexer.
11. An apparatus as claimed in claim 7, wherein said converting means comprise:
a single-side-band demodulator for demodulating said incoming frequency multiplex signal, delivering a baseband signal; and an analog-digital converter for converting said base-band signal, providing said serial digital signal.
a single-side-band demodulator for demodulating said incoming frequency multiplex signal, delivering a baseband signal; and an analog-digital converter for converting said base-band signal, providing said serial digital signal.
12. An apparatus as claimed in claim 7, wherein said output telephone channels being distinct analog channels, said output means comprise at least one digital-analog converter.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR7530234A FR2326818A1 (en) | 1975-10-02 | 1975-10-02 | TELEPHONE TRANSMISSION SYSTEM, MULTIPLEXER AND DEMULTIPLEXER FOR THE IMPLEMENTATION OF SUCH A SYSTEM |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1081379A true CA1081379A (en) | 1980-07-08 |
Family
ID=9160755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA262,529A Expired CA1081379A (en) | 1975-10-02 | 1976-10-01 | Telephone transmission system |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4103110A (en) |
| CA (1) | CA1081379A (en) |
| FR (1) | FR2326818A1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4199660A (en) * | 1977-11-07 | 1980-04-22 | Communications Satellite Corporation | FDM/TDM Transmultiplexer |
| FR2428348A1 (en) * | 1978-06-08 | 1980-01-04 | Trt Telecom Radio Electr | DIGITAL REGULATOR OF THE LEVEL OF A FREQUENCY MULTIPLEX SIGNAL |
| US4324000A (en) * | 1980-01-09 | 1982-04-06 | Communications Satellite Corporation | Termination circuit for FDM/TDM processors |
| US4855894A (en) * | 1987-05-25 | 1989-08-08 | Kabushiki Kaisha Kenwood | Frequency converting apparatus |
| US5351234A (en) * | 1990-12-28 | 1994-09-27 | Nynex Corporation | System for integrated distribution of switched voice and television on coaxial cable |
| JP2738385B2 (en) * | 1996-04-15 | 1998-04-08 | 日本電気株式会社 | Variable bandwidth frequency division multiplex communication system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3605019A (en) * | 1969-01-15 | 1971-09-14 | Ibm | Selective fading transformer |
| FR2188920A5 (en) * | 1972-06-15 | 1974-01-18 | Trt Telecom Radio Electr | |
| US3971922A (en) * | 1974-11-29 | 1976-07-27 | Telecommunications Radioelectriques Et Telephoniques T.R.T. | Circuit arrangement for digitally processing a given number of channel signals |
-
1975
- 1975-10-02 FR FR7530234A patent/FR2326818A1/en active Granted
-
1976
- 1976-09-28 US US05/727,540 patent/US4103110A/en not_active Expired - Lifetime
- 1976-10-01 CA CA262,529A patent/CA1081379A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2326818B1 (en) | 1981-04-10 |
| FR2326818A1 (en) | 1977-04-29 |
| US4103110A (en) | 1978-07-25 |
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