CA1081411A - Method for hermetically sealing an electronic circuit package - Google Patents
Method for hermetically sealing an electronic circuit packageInfo
- Publication number
- CA1081411A CA1081411A CA268,609A CA268609A CA1081411A CA 1081411 A CA1081411 A CA 1081411A CA 268609 A CA268609 A CA 268609A CA 1081411 A CA1081411 A CA 1081411A
- Authority
- CA
- Canada
- Prior art keywords
- sealant
- cover
- substrate
- temperature
- chamber
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000007789 sealing Methods 0.000 title abstract description 9
- 239000000565 sealant Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 239000000919 ceramic Substances 0.000 claims abstract description 13
- 230000008439 repair process Effects 0.000 claims abstract description 6
- 238000002844 melting Methods 0.000 claims abstract 3
- 230000008018 melting Effects 0.000 claims abstract 3
- 239000011261 inert gas Substances 0.000 claims description 14
- 239000012812 sealant material Substances 0.000 claims description 14
- 238000001723 curing Methods 0.000 claims description 11
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical group CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 6
- 239000002904 solvent Substances 0.000 claims description 6
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical compound C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 claims description 4
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 229960004643 cupric oxide Drugs 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- MQJKPEGWNLWLTK-UHFFFAOYSA-N Dapsone Chemical compound C1=CC(N)=CC=C1S(=O)(=O)C1=CC=C(N)C=C1 MQJKPEGWNLWLTK-UHFFFAOYSA-N 0.000 claims description 2
- KRFJLUBVMFXRPN-UHFFFAOYSA-N cuprous oxide Chemical class [O-2].[Cu+].[Cu+] KRFJLUBVMFXRPN-UHFFFAOYSA-N 0.000 claims description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 claims 2
- 208000036366 Sensation of pressure Diseases 0.000 claims 1
- 229910052786 argon Inorganic materials 0.000 claims 1
- 238000004140 cleaning Methods 0.000 claims 1
- 239000001307 helium Substances 0.000 claims 1
- 229910052734 helium Inorganic materials 0.000 claims 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims 1
- 229910052754 neon Inorganic materials 0.000 claims 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 claims 1
- 150000002829 nitrogen Chemical class 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 4
- 239000000155 melt Substances 0.000 description 7
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 4
- 239000000945 filler Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000004064 recycling Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000003431 cross linking reagent Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 230000002311 subsequent effect Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 229940000425 combination drug Drugs 0.000 description 1
- BERDEBHAJNAUOM-UHFFFAOYSA-N copper(I) oxide Inorganic materials [Cu]O[Cu] BERDEBHAJNAUOM-UHFFFAOYSA-N 0.000 description 1
- 229940112669 cuprous oxide Drugs 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/20—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device gaseous at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
METHOD FOR HERMETICALLY SEALING
AN ELECTRONIC CIRCUIT PACKAGE
ABSTRACT OF THE DISCLOSURE
A hermetically sealed electronic circuit package is formed by placing a preformed, uncured sealant between a circuitized ceramic substrate and a ceramic cover. The resultant assembly is placed in an evacuated oven which is preheated to a temperature at least as great as the curing temperature of the sealant. Before the sealant reaches its melting temperature, the oven is backfilled with nitrogen and stabilized at atmospheric pressure. The assembly is maintained in the heated environment for a suf-ficient period of time to substantially cure the sealant.
The resulting assembly may be opened to affect any repairs that may become necessary and then reassembled.
AN ELECTRONIC CIRCUIT PACKAGE
ABSTRACT OF THE DISCLOSURE
A hermetically sealed electronic circuit package is formed by placing a preformed, uncured sealant between a circuitized ceramic substrate and a ceramic cover. The resultant assembly is placed in an evacuated oven which is preheated to a temperature at least as great as the curing temperature of the sealant. Before the sealant reaches its melting temperature, the oven is backfilled with nitrogen and stabilized at atmospheric pressure. The assembly is maintained in the heated environment for a suf-ficient period of time to substantially cure the sealant.
The resulting assembly may be opened to affect any repairs that may become necessary and then reassembled.
Description
BACKGROUND OF THEiINVENTION .
,,, ;. ~. ., Field of the Invention z . - ~ -,, ~ , , . I , This Lnvention is directed to an improved method for packaging electronic circuits, and more particularly, to an improved method for providing a hermetically sealed electronic circuit package.
Prior Axt With the advent of large scale integration (LSI) tech-nology, it is not uncommon to find complicated multi-circuit subsystems contained within a single LSI chip. Fur-ther, it has become increasingly desirable to mount a num-ber of such chips on a single circuitized substrate, there-by forming a small system configuration. To improve the - ~ life and reliability of such a configuration, it is desir-30 able to provide a housing for enclosing the single or multi- -chip configuration on the circuitized substrate.
~ I .
' ~ 108~411 1 The housing or cap must provide a hermetic seal around the chip or chips on the substrate, and desirably the housing is removable to permit access to anyone of the chips that may become faulty to facilitate its repair.
In the prior art it has been conventional to form such a package by mounting chips on a ceramic substrate, provid-ing an inert gas atmosphere around the chips and hermetically sealing a ceramic cap, or the like, over the chips on the substrate. A typical time temperature curve for such a pro-cess is shown in FIG. 1, labeled prior art. The circuit-ized substrate with the chips soldered thereon is capped by a cover with a sealant material placed between the cover and the substrate. Then the entire configuration at ambient temperature is placed in a vacuum. The temperature is initially raised above the melt temperature of the sealant, but below its cure temperature for a specified period of time to enable the surface of the substrate and the bottom of the cover to become properly wetted by the flow of the sealant. Then, the entire configuration is backfilled with an inert gas, such as nitrogen, and the temperature is raised to a point equal to or above the cure temperature of the sealant material, where the assembly is kept for a prescribed period of time until the sealant was effectively cured.
Units made in accordance with this technique have evi-denced a number of problems which have lead to a very low yield for such assemblies, thereby adversely affecting their costs. It was quite often found that pin holes were created in the sealant during the backfilling of the inert gas. Sometimes during the backfilling of 1 the inert gas, because of unequal pressures between the inner part of the package and the outside thereof, a splat-tering of the sealant material occurred, damaging the chips contained within the package. This, of course, substan-tially diminishes the reliability of the units. It has also been found that there is a tendency to have an exces-sive internal flow of the sealant in a manner such that the sealant may be drawn underneath the chip. Then during subsequent temperature recycling of the chip, because of the differing coefficient of expansion between the sealant and the bond of the chip that the bond between the chip and the substrate could be broken.
Other types of seals are made rather than using a flow type material, by brazing or welding techniques to secure the cover to the substrate, but such techniques makes it difficult to remove the cover from the substrate to repair or replace any of the chips on the multichip ceramic sub-strate.
A method related to the method of the present inven-tion is found on page 1924 of the IBM Technical DisclosureBulletin, Vol. 17, No. 7, dated December 1974, in the arti-cle entitled "Thermal Bonding System" by P.W. Schuessler.
OBJECTS AND SUMMARY OF THE INVENTION
It is a principal object of the present invention to provide an improved method for hermetically sealing elec-tronic circuit packages which overcome the disadvantages of the prior art.
A more specific object of the present invention is to provide an improved method for hermetically sealing ~081~11 1 e:Lectronic circuit packages which is both economical and reliable.
Yet another object of the present invention is to provide an improved method for hermetically sealing elec-tronic packages which results in a package that can be disassembled to permit repair to enclosed components of the package.
The foregoing and other objects are accomplished according to one aspect of the invention wherein a cera-mic substrate having a number of LSI chips mounted thereonand a ceramic cover are placed proximate one another with a sealant material placed therebetween, the sealant material being a form of epoxy which can be easily dis-solved, even after it has been cured. The cover and sub-strate with the sealant therebetween are placed in a vacuum-chamber oven. A backfilling with an inert gas, such as nitrogen, is implemented quickly to accomplish a final backfill at an atmospheric pressure before the seal-ant reached its melt temperature. The temperature of this assembly is continually raised up to or above the cure temperature of the sealant, which temperature is maintained for a period of time sufficient to cure the sealant.
The foregoing and other objects~ features and advan-tages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a time/temperature curve representative of a method of the prior art for forming a hermetically -: 108~
1 sealed electronic circuit package.
FIG. 2 is a partial, sectional view of a hermetically sealed electronic circuit package illustrating the prob-lem encountered when using the method of the prior art.
FIG. 3 is a sectional view of an electronic circuit package prior to being hermetically sealed according to the present invention.
FIG. 4 is a time temperature curve illustrative of the method of the present invention for hermetically seal-ing an electronic circuit package.
FIG. 5 is a sectional view of a hermetically sealedelectronic circuit package formed in accordance with the method of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring first to FIG. 1, there is represented a time temperature curve for a method of hermetically sealing an electronic package typical of the prior art. At time zero and at ambient temperature represented by the point 11 on the curve, the to be sealed package was placed in an evacuated oven and the temperature of the package was raised above the melt temperature 13 of the sealant to a temperature 15 which was below the cure temperature repre-sented by the line 17 of FIG. 1. The package was main-tained at the temperature 15 for a prescribed period of time, such as, for example, 40 minutes, to promote wetting of the surface of the substrate and the bottom of the cap to purportedly improve the ultimate seal of the package.
At the end of the period of time and just as the tempera-ture has begun to be raised toward the cure temperature, the oven was backfilled with an inert 1 gas, such as nitrogen, at the time represented by line 19.
Once the temperature of the assembly in the oven reached the cure temperature, it was held there perhaps for a sufficient period of time to effect substantial curing oE the sealant.
One of the difficulties inherent in the foregoing method of the prior art is illustrated in FIG. 2. What has occurred is that the sealant 25 between the substrate 27 and cover 28 has flowed excessively on the surface of the substrate 27 in a manner such that a portion of the sealant 29 is drawn, for example by capillary action, into a position between the bottom of the chip 31 and the top of the substrate 27. After curing and during subse-quent recycling between temperature extremes of the pack-age, because of the different temperature coefficients of the sealant 29, and the solder 33, excessive forces were exerted on the solder 33 between the chip 31 and the sub-strate 27 causing it to break, thereby damaging the cir-cuitry. Also it was found that because the backfilling occurred while the sealant 25 was in a melt state, there could be splattering of the sealant onto the chip sur-face and, in addition, there could be pin holes (not shown) formed in the sealant 25 which would ultimately permi'c a gradual escape of the inext gas enclosed in the package.
Referring next to FIG. 3, there is shown an elec-tronic circuit package assembly according to the present invention prior to being hermetically sealed. A ceramic substrate 41 is suitably circuitized (not shown) on the upper surface thereof and a plurality of chips 43, 45 are bonded on the circuitized surface. Pins 47 are positioned along the edge of the ceramic substrate. A sealant 49 is . ' 1 providcd arousld tllc outer pcriphery of the chips 43, 45 and m~ted with a cover 51 which is placed thereover. The ~reassembled configuration is then placed into a suitable jig or holding device, perhaps with a number of other such t preassembled packages, and is then placed in an evacuated oven. The oven may be preheated to a temperature at or above the cure temperature of the sealant 49, or may be quickly raised to the desired temperature.
The time-temperature curve for the process according 10- to the present invention is shown in FIG. 4. Point 61 is representative of the ambient temperature of the preassem-~led package as it is placed in the oven and evacuated. The temperature of the preassembled pac];age is monitored or cal-culated so that the backfilling with an inert gas indicated by the point 63 on the time axis of FIG. 4 occurs before the temperature of the preassembled package reaches the melt point o~ the sealant, which temperature is represented by the line 65 of FIG. 4. It is imperative that the backfilling with the inert gas be accomplished prior to reaching the melt temperature 65 and that the pressure inside the cover be approximately equalized with the pressure in the chamber prior to the melt point of the sealant being reached. After backfilling with the inert gas, preferably to atmospheric pressure, the temperature of the assembly is continually raised until it reaches or exceeds the cure temperature 67 of the sealant 49. Therefore, the desired time and tempera-ture curve is that represented by curve 69 of FIG. 4. The packaged assembly is then left in the inert gas atmosphere at the curing temperature for a sufficient perioa of time to substantially cure the , . :
1081~11 1 sealant material.
In practicing the present invention, it may be desir-able and perhaps preferable to preform the sealant material o;n the bottom periphery of the cover 51 before mating the cover to the substrate 41, thereby minimizing handling prob-lems, while assuring a better alignment between the cover and substrate. This may be done by die cutting the seal-ant to the desired shape from sheet stock. Then the gasket like sealant is placed on the periphery of the inverted cover and subjected to a temperature above the melt tempera-ture, but below the cure temperature of the sealant, for a short period of time, e.g., 100C. for 10 seconds. The sealant thus flows onto and adheres to the periphery of the cover.
It has been found that an improved bond results if the substrate is cleaned prior to the assembling thereof with the cover and the preformed sealant material for sub-sequent placement in the oven. Any suitable solvents, such as N-methyl-2-pyrrolidone, which will not attack the circuitized substrate may be used for this purpose.
In carrying out the method of the invention, it is preferable that a uniform pressure be applied to the cover during the heating, sealing and curing of the cover to the ceramic substrate. This may be accomplished by placing a suitable weight on the cover when it is placed in the pro-cessing chamber.
Using a process according to the present invention will ideally result in a product as shown in FIG. 5. As can be seen during the heating cycle, the sealant material 49' has flowed slightly on the ceramic substrate 41 and .
- 108~
l up the walls of the cover 51. Also, the cap has settled down toward the substrate, but the relative parameters ar~e chosen such that there still exists a suitable space 71 between the bottom of the cover and the top of the chips 43, 45, so that during subsequent recycling there is no chance of contact being made between the cover and the chips. With the method of the present invention, the interior flow of the sealant 49' is suitably restricted so that it does not contact the solder bonds 73, 75 con-necting the chips 43, 45, respectively, to the substrate 41.
A suitable sealant for use in accordance with the pre-sent invention is an epoxy composition manufactured under the trade name Ablefilm 529, which is manufactured by Ablestik Laboratories. This is basically a 55% epoxy resin, with the balance being a filler such a cupric oxide.
Another suitable sealant material can be formed by combining a cross-linking agent, such as diaminodiphenyl-sulfone, with a basic epoxy, such as Bisphenol A, in com-bination with a filler (cuprous oxide or cupric oxide) and accelerator in accordance with the following propor-tions by weight:
Cross-linking Agent - 4 to 5%
Basic Epoxy - 35 to 50%
Filler - 40 to 55%
Accelerator - .05 to 2%
These materials can be blended together in conjunc-tion with a solvent such as acetone. During the blend-ing operation, the acetone will be volatized off. Alter-natively, the materials can be blended together at ~08~41~
1 an elevated temperature, thereby obviating the need to use a solvent for the blending operation.
In preparing the sealant according to the above formula, it may be desirable to add a flow control agent such as a finely powdered silica in a proportion of 0 to 1.5%. The flow control agent is found to limit the spreading of the sealant 49' during the heating and cur-ing operation.
Both the .~blefilm 529 and the materials made in accordance with the above-described formula are found to be readily soluble even after they have been cured. For example, N-methyl-2-pyrrolidone has been found to readily dissolve these sealants after curing, thereby providing a seal which can be subsequently removed if it is desired to repair or replace a damaged chip on the ceramic sub-strate. The N-methyl-2-pyrrolidone does not adversely affect the circuitization on the substrate or the chips.
It is, therefore, readily apparent that applicant has provided an improved method for fabricating hermetically sealed electronic circuit packages having many advantages over techniques of the prior art. Using the applicant's method, it is also noted that the time for assembling and curing the packages decreases, since the package is immediately taken up to the cure temperature, rather than spending a predetermined time at some intermediate temperature. It is also apparent that the assembly will reach the cure temperature more rapidly by backfilling the ; evacuated chamber at an earlier time, since the heat trans-fer through the inert gas is much more rapid than the radiation transfer that occurs in an evacuated chamber.
10~3~4~L1 1 While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.
What is claimed is:
, ~, :
,,, ;. ~. ., Field of the Invention z . - ~ -,, ~ , , . I , This Lnvention is directed to an improved method for packaging electronic circuits, and more particularly, to an improved method for providing a hermetically sealed electronic circuit package.
Prior Axt With the advent of large scale integration (LSI) tech-nology, it is not uncommon to find complicated multi-circuit subsystems contained within a single LSI chip. Fur-ther, it has become increasingly desirable to mount a num-ber of such chips on a single circuitized substrate, there-by forming a small system configuration. To improve the - ~ life and reliability of such a configuration, it is desir-30 able to provide a housing for enclosing the single or multi- -chip configuration on the circuitized substrate.
~ I .
' ~ 108~411 1 The housing or cap must provide a hermetic seal around the chip or chips on the substrate, and desirably the housing is removable to permit access to anyone of the chips that may become faulty to facilitate its repair.
In the prior art it has been conventional to form such a package by mounting chips on a ceramic substrate, provid-ing an inert gas atmosphere around the chips and hermetically sealing a ceramic cap, or the like, over the chips on the substrate. A typical time temperature curve for such a pro-cess is shown in FIG. 1, labeled prior art. The circuit-ized substrate with the chips soldered thereon is capped by a cover with a sealant material placed between the cover and the substrate. Then the entire configuration at ambient temperature is placed in a vacuum. The temperature is initially raised above the melt temperature of the sealant, but below its cure temperature for a specified period of time to enable the surface of the substrate and the bottom of the cover to become properly wetted by the flow of the sealant. Then, the entire configuration is backfilled with an inert gas, such as nitrogen, and the temperature is raised to a point equal to or above the cure temperature of the sealant material, where the assembly is kept for a prescribed period of time until the sealant was effectively cured.
Units made in accordance with this technique have evi-denced a number of problems which have lead to a very low yield for such assemblies, thereby adversely affecting their costs. It was quite often found that pin holes were created in the sealant during the backfilling of the inert gas. Sometimes during the backfilling of 1 the inert gas, because of unequal pressures between the inner part of the package and the outside thereof, a splat-tering of the sealant material occurred, damaging the chips contained within the package. This, of course, substan-tially diminishes the reliability of the units. It has also been found that there is a tendency to have an exces-sive internal flow of the sealant in a manner such that the sealant may be drawn underneath the chip. Then during subsequent temperature recycling of the chip, because of the differing coefficient of expansion between the sealant and the bond of the chip that the bond between the chip and the substrate could be broken.
Other types of seals are made rather than using a flow type material, by brazing or welding techniques to secure the cover to the substrate, but such techniques makes it difficult to remove the cover from the substrate to repair or replace any of the chips on the multichip ceramic sub-strate.
A method related to the method of the present inven-tion is found on page 1924 of the IBM Technical DisclosureBulletin, Vol. 17, No. 7, dated December 1974, in the arti-cle entitled "Thermal Bonding System" by P.W. Schuessler.
OBJECTS AND SUMMARY OF THE INVENTION
It is a principal object of the present invention to provide an improved method for hermetically sealing elec-tronic circuit packages which overcome the disadvantages of the prior art.
A more specific object of the present invention is to provide an improved method for hermetically sealing ~081~11 1 e:Lectronic circuit packages which is both economical and reliable.
Yet another object of the present invention is to provide an improved method for hermetically sealing elec-tronic packages which results in a package that can be disassembled to permit repair to enclosed components of the package.
The foregoing and other objects are accomplished according to one aspect of the invention wherein a cera-mic substrate having a number of LSI chips mounted thereonand a ceramic cover are placed proximate one another with a sealant material placed therebetween, the sealant material being a form of epoxy which can be easily dis-solved, even after it has been cured. The cover and sub-strate with the sealant therebetween are placed in a vacuum-chamber oven. A backfilling with an inert gas, such as nitrogen, is implemented quickly to accomplish a final backfill at an atmospheric pressure before the seal-ant reached its melt temperature. The temperature of this assembly is continually raised up to or above the cure temperature of the sealant, which temperature is maintained for a period of time sufficient to cure the sealant.
The foregoing and other objects~ features and advan-tages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a time/temperature curve representative of a method of the prior art for forming a hermetically -: 108~
1 sealed electronic circuit package.
FIG. 2 is a partial, sectional view of a hermetically sealed electronic circuit package illustrating the prob-lem encountered when using the method of the prior art.
FIG. 3 is a sectional view of an electronic circuit package prior to being hermetically sealed according to the present invention.
FIG. 4 is a time temperature curve illustrative of the method of the present invention for hermetically seal-ing an electronic circuit package.
FIG. 5 is a sectional view of a hermetically sealedelectronic circuit package formed in accordance with the method of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring first to FIG. 1, there is represented a time temperature curve for a method of hermetically sealing an electronic package typical of the prior art. At time zero and at ambient temperature represented by the point 11 on the curve, the to be sealed package was placed in an evacuated oven and the temperature of the package was raised above the melt temperature 13 of the sealant to a temperature 15 which was below the cure temperature repre-sented by the line 17 of FIG. 1. The package was main-tained at the temperature 15 for a prescribed period of time, such as, for example, 40 minutes, to promote wetting of the surface of the substrate and the bottom of the cap to purportedly improve the ultimate seal of the package.
At the end of the period of time and just as the tempera-ture has begun to be raised toward the cure temperature, the oven was backfilled with an inert 1 gas, such as nitrogen, at the time represented by line 19.
Once the temperature of the assembly in the oven reached the cure temperature, it was held there perhaps for a sufficient period of time to effect substantial curing oE the sealant.
One of the difficulties inherent in the foregoing method of the prior art is illustrated in FIG. 2. What has occurred is that the sealant 25 between the substrate 27 and cover 28 has flowed excessively on the surface of the substrate 27 in a manner such that a portion of the sealant 29 is drawn, for example by capillary action, into a position between the bottom of the chip 31 and the top of the substrate 27. After curing and during subse-quent recycling between temperature extremes of the pack-age, because of the different temperature coefficients of the sealant 29, and the solder 33, excessive forces were exerted on the solder 33 between the chip 31 and the sub-strate 27 causing it to break, thereby damaging the cir-cuitry. Also it was found that because the backfilling occurred while the sealant 25 was in a melt state, there could be splattering of the sealant onto the chip sur-face and, in addition, there could be pin holes (not shown) formed in the sealant 25 which would ultimately permi'c a gradual escape of the inext gas enclosed in the package.
Referring next to FIG. 3, there is shown an elec-tronic circuit package assembly according to the present invention prior to being hermetically sealed. A ceramic substrate 41 is suitably circuitized (not shown) on the upper surface thereof and a plurality of chips 43, 45 are bonded on the circuitized surface. Pins 47 are positioned along the edge of the ceramic substrate. A sealant 49 is . ' 1 providcd arousld tllc outer pcriphery of the chips 43, 45 and m~ted with a cover 51 which is placed thereover. The ~reassembled configuration is then placed into a suitable jig or holding device, perhaps with a number of other such t preassembled packages, and is then placed in an evacuated oven. The oven may be preheated to a temperature at or above the cure temperature of the sealant 49, or may be quickly raised to the desired temperature.
The time-temperature curve for the process according 10- to the present invention is shown in FIG. 4. Point 61 is representative of the ambient temperature of the preassem-~led package as it is placed in the oven and evacuated. The temperature of the preassembled pac];age is monitored or cal-culated so that the backfilling with an inert gas indicated by the point 63 on the time axis of FIG. 4 occurs before the temperature of the preassembled package reaches the melt point o~ the sealant, which temperature is represented by the line 65 of FIG. 4. It is imperative that the backfilling with the inert gas be accomplished prior to reaching the melt temperature 65 and that the pressure inside the cover be approximately equalized with the pressure in the chamber prior to the melt point of the sealant being reached. After backfilling with the inert gas, preferably to atmospheric pressure, the temperature of the assembly is continually raised until it reaches or exceeds the cure temperature 67 of the sealant 49. Therefore, the desired time and tempera-ture curve is that represented by curve 69 of FIG. 4. The packaged assembly is then left in the inert gas atmosphere at the curing temperature for a sufficient perioa of time to substantially cure the , . :
1081~11 1 sealant material.
In practicing the present invention, it may be desir-able and perhaps preferable to preform the sealant material o;n the bottom periphery of the cover 51 before mating the cover to the substrate 41, thereby minimizing handling prob-lems, while assuring a better alignment between the cover and substrate. This may be done by die cutting the seal-ant to the desired shape from sheet stock. Then the gasket like sealant is placed on the periphery of the inverted cover and subjected to a temperature above the melt tempera-ture, but below the cure temperature of the sealant, for a short period of time, e.g., 100C. for 10 seconds. The sealant thus flows onto and adheres to the periphery of the cover.
It has been found that an improved bond results if the substrate is cleaned prior to the assembling thereof with the cover and the preformed sealant material for sub-sequent placement in the oven. Any suitable solvents, such as N-methyl-2-pyrrolidone, which will not attack the circuitized substrate may be used for this purpose.
In carrying out the method of the invention, it is preferable that a uniform pressure be applied to the cover during the heating, sealing and curing of the cover to the ceramic substrate. This may be accomplished by placing a suitable weight on the cover when it is placed in the pro-cessing chamber.
Using a process according to the present invention will ideally result in a product as shown in FIG. 5. As can be seen during the heating cycle, the sealant material 49' has flowed slightly on the ceramic substrate 41 and .
- 108~
l up the walls of the cover 51. Also, the cap has settled down toward the substrate, but the relative parameters ar~e chosen such that there still exists a suitable space 71 between the bottom of the cover and the top of the chips 43, 45, so that during subsequent recycling there is no chance of contact being made between the cover and the chips. With the method of the present invention, the interior flow of the sealant 49' is suitably restricted so that it does not contact the solder bonds 73, 75 con-necting the chips 43, 45, respectively, to the substrate 41.
A suitable sealant for use in accordance with the pre-sent invention is an epoxy composition manufactured under the trade name Ablefilm 529, which is manufactured by Ablestik Laboratories. This is basically a 55% epoxy resin, with the balance being a filler such a cupric oxide.
Another suitable sealant material can be formed by combining a cross-linking agent, such as diaminodiphenyl-sulfone, with a basic epoxy, such as Bisphenol A, in com-bination with a filler (cuprous oxide or cupric oxide) and accelerator in accordance with the following propor-tions by weight:
Cross-linking Agent - 4 to 5%
Basic Epoxy - 35 to 50%
Filler - 40 to 55%
Accelerator - .05 to 2%
These materials can be blended together in conjunc-tion with a solvent such as acetone. During the blend-ing operation, the acetone will be volatized off. Alter-natively, the materials can be blended together at ~08~41~
1 an elevated temperature, thereby obviating the need to use a solvent for the blending operation.
In preparing the sealant according to the above formula, it may be desirable to add a flow control agent such as a finely powdered silica in a proportion of 0 to 1.5%. The flow control agent is found to limit the spreading of the sealant 49' during the heating and cur-ing operation.
Both the .~blefilm 529 and the materials made in accordance with the above-described formula are found to be readily soluble even after they have been cured. For example, N-methyl-2-pyrrolidone has been found to readily dissolve these sealants after curing, thereby providing a seal which can be subsequently removed if it is desired to repair or replace a damaged chip on the ceramic sub-strate. The N-methyl-2-pyrrolidone does not adversely affect the circuitization on the substrate or the chips.
It is, therefore, readily apparent that applicant has provided an improved method for fabricating hermetically sealed electronic circuit packages having many advantages over techniques of the prior art. Using the applicant's method, it is also noted that the time for assembling and curing the packages decreases, since the package is immediately taken up to the cure temperature, rather than spending a predetermined time at some intermediate temperature. It is also apparent that the assembly will reach the cure temperature more rapidly by backfilling the ; evacuated chamber at an earlier time, since the heat trans-fer through the inert gas is much more rapid than the radiation transfer that occurs in an evacuated chamber.
10~3~4~L1 1 While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.
What is claimed is:
, ~, :
Claims (13)
1. A method of fabricating a hermetically sealed elec-tronic circuit package, said package including a circuit-ized substrate, at least one integrated circuit chip mounted on said substrate and a cover adapted to be positioned and sealed over said chip on said substrate, said method com-prising the steps of:
providing a preformed epoxy resin based sealant material between said circuitized substrate and the outer periphery of said cover;
placing the circuitized substrate and the cover with the preformed sealant therebetween is a vacuum chamber pre heated to a temperature at least equal to the curing tempera-ture of said sealant;
evacuating said chamber while continuously raising the temperature of said substrate, cover and sealant toward a temperature at least equal to the cure temperature of said sealant;
backfilling said chamber with an inert gas, and the pressure inside said cover being approximately equalized to the pressure in said chamber, said backfilling being completed prior to the time the temperature of said sealant reaches its melting point; and maintaining said substrate, cover and sealant in said chamber at a temperature at least equal to the cure tempera-ture of said sealant until said sealant is substantially cured.
providing a preformed epoxy resin based sealant material between said circuitized substrate and the outer periphery of said cover;
placing the circuitized substrate and the cover with the preformed sealant therebetween is a vacuum chamber pre heated to a temperature at least equal to the curing tempera-ture of said sealant;
evacuating said chamber while continuously raising the temperature of said substrate, cover and sealant toward a temperature at least equal to the cure temperature of said sealant;
backfilling said chamber with an inert gas, and the pressure inside said cover being approximately equalized to the pressure in said chamber, said backfilling being completed prior to the time the temperature of said sealant reaches its melting point; and maintaining said substrate, cover and sealant in said chamber at a temperature at least equal to the cure tempera-ture of said sealant until said sealant is substantially cured.
2. The method according to claim 1 wherein said sealant is preformed on the periphery of said cover.
3. The method according to claim 1 wherein said sealant is soluble in selected solvents after being cured to there-by permit easy removal of said cover to facilitate repair of said circuitized substrate.
4. The method according to claim 1 wherein said inert gas is chosen from the class of nitrogen, argon, helium and neon.
5. The method according to claim 1 wherein said sub-strate and cover are ceramic, and said sealant material is comprised of approximately 55% epoxy resin.
6. The method according to claim 3 wherein prior to cur-ing said sealant by weight comprises:
4 to 5 percent diaminodiphenylsulfone;
35 to 50 percent Bisphenol A having an average mole-cular weight between 900 and 1400;
40 to 55 percent of an oxide chosen from the class of cuprous oxide and cupric oxide; and .05 to 2 percent of an accelerator.
4 to 5 percent diaminodiphenylsulfone;
35 to 50 percent Bisphenol A having an average mole-cular weight between 900 and 1400;
40 to 55 percent of an oxide chosen from the class of cuprous oxide and cupric oxide; and .05 to 2 percent of an accelerator.
7. The method according to claim 6 wherein said sealant additionally comprises up to 1.5 percent by weight of a flow control agent.
8. The method according to claim 6 wherein said solvent is N-methyl-2-pyrrolidone.
9. The method according to claim 1 wherein a weight is placed on said cover to thereby exert a predetermined pres-sure by the periphery of said cover on said bonding material and substrate.
10. The method according to claim 9 wherein said weight is chosen to provide a pressure between one and one and a half pounds per square inch by the periphery of said cover on said bonding material and said substrate.
11. The method according to claim 1 wherein said chamber is at a temperature at least equal to the curing tempera-ture of said bonding material.
12. The method according to claim 1 wherein said back-filling of said chamber with an inert gas is done to sub-stantially atmospheric pressure.
13. A method of fabricating a hermetically sealed electronic circuit package, said package including a circuitized sub-strate and a cover adapted to be positioned on and sealed to said substrate, said method comprising the steps of:
cleaning said substrate with a solvent;
providing a preformed sealant material between said circuitized substrate and the outer periphery of said cover;
placing the substrate and the cover with the preformed sealant therebetween in an evacuated, vacuum chamber pre-heated at a temperature at least equal to the curing tempera-ture of said sealant;
backfilling said chamber with an inert gas to atmospheric pressure, said backfilling being completed and the pressure inside said cover being approximately equalized to the pressure in said chamber prior to the time the temperature of the sealant reaches its melting point; and maintaining said assembly in said chamber for a suffi-cient period of time to substantially cure said sealant material.
cleaning said substrate with a solvent;
providing a preformed sealant material between said circuitized substrate and the outer periphery of said cover;
placing the substrate and the cover with the preformed sealant therebetween in an evacuated, vacuum chamber pre-heated at a temperature at least equal to the curing tempera-ture of said sealant;
backfilling said chamber with an inert gas to atmospheric pressure, said backfilling being completed and the pressure inside said cover being approximately equalized to the pressure in said chamber prior to the time the temperature of the sealant reaches its melting point; and maintaining said assembly in said chamber for a suffi-cient period of time to substantially cure said sealant material.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US64397875A | 1975-12-24 | 1975-12-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1081411A true CA1081411A (en) | 1980-07-15 |
Family
ID=24582929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA268,609A Expired CA1081411A (en) | 1975-12-24 | 1976-12-23 | Method for hermetically sealing an electronic circuit package |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4159221A (en) |
| CA (1) | CA1081411A (en) |
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| US4349831A (en) * | 1979-09-04 | 1982-09-14 | General Electric Company | Semiconductor device having glass and metal package |
| US4312116A (en) * | 1980-04-14 | 1982-01-26 | International Business Machines Corporation | Method of sealing an electronic module in a cap |
| US4381602A (en) * | 1980-12-29 | 1983-05-03 | Honeywell Information Systems Inc. | Method of mounting an I.C. chip on a substrate |
| US4818812A (en) * | 1983-08-22 | 1989-04-04 | International Business Machines Corporation | Sealant for integrated circuit modules, polyester suitable therefor and preparation of polyester |
| JPS62154868U (en) * | 1985-08-09 | 1987-10-01 | ||
| JPH07120733B2 (en) * | 1985-09-27 | 1995-12-20 | 日本電装株式会社 | Vehicle semiconductor device package structure and manufacturing method thereof |
| US4945524A (en) * | 1987-04-15 | 1990-07-31 | Pioneer Electronic Corporation | Compact optical pickup apparatus for optical disk player |
| JP2633903B2 (en) * | 1988-04-28 | 1997-07-23 | 株式会社日立製作所 | Package manufacturing method |
| US5028984A (en) * | 1988-11-04 | 1991-07-02 | International Business Machines Corporation | Epoxy composition and use thereof |
| US5041396A (en) * | 1989-07-18 | 1991-08-20 | Vlsi Technology, Inc. | Reusable package for holding a semiconductor chip and method for reusing the package |
| US4960634A (en) * | 1990-03-14 | 1990-10-02 | International Business Machines Corporation | Epoxy composition of increased thermal conductivity and use thereof |
| JP2728106B2 (en) * | 1991-09-05 | 1998-03-18 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Cleavable diepoxide for removable device protection in electronic packaging |
| US5309324A (en) * | 1991-11-26 | 1994-05-03 | Herandez Jorge M | Device for interconnecting integrated circuit packages to circuit boards |
| US5268814A (en) * | 1992-05-20 | 1993-12-07 | International Business Machines Corporation | Module packaging |
| US5402006A (en) * | 1992-11-10 | 1995-03-28 | Texas Instruments Incorporated | Semiconductor device with enhanced adhesion between heat spreader and leads and plastic mold compound |
| JP3192507B2 (en) * | 1992-12-18 | 2001-07-30 | 三菱電機株式会社 | Method for manufacturing resin-sealed hollow semiconductor device |
| US5393931A (en) * | 1993-03-04 | 1995-02-28 | Photmetrics, Ltd. | Electrical access to a hermetically sealed chamber using a printed circuit board |
| US5756380A (en) * | 1995-11-02 | 1998-05-26 | Motorola, Inc. | Method for making a moisture resistant semiconductor device having an organic substrate |
| US5932682A (en) | 1995-12-19 | 1999-08-03 | International Business Machines Corporation | Cleavable diepoxide for removable epoxy compositions |
| US20060105494A1 (en) * | 1996-07-23 | 2006-05-18 | Karen Huang | Method and apparatus for cleaning and sealing display packages |
| US5948922A (en) * | 1997-02-20 | 1999-09-07 | Cornell Research Foundation, Inc. | Compounds with substituted cyclic hydrocarbon moieties linked by secondary or tertiary oxycarbonyl containing moiety providing reworkable cured thermosets |
| US6034429A (en) * | 1997-04-18 | 2000-03-07 | Amkor Technology, Inc. | Integrated circuit package |
| US6117705A (en) * | 1997-04-18 | 2000-09-12 | Amkor Technology, Inc. | Method of making integrated circuit package having adhesive bead supporting planar lid above planar substrate |
| US6274927B1 (en) | 1999-06-03 | 2001-08-14 | Amkor Technology, Inc. | Plastic package for an optical integrated circuit device and method of making |
| US6518659B1 (en) | 2000-05-08 | 2003-02-11 | Amkor Technology, Inc. | Stackable package having a cavity and a lid for an electronic device |
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| US6667544B1 (en) | 2000-06-30 | 2003-12-23 | Amkor Technology, Inc. | Stackable package having clips for fastening package and tool for opening clips |
| US6951778B2 (en) * | 2002-10-31 | 2005-10-04 | Hewlett-Packard Development Company, L.P. | Edge-sealed substrates and methods for effecting the same |
| JP4525153B2 (en) * | 2003-06-05 | 2010-08-18 | オムロン株式会社 | Seal structure of terminal and seal material used therefor |
| US6977431B1 (en) | 2003-11-05 | 2005-12-20 | Amkor Technology, Inc. | Stackable semiconductor package and manufacturing method thereof |
| US20070063369A1 (en) * | 2005-09-19 | 2007-03-22 | Bridgestone Firestone North American Tire, Llc | Method of molding a tire |
| US7498646B2 (en) * | 2006-07-19 | 2009-03-03 | Advanced Chip Engineering Technology Inc. | Structure of image sensor module and a method for manufacturing of wafer level package |
| CN101136378B (en) * | 2007-09-10 | 2010-11-10 | 株洲南车时代电气股份有限公司 | Semiconductor device, packaging air tightness detecting method and distribution device |
| US8617927B1 (en) | 2011-11-29 | 2013-12-31 | Hrl Laboratories, Llc | Method of mounting electronic chips |
| US10079160B1 (en) * | 2013-06-21 | 2018-09-18 | Hrl Laboratories, Llc | Surface mount package for semiconductor devices with embedded heat spreaders |
| US9385083B1 (en) | 2015-05-22 | 2016-07-05 | Hrl Laboratories, Llc | Wafer-level die to package and die to die interconnects suspended over integrated heat sinks |
| US10026672B1 (en) | 2015-10-21 | 2018-07-17 | Hrl Laboratories, Llc | Recursive metal embedded chip assembly |
| US10115605B2 (en) * | 2016-07-06 | 2018-10-30 | Rjr Technologies, Inc. | Vacuum assisted sealing processes and systems for increasing air cavity package manufacturing rates |
| CN107805473B (en) * | 2017-11-03 | 2020-11-27 | 烟台德邦科技有限公司 | High-efficiency high-temperature-resistant heat-conducting underfill and preparation method thereof |
| US10950562B1 (en) | 2018-11-30 | 2021-03-16 | Hrl Laboratories, Llc | Impedance-matched through-wafer transition using integrated heat-spreader technology |
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| US2915490A (en) * | 1956-12-10 | 1959-12-01 | Shell Dev | Epoxy resin adhesive compositions, their preparation, and tape containing same |
| US3077639A (en) * | 1959-08-03 | 1963-02-19 | Joseph Waldman & Sons | Sealing means and method of sealing |
| US3341649A (en) * | 1964-01-17 | 1967-09-12 | Signetics Corp | Modular package for semiconductor devices |
| US3383260A (en) * | 1965-04-26 | 1968-05-14 | Mojonnier Inc Albert | Method and apparatus for heat sealing containers |
| US3336257A (en) * | 1965-06-29 | 1967-08-15 | Celanese Coatings Co | High molecular weight thermoplastic resin from the polymerization of diphenols and diepoxides |
| GB1081350A (en) * | 1965-11-10 | 1967-08-31 | Standard Telephones Cables Ltd | Epoxide resin seals |
| US3711939A (en) * | 1970-11-10 | 1973-01-23 | M Stoll | Method and apparatus for sealing |
| US3749601A (en) * | 1971-04-01 | 1973-07-31 | Hughes Aircraft Co | Encapsulated packaged electronic assembly |
| US3943623A (en) * | 1974-08-23 | 1976-03-16 | Nitto Electric Industrial Co., Ltd. | Hollow cavity package electronic unit |
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Also Published As
| Publication number | Publication date |
|---|---|
| US4159221A (en) | 1979-06-26 |
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