CA1091312A - High field capacitor structure employing a carrier trapping region - Google Patents

High field capacitor structure employing a carrier trapping region

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Publication number
CA1091312A
CA1091312A CA299,176A CA299176A CA1091312A CA 1091312 A CA1091312 A CA 1091312A CA 299176 A CA299176 A CA 299176A CA 1091312 A CA1091312 A CA 1091312A
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layer
capacitor structure
high field
recited
field capacitor
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CA299,176A
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French (fr)
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Donelli J. Dimaria
Donald R. Young
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International Business Machines Corp
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International Business Machines Corp
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    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
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    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31683—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors with potential-jump barrier or surface barrier
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS

Abstract

ABSTRACT OF THE DISCLOSURE
A high field capacitor structure includes an insulating layer having a carrier trapping region between two electrodes.
The trapping region improves electric breakdown characteristics of the capacitor structure and is particularly useful in avoiding the low breakdown voltages and high leakage currents normally encountered in structures with asperities, such as SiO2 over poly Si. The trapping region can be formed by chemical vapor deposition (CVD) process, by evaporation or by ion implantation. The trapping region is close to the Si, but far enough away to eliminate the possibility of reverse tunneling from discharging the traps in the absence of an applied voltage.

Description

lQ~

- BACKGROUND OF THE INVENTION
The present invention is generally related to capacitor structures, and more particularly to an improved high field capacitor structure employing a carrier trapping region and having particular application to semiconductor capacitor structures.
Asperities or defects in the silicon surface are generally though to increase insulator leakage current and lead to low voltage breakdowns in metal-oxide-semiconductor (MOS) devices. This has been dramatically shown for thermal oxides grown on top of polycrystalline silicon by D. J.
DiMaria and D. R. Kerr in "Interface Effects and High Conductivity and Oxides Grown From Polycrystalline Silicon", Applied Physics Letters, Volume 27, No. 9, November l, 1975, pp. 505-507. Thermal oxides grown on top of polycrystalline silicon are important for various types of devices based on Si technology, such as the Floating Avalanche - Injection MOS (FAMOS), Rewritable Avalanche Injection Device (RADI), and Charge Coupled Device (CCD). It is believed that these asperities cause locally high fields to occur which in turn lead to localized high dark current densities (via interface limited, Fowler-Nordhiem tunneling) ; and low voltage breakdown.
Asperities on the surface of metallic substrates of thin film capacitors are believed to cause low field break-downs in substantially the same manner as that observed in the case of thermal oxides grown on top of polycrystalline silicon. What is required is a way to reduce the high field points or their effect due to asperities between the substrate and the insulator in a capacitor structure in order to improve the leakage current and breakdown voltage of that structure.

YO977-013 2 ' ~. -l.U'~
~`
~ SU~ARY OF THE INVENTION
-According to the invention, a carrier trapping region or layer is incorporated into the insulator adjacent to the substrate. In the application of the invention to an ~lOS
structure, the trapping region or layer is in the form of electron traps introduced into the SiO2 insulator. The large local current densities due to the asperities readily - -charges up the electron traps at the high field points, -thereby reducing the local fields and current in turn. The trapping region or layer should be as close to the silicon as possible to maximize the effect of the trapped charges i on the local fields but far enough away to eliminate the i'............................................................... .
, possibility of reverse tunneling from discharging the traps .: .
in the absence of an applied voltage.
,:
In the case of an MOS structure in which poly Si is first deposited on single crystal Si and then partially thermally oxidized, three ways of forming the trapping ;;~
region or layer are specifically described. First, a thin thermal SiO2 layer is formed on the poly Si. This thin ' 20 thermal SiO2 layer may be formed by thermally oxidizing the `~ poly Si. Over the thin thermal SiO2 layer, a relatively thick CVD SiO2 layer is deposited. In this structure, the CVD SiO2 layer acts as an electron trapping region.
Second, the electron trapping efficiency of this structure may be substantially improved by depositing a very thin trapping layer over the thermal SiO2 layer before depositing the relatively thick layer of CVD SiO2. A preferred metal for this layer is tungsten, but other atoms, such as aluminum, can also be used. This layer is not :

lUgi~

continuous, but may be thought as many very thin dots as shown by D. R. Young, D. J. DiMaria, and N. A. Bojarcuk in "Electron Trapping Characteristics of W in SiO2", Journal of Applied Physics, August 1977. This structure permits the location of the electron traps to be very precisely defined. Finally, an alternate to the structure which includes the thin layer is a structure where the insulator between the poly Si and the metal electrode is entirely of thermal SiO2. The electron trapping region or layer is formed in this insulator by ion implantation of phosphorus, arsenic or aluminum near the interface between the poly Si and the thermal SiO2.
In the case of thin film capacitors, a typical substrate -may be tantalum or aluminum. Over this substrate, an oxide 15 of the substrate is chemically grown. In the case of a - -tantalum substrate, the insulator would be Ta2O5; whereas in the case of an aluminum substrate, the insulator would be A12O3. As applied to this structure, according to the invention, an electron trapping region or layer is formed closely adjacent to the interface of the substrate and the chemically-grown oxide by ion implantation.
BRIEF DESCRIPTION OF THE DRAWINGS
Other advantages, aspects and uses of the present invention will become clear from the detailed description of the invention, taken in conjunction with the accompanying drawings, in which:
Figure 1 is a cross-sectional representation of a typical MOS structure;
Figure 2 is a cross-sectional representation of a MOS
structure according to one embodiment of the invention;

Figure 3 is a cross-sectional view of a MOS structure ` ~ according to a second embodiment of the invention;
Figure 4 is a cross-sectional view of a MOS structure according to a third embodiment of the invention;
Figure 5 is a graph showing the dark current density measured as a function of the magnitude of the average field for a positive gate bias of Samples A, B and C corresponding to Figures 1, 2 and 3, respectively;
`:
Figure 6 is a graph representing the dark current density 1~ measured as a function of the magnitude of the average field for negative gate bias for the Samples A, B and C;
Figure 7 is a histogram of Sample A of the percentage o dielectric breakdown events as a function of the magnitude of the average field under positive gate bias; and Figure 8 is a histogram of Sample C of the percentage of dielectric breakdown events as a function of the magnitude - of the average field under positive gate bias.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The deposition of polycrystalline silicon on degenerate n single crystal silicon, doping of the polycrystalline, and subsequent thermal oxidation is described, for examplé, in the above-referenced article by D. J. DiMaria and D. R. Kerr.
Figure 1 illustrates this structure in cross-section. The - poly Si is deposited on a single crystal Si substrate and then ~hermally oxidized to produce a sio2 insulator. Over this sio2 insulator is deposited a metallic electrode, typically aluminum. As is illustrated in Figure l, the interface between the poly Si and the thermal sio2 is quite rough and uneven. ~he hiyh points --that is, the points 3Q closest to the metal electrode-- due to these asperities, ., lV~i:31~
.
: -are points of high fields. Although the average current across the interface may be relatively small, the localized high currents, due to the high fields at the localized high points, can cause a local breakdown of the SiO2 insulator at relatively low average fields.
In the MOS structure shown in Figure 2, the thermal SiO2 layer is relatively thin, having a thickness a. This layer may be formed by thermally oxidizing the poly Si. Over : - .
this relatively thin layer of thermal SiO2, a considerably thicker layer of pyrolytic or CVD SiO2 is formed. The thickness of the CVD SiO2 layer is denoted by b. While the thermal SiO2 layer does not have many electron traps, the CVD SiO2 layer exhibits a certain electron trapping efficiency. This electron trapping efficiency is thought to be related to the water content of the CVD SiO2.
A substantial improvement in the structure shown in Figure 2 is achieved by the modification illustrated in Figure 3. Here, a layer of tungsten is first deposited on -the relatively thin thermal SiO2 layer before the thicker CVD SiO2 layer is deposited. This tungsten layer is extremely thin, on the order of about 10l4 atoms/cm2; and as a result, the layer is not continuous. This layer may be considered as consisting of many dots of tungsten. While tungsten has been used in a specific construction of the invention, those skilled in the art will recognize that other atoms could also be used, such as, for example, aluminum.
In order to demonstrate the advantages of the invention, MOS structures, according to Figures l, 2 and 3, were fabricated and designated as Samples A, B and C, respectively, as follows:
,.,i 0~ 3 Samjele A
` Al-thermal SiO2 (450 A)-poly Si (3.5 x 10 3 Q cm n).

Sample B
- Al-CVD sio2 (520 A)-thermal sio2 (70 A)-poly Si .. ..
(3.5 x 10-' Q cm n).

Sample C
Al-CVD SiO2 (520 A)-W (- 1014 atoms/cm2)-thermal SiO2 , (70 A~-poly Si (3.5 x lO 3 Q cm n).
,. -In each of the Samples A, B and C, the circular aluminum gate electrodes had areas of 1.3 x 10 2 cm2 and were approximately 3,000 A in thickness. No post-metalization annealing was performed. All oxide thicknesses were determined by MOS capacitance. The dark current-applied gate voltage characteristics were measured on virgin samples using a constant voltage ramp or by stepping the voltage.
For the constant voltage ramp experiments, ramp rates of 5.1 x 10 2 MV/cm-sec or 9.5 x 10 3 MV/cm-sec were used.
Voltage was ramped in the direction of increasing the magnitude of either positive or negative bias until a current ; 20 level of 8 x 10 7 A/cm2 was reached and then the ramp direction was reversed. The data has been plotted in the graphs of Figures 5 and 6 which have been corrected for the displAcement current ( ~3.5 x 10 9 A/cm2~ due to the time - rate of change of the gate voltage. The initial starting voltage for the ramp experiments was when electronic conduction currents began to dominate over the displacement current. In the voltage step experiments, the magnitude of the average field was increased from O V in 1 MV/cm steps for both gate polarities until the samples suffered ` destructive breakdown. Although there were some detailed differences in the current-voltage characteristics due to -^~ differences in trapped negative charge buildup in the ... .
` structures, the two experimental techniques yielded the same general results.
Figures 5-8 clearly show that a charge trapping layer removes the effect of locally high fields due to asperities at the polycrystalline silicon-thermal silicon dioxide interface. In Figures 5 and 6, the magnitude of the average '~ 10 field (gate voltage magnitude divided by the total oxide thickness of the structure) required for a given current ~`
; measurement in the external circuit is larger when an electron :~ trapping layer is present for either voltage polarity. Note that the structure of Sample C (with the W layer) is better than the structure of Sample B (without the W layer). This is consistent with the experimental observation that the trapping efficiency of the structure with the W layer (Sample C) is greater than the structure with just the CVD
oxide (Sample B). The I-V characteristics for both the structures of Sample B and C, which have a 520 A CVD SiO2 layer, are shifted to much higher average fields than the structure of Sample A. The increased trapping efficiency of the structure with the CVD oxide layer on the thermal oxide layer (Sample B) over ~he structure with just the thermal oxide tSample A) grown on the polycrystalline silicon ~ substrate is though to be related to the water content of : the pyrolytic or CVD oxide. The I-V characteristics of the structures of Samples B and C are in the range of those for ~- MOS structures which have thermal oxides grown from single crystal silicon substrates.

., The sequence of events occurring in the structures of Samples B and C to reduce the effect of asperities is believed to be as follows:
(1) At low-applied gate voltages, localized trapping occurs to rapidly remove the effect of the asperities.
(2) As the field is increased, uniform trapping occurs which shifts the I-V characteristics to higher average fields.

, From the step voltage I-V measurements, localized trapping appeared to occur for the structures of Samples B and C at .
very low current levels (< 7.9 x 10 12 A~cm2) and low-applied fields (< 2 MV/cm) for either polarity. Near this current level, there was a pronounced departure of the I-V
characteristics for the structures of Samples B or C from that of the structure of Sample A. This departure appeared as a ledge (1.5-2 MV/cm wide) where the current increased very slowly up to a level between 7.9 x 10 12 A/cm2 and
3.9 x 10 11 A/cm2. This ledge was wider for the structure ~ of Sample C (with the W layer) than the structure of Sample B
; (without the W layer). After these ledges, uniform trapping appears to be the dominant factor in controlling the I-V
characteristic. The data from Figures 5 and 6 are representative of thls uniform trapping behavior.
The hysterisis in the data represented by Figures 5 and 6 is due to electron trapping. Data similar to Figures 5 and 6 on an MOS structure with a 563 A thermal oxide from a single crystal-degenerate silicon substrate showed less hysterisis for either voltage polarity than that observed for a negative gate polarity on the structure Sample A, as may be seen in Figure 6. The amount of hysterisis for either polarity is greatest for the structure of Sample C, next is i.31;~

the structure of Sample B, and the smallest is for the structure of Sample A. The hysterisis for positive gate bias on the structure of Sample A, as shown in Figure 5, has been reported by D. J. DiMaria and D. R. Kerr in the above-referenced article and elsewhere and is thought to be due to enhanced local trapping in the thermal oxide layer -~ near the high field points due to the large local current densities. In subsequent voltage ramp cycles, all structures showed a memory effect in which negative-charge trapping in the previous cycle pushed the I-V characteristic out to higher average fields at the start of the next cycle. The rapid current increase for positive gate bias on the structure of Sample C is indicative of the beginning of current runaway near destructive breakdown.
If the differences between the I-V data of the structures of Samples B and C, as shown in Figures 5 and 6, are due to i uniform negative-charge trapping in the W layer, one should, in principle, be able to determine the position of this layer -from the voltage shifts between Samples B and C using a techniqiue recently described by D. J. DiMaria in an article entitled "Determination of Insulator Bulk Trapped Charged Densities and Centroids From Photocurrent-Voltage Characteristics of MOS Structures", Journal of Applied Physics, Volume 47, No. 9, September 1976, pages 4073-4077. This photo I-V relationship is:
~ X/L = [1+ ( ¦ ~Vg ¦/L)/ ( ¦ ~Vg ¦/L) ]
where x is the centroid measured from 'he Al-CVD SiO2 interface, L is the total oxide thickness of the structure, and ! ~Vg ¦ and ¦~Vg ¦ are the gate voltages shift magnitudes at a photo current constant current level for positive and negative gate bias, respectively. Using this equation and ' ... .

.31'~
, `., , ; the experimental values of ¦~Vg ¦/L and ¦avg ¦/L from the ;`. data of Figures 5 and 6, the W layer was located at a .` distance of 72 A from the poly Si-thermal SiO2 interface which ` is in excellent agreement with the measured value of 70 A.
Only the data for current levels less than 3 x 10 8 A/cm2 were used in order to avoid the current runaway region on : the structure of Sample C for positive gate bias.
Figure 7 and 8 show the self-healing and the destructive breakdown distributions for positive gate bias (poly-Si : 10 injecting) on the structures of Sample A and C. Both distributions for Sample C in Figure 8 show very few low average field breakdowns which are characteristic of thermally-oxidized polycrystalline silicon surfaces, as shown ~ for Sample A in Figure 7. These histograms in Figure 8 are ; 15 in fact very tightly distributed around an average field of 8.8 MV/cm for such large area capacitors when compared to thermally-oxidized single crystal Si MOS structures.
. The position of the W trapping layer was picked close to the polycrystalline Si-Thermal SiO2 interface to maximize the field reduction between the negative trapped charge and this interface while simultaneously minimizing the possibility of discharge by field-assisted thermal emission or field emission to the CVD oxide conduction band in the field-enhanced region in the CVD oxide layer. However, the W region was chosen far enough away from the polycrystalline Si-thermal SiO2 interface to prevent back tunneling to the poly Si.
Generally, the W region should be greater than about 40-50 O
A. On the other hand, the W region should not be so far away from the polycrystalline Si-thermal SiO2 interface that - 30 the trapped charges have a lessened effect on the fields due to the asperities in the silicon surface. Based on :'' ` lU~131~

practical considerations, the maximum distance of the W region away from the polycrystalline Si-thermal SiO2 interface should not be greater than about 150 A, and preferably on the order of less than 100 A.
While the use of a metal for the trapping layer, such as tungsten, in the structure of Sample C is quite effective, the structure of Sample B demonstrates that other trapping layers can be used to achieve the current reductions and increases in breakdown voltages according to the invention.

- 10 These trapping layers could be formed by ion implantation, evaporation, or chemical vapor deposition. For example, the structure shown in Figure 4 is essentially the same as the structure shown in Figure 1, except that ions have been .
implanted in the thermal SiO2 layer in a region corresponding to the W region in Figure 3. The ions implanted may be phosphorus, arsenic or aluminum. Arsenic has been found to be particularly effective for forming electron traps in the thermal SiO2 layer. The technique of using a trapping layer to increase breakdown voltages could be used in other capacitor structures besides MOS structures. For example, it is known to fabricate thin film capacitors from a tantalum or aluminum substrate by chemically growing an oxide of the substrate as the capacitor insulator. In the case of a tantalum subs~rate, the insulator would be Ta2O5; whereas in the case of an aluminum substrate, the insulator would be A12O3. The substrate and insulator oxide interface has asperities which tend to limit the breakdown field of these thin film capacitors. In this type of structure, an electron trapping region can be formed closely adjacent to the substrate and oxide insulator interface by ion implantation.

Claims (14)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. A high field capacitor structure comprising:
a pair of spaced-apart electrodes; and an insulating layer dispersed between said pair of electrodes, said insulating layer having a carrier trap-ping region therein wherein one of said electrodes is a substrate and the insulating layer is an oxide of the substrate, the interface between the substrate and the oxide having asperities which tend to produce localized high fields, said carrier trapping region being closely adjacent said interface and readily charged to reduce the large localized fields due to the asperities.
2. A high field capacitor structure as recited in claim 1 wherein said structure is a MOS structure comprising a base substrate material of single crystal silicon having deposited thereon a layer of polycrystalline silicon, the layer of polycrystalline silicon being partially thermally oxidized to form a relatively thin thermal oxide layer, a relatively thick layer of CVD SiO2 deposited over the thin thermal oxide layer, and a metallic electrode deposited over the CVD SiO2 layer.
3. A high field capacitor structure as recited in Claim 2 wherein the thickness of the thin thermal oxide layer is sufficiently large to substantially eliminate the possi-bility of reverse tunneling from discharging the traps in the absence of an applied voltage.
4. A high field capacitor structure as recited in Claim 2 wherein the thickness of the relatively thin thermal oxide layer is greater than 4OA.
5. A high field capacitor structure as recited in claim 4 further including a very thin metallic layer between the relatively thin layer of thermal oxide and the CVD SiO2 layer.
6. A high field capacitor structure as recited in claim 5 wherein said metallic layer is tungsten of about 1014 atoms/cm2.
7. A high field capacitor structure as recited in claim 5 wherein the thickness of the thin thermal oxide layer is sufficiently large to substantially eliminate the possibility of reverse tunneling from discharging the traps in the absence of an applied voltage.
8. A high field capacitor structure as recited in claim 5 wherein the thickness of the relatively thin thermal oxide layer is greater than 40 ?.
9. A high field capacitor structure as recited in Claim 1 wherein said carrier trapping region is formed in said oxide by ion implantation.
10. A high field capacitor structure as recited in claim 9 having a MOS structure comprising a base substrate of single crystal silicon on which is deposited a layer of polycrystalline silicon, the layer of polycrystalline silicon being partially thermally oxidized to form the oxide insulator of the capacitor structure, and a metallic electrode deposited over the oxide insulator, the carrier trapping region being formed by ion implantation in a region closely adjacent to said interface.
11. A high field capacitor structure as recited in claim 10 wherein the ions implanted in the carrier trap-ping region are selected from the group consisting of phosphorus, arsenic and aluminum.
12. A high field capacitor structure as recited in claim 11 wherein the ions implanted in the carrier trapping region are arsenic.
13. A high field capacitor structure as recited in claim 9 wherein said capacitor structure is a thin film capacitor formed by chemically growing an oxide on a met allic substrate.
14. A high field capacitor structure as recited in claim 13 wherein said metallic substrate is selected from the group consisting of tantalum and aluminum, and the oxide grown on the substrate is selected from the group consisting of Ta205 and A1203, respectively, said carrier trapping region being formed by ion implantation in said oxide.
CA299,176A 1977-06-21 1978-03-17 High field capacitor structure employing a carrier trapping region Expired CA1091312A (en)

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Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4535349A (en) * 1981-12-31 1985-08-13 International Business Machines Corporation Non-volatile memory cell using a crystalline storage element with capacitively coupled sensing
US4861976A (en) * 1988-06-06 1989-08-29 American Telephone And Telegraph Company, At&T Bell Laboratories Optical or opto-electronic device having a trapping layer in contact with a semiconductive layer
JP2722873B2 (en) * 1991-07-29 1998-03-09 日本電気株式会社 Semiconductor device and manufacturing method thereof
KR100335778B1 (en) 1999-04-08 2002-05-09 박종섭 Semiconductor device and a method of manufacturing thereof
KR100347547B1 (en) 1999-07-30 2002-08-07 주식회사 하이닉스반도체 Method of manufacturing a capacitor in a semiconductor device
US6596617B1 (en) * 2000-06-22 2003-07-22 Progressant Technologies, Inc. CMOS compatible process for making a tunable negative differential resistance (NDR) device
US6754104B2 (en) 2000-06-22 2004-06-22 Progressant Technologies, Inc. Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET
US6724655B2 (en) * 2000-06-22 2004-04-20 Progressant Technologies, Inc. Memory cell using negative differential resistance field effect transistors
US6594193B2 (en) 2000-06-22 2003-07-15 Progressent Technologies, Inc. Charge pump for negative differential resistance transistor
US6559470B2 (en) 2000-06-22 2003-05-06 Progressed Technologies, Inc. Negative differential resistance field effect transistor (NDR-FET) and circuits using the same
US6512274B1 (en) * 2000-06-22 2003-01-28 Progressant Technologies, Inc. CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same
US6518589B2 (en) 2000-06-22 2003-02-11 Progressant Technologies, Inc. Dual mode FET & logic circuit having negative differential resistance mode
US6479862B1 (en) * 2000-06-22 2002-11-12 Progressant Technologies, Inc. Charge trapping device and method for implementing a transistor having a negative differential resistance mode
US7453083B2 (en) * 2001-12-21 2008-11-18 Synopsys, Inc. Negative differential resistance field effect transistor for implementing a pull up element in a memory cell
US6956262B1 (en) 2001-12-21 2005-10-18 Synopsys Inc. Charge trapping pull up element
US7098472B2 (en) * 2002-06-28 2006-08-29 Progressant Technologies, Inc. Negative differential resistance (NDR) elements and memory device using the same
US6912151B2 (en) * 2002-06-28 2005-06-28 Synopsys, Inc. Negative differential resistance (NDR) based memory device with reduced body effects
US6853035B1 (en) 2002-06-28 2005-02-08 Synopsys, Inc. Negative differential resistance (NDR) memory device with reduced soft error rate
US6847562B2 (en) * 2002-06-28 2005-01-25 Progressant Technologies, Inc. Enhanced read and write methods for negative differential resistance (NDR) based memory device
US6795337B2 (en) * 2002-06-28 2004-09-21 Progressant Technologies, Inc. Negative differential resistance (NDR) elements and memory device using the same
US6567292B1 (en) 2002-06-28 2003-05-20 Progressant Technologies, Inc. Negative differential resistance (NDR) element and memory with reduced soft error rate
US6864104B2 (en) * 2002-06-28 2005-03-08 Progressant Technologies, Inc. Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects
US7095659B2 (en) * 2002-06-28 2006-08-22 Progressant Technologies, Inc. Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device
US6806117B2 (en) * 2002-12-09 2004-10-19 Progressant Technologies, Inc. Methods of testing/stressing a charge trapping device
US6812084B2 (en) * 2002-12-09 2004-11-02 Progressant Technologies, Inc. Adaptive negative differential resistance device
US7012833B2 (en) * 2002-12-09 2006-03-14 Progressant Technologies, Inc. Integrated circuit having negative differential resistance (NDR) devices with varied peak-to-valley ratios (PVRs)
US6980467B2 (en) * 2002-12-09 2005-12-27 Progressant Technologies, Inc. Method of forming a negative differential resistance device
US6979580B2 (en) * 2002-12-09 2005-12-27 Progressant Technologies, Inc. Process for controlling performance characteristics of a negative differential resistance (NDR) device
US6849483B2 (en) * 2002-12-09 2005-02-01 Progressant Technologies, Inc. Charge trapping device and method of forming the same
US7005711B2 (en) * 2002-12-20 2006-02-28 Progressant Technologies, Inc. N-channel pull-up element and logic circuit
US9712128B2 (en) * 2014-02-09 2017-07-18 Sitime Corporation Microelectromechanical resonator
US10676349B1 (en) 2016-08-12 2020-06-09 Sitime Corporation MEMS resonator

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL252101A (en) * 1959-05-30
US4003701A (en) * 1971-02-02 1977-01-18 Scott Paper Company Graft copolymerization processes
JPS4840816A (en) * 1971-09-23 1973-06-15
US4004159A (en) * 1973-05-18 1977-01-18 Sanyo Electric Co., Ltd. Electrically reprogrammable nonvolatile floating gate semi-conductor memory device and method of operation
JPS5532040B2 (en) * 1973-08-09 1980-08-22
US3972059A (en) * 1973-12-28 1976-07-27 International Business Machines Corporation Dielectric diode, fabrication thereof, and charge store memory therewith
DE2446088A1 (en) * 1974-09-26 1976-04-01 Siemens Ag STATIC MEMORY ELEMENT AND METHOD OF ITS MANUFACTURING
US4047974A (en) * 1975-12-30 1977-09-13 Hughes Aircraft Company Process for fabricating non-volatile field effect semiconductor memory structure utilizing implanted ions to induce trapping states

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BR7803753A (en) 1979-03-20
DE2805170A1 (en) 1979-01-04
DE2805170C2 (en) 1987-09-24
ES467327A1 (en) 1978-11-01
US4143393A (en) 1979-03-06
NL7806558A (en) 1978-12-27
SE7803097L (en) 1978-12-22
IT1109956B (en) 1985-12-23
AU3469478A (en) 1979-10-11
AU517008B2 (en) 1981-07-02
JPS5849032B2 (en) 1983-11-01
GB1587022A (en) 1981-03-25
SE437744B (en) 1985-03-11
IT7821206A0 (en) 1978-03-15
BE864116A (en) 1978-06-16
JPS548484A (en) 1979-01-22

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