CA1100643A - Microprocessor architecture with integrated interrupts and cycle steals prioritized channel - Google Patents

Abstract

MICROPROCESSOR ARCHITECTURE WITH INTEGRATED INTERRUPTS AND CYCLE
STEALS PRIORITIZED CHANNEL
Abstract A computing system architecture includes a central processing unit having a channel, arithmetic and logic unit, a plurality of working registers, and control logic; a plurality of local storage registers; a main storage; an executable control store; one or more input/output devices; and a multiplexed cycle steal and interrupt request common poll bus.
The storage and input/output devices communicate with and are controlled by the central processing unit over a looped, or unidirectional bus and control channel including a bus in, a bus out, an address and control bus, and a plurality of control lines. Bus out is operated to address the executable control store and main storage, and to provide data to the input/output devices and the local storage registers. Bus in is shared by the input/output devices and all storage devices and registers for transferring data and control information to the central processing unit. Bus in is also used by main storage to receive data from the input/output devices and from the local storage registers. The address and control bus addresses the input/output devices and the local storage registers, thus enabling overlapping of device or local storage data transfers with the accessing of executable control storage and main storage, and with instruction execution.
The arithmetic and logic unit is time shared for data and input/output processing, register/register and storage/register transfers, shift operations, byte manipulations, and address modification.
Both cycle steal and interrupt requests are received by the central processor on the common poll bus.

Description

l Cross References to Related Applications Unidirectional Looped Busses Microcomputer Architecture., Cana-dian Patent Application No. 288,231, filed October 6, 1977, by George Bohoslaw Marenin and Edward David Finnegan, cornmonly assigned here-with.
4. BACKGROUND OF THE INVENTION
4.1 Field of the Invention This invention relates to digital computer memory systems and other data processing systems.
The invention further relates to a cycle steal and interrupt request channel including a common poll bus, and to a function inte-grated and shared arithmetic and logic unit processor architecture.
4.2 Description of the Prior Art State of the art microprocessor designs and provide three or four basic and separate functional components. First is the ROS (some-times RAM) microinstruction address register with its incrementing, branching and linking hardware. Second is the central arithmetic and logic unit (ALU) with its associated registers and data paths.

Third is the addressing and data interconnection with the main stor-age, that is usually treated as input/output (I/O) unit, and is architecturally combined with other system I/O devices. If the micro-processor is sophisticated enough, it will also include a fourth separate section of registers and data paths, usually defined as a channel, for performing priority nested interrupts switching and optionally, priority multiplexed or burst mode cycle steal control (sometimes referred to as direct memory access, or DMA.) Current microprocessors can be classified into two approaches that divide the above noted functions into a multi-chip set. The first approach allocates different functions to separate chips such as an ALU chip, a control chip~ an address chip, an I/O chip, and ROS/P~AM (sometimes with address control) storage chip. The second approach distributes processor functions through a number of identi-cal chips: this approach 1 is known as the "bit slice technique," and usually requires separa~e I/O

2 control chips.

3 Either approach requires extensive chip interconnection, which is ~ limited by the available IIO pins and, consequently results in duplication of logic, and also delays through the required off-chip drivers and 6 receivers. If the data or address busses are bidirectional, no signals 7 may be sent or received until an all off and then an all on control 8 state is established between each chip's drivers and receivers; ~his 9 causes additional delays. Also, each of these bidirectional busses require I/0 ~ins and of~ chip drivers, resulting in a larger chip layout 11 and, even worse, a higher chip power dissipation. To overcome this 12 drawback, some architectures combine the address and data busses into 13 one time multiple~ed "Unibus", compounding further the controls and 14 handshaking delays.
Consequently, a microprocessor archltecture which minimizes the 16 number of drivers and receivers and which can be packaged on a single 17 chip having about 68 pin connections is needed to optimize cost and 18 performance.
19 In existing computer technology, channels with up to 8 nested interrupt levels and 8 cycle steal priority levels with associated data 21 paths, registers and buffers are extremely complex, and generally separated 22 from the central processor on a separate chip. This is because they 23 generally require 600 to 700 logic gates, which is nearly equivalent in 24 logic hardware to an 8 bit microprocessor.
~5 In accordance with this invention there is provid~d a microcomputer 26 architecture including in the central processor an arith~etic and logic 27 unit which is time shared for data processing, in~ut/output processing, 28 transfers of data between registers, and storage and registers, shift 29 operations, byte manipulations~ and address register modifications.
This invention further provides a mi~rocomputer architecture including SA975072 -3_ ~ _ ~

1 a common ?oll bus and control logic for enabling cycle steals and interrupt 2 requests.
3 This invention further provides a plurality of stacks of woxking

4 operand registers, each stack selectable by the executing interrupt level9 and with absolute stack addressing by selecting the page equivalent 6 to interrupt level.
7 In accordance with another aspect of this invention, there is 8 provided, in connection with an unidirectional looped bus, address 9 register means for addFessing storage. During a portion of an e~ecution cycle, the arithmetic and logic unit modifies the contents of the address 11 register, the results being returned to the address register and also 12 loaded onto the bus out for addressing storage. The invention further 13 provides local storage register means for storing the storage address 14 loaded on the bus out for use as a return pointer from an interrupt.

The invention still further provides, for use in a direct memory 16 accessing (or cycle stealing) operation, local storage register means 17 for storing indirect main storage addresses. The indirect starage 18 address is automatically incremented, unless inhibited by the controlling 19 I/0 device, through the arithmetic and logic unit on the way to the output bus as a temporary pointer to write into main storage the data 21 from the input/output means on bus in, or, as a temporary pointer to 22 access main storage data for loading onto the input bus, and thence 23 through the arithmetic and logic unit to the output bus for receipt by 2~ an input/output device.
In accordance with another aspect of the invention, particularly 26 for use when the microprocessor of the invention is used for emulating a 27 different computing apparatus, operand register means are piovided for 2~ storing the opera~ion code of the instruction being emulated. The 29 arithmetic and logic unit is operated to add the operation code being 3~ emulated to the contents of the instruction address register meclns, the ... .
~ SA975072 ~-. . , r~

-6~3 l result being placed on the output bus as a displacement pointer to a 2 table in the executable storage means9 which table provides an immediate 3 pointer tu the microinstruction routine in the execu~able storage means 4 ~or executing the operation code being emulated.
In accordance with a further aspect of the invention, a common 6 lnterrupt and cycle steals polling bus means is provided. Control 7 means, responsive to a request for an allowed interrupt, is provided for 8 causing the change of microinstruction address pointers: the current 9 instruction address being transferred from the address register means into the local storage register location pertaining to the current ll interrupt level, and the instruction address pertaining to the new l~ interrupt level being transferred into the address register means from 13 the local storage register accessed by the new interrupt level code.
l~ In accordance with yet another aspect of the invention, means are provided for detecting a cycle steal request on said common poll bus.
16 After the poll bus has been cleared of interrupt requests, the cycle 17 steal priority is obtained from the common poll bus, and used to address 18 the corresponding local storage register for loading into the address l9 register means the indirect main storage address. The indirect main storage address may be incremented to either store or fetch data from 21 the input/output device under control of the microprocessor, without 22 requiring timing or address information from the input/output device.
23 Brie~ Description of the Drawings 24 Figure l illustrates the manner in which Figures la, lb, and lc are related, Fi~ures la, lb, and lc show a logic diagram of the microcomputer 26 architecture of the invention.
~7 Figures 2a, 2b, 3a, 3b, 3c, 4a, 4b, and 4c are timing diagrams 28 illustrating the execution of a basic instruction set adaptable to the 29 microcomputing system architecture of the invention. Figures 2, 3, and 3~ 4 illustrate the relatlonship between these timing diagram~.

i43 1 Figure 5 is a more detailed logic diagram illustrating the integrated . 2 cycle steal and interrupt prioritized channel.
3 Description of the Preferred Embodiments 4 Referring now to the drawings, particularly FIG. 1, the architecture

5 of the computing system of the invention will be described. The four

6 major physical units of the system shown in FIG. 1 are the following:

7 1. Central processing unit (CPU) 9, inclucling the arithmetic and

8 Logical Unlt 22, a channel Cincluding Bus In 10, Bus Out 20, Address g Bus 21, Common Poll Bus 53, and Control Lines 15,) a plurality of working registers, and control logic.
11 2. Local Storage Registers 14.
12 3. Main Storage 12.
13 4. Read Only Storage (ROS) 16~ sometimes referred to as Executable 14 Storage 16 o~ Microprogram Store 16.
CPU 13 may be implemented, for example, as a single LSI chip, -16 mounted in today's technology into a package requiring less than 70 17 module I/O pins. This CPU package may be mounted, in currently available 18 technology, on a card together with one Read Only Store 16 module, one 19 Local Store 14 module (having, say, 32 registers), two modules for support drivers 13, and an oscillator (shown by output line 59.) A
21 small portion of Mai~ Storage 12 may also be mounted on this card.
~2 However, it is expected that, utilizing currently ~vailable circuit 23 technology, Main Storage 12 would be mounted for the most part on a 24 second card.
Data, Instructions, and Input~Output tI/O) commands are transferred 26 between CPU 9 and other units by way of two unidirectional busses, I/O
27 Co D on Bus In 10, and I/O Common Bus Out 20. I/O.Common Bus In 10 28 receives data from the input/output devices (not shown), Main Storage 12 29 over Bus 11, Read Only Storage 16 over Bus 17 and Local Storage Register 14 over Bus 13. Data on Bus 10 is fed to Program Register 30 and directly S~975072 -6-1 to Arithmetic and Logic Unit 22. It is partlcularly important to note ~ that data and information on bus 10 is fed in one direction with respect 3 to CPU chip 9, no drivers being provided for transferring data off of 4 CPU chip 9 along Bus In 10. Main Storage 12, Local Storage Register 14, and Read Only Storage 16 I~ave the drivers providled or sufficient power 6 to place data on IlO Common Buæ 10. In addition, Main seorage 12 has 7 the facility to take data off of bus 10 placed thereon by Local Storage ~ Register 14 or any input/output device over bus 13. Bus Out ~0 presents g the contents of Output Buffer Register 26 to Read Only Storage 16, Main 10 Storage 12, Local 5torage Register 14, and the I/O devices (not shown.) ~ !
11 For Read Only Storage 16 and Main Storage 12, Co~on Bus Out ~0 serves 12 the function of an address bus, while for Local Storage Reg:isters 14 and 13 the I/O devices, Bus Out 20 is used as a data bus. I/O devices are 14 addressed by a set of 6 Local storage Code Out (LCO) lines 21, which, in this embodiment, per~it direct addressing of up to 64 Local Storage 16 Registers 14 or 63 I/O devices. As previously mentioned, Bus In 10 17 brings micro-instructions or data from the Input/Out devices or storage. -18 Source or destination of Bus Out 20 and Bus In 10 transfers are selected L9 by control lines 15, which after being driven by driver 18 appear as control and clock lines 19. These lines include Local Storage Register 21 select, Read Only Storage select, Main Storage select, Write high byte 22 and Write low byte. An I/O device ls selected by the combination of a 23 valid device address and Local Storage Register select not being active.
24 Validation of Bus Out 20 data transfers is timed by preceeding clock one pulses (one of lines 15). Sample Out signals indicate that LCO and 26 select codes are valid. Sample In is a response to Sample Out to validate 27 bus in data transfers to the microprocessor 9 or command responses from 28 the devices. These signals together with Hold Clock In, which allows 29 Input/Output devices to inhibit the CPU clock advance, per~it totally asyncronous I/O operation.

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~ SA975072 -7-43~

1 Following i9 a list of the input/output interface lines 19, 20, 21, 10, and 31, including a brief note as to their function~
Bus Out 20 provides, herein, 18 lines for I/O device and Local Storage Register 14 data out, Main Storage 12 address out, and Read Only Storage 16 address out.
Bus In 10 provides, herein, 18 lines for micro-instruction from Read Only Storage 16, data in from the I/O devices and Local Storage Registers 14, and Main Storage 12 data in and data out. Poll Bus In 53 provides 7 multiplex cycle steal or 7 interrupt level request lines, to be further explained hereinafter. Poll cycle steal out 77 is one of lines 19 and is used for requesting cycle steal poll on Poll Bus In 53, in place oE interrupts, by clearing poll bus in 53 interrupt priorities, and requesting cycle steal priorities. LSR
Code Out tLCO) Line 21 provides, herein, 6 lines for addressing the up to 64 locations ln Local Storage Register 14, Eor signaling the cycle steal level, or for addressing up to 63 input/output devices.
LSR Select Out includes 5 of control and clock lines 19, includ-ing LSR Select, Storage Select, ROS Select, write high byte1 and write low byte. (If no high and low write specified, then a read operation is implied.) Sample Out is one of lines 19 for indicating that a command or LSR Code Out signals are valid which will be the case during clocks 3-4 and 9-14, as will be described more fully hereinafter. Sample In (not shown) includes one common line for a selected device to respond to Sample Out, validating data which it has placed on Bus In 10, or responding to a command.
Any Cycle Steal In line 68 is used by an I/O device on the sig-nal rise to request a cycle steal poll, and on the signal fall to indicate that its priority is valid on Poll Bus In 53.
Any Interrupt In line 70 indicates that one or more devices .'-~LP6~3 1 have an~interrupt pending o~ Poll Bus In 53, with the priorities indicated. 2 on Poll Bus 53. Oscillator In line 59 provides a continuous square wave 3 clock signal.
4 Reset In (not shown) provides a syste~ rese~ and power on reset 5 input~
6 Clock l or 9 Out is one of lines 19 for continuous timing validating 7 previous Output Buffer Register 26 data on Bus Out 20. Clock 6, 7 Out, ~ or Clock 14, 15 Out (for double cycle instructions), is one of lines 19 g providing a continuous timing, which falls to indicate an instruction ending.
ll Inhibit Storage High Byte is originated by the device to write only 12 the low byte in Main Storage 12. Inhibit Storage Low Byte :Ls originated 13 by the dévice to write only the high byte in Main Storage 12. If the 14 device raises both Inhibit Storage High and Low, then a Main Storage read operation is implied.
16 Storage data select allows Main Storage 12 data to appear on Bus In 17 lO. By inhibiting Storage Data Select, a device can provide its data 18 (which may be the Main Storage Address) on Bus In to be written into 19 Local Storage Register (cycle steal address register.) Control LSR Write is originated by the device to chain data tables 21 in Main Storage or to prevent incrementing the Local Storage Register 14 22 address-23 Local Storage Register Code Out lines 21 addresses 0-63, together 24 with LSR Select Line 19, Addresses Local Storage Register 14 locations 0-63. Locations 16-23 are used for lnterrupts, and locations .4-31 for 26 cycle steals. LCO 21 addresses 1-63 without LSR Selec~ Line 19, address 27 I/O devices 1-63, with address Q reser~ed for cha.nnel functions.
28 Referring now to Central Processing Unit 9, I/O Common Bus In 10 is 29 fed to AL~ 22 and Program Register 30. The output of Program Register 30 is fed along lines 33 to AL~ 22 and to instruction decoder 62. The 1 address portion of an instruction stored in the P register is also fed 2 along line 31 to LSR Control Out Register 40 and to Decrement Register 3 33. The output of Decrement Register 38 is fed along line 39 back to P
4 register 30 and Current Condition Reglster 48 and Count Register 50.
The output of Count Register S0 is fed along line 51 to Decrement Register 6 38 and LSR Code Out Register 40. The output of Current Condition Register 7 48 is fed along line 49 to the preserved Condition Code Register 42.
~ The outputs of both Current Condition Register 48 and Count Register 50 g are also fed along line 43 to ALU 22. 'The data flow of CPU 19 includes 16 bit ALU 22 and the following operand registers:
11 Accumulator Register 34, which can be gated along line 35 to either 12 side of ALU 22.
13 Acc~mulator Extension Register 36, which can be gated to either 14 side of ALU 22 along line 37.
Total register 24 is the output buffer for ALU 22 and is loaded by 16 Bus 23. Program Register 30, as previously noted, holds the micro-17 instruction for decoding at Decoder 62 and execution. The contents of 18 Program Register 3~ can also be gated into ALU 22, this alang Bus 33.
19 Microinstruction Address Register 32 may have its contents gated to ALU
22 along ].ine 29 for address modification or branch and link operations.
21 Count Register 50 is used for shift counting and for the indirect addressing 22 of Local Store Register 14. Its contents can be gated to ALU 22 along 23 line 43 for perfor~ance of various operations to be described hereinafter.
24 OUtpllt Buffer 26 holds data presented on Bus Out 28, which after being ~5 driven at drivers 18 appe~rs as I/O Common Bus Out 20. Specific instructions 26 to be described later save the contents of Output Buffer 26 in Local 27 Storage Register 14 position zero which can then ~e inputed to ALU 22 28 along Bus In 10 for various operations. The output of Total Register 24 2~ appears on Bus 25 and is gated under control of instruction decoder 62 to load Microinstruction Address Register 32, Accumulator Register 34, 1 Extension Register 36, Error Reglster 469 Interrupt ~ask Reglster 44, 2 Count Register 50, Current Condition Register 48, and.Output Buffer 3 Register 26. The output of Interrupt Mask Register 44 is fed along 4 lines 45 and 43 to ALU 22 and along line 45 to interrupt gate 52. The output of Error Register 46 ls fed along lines 47 and 43 to ALU 22. In 6 addition, the output of Total Register 24, the four lower bits, may be 7 gated along line 27 to the higher order four bits of Instruc~ion Address 8 Register 32.
~ Multiplexed cycle steal and interrupt requests Common Poll Bus 53 is fed to interrupt gate 52 and priority encoder 54, the latter for 11 cycle steals which have priority over interrupts. The output of interrupt 12 gate 52 is fed along lines 69 to prlority encoder 54. The output of 13 priority encoder 54 is fed along lines 55 to Current Interrupt Level 14 Register 56, to higher level interrupt test circuit 58, and to LSR
Control Out Register 40. The output of higher level interrupt test 16 circuit 58 appears on line 63 as the force higher level interrupt signal.
17 The output of Current Interrupt Level Register 56 is fed along lines 57 18 to higher level Interrupt Test circuit 58 and to LSR Control Out Register 19 40.
Clocking signals on line 59 from a single phase oscillator are fed 21 to four phase generator 60, the output of which is fed along line 61 to 22 clock 66 and auxillary clock 64 the outputs of which are used in connection 23 with instruction decoder 62 to control the operation of CPU 9, including 24 the gating of the buses to the various operand registers and controlling ~5 the time sharing of the various buses and registers.
26 Referring no~7 to Figure 5 a more detailed description will be given 27 Of the cycle steal and interrupt channel of the i~vention. Where possible, ~8 the sa~e reference numbers as for elements in Figure 1 are used. In 29 this figureJ by way of exampleJ a more detailed description is given of the various controls and latches for implementlng the integrated cycle .~ ..

6~3 1 steal and interrupt prioritized channel. As wlll be apparent to those . 2 skilled in the art, similar and more detailed descripeions of the controls 3 could be provided for the remainder of the syste~l architectures set 4 forth in Figure 1. ~owever~ such is not essential to the understanding of the invention which relates more specifically to the architecture, 6 the detailed controls are readily within the ski:Ll of those practicing ~^
7 in the art and can be provided without undue experimentation from the 8 description of the architecture and of the timing diagrams provided. In g Figure 5, Poll Interrupt/Cycle Steal lines 530-536 represent the individual lines in Common Poll Bus 53 of Figure 1, in negative logic. Mask 44 has 11 as it's output~ lines 450-456. Poll Cycle ~teal Only Latch 75 includes 12 as an output Reset line 80. In Interrupt Gate 52, line 450 (pertaining 13 to the zero bit of Mask Register 44) is ANDED with Poll Cycle Steal Only 14 Latch Reset line 80 and the result Nor'd with line 530, representing the zero bit position of Poll Bus 53; the result appears on line 520. In 16 similar Eashion, bits 1-6 of Mask Register 44 on lines 451-456 are oNDED
17' with Poll Cycle Steal Only Latch Reset line 80 and the results Nor'd 18 with bit positions 1-6 of Poll Bus 53 on lines 531-536, with the results 19 on lines 521-526. Line 520 is fed to NOR circuits 86, 94, and 95. Line 521 is fed to NOR circuits 86, 90, and 95. Line 522 is fed to NOR
21 circuit 86 and AND circuit 91. Line 523 is fed to NOR circuits 86 and 22 90- Line 524 is fed to AND circuits 86 and 92. Llne 525 is fed to AND
23 circuit 88 and NOR circuit 90. Line 526 is fed to AND circuit 93~ The 24 output of NOR circuit 86 appears as -4 Priority line 544 and is fed to ~5 AND gates 87, 88, and 921 to Current Interrupt Code 56 (position 4), to 26 Greater Test 58, and to AND gate 82. The output of NOR circuit 95 27 appears on -2 Priority line 542 and is fed to AND.gate 91~ to Current 2~ Interrupt Code circuit 56 (position 2), to Compare Greater Test circuit 29 58, and to AND gate 82. The output of NOR circuit 90 is fed to AND gate 93. In NOR circuit 95, the output of AND gates 87 and 88 are NOR'd with @~ 11 l lines 520 and 521. In NOR circuit 94, the outputs of AND gates 91-93 are NOR'd with line 520, and appear on line 541, which is Eed to Current Interrupt Code Circuit 56 (position l), Compare Greater Test Circuit 58, and to AND gate 82.
Minus Any Cycle Steal Request line 68 is inverted and fed to set Poll Cycle Steal Only latch 75. The set output of Poll Cycle Steal Only latch 75 is fed along lines 77 to set Cycle Steal Acknowledge latch 76. The reset output of Poll Cycle Steal Only latch 75 is fed along line 80 to inhibit the AND gates in Gate 52 and to clegate Switch Interrupt Levels Latch 84, the output oE which appears on lines 79 and is used to control Load New Interrupt Level line 72 and set Current Interrupt Level line 57. Negative Any Interrupt Request line 70 is fed to Cycle Steal Acknowledge latch 76 and inverted to Switch Interrupt Levels latch 84. Positive logic Enable Interrupt line 71 is fed to Switch Interrupt Levels latch 84. Minus Any Cycle Steal Request line 68 is also fed to Cycle Steal Acknowledge latch 76. The set output of Cycle Steal Acknowledge latch 76 appears as Cycle Steal Acknowledge line 55 which is ANDed at 89 with a clock pulse on line 85. Line 78 is fed to AND gate 82 and to the high order input bit lines 834, 835 to force into those lines a predeter-mined code.
Lines 310-314 represent the low order bit positions of the ad-dress portion of Program Register 30, shown as lines 31 in Figure 1. Lines 310-314 are fed through AND gates 83, where each one is individually ~NDed with Set Microinstruction control line 74 to appear as output lines 831-835, respectively, and thence to LSR
Code Out Address Register ~l0.
The outputs of AND gates 82 are dot ORId to lines 831-833, the low order bit positions at the input of LCO Register ~0. In addition, the output lines from AND gates 81 are also dot OR'd to the low order lines 831-833 into LCO register 40. The outputs of Current Interrupt Code Register 56, appearing on lines 561, 562, and 564 are 1 individually ANDed in AND 81 with Set Current Interrupt Level line 73, and also fed to Compare Greater Test circuit 58. Set Current Interrupt Level line 73, which gates the Current Interrupt Code Re-gister 56 contents to the three low order input lines of LCO Regis-ter 40 also forces the high order input lines 834, 835, in a manner similar to that of line 78, except to a different code, 90 as to place on lines 41 at the output of LCO Register 40 an address to a different Local Storage Register 14 location.

Cycle steals have priority over interrupts and Any Cycle Steal Request 68 instantly cancels the normally continuous interrupt poll-ing by setting the Poll Cycle Steal Only latch 7~ requesting all devices to place their cycle steal priorities on Poll Bus 53 lines 530-536 and withdraw their interrupt requests. The disappearance of Any Interrupt Request line 70 signals microprocessor 9 that all devices have removed their interrupt priority bits on Poll Bus 53, and the disappearance of Any Cycle Steal Request 68 together with Poll Cycle Steal Only latch 75, guarantees Cycle Steal Priority 54 output lines 541, 542, 544 are ready to be set into LCO Address Register 40 together with cycle steal modifier bits formed by lines 78 in high order positions 834-835, and signals Cycle Steal Acknowledge 55 to the I/O devices. The cycle steal LSR in LSR 14 being addressed by lines 41 provides the indirect Main Storage address on Bus 13 that also may be incremented through ALU 22 to either fetch or store data from the deivce. The lowest priority cycle steal level requires no priority bit and its forced device Address part will be zero to allow all binary device addresses.
Early in the cycle steal cycle, Poll Cycle Steal Only latch 75 is reset to revert to the continuous interrupt polling or sequen-tial microinstruction execution; or the Poll Cycle Steal latch 75 may be set again, because it must be first reset to allow the devices to set Any Cycle Steal Request 68 again, if sequential burst mode cycle steals are required. Interrupt Mask Register 44 is ~ .
. ~ .

1 always degated when Poll Cycle Steal Only latch 75 is set. Asyn-chronous device cycle steal requests can be controlled by micro-processor clock gating or by latching the poll bus so that the priority circuitry can be stabilized.
Having described the overall architecture of the system of the invention, a more detailed explanation of the characteristics of the various components, their operation and interaction will be given.
Input/Output Unidirectional Bus Organization The internal ALU closed loop connection of the external input and output unidirectional busses provided by this invention allows internal processing and external I/O data modification, interrupt level switching and cycle steal address incrementing funct:ions for sophisticated multiple level interrupts and cycle steals to share the existing ALU and data path with minimum control logic hardware and without any additional buffering registers.
This is accomplished by employing a unidirectional bus that goes in and out of CPU chip 9. Data and address are mixed on the same output bus. I/O Common Bus In 10 is the only data input bus to CPU chip 9. Main Storage 12 attaches to this bus, as does Local Store 14. While conserving the unidirectional function of Bus In 10 with respect to CPU 9, Main Store 12 uses Input Bus 10 for read-ing or writing data, while Output Bus 20 holds the Main Store i2 address.
Input Bus 10 also acts as an external input to one side of Arithmetic Logic Unit (ALU) 22, the output from which is set in temporary hold Total Register 24. Total Register 24 has one common Output Bus 25 that goes to every operand register inside CPU chip

9. Bus 25 is connected to Output Buffer Register 26, and from there comes out from CPU chip 9 to form I/O Common Bus Out 20, which in this example is a two byte bus. Output Bus 20 supplies clata to Local Store Register 14 and also to a number of I/O devices (not shown). On a time shared basis, Bus 20 is also the address i~

6~3 1 bus for Read Only Storage 16 (or whatever writable control store may be attached, in which the instructions to be executed are stored.) Bus 20 is also the address bus for Main Storage 12. The invention thus provides a unidirectional looped busses architecture which is hybrid in nature, containing a mixture of data and address on Bus Out 20 and data and instructions oo Bus In 10.
The absence of a direct processor chip data path to Main Storage12 is solved by optional pro~essor set result images in LSR 14 and the usage of the unidirectional input bus in the reverse direction with respect to Main Storage 12 from LSR 14. Thus, Input Bus l0 is kept unidirectional with respect to processor chip 9 by allowing Output Bus 20 on every internal data modification microinstruction to optionally set the resut in the selected LSR 14 without any addi-tional instruction or time. This innovation a]lows pipelining and concurrent operations on both busses, permitting Bus Out Register 26 to access the next microinstruction out of ROS 16, while the pre-vious microinstruction is being executed with data on Input Bus 10 in overlapped mode. Similarly, Bus Out Register 26 is used to access Main Storage 12 directly and between these two addressing modes, a narrow data window transfers data to LSR 14 or I/O devices addressed by a separate six (6) bit mini address bus 21, which also signals the respective cycle steal acknowledges or switches interrupt levels.
By reserving one of the 64 LSRs as a Bus Out image register, the processor chip internal data flow can be arranged around a common Arithmetic and Logic Unit (ALU), with Total Register 24 feeding all the other internal data and addressing registers and the outside world through Bus Out Register 26, which also remains preserved for program use as a fourth operand in the LSR 14 image buffer. In this manner any outside I/O device may share AI.U 22 with internal process-ing.

The external unidirectional looped busses also permit total pro-cessor chip internal transparency for interrupt :Level switching and direct SA9-75-072 ~16-, ~

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1 memory channel accessing ~cycle stealing) with automatic storage address 2 incrementing through the common ALU and data path.
3 The looped bus architecture of the system permits instruction 4 execution overlapping and pipelining, examples ot whlch will next be described.
6 In the first example, pipelining occurs whenever ROS instructions 7 are on Bus In 10, which is usually at ~he end ancl the beginning of each B microinstruction cycle, when at the same time I/O common Bus Out 20 9 starts sending data to an I/O device. ~
In a second example, an overlapped operation occurs when data is ll coming in on Bus In 10 from I/O devices or from Local Store 14, and is 12 being processed internally through ALU 22. At that time, I/O Bus Out 20 13 contalns the ROS 16 address, so the next sequential instruction is being 14 accessed.
A third example, of overlapping, is when data from execution of a 16 previous instruction is still to be stored in LSR 14, and execution of a 17 new instruction has already commenced. LSR 14 will be loaded during 18 clock 1 of the new instruction cycle while the new instruction execution l9 started at clock 0. The six lines of LSR Code Out (LCO) Register 40 form an al~iliary address bus 21, 41 that is used to address 64 half 21 words of Local Store Register 14, or up to 63 I/O devices on I/O common 22 Bus Out 20, depending on what type of an instruction is being executed.
~3 The combination of this auxiliary mini address bus and the looped In/Out 24 Bus lO, 20 allow operations to be done in one cycle. An I/O device can place data on 3us In 10, have that data processed through ALU 22, and 26 see the arithmetically or logically modified data on Bus 0ut 20 during 27 the same i~struction, while the device is being addressed by Mini Bus 28 21. This is an advantage over prior art channels which require 3 instructions 29 to do even a simple I/O data transfer withou~ an ALU operation, as follows: First, the processor would have to send an address out on one 6~;3 1 common I/O ~us. Then the device would have to respond through a demand/response 7 interface to signal that i~ has recognized its own address. A second 3 instrnction would be needed for the processor to send out a command 4 specification which would be responded to by the device. Having completed S that, the processor would have to then perform a third instruction, read 6 or write depending on which dlrection the data is to flow.
7 The I/O Common Bus Out 20, i5 multiplexed so that for every instruction 8 that is executed, an overIapped operation occurs. Overlapped means that 9 the next instruction from Instruction Store 16 is accessed, while at the same time, the processor is executing internally the current instruction.
11 This is accomplished over the common busses by allowing, say five clock 12 periods of the eight clocks instruction cycle for addressing ROS 16, and 13 the othe~ 3/3 of the instruction cycle for sending data, either to Local L4 Store Register 14 or to the I/O devices.
Main Storage 12 16 Main Storage 1~ provides addressable and updateable memory for 17 storing data by both the microcomputer and the I/O devices for subsequent 18 retrieval. Data is transferred in both the read and write mode over bus 19 11, with respect to l/O Common Bus In 10. Lines 19 provide clocking and controls, and the address is provided by I/O ~ommon Bus Out 20.
21 Whenever access is made to Main Store 12, an additional cycle is 2~ added, to make the instruction a double cycle instruction. As will be 23 described hereinafter7 during the first cycle an increment, decrement, 24 or other address modification is done on the Main Store 12 address pointer obtained from LSR 14 or B Register 35. (This gives the ability 26 of a stacked oyeration even though a stacked pointer is not used, as an ; 27 automatic increment/decrement system for addressing equates to the same 28 power as stacking pointers.) The Main Storage read or write is performed 29 during the second cycle, after the Main Store 12 address pointer has been updated to obtain the effective new address. The address is held .

1 in Output Buffer 26 for the whole second cycle, hereinafter referred to 2 as the main storage memory cycle, providlng 8 clocks to address Main 3 Storage 12.
4 Main Storage 12 is operated in a pipelining mode, as ollows:
During a main storage fetch operatlon, data is obtained from Main 6 Storage 12 on Bus In 10 and loaded into one of the internal registers in 7 Microcomputer 9. At the end of the fetch operation, at clock 0, when 8 the next instruction is about to begin, the data that has been ~etched g on Bus In 10 from the Main Storage 12 'is gated through ALU 22 and set in Total Register 24 and thence transferred to Output Buffer Reglster 26.
ll The setting of that data in Buffer 26 destroys the current Main Storage 12 address.
13 Read Only Storage (ROS) 16 14 Sometimes referred to as executable control store means, ROS 16 stores the executable instructions comprising the microcomputer control 16 program. These instructions are loaded onto Bus In 10, buffered in 17 Program Register 30, and decoded at Instruction Decoder 6~--whichj l~ tcgether with the ti~ing circuits, controls the gates, registers, and 19 operating circuits to execute the various instructions, in a manner explained more fully hereinafter :Ln connection with Figures 2~4.
21 ROS 16 is operated in a pipelining environment. Thus, at clock 0, 22 which is usually the beginning of each microinstruction, the instruction 23 is set into Program Register 30 from Bus In 10. At the same time, clock 24 O, data is set into the Output Buffer Register 26. Thus, data from Executable Storage 16 addressed on Bus Out 20 is taken from Bus In 10, 26 while at the same time the address on Bus Out ~0 is destroyed. Because 27 of the inherent delays in the circuitry (including the drivers and logic 28 stages,) pipelining occurs with these operations taking place, simultaneously.

29 Local Storage Register 14 Local Storage Register (LSR) 14 comprises a plurality of addressable SA975072 -l9-1 and modifiable register locations. Data is wri~ten into LSR 14 Erom Bus Out 20 and read out onto Bus In 10, as addressed by LCO lines 21. Data placed on Bus In 10 may be directed to Main Storage 12 or to CPU Chip 9. Location 0 in LSR 14 is reserved for saving BuE-fer 26 data, under conditions to be described hereinafter.
Arithmetic Logic Unit 22 Arithmetic and Logic Unit (ALU) 22 is shared on a time multi-plexed basis for processing data, microinstruction address increment-ing, displacement branching, subroutine linking, main storage address-ing, address modification, data Eetching or storing, priority nested interrupt processing, and cycle stealing.
This is accomplished by integrating Address Register 32 with the ALU 22 data flow, and by the use of LSR 14. Address Register 32 (a simple non-incrementing polarity-hold register) time shares ALU 22 on alternating half-cycles to increment or otherwise modify the ROS
16 instruction address. Plus or minus displacement branching and linking is facilitated by this single data path into ALU 22. Since ALU 22 outputs to Output Bus 20, micro-addresses may be stored in LSR 14 as return pointers from interrupts. By the same token, since LSRs 14 gate onto Input Bus 10 and through ALU 22 to Address Regis-ter 32, new interrupt routine pointers can be loaded or previously interrupted routine pointers restored, allowing a priority nested and expandable interrupt structure to be included within the basic ALU 22 data flow. One LSR 14 location (location 0) is reserved to save and restore the Output Bus P~egister 26 contents.
Microprocessor 9 fetches data from Main Storage 12 through Input Bus 10 and ALU 22 for storing in its internal operand regis-ters while Output Bus Register 26 holds the Main Storage 12 address from the selected LSR 14 or operand register (such as Extension Register 36) for simultaneous accessing and updating. Microprocessor 9 data to be stored in Main Storage 12 as - ,,;,, `:, 1 the result of execution of a previous microinstruction is first sent to a selected LSR 14 register through Output Bus Register 26.
The write MS microinstruction gates the LSR 14 data onto Input Bus ]0 to enter Main Storage 12.
In addition, certain LSR 14 locations can also act as indirect Main Storage 12 addresses for direct I/O Device cycle steal operations, one LSR 14 register being assigned to each priority level. The I/O
Devices include their own data length counter. The Main Storage 12 address registers in LSRs 14 are automatically incremented through ALU 22 on the way to Bus Out 20, to address Main Storage 12 for writ-ing therein the I/O data on Input Bus 10 for reading out Main Stor-age 12 data, which by way of Input Bus 10 passes through ALU 22 to be made available to the I/O devices on Bus Out 20. The I/O devices receive microprocessor 9 data on Bus Out 20 and send data to micro-processor 9 on Bus In 10.
Shared ALU 22 is used in decoding emulated instructions. The operation code of the instruction being emulated is added by ALU 22 to the current instruction address in Address Register 32 to obtain a displacement pointer to a table in ROS 16 just below the current instruction being executed. In this manner, a 256 way branch is ob-tained to the ROS 16 instructions for executing the emulated instruc-tion.
By sharing of Instruction Address Register 32, interrupt switch-ing is accomplished through the same data path that exists for basic instruction execution. The instruction address value which is in Address Register 32 is stored in Local Storage Register 14 through ALU 22, Total Register 24, Internal Bus 25, Output Buffer 26, and Bus Out 20. Thus, when an interrupt occurs, the pointer to the next instruction that would have been executed on the current program priority level is preserved in LSR 14. Next, the highest level that is to be executed is determined by using the priority code which is developed in Priority Encoder 54 to generate an address at LCO
Register 40. LCO Register 40 addresses the Local Storage Register 14 location that contains the pointer for the ROS

1~ subroutine for that interrupt level. That pointer is read from Local 2 Store Register 14 over I/O common bus 10 and into microcomputer chip 9 3 through ALU 22 to be set in Total Register 24 before being stored in 4 Address Register 32 and Output Buffer Register 26 to address in ROS 16 the subroutine for the interrupt level that is to be executed. When the 6 interrupt has been serv~ced, the current interrupt subroutine pointer is 7 stored in LSR 14, and the address pointer for the interrupted program i9 B fetched therefro~.
g Program Register Program Register 30 is-a buffer for the current instruction and 11 holds the instruction operation (Op) code that is being executed by 12 microcomputer chip 13.
13 The'count or address field of instructions stored of Program Register 14 30 may be gated directly to Decrement Register 38 and ~o LCO Register 16 Total Register (T) 17 Total Register 24 is set with the output of ALU 22 7 and loa~s Bus 18 25, at least twice during each instruction execution cycle--once with 19 the address cf the next instruction to be executed, and once with the ALU results upon execution of the instruction specified function.
~1 As data from Arithmetic Logic Unit 22 is temporarily held in Total 2~ Register 24 and then is buffered in Output Buffer 26, one function can 23 be performed on Bus In 10, while at the same time another function is 24 being finished on Bus Out 20. This two stage buffering in the loop permits overlapped operations and pipelining.
26 Instruction Address Register 27 Instruction Address Register 32 is modified during execution of 28 each instruction by ALU 22 to derive the address in ROS 16 of the next 29 instruction to be executed.

..~., . ~
.,; ~ .

. --Accumulator Register and E~tenslon Reglster 2 The two working registers are Accumulator Register 34 and Extension 3 RPgister 36. Herein, these registers are each 16 bits, giving the 4 capability of 32 bits for instructions that use shifting, such as shift arithmetically, shift logically left or right, shift left and count or 6 rotate left or right.
7 These registers, together with Count Register 50 and Output Register 8 26 are the internal registers, and are directly addressable by the g microinstructions to perform internal arithmetic and loglcal computations.
They can also be modified with one of the external Local Store Registers 11 14, or vice versa3 with the result stored in one of the lnternal reglsters 12 or in Local Store Register 14.
13 Output Bufter Register 14 Output Buffer Register 26 performs a dual function. Being an ALU
22 operand register it holds data that the microprogram directs to it.
16 Also, an interrupt that forces the transfer of address pointers or any 17 Direct Memory Access (DMA) cycle steal accesses, have to allow both the 18 address and the data to flow through Output Buffer register 26. So that 19 Buffer Register 26 does not loose data placed there by the microprogram, Local Storage Register 14 location 0 is reserved as an image for Output 21 Buffer 26 whenever the microcomputer changes instructions addresses and 22 data, whether under interrupt control or during a cycle steal operation.
23 Subsequently, the Buffer 26 value stored in LSR 14 location 0 as an ALU
24 22 operand value can be recalled. In this manner, no back-up is required on ~icrocomputer chip 9 for Buffer Register 26.
26 Power Drivers 27 As Bus 28 leaves chip 9, it flows through po~er drivers 18, the 28 output of which is Bus Out 20. In a Large Scale Integration (LSI) chip, 29 each driver can only drive one load. Therefore, as Bus Out 20 is a common bus going to a number of units (or loads), it has to be repowered.

1 (In doing this repowering, an expansion on the number of channel lines 2 developed is accomplished by coding the exlsting lines for an up or down 3 level during different clocks periods of each mlcroinstruction cycle oE
4 eight clocks.) Decrement Register 6 Decrement Register 38 is used for counting in all shift, multiply, 7 divide instructions and in the decrement, test and branch lnstructions.
8 Decrement Register 38 has inputs from Program Register 30 whenever a 9 shift operation calls for a direct shift of up to 32 positions and stores the decremented value in Program Register 30. In indirect shifts, 11 where Count Register 50 becomes the shift count value, the same decrement 12 by one is used as in direct shifts and Decrement Register 3~ holds the 13 decremented value before it is returned to Count Register 50.
L4 Since the maximum shift operation that is performed in this imple-mentation is 32, a five bit Decrement Register 38 is sufficient. However, 16 for doing field length operation, Count Register 50 is also used as a 17 field length count. For this operation it requires a full 8 bit decrement 18 function. This is accomplished by cycling the 5 bit Decrement Register 19 38 twice, taking a four bits character from Count Register 50 first, decrementing it and storing the carry into the high order 5th position.
21 The stored carry, if there is a carry, together with the high order 4 2~ bit character from Count Register 50 are decremented to form the full 8 ~3 bit decremented value for l~ading back into Count Register 50.
~; 24 LSR Code Out (LCO) Register LSR Code Out (LCO) Register 40 addresses the I/O device or the LSR-26 Register 14 location with respect to which data is to be transferred.
27 Current Condition Re~lster .

28 The upper four bits of Current Condition Register 48 hold the four 29 condition codes, and the lower four bits hold fonr programmable flags;

these bits form the non-connected high byte of Count Register 50. On SA975072 -24~

6~

1 every arithmetlc operation, the four condi~ions codes are set, for 2 subsequent field linked op~rations. The four conditions are binary 3 carry; twos complement overflow; twos complement minus; and the non-zero 4 indicator-which is cumulative. The non-zero indicator, once set in any field length, will remain set until changed by a nicroinstruction.

6 Count Register 7 The secondary ALU operand register is Count Register 50. Additionally, 8 it may serve as a shift counter. The shifting count originally stored 9 in Count Register 50 is decremented for each shit of Accumulator Register 34, or of Extension Register 36, individually, or of both, when connected 11 together for a double precision shift operation. In a shift left and 12 count instruction, as soon as the high order bit is found, shifting is 13 terminated and the value remaining in Count Register 50 indicates how 14 far the shift has progressed. Therefore, in many operations that value becomes an indirect address pointer to ROS 16 or LSR 14. Thus, Count 16 Register 50 can be loaded from internal Bus 25, and can be modified 17 through ALU 22 with the result loaded in LCO Register 40 for addressing 18 Local Storage 14 on Bus 21 or Input/Output devices on Bus Out 20.
19 For indexing address computations and for calculating effective addresses, Count Register 50 is used as a positive or negative displace 21 ment that is co~bined with data by AIU 22. The result is stored in 22 Local Storage Register 14, or in any internal ~egister on chip 9.

~4 ~8 1 Preserved Condition Code and _ 2 Current Condition Code Registers 3 The output of Current Condition Register 48 is selectively buffered 4 in Preserved Condition Code Register 42. The basic condition codes, set as a result of ALU operations, are: overflow, carry-borrow, cumulative 6 not zero, minus. The current condition codes reflect the result of the 7 most recent arithmetic microinstruction execution. All shift-left high-8 order bits shift into the current carry indicator. On shift left and g count, the high-order bit may set the current carry indicator. Loads, stores, moves, logicals, increments, decrements, jumps and branches do ll not change the condition codes. Codes in registers 42 and 48 can be 12 separately cleared, and can be individually tested by Jump instructions.
13 In additlon to these condition codes, there are four program controlled L4 flag bits, which in combination with the current condition codes form lS Condition Register 48. When a microinstruction is being emulated, the }6 correct current microlevel code is transferred to the Preserved Condition 17 Code Register 42 to preserve the microlevel condition code of the language 18 being emulated at the microlevel.
l9 Interrupt Register Interrupt Mask Register 44 contains the current mask status of the 21 interrupt levels allowed. Interrupt Register 44 can also be modified ; 22 through ALU 22, stored away in LSR 14, or restored therefrom.
23 Error Re~ister 24 The low order bits of Mask Register 44 comprise the one byte Error Register 46, which controls and logs errors. Examples of ~achine check 26 errors which can be logged are: a parity error on an instruction being 27 fetched from ROS 16; a data error from Local Store Register 14; a Main 28 Storage 12 parity error detected by a parity check on Bus In 10; a 29 parity error on data being received from any one of the Input/Output devices; a channel hung condition, where an Input/Output device does not 6~a3 l "handshske" nor allow the microcomputer to proceed to the next microinstruction;
2 or time out errors, such as occur when an I/O instruction is issued to 3 an Input/Output device that does not exist and the address, therefore, 4 is non-detectable. These errors can be set in Error Register 46 and modified, saved, tested, or stored in LSR 14. Any one of these errors 6 being set automatically by the hardware forces the highest ~level 7) 7 interrupt in the microcomputer to go to a subroutine that can either 8 retry the operation or terminate the current func~ion and provide signal g to the operator's console.

4 Phase Generator and Clocks 60, 64, 66 ll A Single phase oscillator 59 is the input to four phase generator 12 60 that runs two clocks: Basic clock 66 and Auxiliary shifting and 13 timeout clock 64. Basic clock 66 is a 2 phase clock that can be stopped L4 every second clock position, with eight clock decode positions provided lS out of 4 overlapping latched states. Basic clock 66 runs through the 16 eight positions every microinstruction cycle. Basic clock 66 also 17 provides a high latch position that is used whenever the microinstruction 18 being executed requires a double cycle, which takes place whenever Main `l9 Storage 12 is accessed; then clock 66 runs through the same eight positions, except this time the presence of the high position flipflop codes the 21 clock 66 output as clocks 8 through 15. Auxiliary clock 64 decode 2 provides four distinguishable time slots together with a high position flipflop which is used whenever the clock goes through a repeat cycle to 24 indicate the maximum timeout of 2 runs through the clock, which is equivalent to one whole instruction execution cycle. Auxiliary clock 64 26 is used whenever a shift, multiply, or divide operation is required.
27 ~uring these ~nstructions main Clock 66 is stopped at its 7th position.

28 This permits cycle steals to proceed in the middle of shift, multiply, 2g or divide extended operations. Auxiliary clock 64 is also used for timeouts when I/O devices are not responding or for handshake operations E;43 1 whenever an I/O device is ound to be on Bus 10 and is tryin~ to inter-change data. If the timeout exceeds the time al:Loca~ed, then Auxiliar~
3 clock 64 times out and sets indicators in Error ~egister 46 to initiate ~ the highest level, or machine check, interrupt.

Integrated Cycle Steal and Interrupt Prioritized ~hannel 6 Referring to Figure 5 in connection with Figure 1, the cycle steal 7 and interrupt functions are acco~plished by Common Poll Bus 53, which 8 provides for 8 cycle steal levels or 7 interrupt request levels.
9 Herein, Poll Bus 53 is 7 bits wide to contain the requests for 7 inter-rupt levels above the current executable program level, a total of ~
11 interrupt levels. Any I/O device can be attached to any of the 7 prioritized 12 interrupt request lines. Polling for interrupts is continuous, except 13 when Poll CS Only Latch 75 is set, and the cycle steal function takes 14 place. As soon as an I/O device requires service from microcomputer 9, it places its request on the assigned priority bit 530-536 of Poll Bus 16 53. Multlplicity of requests will go through Priority Encode logic 54 17 where the highest level request is encoded into a 3 bit code (on lines 18 541, 542, 544) specifying one of the 8 different priority levels. The 19 priority of interrupts is also controlled by Interrupt ~ask Register 44.
If Mask 44 i9 set to allow the interrupt, then the AND circuits in ~1 interrupt gate 52 allow that interrupt to pass on to Priority Encoder 54 22 so as to set the code of the currently requesting priority. This 23 interrupt priority is compared in comparator 58 to the current level 24 stored in 3 bit Current Interrupt Level Register 56. Current Level 56 is continuously compared with any new level from Priority Encoder 54 to-26 see whether the new code is higher than the current one. If it is, 27 then, the next instruction in the current chain will not be executed.
28 Instead the current address pointer in Instruction Address Register 32 ~9 is transferred to the Local Store Register 14 location for the current 3Q level. The new, or higher, level pointer is then brought out from the ~.

6~3 .
1 Local Store Register 14 and put into Instruction Address Register 32.
2 The address for the interrupt routine in Local Storage Register 14 3 ~one of the 8 possible interrupt pointers,~ is derived as follows: the 4 low order 3 bits (on lines 561, 562, 564) from Current Interrupt Register 56 are transferred under control of Gate 81 onto LCO Register 40 input lines 831, 832, ~33. Set Current Interrupt Level 73 loads the high 7 order lines 834, 835, with the remaining bits of the LCO 40 address for storing the interrupted pointer in LSR 14. The new pointer to the g interrupt registers in LSR 14 ïs similarly loaded into LCO 40 on the high order input lines 834, 835 by Set Current Interrupt Level 3 and on 11 the low order lines 831-833 into LCO 40 'rom Interrupt Register 56 after 12 Load New Interrupt Level 7~ has transferred the new Priority 54 lnto 13 Current Interrupt Register 56. This changes the new LCO 40 address to 14 that for the LSR 14 location containing a pointer to the ROS 16 subroutine for executing the interrupt for the selected level, with the address 16 pointer arriving on Bus Out 20 and at In~truction Address Register 32 from 17 Local Store Register 14 through ALU 22 and Total Register 24. At the 18 end of execution of the subroutine of the new interrupt level, a Branch 19 Out instruction is issued. This instruction restores the pointer of the originally interrupted program. Since the subroutine that serviced the 21 interrupt also resets the interrupt, the request for the same interrupt 22 should not be present. If another interrupt comes up on the same level 23 or a higher level, the program will not return to the original program 24 position, but will continue on to handle the newer interrupt priority request. This provides for a full nesting of up to 8 interrupt levels.
26 In addition, for each level, there can exist a multiplic~ty of sublevels.
27 Once a given interrupt level is detected, an Inte~rupt Level Status Word 28 (ILSW) instruction is issued to all I/O devices, and one ~f the 16 29 devices, currently requesting service on any particular interrupt level, must identify itself. (In this manner 16 sublevels can be obtained for 6~3 1 each one of the 8 levels for a total 128 sublevel interrupts.) The 2 Interrupt Level Status Word that is received into one of the microcomputer 3 registers can be used to determine which of the 16 devices on that level 4 is requesting service. This is done by one Shift Left and Count instruction.
The first bit in the highest order position will stop the Shift Left and 6 Count instruction and the remaining count in Count Register 50 will 7 indicate the position of the subroutine for that particular device.
8 Common Poll Bus 53 is also used for cycle stealing. However, it 9 first has to be cleared of all interrupt requests. Any Cycle Steal Request line 68 is set to a negative logic level by a device that is 11 requesting a cycle steal. Once that line sets Poll Cycle Steal only latch 75, immediately Poll Cycle Steal Request line 77 is brought up, 13 the devices are required thereby to remove their interrupt requests from 14 Poll Bus 53 until the cycle steal function has been concluded. As soon as common Interrupt Request line 70 and Any Cycle Steal Request line 68 16 are dropped by all the devices, CS Acknowledge latch 76 is set at the 17 next clock 0~ indicating that Poll Bus 53 contains the cycle steal 18 priority for the requesting device, which goes directly into the Priority 9 Encoder 5~ (bypassing Interrupt Mask gate 52.) This produces 3 bits of an LCO Priority address out of Priority Encoder 54, which is gated at 21 AND 82 by AND 89 line 78 (the clocked output of Latch 76) into LCO
22 register 40--together with the fixed higher order bits addressing pointers 23 in LSR 14 for the cycle steal level which is used as a Main Storage 12 24 address, to either obtain or store data into Main Storage 12 under full control of the I¦O Device~even to the extent of just setting the upper 26 or lower byte (instead of the two bytes in the halfword mode.) Current 27 Interrupt Level Register 56 in this mode stays undisturbed because the 28 interrupt level ~whether it is the program level or any higher level 29 being executed) is just delayed by that one cycle steal instruction breakin. As just ~escribed, a memory access is initially addressed by a / ~ --.

6~

l pointer~from LCO register 40, including three low order blts signiEying 2 which of the ~ cycle steal levels is currently acknowledged, and the 3 high order bits giving a displacement to the local store 14 halfword 4 register holding the indirect memory address. This address reads out from Local Store 14 onto Bus In 10, and is incremented through ALU 22 6 before being set into Buffer Register 26. During Main Storage 12 memory 7 access time, the incremented address on Bus Out 20 can be written back ;
8 updated into i~s Local Stora~e Register 14 cycle steal register or 9 prevented to be written by the acknowlédged I/O device so as to preserve the cycle steal address unchanged. After an access time, data is read ll out from memory 12 on Bus In lO if the I/O device allows the readout 12 selection of Main Storage 12 and inhibiting the write pulses which are 13 control pulses 19 out of the microcomputer. The I/O device can 14 place its own data on Bus In 10 to be written into Main Storage 12.
lS Thus the device has full control of the increment or non-increment 16 function through the integrated ALU and full control of the read or 17 write mode of the operation. In write mode, once that operation has 18 been completed the Input/Output device can still see its own data on Bus l9 Out 20 during the following clock 1. In read mode, the data read out on Bus In 10 flows through ALU 22 into Total Register 24 and Output Buffer 21 26 to be available to all of the devices on Bus Out 20. The only I/O
22 device that will pick up that data in the read mode is the device that 23 will recognize the cycle steal level code on the six LCO address lines 24 21. The processor then reverts back to its normal instruction execution or to the interrupt routine handling that had been suspended for this 26 one D~A (or cycle steal) cycle.

27 Description of Timings 28 Referring now to Figures 2-4, a brief description will be given of 29 the timings for executing the ~icroinstructions. As all instructions have similar execution timing characteristics, a general description is S~975072 ~31-l first given, and will be followed by a more detailed description of each 2 instruction type.
3 The clocking cycle ls divided into eight different times known as 4 clocks O through 7. Clocks 8 through 15 are repeats of clocks O through 7, and the only time that these clocks appear is during a Main Storage 6 12 operation, including DMA. The basic instruction time of eight clocks 7 is divided into two parts for utilization of ALU 22. During clock 7 8 through clock 2, ALU 22 is devoted to incrementing or otherwise modifying g instruction Address Register 32. Clocks 3 through 6 are utilized for ;

processing by all the microinstructions. In this manner, ALU 22 is used ; ll continuously on a 50% basis for instruction execution and 50% for instruction 12 pointer update. The basic window during which the address Eor ROS 16 13 appears on Bus Out 20 starts at clock 3 when the computed new address 14 pointer is loaded from ALU 22 into Total Register 24 and transferred to the Output Buffer Register 26. This address stays unchanged until the 16 following clock zero when Buffer Register 26 is changed to contain the 17 data for either Local Storage Register 14 or any I/O device on I/O
18 common Bus Out 20.
l9 Clock O starts every microinstruction by loading the instruction from Read Only Storage 16 into Program Register 30. This buffering in 21 Program Register 30 permits execution of that instruction while the ROS

22 16 address is changed at clock 3, as described previously, to access the 23 next microinstruction.
~4 Total Register 24 is set at clock 2 with the instruction address and at clock 6 with the data processed by ALU 22 in executing the instruction.

26 During clock 3, the next instruction address is set into Buffer 26 for 27 loadlng on Bus Out 20~ .
28 If the microinstruction requires that data be written into Local 29 Storage Registers 14, it is written during clock 1 of the instruction following which that data was computed, and it is written from Output ~L 3Lg;~OE6~3 . ;

1 Buffer 26 through ~rivers 18 directly into the Local Storage 14 location 2 selected by the six LCO 40 lines. In the same manner data can be transferred 3 to an I/O device by loading it into Output Buffer 26 at clock 0 and with 4 a signal 19 during clock 1 indicating that the data on Bus Out 20 is valid. This data changes at the beginning of clock 3 when the Read Only 6 Storage 16 address appears in Output Buffer Register 26. Any data that ;r 7 is coming into CPU 9 on Bus In 10 for storing or modification has to arrive and be valid at ALU 22 during clocks 3, 4, 5 and 6~-this being 9 the time during which the ALU performs the process specified by the instruction being executed. For the same reason data from LSR 14 is ll placed on Bus In 10 for processing by CPU 9 at clock 2. At clock 3, 12 which allows for signal delays, the data is available for the ALU function.
13 Data from Local Storage Registers 14 is placed on Bus ~n 10 starting 14 at clock 2. It is not gated lnto ALU 22 until the beginning of clock 3, because from clocks 7 through 2 ALU 22 is used for updating Instruction 16 Address Register 32. At the beginning of clock 7, ALU 22 is transferred back to the address incrementing function, having completed its basic 18 microinstruction processing function.

19 Referring to Figure 2, for microinstructions dealing with the Main Storage 12, particularly fetching data from Main Storage 12 into one of 21 the registers of CPU 9, the second cycle (clocks 8-15) has a slight 22 variation in that the next microinstruction is fetched from ROS 16 23 during clock 3 even though execution of the current instruction continues 24 through clock 15 and into the following clock 0, at which time data from ~5 Main Storage 12 is finally set into the specified register of CPU 9 or 26 sent to an I/O Device. In this case (following every instruction accessing 27 Main Storage 12) a new instru~tion is not gated i~to Program Register 30 28 on the following clock 0 as it has already been trapped at the previous 29 clock B of the Main Storage 12 instruction. Also, the window for updating Instruction Address Register 32 is shortened and does not start in 1 equivalent clock 15, but two clocks later at clock 1 and only lasts 2 through clock 1 and clock 2, as that update i5 just a.direct transfer 3 through ALU 22 without any modificatlon (as that has already taken place 4 during clocks 7-10 of the previous Main Storage instruction.) The Main Storage write instruction writes the data into Main Storage 6 12 during the second phase of the instructiQn during clocks 13 through 7 15.
8 Referring to Figure 3, for decimal arithmetic, during the first 9 four clocks, ALU 22 performs the binary equivalent function and stores the intermediate carries for each of the packed decimal digits. A
11 repeat ALU 22 pass is then taken for another four clocks (controlled by 12 auxillary clock 64) for "six" correct to obtain the pure decimal result.
13 Referring to Figure 4, whenever a branch is performed, where the 14 branch address is loaded at clock 7 (such as the branch-on-condition, a multiway table branch in decoding an Op-code from a target language 16 which is being emulated, or when a branch and link is returned by restoring 17 the original address from Local Storage Register 14 into Instruction 18 Address Register 32) then an additional four clock cycles of Auxillary 19 Clock 64 are added to allow time for ROS 16 accessing, since in each of these cases a branch has changed the precomputed look ahead address from 21 the previous instruction.
2~ In shift operations, Auxillary Clock 64 takes two clocks for each 23 single bit shift in either Accumulator Register 34 or Extension Register 24 36; orl it takes 4 clock periods (which is half as much as the basic ~5 microinstruction execution time) for shifting one position of the double 26 precision Accumulator and Extension Registers 34 and 36: these are 27 logically connected together as one double precision register by alternatively 28 cycling through ~LU 22.
~9 For jump operations the basic ALU 22 processing time (clocks 3 through 6) perform the test for equals. greater, or test under mask; the SA97~072 3~-i4~;3 l result o~f the test is not known until the beginning of clock 7, and at . 2 that time a jump decision is madeO If no jump is to take place then the 3 next instruction that has been accessed continues without any delay. If 4 a jump condition is met and one instruction is to be skipped, the basic microcomputer clock takes another dummy microinstruction cycle during ; ~ which it increments for the next microinstruction without executing the 7 microinstruction jumped.
The branch unconditional is a very fast instruction because no g conditions need to be tested, therefor'no auxiliary clock delays are 1~ present. Furthermore, the 12 bit branch address is directly passed 11 through ALU 22 and loaded inCo Total Register 24 at clock 2. From Total 12 Register 24 it passes to Instruction Address Register 32 and Buffer 13 Register 26 at clock 3, thus synchronizing with the normal look ahead 14 accessing of lnstructions.
Instruction Set 16 The basic machine instructions are optimally designed for emulation~
17 and are stored in ROS 16. Often called micro-instructions, these may be 18 referred to simply as instructions in the following discussions, except g perhaps when a distinction between the emulated target machine instructions and the microprocessor instructions is to be emphasized.

21 Common to all instructions are a parity bit in the most significant 22 bit position ~bit 0) and a 3-bit operatisn code (bits 1-3). The remaining 23 bits are subdivided into fields of varying lengths, the nature and ~4 function of which depends on the type of instruction. Since there are only eight distinct operation codPs 9 some of the instruction types are 26 distinguished by decoding additional modifier bits. Most of the instructions 27 are highly encoded and specify or imply a large variety of distinct 2~ operations, many of which are performed sequentially. These sequential ~9 operations are coordianted by a very tightly designed set of timing patterns as set forth in Figures 2-4.

1 Re~erring now to Figures 2-4, the 11 basic in~truction categories 2 will be described. The symbols used in the timing charts to refer to 3 the registers are as follows:
4 Symbol R~
A Accumulator 6 B Extension 7 T Total 8 P Program 9 U Instruction Address N Count (Shift Count) 11 M Output Buffer (Bus Out) 12 I/O Input/Output Device 13 E Error 14 I Interrupt Mask C Current Condition Code 16 PCC Preserved Condition Code 17 L Local Storage Register 18 Each of the instructi.ons may be defined by a 16 bit, including 1 19 parity bit, instruction code. Bits 1-3 define the operation code, and these codes are listed below together with the instruction category;
Operation 21 Instructions Mnemonic Code 22 Control CO 000 2~ Logical Write LW 001 24 Logical Shift LS 001 Logical Move Count LM 001 26 Modify Data MD 010 27 Modify Operand MO , 010 28 Fetch Storage FS 011 29 Immediate ModifyIM 100 Jump ConditionalJC 101 6~3 Branch Conditional BC 110 Branch Unconditional BU 111 3 Control Instruction 4 Referring to Figure 3C, the timing diagram for the control instructions is set forth. Control instructions may be provided, for example, for 6 the following operation: for transferring data, for indirect execution, 7 for setting the interrupt mask, for setting paging, for table branching, 3 for optional mode selections, for operation on preserved condition code and current condition code, for program flags and for I/O transfers. By way of introduction, a number of uses of the control instructions will ll be described.
12 A number of the control instructions relate to interrupt processing.
13 One such-instruction enables an interrupt to take place after the completion 14 of every microinstruction, while another provides for an interrupt lS window during which any pending interrupts will be honored and the 16 interrupt switch made. After that, the interrupts are disabled until 17 the window is encountered again.
18 Other control instructions relate to ROS I/O paging. The four bit l9 ROS 16 page is an internal page specified within Instruction Address Register 32. This page register is used whenever direct branching 21 across the 4K boundaries of directly addressable ROS 16 instructions 22 locations is required. ALU 22 will increment past the 4K boundaries all the way through 64K halfwords of ROS 16. Also, the interrupt switching 24 pointers provide full 16 bit addressing, and not merely 12 bits.
Therefore, it is also capable of addressing full 64K complements of 26 instructions.
27 Other contro] instructions control the four 1ag bits. They are 28 the lower four bits of C Register 48, that together with the four condition 29 codes form the nonconnected upper byte of Count Register 50. The flag 30 bits can be set by the programmer for different indications and can be 1 used as switches in the subroutine. The flag bits can be stored or 2 restored together with the condition codes and the lower byte Count ; 3 Register 50 into and out of LSR 14 on interrupt switching.

4 The remainlng control instructions deal with the condition code.
There are two levels of condition codes, each having four bits indicating 6 binary carry, twos complement overflow, two complement high order minus 7 bit, and cummulative non-zero. The Current Condition Code Register 48 8 upper four bits change on every arithmetic operation as well as on a ; 9 shift left logical, shift left and count, multiply, and divide. For other instructions of the logical nature, the registers themselves can 11 be tested for zero or non-zero, ones or mixed ones and zeros. The 12 Preserved Condition Code Register 42 stores the same four bits aa Current 13 Conditiohs Code 48, except it is under microprogram control for transferring 14 and accumulating the equivalent of condition codes of the macro language being emulated.
16 By way of example, the following control operations are used in the 17 embodiment of the microcomputer system of the invention.
18 Control operation load immediate data (KBUS) operates to load the 19 data field of the instruction into the Output Buffer 26 high order bit positions. Local Storage Registers 14 register 0 data bits 0--4 are 21 loaded into the low order bit positions of Buffer Register 26, and the 22 contents of Buffer Register 26 are written into Local Storage Registers 23 14 register 0.
24 Control Operation Transfer LSR Data to I/O Device (KLSR) provides a ~5 four bit field for addressing Local Storage Register 14 registers 0-15.
26 Data from the addressed Local Storage Register 14 is transferred to 27 Output Buffer 26 and onto Bus Out 20. A six bit field of the KLSR

2~ instruction provides a device address, which is loaded into LCO register 29 40 for addressing Input/Output devices 1-63.
3~ Control instruction Transfer Immediate Data to I/O Device ~KLCO) 1 loads part of Output Buffer Reglster 26 with immediate data from the 2 instruction code, with the re~ainder loaded from selected Local Storage 3 Register 14 register 0 bits. Data in other bit positions of the instruction 4 code are loaded to LCO Register 40 for the device address. The contents of Output Buffer Register 26 are loaded into Local Storage Register 14 6 register 0.
7 Control operations Set Interrupt ~ask (KILM) provides the interrupt 8 mask bits for Register 44,- with a one in a bit position enabling an 9 interrupt for the corresponding level. One bit in the instruction code specifies whether to save or set the interrupt mask bits.
ll Con~rol operations are provided for setting paging of Read Only 12 Storage 16. KLAP has a field for specifying pages 0-15, and KRAP specifies 13 page 16.- Each page represents 4,096 half words.
14 Control operations for table branching specify the register or reglster portion to be added or Exclusive OR'd to Instruction Address 16 Register 32 to yield the next sequential address in ROS 16 for execution.
17 These are set forth below:
18 Mnemonic Add to IAR 32 19 KIAL Accumulator Register 34 low byte KIXL Extension Register 36 low byte 21 KIBL Output Register 26 low byte 22 KIEL Bus In 10 low byte KIA~ Accumulator Register 34 low hex 2~ KIXH Extension Reglster 36 low hex KIBH Output Register 26 low hex 26 KIEH Bus In 10 low hex 27 KIAZ Accumulator Register 34 low zone 28 KIXZ Extension Register 36 low zone 29 KIBZ Output Register 26 low zone KIEZ Bus In 10 low zone KIAS Accumulator Register 34 low six bits ~ KIXS Extension Register 36 low si~ bits 3 KIBS Output Register 26 low six bits 4 KIES External Bus In 10 low six bits Control operations branch out (KILB) 9 transfers the current Instruction 6 Address Register 32 contents to the Local Storage Register 14 register 7 for the current interrupt, resets the current interrupt, samples for a 8 new interrupt, and transfers to Instruction Address Reglster 32 the 9 contents of ehe Local Storage Register 14 location for the new interrupt level.
11 Control operation KSIE provides three 2 bit fields (II, EE, and SS) 12 for specifying the interrupt code (enabling an interrupt or sampling the 13 interrupt and then disabling further interrupts,) speci~ying error mode, 14 and specifying Main Storage 12 byte address (no change; reset, or set byte mode.) 16 Code 01 in one or more of each of the interrupt code (II), error 17 mode (EE), and Main Storage byte address (SS) fields of the KSIE control 18 operation are reserved to specify additional control operations, in 19 which the interrupt code9 error mode, or main storage byte address mode characteristics of the KSIE control instruction are preserved or replaced 21 as set forth in the table below. If the control code shows II, EE, or 22 SS, then the KSIE control instruction defines the operations specified 23 by the interrupt code, error mode, or main storage byte address byte 24 mode, respectively:

Mnemonic Instruction Code Field Description 26 KPIE IIE~Ol Reset preserved condition 27 .code (not overflow) 28 KPSI IIOlSS Reset preserved condition 29 code (all) `` SA975072 -40-1 KCSE 01EESS OR current condition 2 code to preserved 3 condition code and 4 reset current condition code.
KTPI II0101 Reset current condition code and preserved 8 condition code (not g ' overflow) KCPS 0101SS Transfer current 11 condition code to 12 preserved condltion code 13 and reset current 14 condition code KCPE 01EE01 Transfer current condition 16 code to preserved 17 condition code (except 18 OR overflow) and reset L9 current condition code.
Control operation KNTC performs the function KTPI. In addition, 21 controls are set to perform a KCSE following the next instructions if it 22 is an arithmetic operation. Flag 4 is also rese~ "even" or set "odd" on 23 the result.
~4 Control instruction KPCC performs a direct transfer of the preserved condition code to the current condition code.
26 Control instruction KFCC specifies whether Current Condition Code 27 Register 48 is to be saved or set, and specifies the positions to be 2~ saved or set: carry-borrow, overflow, minus, cumulative, not zero, or 29 flags 1 through 4.

6~3 .

1 Main Storage Instructions 2 The Logical Write'(LW) and Fetch Storage (FS) instructions comprise 3 the main storage instruction grouping. Wi~h these instructions, described 4 in Figure 2, data can be read from Main Storage 12 and placed into the four basic internal data registers: Accumulator Regi~ter 34, Extension 6 Register 36, Count Register 50,'and Output Buffer Register 26.
7 Data that is fetched from Main Storage 12 is addressed by Extension 8 Register 36, or by one of'the Local Storage Registers 14, as specified 9 in the instruction address: The address can be initially updated with 1~ an increment or a decrement to provide a continuously moving pointer to 11 Main Storage 12 on Commcn I/0 Bus Out 20, or it can be oscillated at an 12 effective address by adding to a specified pointer the N Register block 13 50 displ'acement (positive or negative.) 14 The halfword or byte addressing mode can be specified for the storage instructions. The IBM 1130 addresses its ~ain storage data in a 16 halfword mode. The IBM 360/370 and the IBM System/3 use the byte addressing 17 mode, even soj it may fetch one or two bytes in any one access. Since 18 the architecture of the System/3 instruction set allows the instructions 19 to be either 3, 4, 5, or 6 bytes, the instructions themselves are not aligned on the halfword boundaries. Therefore for ease of emulation, 21 the microcomputer of this invention provides halfword alignments by byte 22 twisting the data from Main Storage 12 in ALU 22 so as to align any 23 specific byte in one position, such as, for example, the instruction 24 operation code to always appear in the low order byte.
~5 Logical Write Instruction 2~ As previously noted, there is no direct path for data from CPU 9 to Main Storage 12. This is because Bus Out 20 is used as the Main Storage 28 address bus and therefore is not available for data. Bus In 10 is 29 bidirectional only with respect to Main Storage 12. The reason for not permitting it to be bidirectlonal with respect to CPU chip 9 is to *Registered Trade Mark of International Business Machines Corporation 1 conserve area on CPU chip 9, since the output drlvers required to place 2 data onto Bus 10 would use up a large amount of area and power on chip 3 13, and consequently, are not included.
4 The four Logical Write instructions select halfword, low byte, or high byte modes; and store in Main Storage 12 data taken from an Addressed 6 Local Storage Register 14 location or from an I~O device.
7 Logical Write from LSR
8 In the first Logical Write instruction, data from Local Storage g Register 14 location 1 is written illtO~ the Main Storage 12 location addressed by one of Local Storage Register 14 positions 0 63. An LSR 14 11 register 1-63 is selected and the contents incremented or decre~ented by 12 one, or left unchanged, before setting Output Buffer Register 26 to 13 address Main Storage, with the updated address being rewritten into the 14 above selected Storage Register 14 location 1-63. Specification of Local Storage Register 14 location 0 as the address source selects Count 16 Register 50 as the indirect address of the Local Storage 14 register to 17 be used as the source for the address for Main Storage 12. A storage 18 write cycle is performed with the data obtained from Local Storage 19 Register 14 position 1 that has ueen switched on to Bus In 10. As an option, the address modification code (two bits of the op code), if set 21 to 10 will select low byte or high byte only to be written into Main 22 Storage 12. If a Control Instruction has previously set byte storage 23 addressing mode, all plus or minus address updates will function as plus 24 or minus 2 and the high byte selection will force a -1 address update (low byte does not modify the address) with the resulting address, even 26 or odd s~oring the high or low byte, respecti~ely. Also, ehe original 27 Output Buffer Register 26 contents will be selected from Local Storage 28 Register 14 location 0.
29 Logical Write from LSR 0-63 Addressed by ~xtension Register 36 The second instruction is similar to the first one, except that the 6~3 1 data to be written into Main Storage 12 is obtained from a selected ; 2 Local Storage Register 14 (position 0-63) and the Storage Address for 3 Main Storage 1~ ls obtained from Extension Register 36. The low or high 4 byte operations described above are also available.
Logical Write from I/O Device 0-63 Addressed by same LSR 0-63 6 The third instruction is similar to the first logical write lnstruction 7 described, except that the same LSR 14 (0-63) code that selects the 8 address register also selècts the I/O device (0-63), to provide the data g on Bus In 10 to be written into Main Storage 12.
Lo~ical Write from I/O Device 1-63 addressed by Extension Register 36 11 The fourth instruction is similar to the second Logical Write 12 Instruction, described abo~e, except that the data to be written into 13 M2in Storage 12 is provided by the selected I/O device (1-63) on Bus In L4 10.
Fetch Storage 16 The Fetch Storage ~FS) instructions are designated for hal~word 17 mode. For setting storage byte addressing in place of halfword addressing, ; 18 see the Control instructions. ~Current Condition 48 + Count 50 or g Interrupt Mask 44 + Error 46 are always used together in byte mode and the upper byte is not zeroed on a Fetch Storage Command.) 21 Lodd from Storage to CPU 9 Registers with LSR 14 Address (llalfword 22 Address Mode):
23 An LSR 14 register (1-63) is selected and the contents modified by 24 ~ 1 or OR 1 before setting Output Buffer 26 (not LSR 14 location 0) Register to Address Main Storage 12. If modification was 1 the Output 26 Buffer Register 26 contents are updated into the selected register in 27 LSR 14. A storage read cycle is now performed and Storage 12 data out 28 is switch onto Bus In 10 to be set into the Accumulator 34, Extension 29 36, Buffer 26, or Count 50/Error 46 operand registers selectively.
Interrupt 44 + Error 46 registers may be selected by KSIE Control SA975072 _a4_ 1 Instruction in place of Condition 48 ~ Count 50 registers. (Count 2 50/Error 46 register has only the low byte.) L,SR 14 location O selects 3 indirect addressing of LSR 14 from operand Count Register 50 low-order 4 6 bits. Also, the original Output Buffer 26 data will be selected from LSR 14 location 0.
6 With BUS Operand Address (~alfword Address Mode):
7 This instruction is similar to the next instruction described 8 except that Output Buffer (meaning LSR 14 location 0) Register 26 is 9 used in place of Extension 36 Addressi~g Register and the auxiliary Bus Out 20 address transfer acts as a halfword move of Buffer 26 to LSR 14 1 locations 1-63 or the Bus Out 20 address update into LSR 14 location 0.
12 With XT~ Operand Address (Halfword Address Mode):
13 Extension Register 36 contents are modified by 0, ~1, or by adding 14 the ~ount 50 operand displacement before setting the Output Buffer 26 (not LSR O) Register to address Main Storage 12. The Buffer Register 26 16 updated value is rewritten into Extension Register 36. A read Main 17 Storage 12 cycle is started. An auxiliary transfer is performed (before 18 the Main Storage 12 data is available) provided that LSR 14 selection is 19 from 1 to 63, not zero. Optionally, the Address Register 32 contents are written into the selected LSR 14 register. Finally, the Main Storage 21 12 data is switched onto Bus In 10 to be set into Accumulator 1~, Extension 22 36, Output Buffer 26, or Count 50/Error 46 operand registers, selectively, 23 as in the first FS instruction. Also, the original Output Buffer 26 24 data will be selected from LSR 14 location 0.
Load from Storage to I/O Devices (~alfword Address Mode):
2~ This instruction is similar to the one above except that Address 27 Register 32 can be selected from Extension Register 36 or the LSR 14 28 location equal to the InputtOutput devlce selected and updated. The Main Storage 12 data is set into Buffer Register 26 (not LSR 0), from where it is sent to the selected Input/Ou~put device (1-63) with a 1 Sample Out pulse~ and no auxiliary transfers take place. Device O
2 selects indirect addressing of the device from the operand Count Register 3 50 low-order 6 bits. Also, the original Buffer 26 data will be selected 4 from LSR 14 location 0.
Arithmetic and Logical Instructions 6 Referring to ~igure 3 the ari~hmetic and logical instructions are 7 modify data (MD~ and modify operand (MO~. The arithmetic include add with or without carry, and substract. They can be performed in binary ~ .wos complement or decimal packed (unsigned one digit in every hex 4 bits of data.) The arithmetic functions can be performed within the 11 microcomputer between the internal registers (Accumulator Register 34, 12 Extension Register 36, Count Register 5~, and Output Buffer Register 13 26.) In-addition, Accumulator Register 34 or Extension Register 36 can 14 be arithmetically combined with one of the 64 Local Store Registers 14 with the result stored either in one of Local Store Registers 14 or in 16 Extension Register 36. All the arithmetic instructions performed within 17 microcomputer 9 regis~ers can be performed in halfword mode, upper byte 18 alone mode, lower byte mode, or low order 4 hex bits mode. The other 19 bits in each of these configurations remains unchanged.
The logical instructions include AND, OR, and Exclusive-OR. These 21 operations, when performed on the internal registers alone, as in the 2~ arithmetic mode, can be performed in the hex low four bits, the low 23 byte, the high byte, or the halfword mode. Similar functions can also 24 be performed with Local Store Register 14, except all these external-to-internal or internal-to external logical functions can only be carried 26 out in the halfword mode.

27 Modify~_ ata 28 By the Modify Data command Accumulator Register 34 or Extension 2~ Register 36 can be modified in place with the contents of a Local Storage Register 14 that remains unchanged. Also, a specified Local Storage 6~3 1 Register 14 can be modified with the contents of Extension Register 36, with the Extension Register 36 remaining unchanged and the re-sult set in the selected Local Storage Register 14. In addition, any Input/Output device can be selected to supply data on Bus In 10. This data can be modified with the data in Extension Register 36 with the result returned to the same Input/Output device by setting data into Output Register 26 (not LSK 0) and thence to Bus Out 20 and also goes into Local Storage Register 14 position 0 only if the address portion of the modified data instruction is set at 0, producing 0 data on Bus In 10. By using the OR function, a move is made from Extension Register 36 to Output Register 26. By using the AND Func-tion, Output Register 26 is set to all zeros.
The modifying functions that can be specif:ied by the ModiEy Data instruction are: add binary Wittl or without carry or decimal packed with carry, subtract binary or decimal packed with borrow (subtraction cannot be from a selected Local Storage Register 14 or Input/Output device, except in reverse), AND, OR, and Exclusive OR.
Specifying Local Storage Register 14, position 0 selects indirect addressing of the Local Storage Register 14 or Input/Output device from the low order 6 bits of Count Register 50.
Modify Operand With the Modify Operand (MO) instructions, Accumulator Register 34 can be modified in place with Extension Register 36, or Extension Register 36, accumulator Register 34, that remain unchanged. Also, Accumulator Register 34 or Extension Register 36 can be modified in place with Count 50/Error 46 Register. Also, Extension Register 36 can be modified in place with Output Buffer Register 26. With Ex-tension Register 36 ~ero, an OR Eunction in place with LSR 14 loca-tion 0 (Output Buffer Register 26) produces an Output Buffer Regis-ter 26 move to Extension Register 36 and also to LSR 14 (position 1 - 15).
The modify functions are the same as in the Modify Data (MD) instructions except that Move functions between any combination of 6~3 Accumulator 34, Extension 36, or Count 50 and Error 46 operand re-gisters are added, and subtraction cannot be from Count 50/Error 46 operand registers except in ,.v~ SA9-75-072 -47a-1 reverse. In addition, all the above functions can be per~ormed in 2 either halfword, high byte only, low byte only or low hex digit only, 3 except that the high byte of Count 50/Error 46 operand register does not 4 exist. After each of the above functions are completed, an auxiliary halfword result (high byte of Count 50/Error 46 = Current Condition 6 4~/Interrupt Mask 44) move can be performed to a selected LSR 14 location 8 Logical Shift 9 Referring to Figure 4, Shift operations can be executed either left or right, one bit at a time. The length o~ the shift depends on the ll length of the register. Accumulator Register 34 and ExtensLon Register 12 36 each can be shiEted from one to sixteen positions. For multiply and 13 divide,-when double precision is required, Accumulator Register 34 ~4 becomes the high order register of Extension Register 36, and together they form a coupled 32 bit register that can be shifted from 1 to 32 16 positions in any of the following modes: shift right arithmetic, shift 17 left and count, shift left logical, shift right logical, shift left and l~ rotate, and shift right and rotate. Faster operations which are equivalent 19 to a rotate of the 16 bit registers eight positions, otherwise known as byte twists, can be performed in one microinstruction cycle.
21 Immediate Modify 22 The Immediate Modify (IM) instructions are illustrated in Figure 23 3C.
24 A byte of data from Program Register 30 (op bits 3-15) is combined with the low order byte of Accumulator Register 34, Extension 36, or 26 Count 50/Error 46, selected by a previous KSIE Control instruction. For 27 the Accumulator 34 or Extension 36 operand registers, combining functions 28 are Subtract, Load, OR, AND, XOR, ADD. Any carry or borrow generated by ~9 ADD or Subtract is propagated into the high-order byte. For the Count 50/Error 46 register, combining functions are OR~ AND9 LO~D, ADD. For SA975072 -4t3-1 Add or Subtract functlons the immediate byte data is incremented or 2 decremented by one, and any incoming carries will be ignored with a new 3 condition code set.
4 Jump Conditional Referring to Figure 4B, the Jump instruction is performed whenever 6 a test is false. The tests, performed against a mask byte in the instruction 7 on the low order 8 bits of a selected register, are as follows: mask 8 e~uals the low byte, mask is greater than the low byte, mask bits are g tested for on bits in the low byte and the remaining non-selected bits are ignored, or mask is tested for the OFF bits in the low byte and the 11 remaining bits are ignored. Condition Register 48 can be tested under 12 mask with ON/OFF bits selection and a jump on any combination of conditions.
13 Condition Register 48 has 4 condition codes and 4 program controlled 14 flag bits. IE the teit is false, the next instruction is skipped.
Also 9 the high hex zone digits in Accumulator 34 or Extension 36 operands 16 can be tested for all zeros.
17 Branch Operations 18 The branch operations are Branch Conditional and 8ranch Unconditional.19 They can be performed to any 4K range of Executable Stora~e 16. By storing the Current Instruction Address Register 32 plus 1 into one of 21 Local Store Registers 14 before taking the branch unconditional a branch 22 and link operation is performed. The reverse, taking the address so 23 stored in Local Store Register 14 and moving that address pointer back 24 into Instruction Address Register 3~, performs the return to the subroutine from which branch and link was originally taken.
26 A second grouping of branch instructions performs the multiway 27 table branching which can be done on the low orde.r 4 hex bits in the 28 microcomputer registers, on the next four which are the zone 4 bits 29 while lgnoring the low order 4 or 6 bits, or Oll the total 8 bits, thus providing a full 256 table branch from which the 8 bit Op-code can be SA975072 -49_ `6~3 decoded by a Branch Uncondit~onal instruction out of the table 2 A third group of branch instructions provides signed displacement 3 branching on 16 different condltions; such as register zero or not ~ zero, register negative or not negative Displacement branching is performed by taking the 8 bit displacement from the Lnstruction and 6 adding it as a signed 16 bit number to Current Instruction Address 7 Register 32 8 Other instructions allow displacement branching based on Count g Register 50 being decremented by 1 or by 16 and branches taken if the 1~ result is all zeros or not all zeros, if the low order 4 bits are all 11 ~eros or not all zeros, if the low order 4 bits are all ones or not all 12 ones, if the high order 4 bits are all ones or not all ones, and so 13 forth ~4 Logical Move Count Referring to Figure 3B, Logical Move Count (LM) instructions selectively 16 move the contents of a specified register 1-63 in Local Storage Register 17 14 and to the Lnstruction Address Register 32, Accumulaeor Register 34, 18 Extension Register 36, or the Combined Current Condition and Count 19 Registers 48, 50 During this transfer, the value may be modified by 0, -1, or ~1, (except for moves of single bytes into Accumulator Register 21 34 or Extension Register 36), and the value as modified is written back 22 into the selected register 1-63 of Local Storage Register 14 Conversely, 23 the specified register (Instruction Address Register 32, Accumulator 24 Register 34, Extension Register 36, or the combined Current Condition and Count Registe.s 48, 50) may be moved into the selected location 1-63 26 of Local Storage Register 14 with modification by 0, +1, or -1 (except 27 for moves of single bytes of data from Accumulator Register 34 or Extension 2~ RegiAter 36 ) The byte moves can specify either the high or low byte o~
29 Accumulator Register 34 or Extension Register 36, but no modification is performed on moves between Accumulator Register 34 or Extension Register 1 36 and~the specified register in Local Storage RPgister 14. The Instructlon 2 Address Register 32 value is composed of the 16 bit address for Read 3 Only Storage 160 The Current Condition Register 48 can only be selec~ed 4 as the upper byte of the combined Current Condition and Count Registers 48, 50 if no increment or decrement is specified. Also, Interrupt 6 Regist~r 44 and ~rror Register 46 will be substituted for the Current 7 Condition and Count Registers 48, 50 if set by the KSIE control instruction 8 previously described. When the Logical Move Count Instruction specifies g Location 0 in Local Storage Regi~ter ;4, indirect addressing of Local Storage Register 14 is selected from the low order 6 bits of Count 11 Register 50, except selection of the Current Condition and Count Registers 12 ~3, 50 as the destination or the source register for the ~ove operation 13 will move data to or from Current Condition and Count Registers 48, 50 14 from or to Local Storage Register 14 Location 0.
Input/Output 16 There is no distinct I/O instruction as such; direct-program-17 controlled transfers of data or control messages to or from an I/O
18 device are performed by the following instructions: Fetch Storage, 19 Logical Write Storage, Modify Data, and Control.

The Fetch Storage instruction transfers data from MS 12 to an I/O
21 device via the internal data path of buses 23, 25, 28. The Logical 22 Write instruction transfers data directly from an I/O device to MS 12 23 via Bus In 10 without passing through processor 9, utilizing the address 24 from Extension Register 36 or any of the LSR 14 registers. The Modify Data instruction brings data from an I/O device, performs an ALU 22 2~ operation on it with Extension operand 36, and returns the result to the 27 I/O device through Output Buffer Register 26. A Control instruction can be used to output data to a device either from a specified LSR 14 (0-15) 29 or from an immediate data field in the instruction. Other Control Instroctions can transfer data from any I/O Device to Accu~ulator Register SA975072 -51~

~0~6g3 1 34, Extension Register 36, or LSR 14 Registers 0-15.
2 In all cases, the device address, specified by the instruction 3 either directly in the address field or indirectly as the contents of 4 Count Register 50, is transmitted to the I/O device by LC0 40 lines 21, 41, which are also used to address LSR 14. The transfer is synchronized 6 by a pair of handshaking signals, Sample In and Sample Out. These 7 signals together with Hold-Clock-In permit asynchronous operation of the 8 I/O transfers, independent of line length and device operation delays.
g While the invention has been described with respect to preferred embodiments thereof, it is apparent that the foregoing and other changes 11 may be made thereto without departing from the invention.

SA~75072 -52-

Claims (22)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. In a computing system including data storage means and at least one input/output device, apparatus for controlling direct memory access-ing of said data storage means by the input/output device for select-ively storing or reading data signals in said data storage means, comprising:
storage register means;
first bus out means;
second bus out means;
first bus in means;
second bus in means;
priority encoder means responsive to a direct memory access re-quest on said first bus in means for loading onto said second bus out means priority level addressing signals for addressing said storage register means;
said storage register means being responsive to said priority level addressing signals for loading onto said second bus in means data storage addressing signals for addressing said data storage means;
arithmetic means for selectively loading onto said first bus out means data storage addressing signals and data signals received on said second bus in means;
said data storage means being responsive to data storage address-ing signals on said first bus out means for selectively reading from or loading onto said second bus in means said data signals.

2. In a computing system as defined in claim 1 including apparatus for transferring data between said data storage means and said input/output device in a cycle steal mode, further comprising:
executable storage means for storing signals executable by said computing system;
instruction address register means for sequentially storing instruction address signals;
storage register means for sequentially storing data storage address signals;
said arithmetic meamsn having means for selectively modifying said instruction address signals and said data storage address sig-nals;
said first bus out means including means for selectively com-municating modified instruction address signals from said arith-metic means to said executable storage means and to said instruction address register means, modified data storage address signals from said arithmetic means to said data storage means and to said stor-age register means, and data signals from said arithmetic means to said input/output device;
means for communicating instruction address signals from said instruction address means to said arithmetic means; and said second bus in means including means for selectively com-municating data signals from said input/output device to a loca-tion in said data storage means addressed by said data storage address signals on said first bus out means, data signals from said data storage means to said arithmetic means, and data stor-age address signals from said storage register means to said arithmetic means.

3. The apparatus of claim 1 wherein said storage register means stores into the location addressed by said priority level address-ing signals data storage addressing signals loaded onto said first bus out means.

4. The apparatus of claim 3 wherein said arithmetic logic means selectively increments or decrements said data storage addressing signals received on said second bus in means.

5. The apparatus of claim 1 further comprising:
a second input/output device;
interrupt level register means responsive to an interrupt re-quest signal placed on said first bus in means by said second input/
output device for loading onto said second bus out means interrupt level addressing signals indicative of the interrupt level of said second input/output device;
executable storage means for storing addressable instructions for execution by said apparatus;
said storage register means being responsive to said inter-rupt level addressing signals for loading onto said second bus in means for communication to said first bus out means through said arithmetic logic means the address in said executable storage means of the first instruction for processing the new interrupt.

6. The apparatus of claim 1 wherein said central processing unit further comprises timing and control means for executing said direct memory accessing;
whereby said input/output devices need only specify the di-rection of data transfer.

7. In a computing system as defined in claim 1 including apparatus for processing interrupt requests from said at least one input/output device, further comprising:
instruction address means for computing and storing an address of a next sequential instruction to be executed by said computing system;
said second bus out means including means for addressing said at least one input/output device;
said second bus in means including means for receiving data signals from said at least one input/output device at said computing system;
said first bus out means including means for communicating data signals from the computing system to the at least one input/output devices;
interrupt level control means for computing and loading onto said second bus out means interrupt level address signals;
said first bus in means including means for receiving inter-rupt request signals from an input/output device at said computing system;
said interrupt level control means being selectively respon-sive to an interrupt request for loading said next sequential in-struction address for a current interrupt level onto said first bus out means and current interrupt level address signals onto said second bus out means;
whereby the next sequential instruction address for the cur-rent interrupt level is available on said first bus out means and identified by the current interrupt level address signals on said second bus out means for storage of said next sequential address by said storage register means attached to the first and second bus out means.

8. The apparatus of claim 7 wherein said interrupt level control means is further responsive to said allowed interrupt request for loading onto said second bus out means allowed interrupt level address signals, and wherein said instruction address means is responsive to said allowed interrupt level address signals being loaded onto said second bus out means for receiving from said second bus in means the address of the first instruction to be executed by said computing system at said allowed interrupt level.

9. The apparatus of claim 8 wherein said storage register means is addressable by current interrupt level and allowed interrupt level address signals on said second bus out means for respect-ively storing said next sequential instruction address for the current interrupt level from said first bus out means and load-ing said address of the first instruction at said allowed inter-rupt level onto said second bus in means.

10. A computing system as defined in claim 1 wherein said arith-metic means is capable of performing arithmetic and logical opera-tions on information and address data;
said computing system further comprising:
a first buffer means for storing output data from said arith-metic means for selectively forwarding to a plurality of operand registers over an internal data bus;
a second buffer means for storing said output data gated thereto over said internal data bus and for loading said output data onto said first bus out means said output data including over-lapped address and information data for selective communication to a plurality of devices; and said second bus in means being capable of communicating data from said plurality of devices to said arithmetic means.

11. A computing system as defined in claim 1 wherein said arithmetic means includes means for selectively arithmetically or logically modifying input data and addresses; and further comprising:
instruction address register means for storing control program instruction addresses;
a plurality of operand register means for storing data; and clock and control means for gating the contents of said instruc-tion address means to said arithmetic means for selectively incre-menting, decrementing, and displacement modifying said control pro-gram instruction address during a first portion of an instruction execution cycle; and for gating selected operand register means to said arithmetic means during a second portion of said instruction execution cycle.

12. The system of claim 11 further comprising shift counter operand register means, addressable by said control program instruction for transferring data to or receiving data from said arithmetic means;
for selectively indexing main storage addresses and for deriving indirect control program instruction addresses.

13. A computing system as defined in claim 1 further comprising:
first register means for buffering an output of said arith-metic means;
an internal bus;
a plurality of operand registers selectively providing an input to said arithmetic means, said operand registers including second register means for loading signals onto said first bus out means; and third register means for storing executable instruction address signals;
said arithmetic means being operable during a first portion of an exeuction cycle for modifying said instruction address signals, and during a second portion of an execution cycle for executing an instruction to generate output data signals;
said first register means being responsive to the output of said arithmetic means during said first portion of an execution cycle for transferring updated instruction address signals to said internal bus for communication to said second and third register means, and being responsive to the output of said arithmetic means during said second portion of the last-mentioned execution cycle for transferring said output data signals to said internal bus for communication to at least one of said operand registers; and said second register means being operable for transferring said modified instruction address signals and said output data sig-nals received on said internal bus to said first bus out means dur-ing respective portions of an execution cycle, with at least one of said respective portions overlapping with the first portion of a subsequent instruction execution cycle.

14. The computing system of claim 13:
wherein said storage register means includes means for stor-ing address data loaded onto said output bus;
whereby address data loaded onto said first bus out means is stored as a return pointer from interrupts.

15. The computing system of claim 14, further comprising control means for gating the contents of said storage register means onto said second bus in means for loading through said arithmetic means into said third register means;
whereby new interrupt pointers may be loaded and previously interrupted routine pointers may be restored to said third regis-ter means thereby enabling priority nested interrupt processing.

16. The computing system of claim 14, wherein:
said arithmetic means is selectively operable to modify data storage address data received over said second bus in means from said storage register means for loading by said second register onto said first bus out means; and said airthmetic means is further selectively operable to re-ceive data from said second bus in means for loading by said second register onto said first bus out means;
whereby, during cycle stealing operation, said arithmetic means operates to modify data storage addresses and to transfer data from said data storage means to said first bus out means for com-munication to an input/output device.

17. The computing system of claim 13 further comprising:
fourth register means for storing the operation code of an emulation instruction to be executed; and said arithmetic means being further selectively operable to combine said operation code with the contents of said third re-gister;
whereby a displacement pointer is obtained for addressing a subroutine for executing said emulation instruction.

18. A computing system as defined in claim 1, further including an instruction store, and further comprising:
an internal looped bus means for communicating data signals from an output of said arithmetic means to said first bus out means, said looped bus means including:
first register means for storing the output of said arithmetic means; and second register means for storing the output of said first register means;
an address register means for storing the location in said instruction store of an executable instruction; and control means operable during a first portion of an instruction execution cycle for operating said arithmetic means to calculate a next instruction address and loading the result through said first register means into said address register means; and operable during a second portion of an instruction execution cycle for operating said arithmetic means to execute an instruction received on said second bus in means and loading the execution result into said first register means.

19. The system of claim 18 wherein said control means is further operable to load said next instruction address from said first register means through said second register means onto said first bus out means.

20. The system of claim 19 wherein said control means is further operable to load said execution result from said first register means through said second register means onto said first bus out means.

21. The system of claim 20 wherein said execution results include operand values selectively addressable to one of a plurality of internal operand registers by an instruction on said second bus in means, wherein said second register means is an operand register, and further comprising third register means operable for storing operand values addressed to said second register means by said instruction; whereby execution results which are operand values addressed to said second register means by said instruction and loaded onto said first bus out means are temporarily buffered in said third register means, and next instruction addresses and exe-cution results addressed to the other operand registers and placed on said output bus by said second register are not buffered in said third register means.

22. A computing system as defined in claim 1 wherein said arithmetic means is selectively operable during an exe-cution cycle for computing a next instruction address and an exe-cution result; and further comprising:
an instruction register means for storing an instruction for execution by said arithmetic means and for specifying the operand register to receive the execution result;
an output register means selectively operable during each said execution cycle and responsive to said arithmetic means for loading each said instruction address and each said execution re-sult onto said first bus out means;
said storage register means operable, when said output register is specified by said instruction as the operand register, for stor-ing the execution result loaded onto said first bus out means.