CA1103360A - Plural channel error correcting methods and means using adaptive reallocation of redundant channels among groups of channels - Google Patents

Abstract

PLURAL CHANNEL ERROR CORRECTING METHODS AND MEANS
USING ADAPTIVE REALLOCATION OF REDUNDANT CHANNELS
AMONG GROUPS OF CHANNELS
Abstract of the Disclosure Where data is recorded on logically independent sets of parallel channels or tracks, the correction of error of very long (infinite) length cannot be advantageously treated by conventional coding methods unlike finite length error such as single shot or burst noise. To ensure the correction of channels in error from data recovered from a multi-channel storage medium, a fixed number of channels per set are dedicated to error checking bits. In this invention, more than the usual number of channels in error in any one set are made correctable by adaptively reallocating the unused redundant channels in the other set. This is accomplished by encoding and recording in the first redundant channel in.
each set vertical parity checks limited to that set while encoding and recording in the second redundant channel of each set, the parity of data taken over both sets of channels in a predetermined positively or negatively sloped direction.
With this type of parity information so recorded, then the data obtained from up to three known erroneous channels in any one set may be corrected, provided that two sets together aggregate not more than four channels in error. Advan-tageously, the vertical and cross-parity checking infor-mation can also be used to generate an internal channel-in-error pointer for the first erroneous track in each set.
Additionally, this data can be made to yield a second internal channel-in-error pointer in at least one of the sets.
Lastly, error patterns are identified upon decoding at the intersection of at least two error syndromes one of which is derived from cross-parity checking bits.

Description

3 Background of the Invention 4 This invention relates to the detection and correction of channels in error in a parallel multi-channel data handlins 6 system such as a magnetic tape storage syst~m. I~ore p~rticu-7 larly, the invention relates to increasing the number of 8 correctable channels in error among logically independent 9 sets of channels recorded on the same medium without increasinc tne number of redundant char.nels per set.
11 In magnetic tape storage systems; industry standards 12 have governed tape size, data format, and recording density.
13 Conventionally, one-half inch width tape has been used for 14 recording nine tracks thereon. By custom, data are recorded on 9 parallel channels with 9-bit bytes across the tape.
16 Consideration in this invention is given to the recording 17 and recovery of data recorded upon two or more logically 18 independent sets of channels on the same medium.
19 Magnetic tape is soft and pliable. Unlike other forms of moving magnetic storage media, such as rigid magnetic disks, 21 magnetic tape storage systems re~uire the tape to move in 22 non-uniform contact relation with one or more fixed heads 23 as data is being transferred to or from the tape. Any loose 24 particles of debris between head and tape or spots on tape ~ th missing iron oxide causes loss of signal amplitude.
26 Under the circumstances, it is possible for the read back 27 clock in the erroneous channel to lose synchronization with 28 the data in other channels. Consequently, the recording and 29 playback of data from the tape may be in error over very lon~ segments. Ir. this regard, th~ noisy length o~ tape .

ilu336u 1 poses a data recovery problem unlike that of either single shot noise or burst noise. Characteristically, single shot and burst noise induced errors are usually of finite duration. The recon-stitution of the infected data is obtained by the use of error checking codes with cyclic properties. These codes are complex both in their theory and use. Illustrative of a magnetic tape storage device capable of variable density recording and utilizing a cyclic code for error detection and correction purposes is the IBM*
3803 Controller for the IBM 3420 Models 4, 6, and 8 Tape Drives.
The code actually employed is described in Hong et al United States Patent 3,868,632.
The present commercial practice is to reserve two out of nine channels for recording redundant information about the remaining seven channels of the set. This enables up to two channels in error to be subsequently corrected. If there is contemplated the recording of two or more sets of parallel channels on a tape, there would con-tinue to be reserved two redundant channels per set. With this for-mat in mind, suppose one set of channels contained three channels in error while a neighbor set had none. It is clear that using pre-sent error checking techniques, there would be no effective way totake advantage of the unused redundancy of one set in order to assist in correcting multiple channels in error in another set.
The prior art is typified by Patel United States Reissue Patent Re28,923; Hong et al United States Patent 3,868,632 and Louis IBM
Technical Disclosure Bulletin, Vol. 14, page 3846, May 1972. In this regard, both Patel and Hong are directed to error correction in a nine-track tape. That is, where both the data and the redundant channel *Registered Trade Mark 1 are part of the same logical set. Louis describes a method

2 of record recovery from a plurality of tapes by the calcula-

3 tion of a data value replacing unavailable data from a simple

4 parity modulo 2 added to the remaining available data.
The limitation in error correction among multiple and 6 logically independent sets of channels is to be distin-7 guished from methods of correcting up to three known 8 erroneous channels in a single set. The latter correction 9 methods utilize codes which require an equivalent of three redundant channels as descri~ed by Patel in USP 3,851,306.
11 To use such methods and their underlying codes requires 12 three redundant channels in each of two interleaved nine-13 channel sets of an 18-channel tape system, that or.e could ~ correct up to three known channels in error in each set.
lB However, the redundancy of three channels per set of nine is 16 wasteful, especially in view of the expectation that the 17 occurrence of three erroneous channels in both sets simul-18 taneouæly is highly unlikely.
19 Summary of the Invention It is an object of this invention to correct channels 21 in error on a parallel multi-channel storage system. It is a 22 related object to correct multiple channels in error even 23 where the number of error channels exceeds the number of 24 redundant channels per set. It is yet another ob~ect to correct multiple channels in error in a first set utilizing 26 information recorded on redundant channels in a second set.
27 It is yet another o~ject that such channel correction be 28 obtained independent of the direction of data recording, 29 i.e. in the in-channel or cross-channel direction on the medlum.

SA977025 -~-11(~3360 1 The foregoing objects are satisfied by an apparatus which encodes parity checking bits in two redundant channels of each set of a pair of logically independent sets of channels. There is encoded and recorded in the first redundant channel in each set vertical parity checks limited to the data recorded in the channels of its own set, while there is encoded and recorded in the second redundant channel cross-parity checks taken over all of the channels in both sets in a predetermined positively or negatively sloped channel direction. Alternatively, the cross-parity checks (diagonal checks) of the second redundant chanrel can be recorded as check bytes distributed among data bytes at fixed intervals.
The correction of error is the calculation of a data value to replace a corresponding error value. In the ;nstant invention, this is achieved by firstly deriving an error correction signal from the logical values of at least a pair of intersecting syndromes, the syndromes being obtained from the redunant channel parity data inclusive of the error.
For each pair of inte~secting syndromes, at least one syndrome is re-quired to be taken in a diagonal direct;on. Secondly, up to three known channels in error in any one set may be corrected from the recorded information by combining error correction signals derived from the logical values of the intersecting syndromes with the originally re-corded channel data. This is provided that the two sets together indicate not more than four channels in error. This adaptive feature may be extended to parallel multi-channel systems having three or more logically independent set~ of channels. Also, the reallocation of unused redundancy can further be extended SA~-77-025 - 5 -1 to the trade-off Detween the detection and correction of 2 channels in error. In this latter regard, analog devices 3 can be used to detect error and provide external error-4 pointers, thereby increasing the correction capability of this invention.
6 It is possible in this invention to generate internal 7 pointers to channels-in-error. In one version, a channel 8 error pointer can be generated for the first erroneous 9 channel in each set from the recorded parity bits. By a further adaptive usage, a second channel-in-error pointer 11 in at least one set can also be generated without any 12 increase in the number of redundant channels in either set.
13 It is yet another aspect of this invention, that the 14 distinctive data formats can be used in the encoding, re-cording, retrieval, and decoding as data in a parallel multi-16 channel data handling system. In a first format, the 17 diagonal parity of check bits appears in separate chec~ing 18 channels. In a second format, t~e diagonal parity check 19 bits appear as check bytes distributed among data bytes at fixed ir.tervals. In still another variation, the format 21 records information as bytes across the channels, or bytes 22 along the channels.
23 In the prior art, data and redundant channels were cross-24 correlated only among themselves. With the advent of recording data in plural independent sets upon the same medium, this 26 invention teaches that unused redundancy may be reallocated 27 with a modest amount o~ cross correlation among the data in 28 channels of both sets. This is achieved by encoding the 29 error checking information on the basis of diagonal cross channel parities taken across both sets in combination with 31 vertical parities t2ken only within their own set.

SA977025 _5_ 11(~3360 1 The foregoing and other objects, aspects, and advantages of the invention will be apparent from the following more particular des-cription of the preferred embodiment of the invention as illustrated in the accompanying drawing.
Brief Description of the Drawing FIG. 1 is a block representation of a parallel multi-channel storage system inclusive of the parity encoder for data writing and parity decoder for data error checking when data reading according to the invention.
FIG. 2 shows a cross track parity encoder correlated with the track and bit positions as used with a vertical data byte tape format.
FIG. 3 also shows a cross track parity encoder correlated, how-ever, with an in-track data byte tape format.
FIG. 4 exhibits a cross track parity encoder in which both the cross track parity as well as the data byte are recorded in vertical byte tape format.
FIG. 5 shows the general logic for an adaptive cross parity decoder showing the calculation of the necessary parity syndromes, the detection of error and the generation of a stream of corrections for channels in error from among two sets.
FIG. 6 shown of the sheet of drawings bearing FIG. 1 illustrates the occurrence of three erroneous channels or tracks in a first set together with one erroneous track in a second set.
FIG. 7 is a detailed logic representation of the syndrome genera-tor for set A.
F~G. 8 is the detailed logic for the syndrome processor for set A.

~LM/W15 l~U3360 1 FIG. 9 shows the detailed logic for the syndrome processor for set B, while FIGS. 10 and 11 shown on the sheet of drawings bearing FIG. 7, represent the detailed logic respectively of the error pattern generator and the error corrector for set A.
FIG. 12a-b depicts the generation of a first channel-in-error pointer in Set A.
FIG. 12c-f depicts the generation of a second channel-in-error pointer additional to the first pointer in at least one set by means of adaptive usage of the cross parity checks.
FIG. 13a shown on the sheet of drawings bearing FIG. 10, represents the detailed logic for the generation of a first channel-in-error pointer in Set A.
FIG. 13b-c represent the detailed logic for the generation of a second channel-in-error pointer Set A when the first pointer is given to be other than 8th track or 8th track respectively.
FIG. 14 illustrates the vertical and diagonal parity checks with three sets of channels.
Description of the Preferred Embodiment Referring now to FIG. 1, there is shown a general block diagram of a parallel multi-channel storage system incorporating the invention.
Information from source 1 is applied to buffer/controller 3. The con-troller orchestrates the formatting of the data, securing the necessary parity encodings, and causing said formatted and parity encoded data to be recorded on two sets of logically independent parallel channels in storage unit 5. Correspondingly, buffer/controller 7, when activated, reads data previously recorded on said parallel channels, reformats and decodes said data for applicaticn to a utilization device 11.
SA~-77-Q2~ - 8 -11~3360 1 Operationally, information in buffer 3 is fed in parallel 2 form to an error correction encoder 9 over paths 2 and 4 3 wherein check and parity bits are sequentially generated for 4 information signal sets referred to as bytes. As these parity and check bit signals are recorded along with the information 6 signals, then upon reading of both from the storage unit 5, 7 the additional (redundant) signals may be used to correct any 8 errors in the information signals. The decoder 19 of the SA97~025 -8a-11(~3360 1 present invention, enables calculation of syndromes using 2 signals grouped in a so-called vertical direction, and in a 3 positively or negatively sloped cross channel (diagonal) 4 ~ direction.
Referring now to FIG. 2 there is shown the format for 6 recording 18 parallel tracks along a tape. This format is 7 similar to the nine-track format in which one of the tracks 8 (track 8) is reserved to record "parity" over the other 9 8 tracks. Such parity bit is known as the vertical redundancy check (VRC) bit as set forth in U. S. Patents 11 3,508,194, 3,508,195, and 3,508,196. Each byte Am consisting 12 of 8 bits and the VRC bit is simultaneously recorded in each 13 of the 9 tracks of each of the sets. It may be recovered 14 from such recorded channel by readback and reassembly into bytes in accordance with Floros USP Re25,527. In the FIG. 2 16 format track 0 in each set of 9 tracks is also reserved for 17 parity encoding. Each cross track (diagonal) parity checks 18 dma and dmb represent the simple parity of bits recorded in 19 a positively or neyatively sloped cross channel direction.
In contrast, the VRC bit for the mth bit position for the 21 channels of set A covers only those bits in the vertical 22 direction limited to set A while the same is true for the 23 corresponding VRC bit for the mth position for set B.
Given that there are 18 parallel tracks recorded along the tape, then the tracks may be grouped into two sets as 26 shown. Set A consists of any 9 parallel trac~s, while set B
27 consists of the remaining 9 parallal tracks. In FIGS. 2, 3, 28 and 4, the two sets are shown side by side with a particular 29 ordered arrangement of the tracks. In practice, the tracks from the two sets may be interleaved and may be arranged in 31 any other order.

SA977025 _9_ 11(~3360 1 Let Am(t) and Bm(t) denote the mth bit in the tth track 2 of set A and set B respectively. The track number t takes 3 on the values from O to 8 in each set. The bit position m 4 takes on values from O to M. The oth and the 8th tracks in each set are check tracks. Each check bit in the oth track 6 Of set A provides a parity check along the diagonal with 7 positive slope involving, as previously mentioned, bits from 8 both sets as seen in FIGS. 2 through 4. As an example, the g mth diagonal check of set A termed dma check is given by the encoding equation;

12Am() ~ 1 Am-t(t) tO ~m-t-8(7 t) (1) 14~ = modulo 2 sum 150 - exclusive OR

17 Each check bit in the oth track of set B provides a 18 parity check along the diagonal with negative slope involving 19 bits from both sets as seen in FIGS. 2 through 4. The mth diagonal check of set B, called dmb check is given by 'he 21 encoding equation:

23 m() ~ 1 m-t( ) ~ O m-t-8( ) (2) ~5 In this invention, parity is ta~en to mean "even parity."
26 "Even parity" is the assigning of a bit value in the "parity 27 position" so that the number of ones, including the parlty bit 28 over the range of interest is even (a modulo 2 sum).
29 Equations (1) and (2) can be rewritten in a symmetrical form as:

` ~
~1~3~6~) t=0 m-t(t) ~ Bm_t_8(7-t)] = 0 t=0 m-t(t) ~ Am_t_8(7-t)] = 0 6 Referring particularly to FIG. 2, at t~e beginning of 7 the rec~rd, computations of the diagonal check bits for 8 positions 0 through 15, involve data bit values from void 9 positions (negative position numbers).
These data bit values will be arbitrarily considered 11 to have 0 binary value. Likewise, at the end of the record, 12 in order to provide diagonal checks to all bits in each 13 track, the oth check track in each set should be extended 14 15 positions. The check bits on the extended positions also 1~ involve some data bit values from void positions. This also 16 will be assumed to have 0 binary value.
17 Each check bit in the 8th track-of set A is a vertical 18 parity over the same bits of the same position m in set A.
19 The mth vertical parity check of set A designated Vma, is denoted by the equation:

22 ~ Am(t) - 0 (5) 24 Similarly, the mth vertical parity check of Set B designated Vm is formed by the equaticn:

27 ~0 Bm~t) O (6) ~8 29 One other general aspect of the formats shown in FIGS.
2 through 4 should be mentioned and this concerns the relation-31 ship to the recording of information and the direction of the i~J3~U

1 track. In FIG. 2 the data bytes for each track set are 2 recorded in the vertical direction. This also includes the 3 cross track parity bit. Thus, for byte Ao each of the 7 inror-4 mation bits are recorded in the 0 bit position across tracks 1 through 7 while the cross track parity bit is recorded in 6 the 0 bit position for track 0. The same occurs for say byte 7 B4 for recording information in the other set of tracks (set B).
8 In the format shown in FIG. 3, track 0 in each set is 9 still reserved for recording the cross parity bits. ~owever, data bytes are recorded in ~he in-track direction. In 11 this format, the 9 track record is partitioned into blocks, 12 each block containing 7 data bytes and two check bytes 13 placed along the tracks. While there are still two check 14 tracks as shown in the format of FIG. 2, however, the conventional 8 bit bytes are used in the encoding and de-16 coding process and are recorded as bytes along the tracks.
17 This is distinguished from ~sing the characters across the 18 tracks which consist of 7 data bits and 2 check bits in the 19 format of FIG. 2.
Referring now to the format in FIG. 4, one must reca~l 21 the format from FIG. 2 where the diagonal parity of check 22 hits appear in two check tracks. In that format, the vertical 23 characters Am and Bm consists of 7 data bits and 2 check bits.
24 This is distinguished from the conventional 5 track recording o~ one-half inch magnetic tape with a vertical character or 26 bytes consisting of 8 data bits and a vertical parity check 27 bit. ~n the format of FIG. 4, Ao~ 8' 16' 24 ' P
28 the diagonal parity check with positive slope while ~o~ ~8' 29 B16, B24---, provide the diagonal parity check with negative slope. All other bytes are data bytes consisting of the con-31 ventional 8 data bits with a vertical parity check bi .

il(~336U

1 Juxtaposed to each of the multi-track tape formats in 2 FIGS. 2 through 4, a counterpart encoder 9 of the shift 3 register type is capable of generating the cross track parity bits to be subsequently recorded by buffer/controller 3 on the 0 track in storage unit 5 of the respective sets, for 6 the formats of FIG. 2 and ~. In the case of the vertical 7 format of FIG. 4, a full byte of cross check Farity bits 8 must be vertically recorded.
9 Referring now to FIG. 2, encoder 9 consists of a 7-stage flip-flop shift register, FF~, FF2, ... , FF6, and FF7.
11 Interposed between each shift register stage is a multiple 12 input, single output exclusive OR gate (XOR). XOR gates 195, 13 197, .... 205 in addition to coupling one registe: stage to 14 another (FF2 to FFl) also have dedicated inputs to bits positioned diagonally across the tracks of bcth sets. In 16 this ~egard, XOR gate 193 terminates Bm 8(7) while the 17 remaining XOR ~ates terminate two inputs each. XOR 195 18 termi~ates Am(l) and Bm ~(6) down to and including XOR 207 19 terminating Ai~'7) and Bm 8(G) Encoder g in ?IG. 2 implements equation 1 for the calcu-21 lation of Am(0). Now Am is a 7 bit data character while Bm 22 is an 8 bit ~haracter which includes the check bit pre-23 viously computed. The check bits Ao(0), Al(0), A2(0) 24 Am(Q) are generated in a continuous shift and are generated at the output of XOR 193 of shift register 9 as the 7 and 8 26 bit Am and Bm 8 characters are entered in order. The mth 27 check bit Am(0) is generated when Am and Bm 8 are enter~d.
28 Note, that Am or Bm with negative value of m is an all 0 29 charaoter. A counterpart encoder for generating the cross hyte parity bits for Bm(0) defined by equation 2, although 31 not shown, can easily be c~nstructed.

S~9/7025 -13-11(~33~0 1 Referring now to encoder 9 in the in-track data byte 2 format for FIG. 3, there is now notation G and H for in-3 track bytes and some variation in the bit assignments to the 4 counterpart XOR's to conform to the requirements of the format. As shown ~ is an all 0 byte, while H8n 8 is a 6 previously computed check byte. The other G8n+p and H8n p 1 7 are 8 bit data bytes (p varying between 0 and 7). Check 0' 8' G16, ..., G8n are generated i~ a continuous 9 shift and enter process bit by bit at the output of the shift register as the ~ byte znd data bytes including check 11 bytes from Set B are entered in the order shown. Again, 12 Gm or Hm with negative value of m is an all 0 byte. Note 13 that in this embodiment XOR 193 terminates two inputs, 14 namely G8n+p (0) and H8n_p_l~0). The logic for defining the computation of the parity bit is represented respecti~-ely in 16 this diagram in accordance with the relationship of Am(t), 17 8m(t) of the equation (3) and for the counterpart encoder 18 for set B, as per equation (4).
19 Referring now to encoder 9 in FIG. 4 relating to vertical cross track and data byte format, ~ is an all 0 byte while 21 the A8n+p and B8(n-1)+p are 8 bit data bytes with p ransing 22 between 0 to 7.

24 ~ ~ J B8(n-1) ~ ~bit order reversed ~8n+1 B8(n-1)+1 ~ J for all B bytes.) 26 A8n+2 B8(n-1)+2 27 A8n+3 28 A8n+4 29 . .
.
31 A8n+7 8(n-1)+7, 336~

y Ao~ A8, A16 ... A8n as are the check bytes 2 interspersed among data bytes as shown in FIG. 4. These 3 check bytes are generated in a continuous shift and enter 4 process. This occurs as the bit by bit ou~put of the shift register responds to the ~ byte and data bytes entered in 6 the above order. Also note that A or B with negative value m m 7 of m is an all 0 byte. Again equations 3 and 4 define the 8 necessary logic for the organization of a shift register to 9 generate the checking bit. Also, XOR 193 in this embodiment terminates two inputs as does XOR in the FIG. 3 embodiment.
11 It should be especially observed that the bit order for 12 B8(n l)+p is reversed. Parenthetically, vertical parity check 13 generation may be accomplished by a simple modulo 2 addition 14 of all the bits taken in the vertical track direction.
At this point the reader is reminded that the organiza-16 tion of buffers 3 and 7, as well as the internal controls 17 of storage unit 5, are part of the prior art so that the 18 detailed relationship between encoder 9 and buffer 3 bears 19 much the same relationship as that to be found between the IBM 3803 controller and the 3420 tape drive.
21 The focus of interest shifts from the mechanisms by 22 which the vertical and cross channel parity bits are generated, 23 formatted and recorded on parallel multi-channel storage 24 media to the ultimate object of the invention. This is namely the correction of channels in error among two or 26 ~ore logically independent sets of channels utilizing the 27 unused redundancy of channels in a neighboring set. In 28 ~ubsequent discussion attention will first be directed to 29 error syndromes and then the decoding process. The dis-cussion of the decoding process will include firstly, separate ~1 descriptions of 3 track correction and track correction SA977025 -lS-11(.~3360 l and l track correction in set A with pointers. Secondly, 2 embraced in the decoding process is a discussion of genera-3 tion of the first track pointer in set A. Also, discussed 4 is the generation of second track pointers in set A when the first track in error is known. Once the pointers are 6 generated, then the errors can be corrected as discussed in 7 the first procedure. Finally, error correction and pointer 8 generation in set B is discussed.
9 Referring now to FIG. l, decoder 19 is shown inter-acting with buffer 7 in receiving data over paths 21 and 35 11 and returning decoded data over paths 33 and 47. FIG. 5 12 is a logical diagram showing the details of the adaptive 13 cross parity decoder. Data applied over input path 21 14 and path 35 are respectively applied to independent processins paths. The processing path consisting of elements 23, 25, 16 27, 29, and 31 is directed to generating error correction 17 for the channels in set A while elements 37, 39, 41, 43, 18 and 45 generate error correction for the channels in set B.
19 Data with error on the parallel tracks of Set A is applied on path 21 to data distributor 23. Correspondingly, data 21 on the 9 tracks of set B are applied via path 35 to data 22 distributor 37. Correction information for the data from 23 set A is returned ~o the decoder over path 33 and correction 24 information for set B is returned to the decoder over paih 47.
It will be observed that each of the processing paths consists 26 of the same functional losic, such as the data distributor 23, 27 a syndrome generator 25, a syndrome processor 27, an error 28 pattern generator 29, and an error corrector 31. The 29 corresponding processing path elements for set B are 37, 39, 41, 43, and 45 in that order. ~irst, consideration should 31 be given ts error syndromes.

il(~33~;0 1 Syndrome Determination 2 Let the bit values as they are read from the tape for the 3 sets be denoted as ~m(t) and Bm(t) respectively. These read 4 back bits may be corrupted by errors. Significantly, the result of the parity checks of equations (3), (~), (5), and (6) 6 apply to t~e read back data is called "the syndrome of 7 error." A non-zero "syndrome" is a clear indication o~
8 the presence of an error.
9 The mth diagonal parity check of set A yields the syndrome:

11 dm ~ [Am-t(t) ~ Bm-t-8(7-t)~ (7) 14 The mth diagonal parity check of set B yields the syndrome:

17 sdm = ~ [Bm_t(t) ~ Am-t-8( (8) 19 The mth vertical check for set A yields the syndrome:

21 m t=0 m 23 The mth vertical chec~ for set B yields the syndrome:
2~
Svm = ~ 0 Bm( (10) ~7 The modulo 2 difference between the read Am(t) 29 and the written Am(t) is called the error pattern em(t) llQ3360 1 in the mth positior. of the tth track in set A where 3 m( ) m( ) m( ) (li) Similarly, for Set B, 7 em(t) = Bm(t) ~ Bm(t! (12) 9 Combine equations (3) and (7), Equations (~) and (8), equations (5) and (9) and equations (6) and (10) and substitute 11 em(t) and em(t) of equation (11) and (12). Then 13 sdm = ~ [em-t(t) ~ em_t_8(7-t)~ (13) sdm = ~ [em t(t) ~ em-t-8( )] (14) 17 m t=0 m (15) 19 SVm = em(t) (16) 21 Many different types of errors can be corrected by 22 processing these syndromes. In tapes, the predominant 23 errors are track errors caused by large sized defects in 24 the magnetic medium. The erroneous track may be identified by detecting loss of signal, excessive phzse error, inad-26 missible recording pattern, or any other similar external 27 pointer. In the absence of such external ~ointers, the 28 erroneous track can still be identified by 2rocessing the 29 syndromes. Any one of the following ccmblnations of track errors can be corrected by processing the syndromes.

SA977025 -'8-1 1. Up to three known tracks with errors in one 2 sèt and up to one known track with errors in the other 3 set.
4 2. Up to two known tracks or one unknown track with errors in each of the two sets.
6 3. Up to two tracks in error (one of which is known) 7 in one set and up to one known track with errors in the 8 other set.
9 Decoding Process and Means The deco~ing process includes the accessing of data 11 and the transferring of the data from the parallel multi-12 channels of storage unit 5 to the buffer/controller 7. Here, 13 buffer/controller 7 coacting with decoder 19 ascertains 14 whether, in fact, any of the channels are erroneous and generate correction signals. In discussing multiple track 16 correction, one is reminded of the trade-off between using 17 redundancy to establish the fact that the bits in a given 18 channel are in error and/or using that redundancy to correc~
19 the error. Correction of error is the calculation of a data value to replace a corresponding error. In the instant 21 system, this is achieved by combinins the logical values of 22 intersecting syndromes inclusive of the error. In this 23 sense, each pair of intersecting syndromes requires one 24 syndrome whic~ is taken in a diagonal direction.
Up to the present point, reference has occasionally 2~ been made to the use of pointers for designa~ing a channel 27 or track in error. In much of the subsequent discussion 2~ reference will continue to be made to pointers, their 2g generation and use. Pointers may be externally derived or 3~ internally generated. In this regard, external pointer SA97702~ -19-11(~3360 1 generation usually requires some form of analog senslng of 2 the playback conditions of data recorded on any Oc the 3 several channels. The manner and means of external pointer 4 generation is beyond the scope of this invention. Suffice to say that in the absence of external pointers, this invention 6 includes means for generating one or more internal pointers 7 for error correction purposes as well as in the presence of 8 external pointers. The following comments are directed to 9 the generation of pointers and the interrelationship between internal and external pointers. This should provide a basis 11 for the consideration of the detailed multiple channel or 12 track correction in each of the logically independent sets 13 with the aid of pointers.
14 A record is written on a tape with the object to play it back error-free. When a tape is started and a record is 16 at m = O, one can assume there are no errors and all the 17 pointers are off. If, after a period of time, an error 18 occurs on one of the channels, for example Set A, and further 19 no external pointer was raised to indicate the channel error, it is necessary to generate a first internal error 21 pointer to identify the channel. In the embodiment of this 22 invention, this can be accomplished within seven digit posi-23 tions along the channel before the error has occurred.
24 Once the first internal pointer in Set A was generated, it would be kept on for the correction of errors in the 26 indicated channel for the duration of the playback operation.
27 Of course, such an assignment of a pointer might llnduly limit 28 the correction capacity of the system. Thi~ is especially 29 true if there was no continuous error in the indicated 3~ channel. Consequently, some systems provide that a pointer SA977~25 -lga-11~3360 1 can be extinguished if no error occurs within a predeter-2 mined interval after initial error detection.
3 In this hypothetical example assume the occurrence of 4 an error in a channel in Set B. The channel identity will be generated by either an external or internal first pointer 6 in that set. Because each set includes two redundant 7 channel equivalents, it follows that the detection of a 8 first channel in error in Set ~ is well within the correction 9 capabilities of the system. It is further the case that the first pointer in Set B will be kept on for the correction of 11 errors in the indicated channel. But what happens if another 12 error occurs in Set B? This can likewise be indicated by a 13 second pointer. However, the pointer to any third channel 1~ in error in Set B can only be externally senerated.
To restate the situation, the first internal 16 pointer in any given set gates on in the absence of any 17 other pointers with respect to that set. This implies that 18 a first internal pointer in Set A will be gated on given no 19 other pointers in Set A and up to two pointers on in Set B.
Relatedly, a second internal pointer in Set A may be internally 21 activated only when there exists a first pointer for Set A
22 and there are no more than one pointer on for Set B. The 23 second internal pointer is activated irrespective of whether 24 the first pointer is internally or externally generated in that set.
26 While intexnal pointers are believed to be most reliable, 27 at the most three of the four pointers available in 28 the system o~ the preferred embodiment may be generated 29 internally. Also, two simultaneous internal pointers cannot be generated in the same set. This is because the SAg7~025 -i9b-11(}3360 1 second internal pointer requires the existence of a first 2 known pointer as a condition precedent.
3 As previously mentioned, the ensuing discussion will 4 describe the method and means for multiple track correction and pointer generation. In this sense, the generation of 6 internal pointers takes advantage of the diagonal parity 7 checks covering all of the channels in both sets as well as 8 the vertical parity checks limited to the channels of their 9 respective sets. This is also involved in the dynamic reallocation of redundancy unused in one channel set for the 11 channel error correction in the other channel set.
12 Three-track Correction in Set A With Pointers 13 Referring now to FIG. 6, there is depicted three 14 erroneous tracks in Set A. Errors, confined to the three known tracks in Set A, are correctable if Set B is either 16 error free or has only one known track in error. The 17 erroneous tracks are there indicated by track error pointers, SA9 7 7 0 2 5 - 1 9 c-11(~3360 1 i, j, k in Set A and pointer y in Set B. If pointer y is 2 undefined, then Set B is assumed to be error free.
3 For convenience in decoding, pointer i is the lowest 4 and pointer k is the highest of the track indices among the erroneous tracks from track numbers 0 .o 7. Track j 6 is the remaining erroneous track so that either 8 (i < j < k) or (j = 8 and i < k.) Since Set B in FIG. 6 has only one known track in 11 error, the vertical parity check syndromes SVb yield the 12 error patterns for this track. On eliminating the known 0 13 value of error pat~erns correspondin~ to the error free 14 tracks, then equation (16) can be rewritten as 16 SVm = em(y) (17) 18 Making the assumption t~a~ al' errors are co_rected up 19 to the (m-l)st byte and the syndrome equation- are adjusted for all error patterns, then as is apparent from FIG. 6, 21 the error patterns for the mth position of tracks i, j, and 22 k of Set A can be determined from the diagonal syndromes 23 Sdm+i (positive slope) and Sdm+l5 k (negative slope, and the 24 vertical syndrome SVm . The equations for these syndromes may be obtained from equations (13), (14), and ~15) upon 26 elimination of the known 0 error patterns corresponding to 27 the error free trac~s and the corrected error patterns up to 28 the (m-l)st position in each track. Thus, 11~33~i0 1 Sda = em(i) (18) m+l5-k ~em(k) ~ em+l5 (y) if y < 8 ~ea(k), if y=8 or y is undefined (19) 7 SVa - em(i) ~ ea(j) ~ em(k) (20) 9 From Equation (17) we have 11 SVm+l5_y_k = em+l5-Y~k(Y) (21) 13 Then equations (18), (19), (20) and (21) yield the error patterns:

ea(i) = sda+i (22) 17 em(k) = Sdm+l5-k ~ SVm+l5-y-k,if Y

19 Sdm+15-k if y=8 or y is undefined (23) 21 em(j) = SVm ~ em(i) ~ ea(k) (24) 24 The mth bits and tracks i, j, and k are, then, corrected using these error patterns according the following relations 26 (25), (26), (27):

28 Am(i) = Am(i) ~ em(i) (25) Am(j) - Am(;) ~ em(;) (26 32 Am(k) = A~(k) ~ ea(k) (27) 11(?3;~60 1 As may be recalled, the values Am(i) denote the bit 2 values corresponding to Am(i) as they are read back from 3 the tape.
4 Prior to the correction of the next position, it is necessary to modi~y the syndromes affected by these correc-6 tions. The modification is shown by an arrow from the 7 previously calculated value of a syndrome with its mcdifica-8 tion to its new value:

sdm+i ~ Sda ~ e~i) (28) 12 Sdm+j C sdm+j ~ em(j) if j<8 (29) 14 Sdm+k < Sdm+k ~ ea(k) (30) 16 Sdm+l5_, ~ Sdm+15-i ea(i) (31) 18 Sdm+15~ Sdm+15-j ~ em(j) if j<8 (32) Sdm~l5_k ~- - Sdm+l5-k em(k) (33) 23 The foregoing correction procedure can be applied to 24 the next bit position by incrementing the ~Jalue of m by 1.
Two Channel Correction in Set A With Pointers 26 Errors in two known tracks in Set A can be corrected 27 if Set B has at the most one unknown track or two known 28 tracks in error. The erroneous tracks in Set A are indicated 29 by the channel error pointers i and j where i < ,.

-llQ3360 l If it lS assumed that errors are corrected up to the 2 (m-l)St bit position in each track and the syndrome equations 3 are adjusted for all corrected error patterns, then it can 4 be shown that the error patterns for the mth bit positions of tracks i and j of Set A can be determined from the syn-6 dromes Sdm+i and Svm. The equations for these syndromes 7 can be obtained from equations (13) and (15) respectively.
8 Upon elimination of the known 0 error patterns corresponding 9 to the error free channels and the corrected error patterns up to the (m-l)St position, then the syndromes can be expressed ll as:

13 sdm+i em(i) (34-1) Sva = em(i) ~ em(i) (34-2) 17 Equations (34~1) and (34-2) yield the error patterns:

19 ea(i) = sdm+i (35) 21 em(j) = Sva ~ em(i) (36) 23 The m bit-positions in tracks i and j are then corrected 24 using these error patterns:
26 Am(i) = Am(i) 0 em(i) (37) 28 Am(j) = Am(j) ~ ea(j) ~38) 2~

llQ3;~60 l Before proceeding for the correction of the next position, 2 it is necessary to modify the syndromes affected by these 3 corrections as was done in the case of three channels in 4 error. As before, the modification is shown by an arrow from the previously calculated syndrome value to its new 6 value:

8 sdm+i ~ _ Sdm+i ~ em(i) (39) Sdm+l5_i { ------ sdm+l5-i e~(i) (40) 12 Sdm+l5-j< Sdm+l5-j em(j) if j<8 (41) 14 sdm+j ~ - sdm+j ~ em(i) if j<8 (42) 16 The foregoing correction can be applied to the next position 17 by incrementing the value of m by l.
18 The correction procedure for two known tracks in error l9 is the same as that for three known tracks but for the fact that only two error patterns are calculated from the two 21 local syndromes. Thus, the two track case can be viewed as 22 a special instance of the three track correction procedure.
23 One Channel Correction in Set A With Pointer -24 Errors confined to only one known channel ln Set A
can be carrected by means of only the vertical parity check 26 syndrome of Set A. Under these circumstances, Set B may have 27 up to three known channels in error.
28 An error pattern for the mth position in only one known 29 track will be indicated by the vertical parity check syndro~e Svm. If this error occurred in the jth track and the other 11~3360 1 tracks or channels were error free, then asain from 2 equation (15) the following relation obtains:

4 Svm = ea(j) (43) 6 Thus, the error pattern is given by the syndrome Sva.
7 Track j is then corrected using the error pattern as m(i) = ~m(i) ~ em(;) (44) 11 Before proceeding for the correction of the next position, 12 it is necessary once more to modify the diagonal check 13 syndrome Sdm+j as it is affected by this correction. The 14 modification is given by 16 Sda+j ~ Sdm+j ~ em(;) (45) 18 The correction for the next position can be performed by 19 incrementing m by 1 and repeating the above procedure.
Once again it may be noted that the correction procedure 21 for the one known erroneous channel can be also implemented 2~ as a special case of the correction of three known erroneous 23 channels.
24 Generation of First Channel-in-Error Pointer And Sinqle Channel Correction in Set A
Given No Other Pointers 26 Errors confined to only one unknown channel in Set A
27 can be detected and coxrected if Set B has, at most, one 28 unknown or two known channels in error. It is assumed that 29 errors in all channels in Set B are corrected up to the (m-l)St bit position and the syndrome values are adjusted 31 for all correct~d error patterns. When all ch~nnels in Set SA9~7025 -25-1~33~0 1 are error free, the parity check syndrome Svm and Sdm+i are 2 equal to zero for O<i<7. When any of these syndromes are 3 found to be non 0, then it is an indication that an error 4 is present in at least one of the channels in the vicinity, within the next 7-bit positions. Assuming that only one 6 erroneous channel is affecting the syndromes, the index of 7 the erroneous track can be determined by examining svndromes 8 Sdm+7 and Svm as the bit position value m progresses. The g following statements chara~terize the generation of first channel-in-error pointer and single channel correction in 11 Set A given no pointers.
12 Referring now to FIG. 12a, there is shown the generation 13 of a first track error pointer derived from the intersection 14 of a vertical and diagonal syndrome.
Assertion 1 16 Referring again to FIG. 12a let m and n be the lowest 17 values of bit positions such that m<n and 19 sdm+7 ~ (46) 21 and Svn ~ 0 (~7) 23 Then track j is in error starting at bit position n and 24 j = 7 - (n-m) (48) The value j<0 is an indication of an uncorrecta~le error 26 involving t~o or more tracks.
27 Referring now to FIG. 12b, there is shown a generation 28 of a first track error pointer also from the intersection of 29 a vertical and diagonal syndrome where the unknown errcneous track is that cf track 8 dedicated to recording vertical 31 parity checks.

11(~3360 1 Assertion 2 2 In FIG. 12b, let n be lowest value of bit position s~ch 3 that 4 Svn ~ (49) and 6 Sdm+7 for all m~n.

8 Then track 8 is in error starting at bit position n.
g The implementation of the above two assertions fits in the general iterative decoding procedure as the bit-position 11 value m is incremented in an iterative manner. A counter 12 will be set to 7 when Sda+7 ~ 0 is detected for the first time.
13 As the bit-position m is incremented forward, the counter will 14 count down each time by one until the bit position n is reached, where Svn ~ 0. The resultant count value gives the 16 index of the erroneous track. If the count goes below the 17 value 0, then the error is spread in more than one track and 18 is uncorrectable. If Svn ~ 0 is detected first and Sda+7 = 0 lg even when m=n, then the track 8 is in error. The error pattern for the erroneous track can be obtained as usual.
21 The syndromes are always adjusted for the corrected error 22 patterns before incrementing the value of m.
23 ~eneration of Second Channel-in-Error Pointer and Two Track Correction 24 in Set A Give~ One Pointer -Consider the case when Set ~ is being corrected for 26 errors in a known erroneous track and another unknown track 27 in Set A begins to be affected b~ errors. This second unknown 28 erroneous track can be detected and both erroneous tracks 29 o~ Set A can be corrected provided that Set B has at the most one known track in error.

11(~3360 1 For simplicity, first we will explain the method for the 2 case when tracks 0 to 7 in Set B are er or-free. Later it 3 will be easy to see how the equations can be modified to 4 include the effect of a known erroneous track in Set B.
Let j denote the known erroneous track in Set A and we 6 assume that, so far, all rem~ining tracks in Set A were error 7 free. Also assume that all errors are corrected up to (m-l)St 8 bit-position and the syndrome values are adjusted for all ~ corrected error-patterns.
The error pattern of the mth position of the jth track 11 affects the syndromes Sdm+j, Sdb+l5 j and Svm. In the absence 12 of errors in any other tracks, it follows that 14 Sdm = Sdm+15-; = SVm (A-l) 16 and the error pattern for the mth position for the jth track 17 is given by 19 em(i) = Svm (A-2) 21 When any part of the syndrome relationsh p of ~quation ~A-l) 22 is violated, it is an indication that an error is present 23 in another track in the vicinity (within the next 15 bit 24 positions). Assuming that only one other erroneous track is beginning to affect the syndromes, the following state-26 ments hold.
27 Assertion 3 2~ With reference to FIG. 12c, let j, (j<8~ be -the known 29 erroneous track and let m and n be the lowest values of bit positions such that m<n and 11~3360 1 Sdm+j ~ Svm , (A-3) 3 and Sdn+15-j ~ Svn . (A-4) then the track i is in error at bit position n and 7 i = j - (n-m) (A-5) 9 Note that values i<0 implies there are more than .wo unknown erroneous tracks. Furthermore, the error p~tterns are 11 given by 13 ea(i) = sda+i ~A-6) and ea(j) = Svm ~ em(i) (A-7) 18 Assertion 4 19 With reference to FIG. 12d, let j, (j<8) be the known erroneous track and let m and n be the lowest values of bit 21 positions such that m<n and 23 Sdm+15-j ~ Svm (A-8) and sdn+j ~ Svn ~ (A-9) 27 then, the track k is in error at bit position n and ~9 k = j + (n-m). (A-10) SA977025 ~29-lla3360 1 Furthermore, the error patterns are given by 3 em(i) = sdm+j (A-ll) and em(k) - Svm ~ em(i) (A-12) 7 The value kC7 indicates that the unknown erroneous track is 8 in Set B.
9 The following Assertions 5 and 6 cover the case when one of the two erroneous tracks is the parity check track 8.
11 Alternatively, track 8 can be included into the computations 12 of the diagonal parity checks and syndromes in which case 13 track 8 will be automatically covered by Assertions 3 and 4.
14 Assertion S
With reference to FIG. 12e, let j (j<8) be the known -16 erroneous track and let m be the lowest value of bit position 17 such that 19 sdm+j ~ Svm (A-13) 21 and Sdm+15-j ~ Svm (A-14) 23 then, the track 8 is in error at bit position m.
24 Furthermore, the error patterns are given by 26 em(j) = Sda+j ~A-15) 28 ea(8) = Sva ~ em(j) (A-16) SA977025 _30-11~3360 1 Assertion 6 2 With reference to FIG. 12f, let j (j=8) be the known 3 track in error and let m and n be the lowest values of bit 4 positions such that n = m+k and 6 Sdm+l5 ~ (A-17) 8 Sdn+k ~ (A-18) then the track k is in error at bit position n.
11 Furthermore, the crror patterns are given by : 12 -~ em(k) = Sdm+k (A-l9) e (8) = Svm ~ ea(k) (A-20) ` 17 Note that if ~7, then the unknown erroneous track is in Set B.
~18~ Now we show thc~modification for the more general case when ~19 5et B has at the~mo-t one track in crror. Lct y, (y<8) be ~2~:~ ; the erroneous~track in Set B. The error patterns for this 21~ ~ tra~ck are al} known rom the vertlcal parity check syndrome Svm: of Set 8.~ These error patterns also affect the values ~M~ 23 ~ of~diagonal parity check syndromes Sdm. In order to account ``:24~` or thc effect of thcse error patterns in Assertions 3, 4, 25~ 5 and 6 we use~the adjusted values Sdm ~ Svm y in place of b 26:: Sdm~for any required value:of m. In particular, in Assertions ~27~ 3~ 4 and 5 rcplace Sdm+l5_j by Sdm+l5 j ~ S~m+15 j y and in ~28 ~ Asscrtion 6, replace Sdb+l5 by Sdb+l5 ~ Svb+l5_y.
2g~ The proo~s of Assertions 3, 4, $ and 6 follow from the geometrical structure:of thc code, (FI~S. 12c-f). The imple-3L mcntation fits in the general iterative decoding procedure , :

~: :
~ SA977025 -31-, , .

11(~3360 1 as the bit ~osition value m is incremented in an iterative 2 manner. An additional counter to count from 0 to 7 will be 3 required to count the value of (n-m) in order to deter~ine 4 the index of the erroneous track. The second equation in each assertion need not be obtained for n greater than m+7.
6 The syndromes are always adjusted for the corrected error 7 patterns before incrementing the value of m.
Note that the effect of the second erroneous track in 9 Set B can be detected in a similar manner. Note also that because of the adaptive usage of the parity check track, 11 the effect of an unknown erroneous track in one set shows 12 up earlier in the other set as a trac~-error-pointer value 13 larger than 7. (Refer to Assertion 4.) 14 The Decoder Embodiment Data read from the respective Set A and Set B of tracks are 16 respectively applied over paths 21 and 35 to data distributors 17 23 and 37 as per FIG. 5. Each data distributor applies to its 18 counterpart error corrector, the bit values as they are 19 read back from the tape. Consequently, data distributor 2~ 23 applies Am(t) over path 49 to corrector 31. At the ~1 same time, distributor 37 applies Bm(t) over path 101 to 22 error corrector 45. The error corrections ea from error ~3 patt rn generator 29 is applied to corrector 31 over path 24 77. In the same vein, error correction pattern eb from pattern generator 43 is applied to corrector 45 over path 26 99.
27 Referring now to FIG. 11, there is shown a typical 28 error corrector 31. The corrector includes a plurity of 29 XOR gates 331, 333, .... 335, and 337. Each XOR gate term-inating a counterpart digit from Am(t) and ea. The simul-31 taneous parallel output from the XOR gates is represented 11~13360 1 as Am(0), Am(i), ... , Am(6), Am(7) on the bit lines of 2 path 33. In this regard, the correction represents the 3 logical equivalent of equations (25), (26), (27). The 4 remainder of the description concerns the production of the error correction patterns em and em by the syndrome 6 generator 25, processor 27 and error pattern generator 29 7 for Set A and generator 39, processor 41, and pattern generator 8 43 for Set B.
9 Referring now to FIG. 7, there is sho~n the syndrome generator 25 for Set A. Generator 25 provides on path 63 11 a vertical parity syndrome Svm for Set A, a displaced vertical 12 parity syndrome Sva+l5 j z for Set A on path 61 and a dis-13 placed cross trac~ or diagonal parity syndrome Sda+l5 from 14 Set A channels across and including Set B channels on path 59.
It should be observed that the vertical parity syndromes 16 are no more thzn the exclusive ORing of the counterpart 17 bytes respectively read from the mth and the m+l5-j-z bit 18 positions of Set A along the tape extent. The input/output 19 relationship for XOR 217 and XOR 215 correspond to equation (9)-21 The (m+15)th diagonal parity check syndrome on path 59 22 is obtained from the shift register encoding of Am+l5(t) and 23 Bm+7(7-t) according to the relation Sdm+l5 = ~ [A (t) o ~4 Bm+7 t(7-t)3 corresponding to ~quation (7). Here, at the 26 instant of decoder time position m, 8 vertical bits from 27 Set A in the (m+l5)th bit position are applied together with 28 8 vertical ~its from Set B in the (m+7)th bit position as 29 taken in inverted order over counterpart paths 51 and 57 as inputs to corresponding XOR gates 204, .... 211, and 213.

SA977025 _33_ 11~'3360 1 The outputs on path 59 and 61 from generator 25, are 2 in turn applied to syndrome processor 27. The vertical 3 parity syndrome Svm is forward coupled in processing path 4 for Set A has an input to error pattern generator 29 over path 63. In the processing path for Set B, the signal on 6 path 8 7 coupling generator 39 to error pattern generator 7 43 suffices.
8 Referring now to FIG. 8, there is shown a logic g diagram for syndrome processor 27. The inputs to the syndrome processor are the error correction patterns em and 11 em appearing on individual bit lines over paths 99 and 77.
12 Also, the positively sloped diagonal syndrome Sda+l5 and 13 the displaced vertical syndrome for Set A Sva+l5 j z are 14 resp~ctively applied as an input to shift register stage FF15 and exclusive XO~ gate 253. Parenthetically, the 16 output of XOR 2~3 represents an intersection indicated by SA
17 of a diagonal syndrome Sdm+l5 z and a vertical syndrome 18 Svm+l5 j z, which intersection covers one of the tracks in 19 Set A. It should be noted that the signal representing the intersection on path 69 is applied as an input to error 21 pattern generator 43 in the Set B processing path. A counter-22 part signal SB from syndrome prccessor 41 indicative of a 23 syndrome intersection located in one of the tracks in Set B
24 is applied over path 71 to error pattern generator 29 in the Set A processing path.
26 Shift register stages FF15, FF14, F~8, ~ FF0 stores 27 all the displaced values from 1 to 15 of the syndrome Sda.
28 The XOR gates 219, 221, --- 223, 225, 227, --- 229, 231 29 modifies the stored syndrome values in accordance with equa-tions (28)-(33) for the corre_ted error patterns eb and ea SA977025 _34_ llQ3360 1 of the pr~vious cycle as the syndrome values are displaced 2 into their new positions and the new cycle begins for the 3 next in position.
4 Shift register stages FF15, FF14, .... FF8 in which the input into all stages but the first is the moduIo 2 6 edition of the shift register stage contents and the error 7 correction pattern eb. Si.nce AND gates 247, 245, ... , 243 8 have a pointer indication (z) on path 67 as to the location g of a channel in error in Set B, then the syndrome Sda+l5_z from OR gate to 51 represents the positively sloped diagonal 11 syndrome intersecting the channel in error in Set B yielding 12 its calculated value.
13 All displaced values from 1 to 15 of the diagonal syndrome 14. Sdm are made readily available by means of the shift register logic of stages FF7, FF6, ... , FFl, FF0; the associated AND
16 gates 241, 239, 111, 237, 235 and OR gate 249 select out the 17 ith displaced value Sdm+i as required for equations (18) 18 and (22). The XOR gates 225, 227, .... , 229, 231 modify the 19 stored syndrome values by means of the corrected error patterns em from the previous cycle as the syndrome values 21 are displaced into their new positions. Also, a mismatch 22 between the contents of a register position FF0 and em~0) 23 both inputting to XOR gate 231, indicates the presence of an 24 uncorrectable error on path 233.
Referring now to FIG. 10, there is shown error pattern 26 generator 29 for Set A. The output corrective error pattern 27 for Set A appears on the corresponding bit lines of path 77 28 as em(0), em(l~, ... , em(7), em(8). Each of the QR gates 29 291, 293, ... , 295, and 297 terminate corresponding AND
gates from a series of AND gates. For example, OR gate 11(~3360 1 291 terminates AND gates 299, 301, and 303. AND gate 299 2 is from the series of AND gates 299, 305, ... , 311, and 3 317; AND gate 301 is from the serles 301, 307, ... , 313, 4 and 319; AND gate 303 is from the series 303, 309, 315, and 321. Now when one or more of the pointers i, j, 6 or k are active, then an appropriate "1" appears on paths 7 65, 81, or 79. If track 1 in Set A were erroneous and i 8 was the pointer thereto, then the i = 1 conductor of path 65 g terminating in AND gate 305 would be activated. When "more 1~ than one track in error" is activated, the diagonal error 11 syndrome Sdm+i on path 75 passes through AND 323. This is 12 the value of error pattern em(i) ~cccrding to EquatiGn (22~.
13 The signal em(i) on path 329 is distributed as one of the 14 inputs to all of the AND gates of the series 299, 305, 311, and 317. Given that only i = 1 conductor on path 65 is 16 activated, then the signal em(i) passes through AND gate 17 305, through OR gate 293 on that conductor of path 77 18 designated em(l).
19 If three tracks are in error in Set A then the AND gate 327 is activated and the composite syndrome SB cn path 71 21 pass~s through. This is the value of error pattern em(k) 22 according to Equation (23). The signal on path 333 is dis-23 tributed as one of the inputs to all of the AND gates of the 24 series 303, 359, 315, 321. The signal ea(k) passes through one of the AND gates depending on the value of k. For 26 example, if k=7 then the AND gate 321 is activated and the 27 signal em(k) passes through AND gate 321 through OR gate 297 28 and appears as ea(7) on the corresponding conductor of path 77.
29 Now a vertical parity syndrome Sva from syndrome generato-25 over path 73 inter~cts with the error patterns em(i) and ~A977025 -36-1 ea(k) through the XOR gate 32S, according to Equation (24).
2 The output of the XOR gate 325 is then the value of the 3 error pattern em(j) on path 331. The signal on path 331 4 is distributed as one of the inputs to all of the AND gates of the series 301, 307, 313, 319, 325. The signal em(j) passes 6 through one of these AND gates depending on the value of j.
7 For example, if j=6 then the AND gate 313 is activated and the 8 signal em(j) passes through AND gate 313 through OR gate 295 9 and appears as em(6) on the corresponding conductor of path 77.
Note that the values of pointers i, j and k satisfy the 11 relation (i<j<k) or (j=8 and i<k).
12 Referring again to FIG. 6, where three channels in 13 error i, j, and k, representing tracks 2, 4, and 5 in Set A
14 and pointer y indicative of track 3 in error in Set B are shown. It is clear that the error value for the vertical 16 parity syndrome Svm is ambiguous as to whether the bit in 17 error is on any of the tracks 2, 4 or 5. This ambiguity 18 is resolved if recourse is made to that diagonal parity 19 error syndrome which crosses the least number of tracks in ~rror. Thus, a negatively sloped diagonal syndrome such 21 as Sdm+l5_k terminating in track 0 of Set B some 3 positiGns 22 to the right while intersecting the mth bit position in 23 error in track 2 of Set A would nevertheless have to cross 24 3 other tracks in error. These tracks would be namely track 3 in Set B and tracks 5 and 4 in Set A. The diagonal parity 26 syndrome crossing the fewest number of tracks would be a 27 syndrome te~minating in track 0 of Set A positively sloped 28 and terminating at bit position m+2. It is designated Sdm+i.
29 The diagonal parity syndrome for identifying the error in track 5 of Set A at the mth bit position would also be ~1~'3360 1 r.egatively sloped and terminating in track 0 of Set ~ and 2 designated bv Sdm+l5 k In contrast, a positively sloped 3 diagonal error syndrome terminating in track 0 of Set A
4 would intersect one more track in error than the negatively sloped diagonal. Since this latter diagonal may also intercept 6 an erroneous track in Set B advantage must be taken of the 7 vertical parity Sdm+l5 y k terminating in track 8 of Set B.
8 This provide discriminatina value. It is only after the 9 values for the i and k tracks have been ascertained that attention is directed to the intermediate j track. To re-11 capitulate, first we removed the unknown error value of 12 tr~ck i. This was followed by the removal of the unknown 13 value in track k. It now becomes possible to discern 14 whether there is an error in the track 4 by the vertical syndrome SVm.
16 Embodiment of Generation of First and Second Error Pointers 18 Referring now to FIG. 13a, there is shown a first 19 error pointer generator for obtaining an index of the first erroneous channel in Set A in the absence of any pointer.
21 It is understood that Set B has, at most, two known tracks 22 in error. The generator comprises a pair of latches 401 and 23 407 respectively starting and stopping a count-down ring 24 counter 4G5. The output of the ring counter 409 represents pointer j. The latches 401 and'407 are respectively responsive 26 to syndromes Sdm+7 and Svm. When Sdm+7 = 1 then latch 401 27 is set and the count in counter 405 is set to 7. For each 28 change in the bit position m along the track, the counter is 29 decremented b~ 1. In contrast, when Svm = 1 then latch 407 is set and counter 405 is stopped. The value of the counter 11(~3360 1 at this juncture constitutes the pointer j. For the special 2 case when latch 407 is set before latch 401, then, the 3 pointer index j is equal to 8.
4 Referring now to FIG. 13b, there is shown a second error pointer generator for Set A when the first pointer is directed 6 to a track other than 8. A generator comprises a pair of ring 7 counters 405 and 406 respectively outputting at ports 415 and 8 417 pointer i and pointer j. Latch 401 sets ring counter 405 9 of the count-down type to the value j whiie latch 407 sets ring counter 406 of the count-up type also to value j. Stop 11 and gate out signals are provided over a common path to both 12 ring counters when AND gate 413 is actuated by both latches 13 being set. Relatedly, the output 427 of AND gate 411 indicates 14 the setting of second pointer to the value j = 8 only upon the simultaneous mismatch of inputs to XOR gates 423 and 16 425. In this latter sense, a mismatch of inputs Sda+i and 17 Svm on paths 75 and 63 to XOR gate 423 sets latch 401 while a 18 mismatch of inputs Svm and SB on paths 63 and 71 to XOR gate 19 425 sets latch 407.
The em~odiment in FIG. 13~ should be taken together with 21 the format shown in FIG. 12c,d and e. Operation can be under-22 stood, i~ it is appreciated that one is given a pointer i<8 23 in Set A. Initially, i and j are set equal to each other and 24 value k such that i = j - k. The object is to obtain a second pointer and reassign values such that i<j, where Set 26 B has, at the most, one known track in error. In other 27 words, one pointer j<8 in Set A, and at most, one pointer in 28 Set B are the required conditions to activate this generator.
29 Now the input S~ on path 71 represents Sdm+l5 k ~
Svb~l5 k y for k = j. Upon the condition that Sdm+i ~ Sva ii~'3360 1 for i = j then a 1 output from XOR gate 423 sets latch 401.
2 This in turn, sets counter 405 to the value j. L~kewise, 3 when SB ~ Svm then a 1 through XOR gate 425 sets latch 40' 4 and counter 406 to value j. As m is incremented by 1, then counter 405 decrements by 1 and counter 406 increments by 1.
6 ~owever, if both latches 401 and 407 are set, the counters 7 stop by way of a signal passing t~rough AND gate 413. At 8 this juncture pointer i is equal to the colnt in counter 405 g while pointer j is equal to the count in counter 406. The special case when the latches 401 and 407 are simultaneously 11 set at the same value of m, then sets the second pointer 12 index j = 8.
13 Referring now to FIG. 13c there is shown a second error 14 pointer generator for Set A when the first error pointer is on track 8. The object is to obtain a second pointer i 16 given first pointer j = 8. Initially, set i = k = 0.
17 Set B has, at most, one known track in error. The generator 18 comprises a ring counter of the count-up type 406 set to 0 19 by latch 423 and stopped with the contents gated out by syndrome Sda+i on path 75. Latch 423 is set when SB is 1 21 while the counter is stopped when the syndrome driving path 22 75 is 1.
23 Initially, i and k are set to 0. SB represents Sdb+l5 k 24 Svm+l5 k y where k = 0. SB = 1 sets the counter to 0. The counter increments by 1 as m is incremented by 1. In this 26 case, k remains 0 whereas i follows the value of the counter.
~7 Notably, Sda+i equal to 1 stops the ~ounter and the count is 28 equal to the pointer index. Note that as pointed out in 29 FIG. 12f, one pointer set to j = 8 in Set A, and at most one pointer in Set B are the xequired conditions to activate 31 this generator.

S~977025 -40_ 1103;~60 1 Error Correction In Set B
2 The previously described error correction method steps 3 and pointer generation steps possess a built-in mirror-image 4 symmetry around Set A and Set B. In particular, the encoding and decoding equations for Set B can be obtained from those 6 of Set A by substitution of appropriate variables, namely:
7 Am '~ ~Bm i ~--~ x 8 Sda ~Sdb jt ~y S ~ <- ~SVm k( ~ z em ~ ~ ~ em 11 ' 12 Thus, the following types of errors are correctable in Set B
13 by applying the decode process as described for Set A.
14 1. Up to three known erroneous trac~s in Set B
when Set A is error-free or has only one known 16 track in error.
17 2. Up to two known erroneous tracks in Set ~
18 when Set A has at the most one unknown or two 19 known erroneous tracks.
3. Up to one known erroneous track in Set B
21 independent of Set A.
22 4. Up to one unknown erroneous track in Set 8 23 when Set A has at the most one unknown track 24 or two known tracks in error.
2~ 5. Up to two erroneous tracks in Set ~ (one of 26 which is known) when Set A has only one known 27 track in error.
28 The General_Case 29 Thus far, attention has been focused on the case of two sets of 9 tracks in an 18-track system. However, the result 11~3;~60 1 may be generalized into a system with any number of tracks 2 in which ~he two sets may not have equal number of tracks.
3 Set forth below are the encoding equations for such a system.
4 If Set A has (Tl+2) tracks and Set B has (T2+2) tracks, then encoding equations (3), (4), (5) and (6) can be 6 rewritten for this general case as Tl T
g t=0 t t=0 m-t-T (T2-t) = 0 (50) T T

11~ 0Bm_t(t) ~ ~ 0 m-t-T2 (Tl t) 0 (51) (Tl+l) 13 ~Q A (t) = O (52) 14 t=0 m (T2+1) 16 ~ Bm(t) = O (53) 18 The decoding equations can be formulated for the general case 19 in a similar manner. If T2 is not equal to Tl, the decoding equations still remain substantially similar for Set A and 21 Set B which allows the use of same decoding hardware for the 22 two sets by time-multiplexing the decoding process. One 23 effect of increased nu~ber of tracks is the fact that the 24 enco~ing and decoding processes involve corresponding number of bit-positions along the tracks. This, in turn, determines 26 the size of the encodin~ and decodin~ buffers and processing 27 time delay. Another effect of the increased number of tracks 28 is the corresponding increase in th~ number of additional 29 check bits at the end of the record in order to complete the two diagon~l parity checks. ~n general, the two diagon~l 31 check tracks will be extended by T1 + T2 additional positions.

1~3360 1 Adaptive Use of Cross Parity Checks in A Svstem Havina 3 or More Sets of Channels 2 - _ , 3 Heretofore there has been described a parallel multi-4 channel data handling system in which the channels of the system were divided into mutually exclusive sets and the 6 channel errors in these sets were corrected by means of 7 cross parity checks and vertical parity checks. By means 8 of adaptive usage of these parity checks, it was shown that 9 up to 3 known erroneous channels could be corrected in any one of the sets provided that the number of erroneous 11 channels in the two sets together did not exceed four.
12 Referring now to FIG. 14, the~e is shown a format using 13 vertical and diagonal parity checks with 3 sets o~ channels.
14 In this regard, let Tl, T2, T3, denote the number of data channels in Set A, Set B, and Set C, respectively. Each 16 set will have its own vertical parity check channel. Two 17 additional check channels or tracks will provide overall 1~ parity checks along the diagonal with positive slope and 19 along the diagonal with neoative slope, both encompassing all data tracks. The total number of channels in the 21 system is 2 + (Tl+l) + (T2+1) + (T3+1).
22 The parity chec~ along the diagonal with positive 23 slope in FIG. 13 is desigr.ated dm check, and is recorded 24 in the 0th track on the side of the first set. The corresponding encoding equation is g ven by 27 Am() ~ 1 Am_t(t) ~ m-t-Tl 0 ~ 1 Cm-t-Tl-T2(t) (B-l) 29 The parity check along the diagonal with negative slope termed the dm check, is also recorded in the 0th track but SAg77025 -43-il(J'3360 1 on the side of the last set (Set C). Its corresponding 2 encoding equation is given by 4 Cm(0) = ~ Cm-t ~T3-t) ~ ~ 1 Bm-t-T3(T2 t) ~ ~-1Am-t-T2-T3( 1 (B-2) 7 The vertical parity check is recorded in a separate 8 check track for each set. Its corresponding encoding equations g are Am(Tl+l) = ~ 1 Am( ) (B-3) l T
12 Bm(T2+1) = ~ 1 Bm( ) (B-4 14 Cm(T3+1) = ~ 1 Cm~ - (B-5) 16 These parity checks provide the following error correction 17 capability.
18 1. The vertical parity check in each set provides 19 correction of one known erroneous track in that set.
21 2. The vertical parity check of a set in conjunction 22 with one of the two diagonal parity checks provides 23 correction of two known erroneous tracks in that set.
24 3. The ver.ical parity check of a set in conjunction with one of the two diagonal parity checks provides 26 detection and correction of one unknown erroneous 27 track in that set.
28 4. The vertical parity check of a set in conjunction 29 with ~oth the diagonal parity checks provides correction of up to three unknown erroneous 31 tracks in that set.

SA977025 -44_ ~ 3 ~S O

1 5. The vertical parity check of a set in conjunction with both the diagonal parity checks provides correction of one known and one unknown erroneous tracks in that set.
Each of the two diagonal checks can aid the error detection and/or correction in one set only. Thus, the error correction capability as described in (4) and (5) above is available to any one set only.
Similarly, the error correction capability as described in (2) or (3) above is available to any two sets only.
The decoding equations and their implementation can be derived by considering various channel-in-error combinations as was illustrated in the two logically independent sets of channels.
While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. In particular, the function described herein can be easily implemented with programmable logic arrays and/or software means with-out departing from the spirit and scope of the invention.

Claims (12)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. In combination: a parallel multi-channel data handling system said channels being partitioned into a first and a second set; and apparatus for correcting up to three channels in error in any one set, the other set having no more than one channel in error; said appara-tus comprising:
means for encoding and writing into a first channel in each set vertical parity checks limited to that set;
means for encoding and writing into a second channel of each set parity checks taken over both sets of channels in a predetermined positively or negatively sloped direction;
means for determining syndromes from the parity checks and data written into the channels;
means responsive to external pointers designating at least one known channel in error for generating correction signals from at least two syndromes intersecting the same error in the known channel; and means for correcting said errors by logically combining the cor-rection signals with the original known channel data.

2. In a parallel multi-channel data handling system according to claim 1, wherein said apparatus further com-prises:
means responsive to the syndrome determining means for generating an internal pointer to an unknown channel in error in the first set having a first known channel in error and the remaining set having at most one known channel in error.

3. In a parallel multi-channel data handling system according to claim 1, wherein of the two intersecting syn-dromes, one of which is a diagonal syndrome.

4. In a parallel multi-channel data handling system according to claim 1, wherein said means for generating correction signals include means for selecting as between two diagonal syndromes the one closest to the channel in error.

5. In a parallel multi-channel data handling system according to claim 1, wherein the means for generating correction signals includes means for modifying the diagonal check syndrome by logically combining said syndrome with the correction signal in the same manner as the correction signal is combined with the original channel data.

6. In a parallel multi-channel data handling system according to claim 1, means responsive to an external pointer designating a known error channel in the first set and to a mismatch among two syndrome intersecting the same error in the known channel for generating an internal pointer to an unknown error channel in the same set as a function of the displacement between the first and a subsequent mis-match.

7. In a parallel multi-channel data handling system according to claim 6, wherein the means for generating an internal pointer includes:
a counter initialized to the number of the known channel in error;
means for selectively incrementing or decrementing said counter; and logic means coupling the syndrome determine means for causing the incrementing means to change the counter value such that if a near or far diagonal syndrome is unequal in the first mismatch then the counter is incremented until a vertical syndrome is detected as being unequal in a second mismatch.

8. In a parallel multi-channel data handling system according to claim 7, wherein the means for generating an internal pointer includes:
means for pointing to the first redundant channel if the vertical syndrome is unequal in the first syndrome mismatch.

9. In an apparatus for decoding data written into a plurality of parallel channels, said channel plurality being partitioned into logically independent sets, a first channel of each set containing vertical parity checks limited to that set, diagonal parity checks taken over all channel sets in a predetermined positively or nega-tively sloped direction being formatted from one of a group con-sisting of bits written into a second channel in each set, and re-gularly spaced bytes written in the cross-channel direction; the combination comprising:
means for determining syndromes from the parity checks and data written into the channels; and means responsive to an external pointer designating a known error channel in a first set and to a mismatch among the vertical and diagonal syndromes intersecting the same error in the known chan-nel for generating a pointer to an unknown error channel in the first set as a function of the displacement between the first and subsequent vertical and diagonal syndrome mismatch, the number of channels in error in any one set not exceeding 3 while the aggregate of channels in error cannot exceed 4.

10. In an apparatus for decoding data written into a plurality of parallel channels as defined in claim 9, means responsive to a match between the vertical and diagonal syndromes intersecting the same error for generating a first chan-nel in error pointer as a function of the bit position displacement in the in-channel direction between the vertical and diagonal check-ing bit positions, the errors being confined to only one unknown chan-nel in the first set and at most two channels in the second set.

11. In an apparatus according to claim 10, wherein the channel pointer means includes a free-running ring counter of the count-down type;
first means responsive to the occurrence of a diagonal syndrome for setting the ring counter to a predetermined value; and second means responsive to the occurrence of a vertical syndrome for inhibiting the ring counter and gating out its contents.

12. In an apparatus for decoding data according to claim 9, where-in the means for generating a pointer to an unknown error channel responsive to a pointer designating a known error channel includes a first and second free running cyclic counter, said first counter being of the count-down type while the second counter being of the count-up type; and means responsive to the external pointer for set-ting both counters to a value indicative of the known channel in er-ror, the counters respectively being decremented or incremented each time the bit position along the channel changes until a vertical syn-drome is detected as not being equal to the other syndromes in the first set.