CA1103369A - Multi-instruction stream branch processing mechanism - Google Patents

Abstract

MULTI-INSTRUCTION STREAM BRANCH PROCESSING MECHANISM
ABSTRACT
In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from three independent instruction streams identified by multiple branch instructions, some of which may be conditionally executed. A number of pointers identify a particular one of the multiple instruction buffers. A first pointer identifies one of the instruction buffers which is to receive the target instruction identified by a branch instruction decoded from another instruction stream contained in another instruction buffer. Various branch instructions are predicted to be successful or unsuccessful, and in response to this prediction, a second pointer is set to control gating of the proper instruction to an instruction decoding mechanism, either from the original instruction stream of the branch instruction or from the instruction buffer which contains the target instruction. A third pointer identifies the one of the multiple instruction buffers which contained the instruction last transferred to the instruction execution unit. A fourth pointer, contained in a queue of predecoded instructions, and which is associated with each branch instruction to be presented to the instruction execution unit, identifies the one of the instruction buffers which was enabled to receive the target instruction. Result signals from the instruction execution unit, in response to execution of conditional branch instructions, will reset various pointers and busy triggers associated with each instruction buffer, set one pointer to the same condition as another pointer, or leave certain pointers in a present state, such that the next sequential instruction to be transferred to the instruction execution unit is from the proper instruction stream based on the result of the branch on condition instruction.

Description

13 Field Of The Invention The present invention relates 14 to data processing systems and more particul~rly to data processing systems which encounter conditional branch 16 instructions in an instruction preprocessing unit which 17 prefetches, predecodes, and queues multiple instructions 18 for sequential presentation to an instruction execution 19 unit.
Prior Art The IBM System/370 Family of Computers 21 defined by the System/370 Principles of Operations, Form 22 No. GA22-7000, are required to execute conditional 23 branch instructions. Conditional branch instructions 24 specify a condition to be tested for, and the address of a new instruction to be executed if a specified 26 condition is met. Otherwise, instruction processing 27 continues in sequence from the conditional branch 28 instruction. In high-performance, pipelined computers, 29 an instruction preprocessing function (IPPF) may be D-PO9-77-005 ~ -2-' ' . ` - :
- - - :: --' : .

1 used to prefetch instructions from main memory and

2 prepare a plurality of them for sequential execution

3 by an execution unit. When the IPPF decodes a conditional

4 branch instruction, a preceding instruction which will establish the condition to be tested may not have been 6 executed. It will therefore be uncertain as to whether 7 the instruction identified by the address information of 8 the branch instruction will in fact be executed. Some 9 strategy must be adopted to allow the IPPF to continue prefetching of instructions from memory and predecoding 11 of these instructions beyond the branch instruction to 12 maintain the queue of instructions for presentation to 13 the execution unit.
14 U. S. Patent 3,418,638 assigned to the assignee of the present application, issued December 24, 1968 to 16 D. W. Anderson et al and entitled "Instruction Processing 17 Unit For Program Branches" discloses the conditional 18 branch handling mechanism of the IBM System/360 Model 90.
19 Instructions were prefetched, predecoded and immediately transferred to a plurality of execution units whereby 21 overlapped instruction processing and execution could 22 be achieved. A complicated mechanism was provided for 23 transferring conditional branch instructions to various 24 execution units followed by further instructions which were especially marked as being conditional, and which 26 may or may not be executed dependent upon the outcome 27 of the conditional branch. The instruction unit contained 28 only a single set Gf instruction buffers which limited 1 the capability of the instruction unit to decode only 2 a single conditional branch instruction and prefetch 3 only a single target instruction stream.
4 U. S. Patent 3,551,895 which is assigned to the assignee of the present application and which issued 6 December 29, 1970 to G. C. Driscoll, Jr., entitled 7 "Look-Ahead Branch Detection System" discloses another 8 high performance computer system for prefetching and 9 predecoding instructions including conditional branch instructions. This patent discloses a requirement 11 for a special instruction called an "Advance Branch"
12 instruction which was utilized by an associative memory 13 and look-ahead trees for prefetching target instruction 14 streams when conditional branches were encountered.
Another prior, high-performance system, is the IBM
16 System/370 Model 168 which includes an IPPF for prefetching 17 and predecoding a plurality of instructions to be presented 18 in sequence to an execution unit. In the System/370 19 Model 168-III Theory of Operations, Diagrams Manual (Vol. 2), I-Unit, Form No. SY22-6932-3, the IPPF mechanism 21 is fully described. In this system, two separate 22 instruction buffers are included such that prefetching 23 and predecoding of instructions either from the instruc-24 tion stream of a conditional~branch instruction, or from the target instruction stream can be effected. A
26 prediction is made during decode of conditional branch 27 instructions as to w~ether or not the branch is likely 2~ to be successful or unsuccessful. Further decoding 1 from either the original instruction stream or the 2 target instruction stream will be effected based on 3 this prediction, and preprocessed instructions will 4 be buffered in a queue for sequential presentation to the execution unit. The success or failure of a 6 condition tested will ultimately determine whether the 7 previously decoded instructions are from the proper 8 instruction stream. Since only two instruction buffers 9 are provided, only the set or reset state of a trigger is required to control the proper gating of instructions 11 to a decoding mechanism from the proper one of the two 12 buffers.
13 The provision of only two instruction buffers in 14 the System/370 Model 168, permits only a single conditional branch instruction to be outstanding at 16 any one time. If a second conditional branch instruction 17 is detected in the instruction decoding mechanism, the 18 IPPF mechanism must cease functioning until the first 19 conditional branch is resolved, because a second target instruction stream may not be prefetched.
21 SUMMA~Y OF T~E INVENTION
22 It is the principle object of the present invention 23 to provide a high-performance, highly-overlapped, data 24 processing system capable of prefetching, predecoding, and queueing multiple instructions beyond two pending 26 conditional branch instructions.
27 In accordance with the present invention, the IPPF
28 mechanism includes three separate instr~ction-fetching 29 mechanisms referred to as instruction streams A, B, and C.

6~

1 Each instruction stream includes an instruction address 2 register (Instruction counter) and a set of four, double-3 word buffers for storing prefetched instructions from 4 storage. The prefetching of instructions into the instruc-tion buffers and selection of one of the three instruction 6 buffers for gating of individual instructions to an 7 instruction decoding register is controlled by logic which 8 keeps track of the status of each instruction stream, 9 allocates instruction streams to target instruction streams, deallocates or resets instruction streams based on the 11 results of conditional branch instructions, and manages 12 a set of instruction stream pointers that control stream-13 related activities throughout the IPPF.

FIGURE 1 is a block diagram of the major functional 16 units of a data processing system including an instruc-17 tion preprocessing function (IPPF).
18 FIGURE 2 is a block diagram showing the major 19 functional units of an IPPF.
FIGURES 3A, 3B, and 3C when arranged vertically, are 21 a more detailed bloc~ diagram of an IPPF.
22 FIGURE 4 is a block diagram of an execution unit 23 showing those por~ions responding to, and signalling the 24 resul~ of, conditional branch instructions.
FIGURE ~ shows the format of System/370 branch 26 instructions.
27 FIGURE 6 is a logic diagram for predicting whether 28 the results of branch instructions will be successful 29 or unsuccessful.

336~

1 FIGURE 7 is a block diagram showing the coding of 2 branch status information from instruction decoding, 3 and signals generated in the execution unit indicating 4 the result of the branch testing function.
FIGURE 8 is a more detailed logic diagram of the 6 branch result decoding shown in FIGURE 7.
7 FIGURE 9 is a block diagram showing pointers utilized 8 for controlling the ingating and outgating of three 9 instruction stream buffers.
FIGURE 10 is a timing diagram showing various 11 timing relationships between a request for an instruction 12 fetch to storage and the return of instructions for gating 13 into instruction buffers.
14 FIGURE 11 is a state diagram of the instruction fetch sequencer associated with each instruction stream buffer.
1~ FIGURE 12 is a timing diagram showing the relation-17 ship of instruction decoding to instruction queueing 18 and presentation of instructions to an execution unit 19 in sequence.
FIGURES 13A and 13B are a logic diagram of the 21 ingating ~nd outgating control of one of the instruction 22 stream buffers.

24 FIGURE 1 shows the major functional portions of a high-performance data processing system. A major 26 portion of the present invention is found in an 27 Instruction Preprocessing Function (IPPF) 20. The D-PO~-77-005 -7-36~

1 IPPF 20 communicates with a Processor Storage Control 2 Function (PSCF) 21, which includes a high speed buffer 3 or cache, to obtain sequences of instructions from 4 Processor Storage 22, and initiate the transfer of data operands to an execution unit or E-Function unit 6 23. The IPPF 20 also communicates with the E-Function 7 23 to transfer instructions one at a time, in sequence, 8 to the E-Function 23. Results of instruction executions g in the E-Function 23 will be communicated back to the IPPF 20 to provide control to dictate the sequence of 11 instruction execution.
12 Remaining portions of a data processing system, 13 not pertinent to an understanding of the present 14 invention, include Channels 24, a Console 25, and Maintenance and Retry Controls 26.
16 FIGURE 2 depicts four major functional areas 17 within the IPPF 20 of FIGURE 1. These include three 18 instruction stream prefetch logic 27, instruction 19 predecode 28, address formulation 29, and an interlock mechanism 30. The IPPF 20 will be shown to have the 21 ability to store, or queue, four predecoded instruc-22 tions for presentation in sequence, one at a time, 23 to the E-function 23. This includes information as to 24 data operands to be fetched, general purpose registers to be utilized, starting address information for a 26 microprogram controlled control store, and various 27 other control signals to be more fully described. A
28 great number of the instructions to be decoded require D-PO~-77-005 -8-llU336~

1 address arithmetic to be accomplished in the IPPF 20 2 and therefore address formulation logic 29 is provided.
3 A number of interlocks 30 are required to insure that 4 proper data for use in address formulation and instruction predecoding is available prior to entry of decoded instruc-tion information into the four-position queue.
7 It is a major function of the present invention to 8 control the logic and gating circuitry of the three 9 instruction stream prefetch mechanism 27. This mechanism includes three separate instruction buffers, each 11 capable of storing a plurality of instructions from 12 three separate instruction streams to be utilized, one 13 at a time, in the instruction predecode mechanism 28.
14 It is the control of the three separate instruction buffers in response to encountering conditional branch 16 instructions which gives rise to the present invention.
17 When FIGURES 3A, 3B, and 3C are arranged vertically, 18 more detail of the IPPF 20 iS shown. In block diagram 19 form, FIGURE 3A comprises the instruction fetching and decoding logic. FIGURE 3B comprises the address 21 arithmetic logic, and FIGURE 3C shows some of the 22 interlock mechanism associated with the IPPF 20.
23 In FIGURE 3A, three separate sets of instruction 24 buffer registers, noted generally at 31, 32, and 33, are shown. Each set of instruction buffer registers, noting 26 the set labeled I-Buffer A in particular, when selected, 27 will receive 64 bits of instruction information each -~1~3;}69 1 time an instruction fetch request is transmitted to the 2 PSCF 21. Depending on the instruction address counter 3 value associated with a particular set of instruction 4 buffers, the ~4 bits of instruction information will be gated into a particular one of the four registers shown.
6 Therefore, 32 eight-bit bytes of instruction information 7 can be prefetched and stored in each of the sets of 8 instruction buffers 31, 32 or 33.
9 In the disclosed system, instructions will be decoded one at a time in the IPPF 20. The particular 11 instruction to be decoded in the proper sequence will 12 be transferred to an I-Register 35 which will contain 13 32 bits of instruction information. A set of gates 14 noted generally at 36 will be energized in accordance with instruction counter address information to transfer 16 the proper one of a plurality of instructions from the 17 one of the instruction buffers currently being utilized 18 during instruction execution to the I-Register 35 for 19 subsequent decoding. The set of gates 36 shown are necessary to accommodate the fact that in the IBM System/360 21 and System/37~ architecture, instructions can be of varying 22 lengths, including two 8-bit bytes, to four or more bytes.
23 Various gate combinations will be enabled to insure 24 that for each instruction to be decoded, the 8-bits of the operation code will be placed in bits 0-7 of 26 the I-Register 35. Depending on the format of the 27 particular instruction being decoded from I-Register 28 35, bits B-15 may be mask bits, coded information D-PO9--77-005 -1~-li~3369 1 concerning the length of variable field operands~ or 2 addresses of General Purpose Registers. Bits 12-15 3 and 16-19 may designate particular ones of sixteen 4 general purpose registers in accordance with address formulation in the System/360 and System/370 architecture.
6 Bits 20-31, of four byte instructions, are a displacement 7 field entering into the generation of address information 8 for accessing data operands from storage.
9 The instruction decoding mechanism of the IPPF 20 includes hardware decode 37, array decode 38, and Control 11 Store Address Register (CSAR) decode 39. The decoding 12 of each instruction in I-Register 35 requires two clock 13 cycles within the system. During the first clock cycle, 14 certain information concerning the instruction being decoded must be available as quickly as possible and this 16 information is provided through the hardware decode 37.
17 Not until the second cycle of each instruction decode is 18 certain other information required and this information 19 is obtained from the array decode 38 where the OP-code bits 0-7 are used to address the random access array to 21 provide a plurality of control signal lines 40 and another 22 plurality of control signal lines 41.
23 The results of the instruction decodin~ function 24 just discussed are stored as instruction execution control information in one of four registers of an Instruction 26 Queue 42. Part of ~he execution control information 27 is received on a line 43 which is the 8-bits of the 28 OP code indicating the basic function to be performed D-PO9-77-~05 -11-36g 1 by the E-function unit. In many known microprogrammed 2 control systems, in which a control storage device contains 3 microprograms, the eight OP code bits would be utilized 4 to address the first micro instruction of a sequence of micro instructions to effect execution of the instruction.
6 To enhance the performance of the microprogram control 7 system, additional binary bits utilized for the first 8 cycle of access to the control store are provided on 9 line 44 which have been developed from the CSAR decode 39 which responds to mask information contained in 11 bits 8-15 of the instruction being decoded, and the control 12 signal lines 41 obtained from the array decode 38. Addi-13 tional execution control information is obtained from the 14 array decode 38 on line 40. Further, line 45 represents operand address information obtained from the address 1~ formulation mechanism to be discussed in connection with 17 FIGURE 3B. The execution control information from one 18 of the four registers of the Instruction Queue 42 will 19 be transferred to the E-Function 23 for each execution.
The prefetching of instructions in a particular 21 instruction sequence A, B, or C, into a particular one 22 of the instruction buffers 31-33, continues in parallel 23 with the presentation of a single instruction to the 24 I-Register 35, and presentation of execution control information to an empty one of the four registers of 26 the Instruction Queue 42. A signal from the E-Function 27 23, indicating completion of an instruction execution 28 by the E-Function 23, will be the signal which gates the 29 next execution control information, in sequence, from D-PO9-77-00~ -12-3365~

1 one of the four registers of the Instruction Queue 42 2 to the E-Function for execution. As long as an empty 3 register in the Instruction Queue 42 is available, 4 instruction decoding and entry of execution control information into the empty Queue 42 can proceed.
6 In addition to the ~act that all four registers of 7 the Instruction Queue 42 are full, indicating instruction 8 decoding should be suspended, certain other machine 9 conditions, broadly classified as interlocks, to be more fully discussed, may suspend instruction decoding. Part 11 of the instruction decoding process is the formulation of 12 storage addresses from combinations of address bits 13 contained in each instruction, and the data content of 14 instruction addressable general purpose registers in accordance with the IBM System/360 and System/370 16 architecture. An interlock, preventing or suspending 17 instruction decode, would be energized if an instruction 18 contained in the Queue 42 has not been executed, and this 19 instruction is to load information into a general purpose register to be utilized for forming an address of an 21 instruction presently contained in the I-Register 35. In 22 this situation, decoding of the instruction in I-Register 23 35 must ~e suspended until the information is availa~le 24 from the unexecuted instruction.
~5 The I~M System/360 and ~s~em/37Q architectures 26 specify instruction addressable general purpose registers.
27 The~e are normally physically contained and utilized in 28 an execution unit, and such is the case in the system 2~ being discussed. However, to speed up address arithmetic, 1 a second copy of the 16 general purpose registers is 2 contained in the IPPF 20. These are shown at 46. The 3 normal path, to be discussed, for entering information 4 into the general registers 46, is through a working register labeled C-reg. in the E-Function 23, and would 6 be entered into the general registers 46 on a line 47.
7 Lines 48 and 49 receive general register address infor-8 mation from the I-Register 35. The outputs of the general g register 46 are applied to the address arithmetic mechanism of FIGURE 3B to be discussed, along with 11 displacement address bits 20-31 from I-Register 35 along 12 lines labeled 52.
13 In FIGURE 3B, most of the address formulation hardware 14 of the IPPF 20 is shown. An address adder 53 receives the displacement bits 20-31 on line 52 and the output 16 of general registers 46 on lines 50 and 51 to provide 17 the IBM System/360 and System/370 architected storage 18 address information which is a summation of twelve dis-19 placement address bits 20-31 (D2), twenty-four address bits representing a base value (B2), and 24 bits of 21 index information (X2).
22 Another input to the address adder 53 is from a line 23 54 which originates from a bypass mechanism 55 in FIGURE
24 3A. The bypass mechanism 55 is utilized to recognize those interlock situations in which the instruction contained 26 in I-Register 35 re~uires data from a general register 46 27 which has not yet received this data from storage in 28 response to a previously decoded instruction. When the 29 data is returned from storage in response to the previously llG336,~

1 decoded instruction, bit positions 40-63 on the buffer 2 data bus 34 will be diverted by the bypass mechanism 3 55 to the proper input of the address adder 53 at the 4 same time the data is being returned, in the normal fashion, tO the general registers in the E-Function 23, 6 and through the C register into the general registers 46 7 on line 47. This mechanism permits the resumption of 8 instruction decoding of the instruction in I-Register 9 35 at least one cycle earlier than if the bypass mechanism 55 were not present.
11 FIGURE 3~ shows additional address formulation 12 logic referred to generally at 29 in FIGURE 2. A
13 length incrementer 56 has two inputs, one of twenty-four 14 bits and another of eight bits, and an output of twenty-four bits. The twenty-four bit input is from a group 16 of triggers designated as the Process Address Register 17 (PRAR) 57, and the 8 bit input is from a group of 18 triggers designated as the Length Register (LR) 58.
19 The twenty-four bit output feeds a group of latches designated as the Process Adder Latches (PRAL) 59, 21 Address Incrementer Latches 60, and various compare 22 circuits to be further identified. The input to PRAR
23 57 is from PRAL 59 which can be initialized from the 24 Address Adder 53, an Address Incrementer 61, or a bus 62 from the E-Function 23. The input to LR 5~ is 26 from Length Logic 63 of FIGURE 3A via length latches 27 (LL) 64, and is a result of the needs of variable field 28 length operand instructions being decoded.
D-PO9-77-005 -lS-llC~369 1 A further set of latches 65 are shown at the out-2 put of the Address Adder 53. The address information 3 in PRAL 59 is transferred to the PSCF 21 on a bus 66 for 4 accessing storage. The output of the incrementer latch register 60 is presented to the E-Function 23 on a bus 67 6 to a working register identified as a C Register. The 7 address information transferred on bus 67 to the E-Function 8 23 is for the purpose of providing address information g to the E-Function 23, when the E-Function 23 is required to send address information to the PSCF 21.
11 A number of 24 bit address registers are shown in 12 FIGURE 3B. These registers are provided address infor-13 mation from the output of the Address Adder latch 65, 1~ or address incrementer latches 60, and all provide outputs back to the address incrementer 61 on a bus 68. The 16 Translation Exception Address register (TEA) 69 is 17 utilized during a system state of a virtual memory 18 system wherein, prior to access requests to storage, 19 where address translations may not have previously been done, a trial search for an address translation can 21 be attempted. The TEA register 69 holds the logical 22 address associated with an access exception detected 23 during preprocessing of an instruction in I-Register 24 35, but has meaning only when operating in the trial mode. The register 69 can be set from the Address 26 Adder latches 65, or the incrementer latches 60.

11C~336Y

1 A Source Address register (SRC) 70 and a Destina-2 tion address register (DST) 71 each consist of 24 bits.
3 Registers 70 and 71 are used primarily for holding 4 source and destination fetch addresses in accordance with the source and destinations utilized in IBM
6 System/360 and System/370. The registers 70 and 71 7 can be initialized from the Address Adder latches 65 8 for IPPF 20 generated requests, and from the bus 62 9 via the incrementer latches 60 for E-Function 23 generated re~uests. The registers 70 and 71 can be 11 incremented or decremented via the incrementer 61 12 and their contents can be made available to the 13 E-Function 23 on bus 67.
14 Twent~-four bit address registers 72 through 77, designated OAA through OAF, are each associated, on a 16 one to one basis, with six operand buffers located in 17 the E-Function 23. An operand address register/operand 18 buffer pair, along with their associated controls are 19 capa~le of fetching a singl~ double word from the PSCF
21 and holding it. The address incrementer 61 is 21 available to the operand fetching mechanism. Any one 22 of the operand address registers 72 through 77 may be 23 gated to the Address Incrementer 61 and have 0 or 8 added 24 to it, and the Incrementer 61 output may be gated back 2S to any of the operand address registers 72 through 77.
26 There are two fetching mechanisms in the IPPF 20 which D-PO9-77-a05 -17-~lu336s 1 share the register 72 through 77. One is known as 2 the destination fetching mechanism and the other is 3 known as the source fetching mechanism. When both 4 mechanisms are active, each is allowed to use three operand address re~isters. When only the source 6 mechanism is active, on certain instructions, it may 7 use all available operand address registers.
8 The remaining twenty-four bit address registers 9 78, 79, and 80, labeled IAA, IAB, and IAC, respectively, are each associated with the sets of instruction 11 buffers 31, 32, and 33 respectively, and represent 12 Instruction counters. The contents of the active 13 instruction address register 78, 79, or 80, which is 14 being utilized to fetch instructions from the PSCF
21 on bus 35 of FIGURE 3A, is incremented by eight 16 between fetches under control of its sequencer.
17 The content can also be decremented by 8 or 16 in the 18 Address Incrementer 61 in the event that the PSCF 21 19 rejects a request or re~uests, and the address must be recreated.
21 Continuing with the discussion of instruction 22 accessing and the manipulation of address information 23 in instruction address registers 78 through 80, 24 FIGURE 3C shows a difference register 81, 82, and 83 2S associated with each of the instruction address 26 registers 78 through 80. Each difference re~ister 81 27 through 83 consists of five bits, and contain the ~ia33g~

1 value which must be subtracted from its associated 2 address registers 78 79, or 80 to obtain the instruction 3 counter value of the associated instruction stream A, 4 B, or C in the I buffers 31 through 33 in FIGURE 3A.
When an instruction address registers 78, 79 or 80 6 is initiated with a new value, the associated difference 7 register 81, 82, or 83 is set to 0. Thereafter, the 8 difference register of the active I-stream A, B, or C
g is subject to an update on each cycle. If the associated instruction address register is incremented 11 or decremented, the difference register 81, 82, or 83 12 is updated by an associated adder 84, 85, or 86 by an 13 equal amount. The amount may be plus 8, minus 8, 14 or minus 16. During the first cycle of execution from its associated instruction stream A, B, or C, 16 the difference register 81, 82 or 83 is decremented 17 by a value equal to the length of the instruction 18 transferred to the instruction register 35 of 19 FIGURE 3A. The value may be minus 2, minus 4, or minus 6. If the instruction being gated to the E-21 Function 23 from the instruction queue 42 of FIGURE 3A
22 is a System/360 or 370 Branch and Link instruction, 23 the difference re~ister 81 through 83 associated with 24 the instruction stream 31 through 33 from which the ~ranch and link instruction has been obtained, is 26 decremented by an additional value equal to the length 27 o~ the instruction. When it is necessary to calculate 28 the instruction counter value for a particular one of D-PO9-77-0~5 -13-11~36~

1 the instruction streams 31 through 33, the associated 2 difference register 81 through 83 is subtracted from 3 the associated instruction address register 78 through 4 80 in the Address Incrementer 61.
The remaining block diagram of FIGURE 3C relates 6 to certain interlocks noted generally at 30 in FIGURE
7 2. A number of compare circuits, one of which is 8 noted at 87, detect various equality conditions between 9 the address information on line 88 from the Length Incrementer 56 of FIGURE 3B, and address information on 11 a line 89 from the PRAR 57 of FIGURE 3B. The IBM
12 Sy~tem/360 or 370 architecture includes an instructiGn 13 format called SS, wherein two operands from storage, 14 each of which have a variable length are designated.
A companion comparator 90 to that of 87 will detect 16 a condition which must be recognized known as SS Word 17 Overlap. This condition, indicates that the source 18 and destination operands have fields which overlap 19 each other destructively.
Another situation which must be recognized, and 21 processed, is a situation where an instruction which 22 is execu~ing or awaiting execution in the instruction 23 Queue 42 of FIGURE 3A, is going to change an operand in 24 storage, and a subsequent instruction decodes a need for fetching the same operand from the same location.
26 In this situation, the data for the later instruction 27 must not be fetched until after the data from the ~i~336g 1 earlier one is stored. System/370 architecture requires 2 that this Operand Store Compare condition be detected 3 even in situations where the two references to the 4 location are made using different virtual addresses.
To accomplish this, the circuits detecting Operand 6 Store Compare will ignore bits 8 through 20. This 7 will result in some compares being detected which are 8 not real. To detect the Operand Store Compare condition, 9 each register position of the Instruction Queue 42 has two addresses associated with it which contain the 11 beginning and ending addresses (modulo 2K) of the storage 12 field which the instruction modifies.
13 The lower limit address is the logical address 14 from the instruction, and the upper limit address is generated in the Length Incrementer 56 of FIGURE 3B.
16 There is also a bit associated with each register of 17 the Instruction Queue 42 indicating that the instruction 18 is to alter storage. The lower limit (LL) address 19 information for each instruction queue register (0-3) is placed in an associated register 91 through 94, 21 and the upper limit (UL) address information is placed 22 in an associated register 95 through 98. As operand 23 address information is created in the Length Incrementer 24 56, it is indicated on ~usses 88 and 89. Compare circuits, shown generally at 99 and 100, detect the 26 situation in which an instruction being decoded in 27 I-Register 35 must be delayed until a previous store 28 is executed.

11(~336~

1 Another interlock situation is noted by compare 2 circuits noted generally at 101 and 102, which will 3 detect a situation where an instruction fetched from 4 storag~ has the same address indicated on bus 88 or 89 for an instruction being decoded which will store data 6 into the same location as the pre~etched instruction.
7 FIGURE 4 shows a block diagram of some of the 8 major registers and data paths within the E-Function 23 9 of FIGURE 2. The major unit of the E-Function is an Arithmetic and Logic Unit (ALU) 103 which consists of 11 a 64 bit adder, an 8-bit adder, 64 bit shifter, and 12 a multiply unit. Data to the ALU 103 will be applied 13 from a set of working registers 104 labeled A, B, C and 14 D. The working registers 104 are not addressable by programmed instructions, but are accessed through 16 execution sequeneing. A local store 105 is included 17 in the E-Function, and this is comprised of 16 general 18 purpose registers and four floating point registers 19 as specified in the architecture of IBM System/360 and 370, and are addressable by information in program 21 instructions. When data is to be entered into one 22 of the local store registers 105 from main storage, 23 the data will be received from the PSCF 21 on a bus 24 106. The data i~ entered into one of six operand buffers 107 labeled A through F. Operand buffers A through 26 F have been previously referred to in connection with 27 the associated operand address registers 72 through 77 28 in FIGURE 3B. The data received on bus 106 will be ~ 33~

1 transferred through one of the working registers 104, 2 and then over a bus 108 to the addressed local store 3 register 105. The address of the local store register 4 105 to be manipulated during an instruction execution is entered into local store address registers 109 which 6 receive the address information in turn over a bus 7 110 and 111, as part of execution control information 8 transferred from the Instruction Queue 42 of FIGURE 3A.
g As mentioned earlier, a set of addressable general purpose registers 46 is shown in FIGURE 3A and the bus 11 47 is shown where~y data being stored into an addressed 12 local store register 105 will also be transferred through 13 the C working register to the identical register in 14 the IPPF general register 46.
Other execution control information transferred 16 from the Instruction Queue 42 is entered into an E
17 register 112. This information includes the 8-bit 18 OP code of the instruction to be executed, and the 19 subsequent 8 bits of instruction information which may be either addresses of general purpose registers 21 105, or length information for variable field length 22 operands.
23 All data to be utilized in the ALU 103 may come 24 from two registers of the local store 105 through working registers 104, one operand from local store 105 and 26 another operand from an operand buffer 107, or intermediate 27 results from the ALU stored into a working register on a 28 ~us 113. Data to be stored in main store from the D-PO9-77-005 ~23-~lG336~

1 E-Function will be on a bus 114 at the output of the 2 64 bit shifter. As also shown, bus 62 from the output 3 of the 64 bit shifter is the input provided to the 4 address incre~enter latch 60 of FIGURE 3B.
In discussing the present invention, reference will 6 be made to branch status, and branch results. Shown in 7 block diagram form is branch result logic 115 which receives, 8 as part of the execution control information from the g Instruction Queue 42, branch status information on lines labeled 11~. The branch status signals on line 116 11 indicating a particular kind of branch instruction being 12 executed, will be logically combined with results from 13 the ALU 103 on a line 117 to signal back to the IPPF 20 14 the results of data manipulations which determine the success, or not, of conditional branch instructions.
16 Three signals returned to the IPPF to control the proper 17 sequencing of instruction execution in response to branch 18 instructions are provided on lines 118, 119, and 120.
19 Line 118 labeled BC Successful will indicate whether or not a branch on condition instruction has been successful.
21 The branch on condition instruction in IBM System/360 and 22 370 is an instruction which samples for a particular 23 condition code setting to determine whether or not a 24 target instruction of a branch instruction shouid be accessed. Line 119 labeled B=l will signal the results 26 of a branch instruction which looks for a value of zero 27 in the B working register. Line 120 labeled B ~ A, will 28 signal that the contents of B ~orking register are ~P~g-77-005 -24-11~336~

1 greater than the contents of the A working register.
2 Details for the generation of the branch status signals 3 116 and use of the branch results on lines 118, 119 and 4 120 will be more thoroughly described.
The basic sequence control for any instruction 6 execution is by means of microprograms, or microinstruc-7 tion sequences from a control store 121. Each microinstruc-8 tion read from the control store 121 will be entered into 9 a Control Store Data Register 122. The decoding of various fields within a microinstruction in register 122 will 11 create a number of control lines labeled 123 for energizing 12 and sequencing all the gating of information within the 13 E-Function 23. Another set of lines, labeled 124, include 1~ address information to be utilized in ~he Control Store Address Register (CSAR) 125, and control sequence of 16 microinstructions read from the control store 121.
17 At the completion of execution of any particular 18 instruction received from the IPPF, the control store 19 data register and control 122 wilL issue a signal to the IPPF 20 on a line labeled 126 and called IPPF END OP.
21 In response to the signal on line 126, the next 22 execution control information stored in the Instruction 23 Queue 42 of FIGURE 3A will be transferred to the E-24 Function. The starting microinstruction to be obtained from the control store 121 is addressed by a decoder 26 127 ~ased on ten address bits inserted into the control 27 store address register 125 from the Instruction Queue 28 42. The ten address bits are obtained as a result of D-PO9-77-0~5 -25-1~33G9 1 transferring on lines 128, the eight-bits of the OP code 2 to be executed. In addition, bits three and four of the 3 initial address in address register 125 are obtained 4 from the previously mentioned CSAR decode 39 of FIGUR~ 3A, and these bits are received on lines 129 and 130.
6 FIGURE 5 shows various conditional branch instruc-7 tions utilized in IBM System/360 and 370. There are four basic instructions called Branch on Condition, g Branch on Count, Branch on Index Low/Equal or High, and Branch and Link. Most of these are included 11 in two different formats, such as Branch on Condition 12 in which the target address, if the branch is to be 13 taken, is contained in a general purpose register 14 identified by four bits designated R2. In the other format, the address of the instruction to branch to, 16 or the target instruction, will be specified by the 17 address formulation achieved by adding together the 18 contents of base register B2, index register X2, and 19 the displacement field D2 of the instruction. In both formats, four bits labeled Ml, specify a mask 21 which indicates the particular condition code setting to 22 cause a branch. If the condition code setting is as ~3 specified by the code designated by the mask Ml, the branch 24 will be successful. ~hen the condition code setting does match the mask Ml, the signal BC Successful on 26 line 118 of FIGURE 4 ~ill be received by the IPPF 20.

~II336~

1 In the Branch on Count instruction, the content of 2 the general purpose register specified by Rl is 3 algebracally reduced by 1. When the result is 0, 4 normal instruction sequencing proceeds with the next instruction in sequence. When the result is not 0, 6 the next instruction executed will be accessed from 7 the target instruction address. The results of the 8 incrementing of the register specified by Rl ~ill be g manifested in the B working register and signalled on line 119 labeled B=l.
11 There are two Branch and Index instructions labeled 12 Branch on Index High, and Branch on Index Low or Equal.
13 In these instructions, an increment is added to the 14 operand specified by Rl, and the sum is compared algebracally with a comparand. Subsequently, the 16 sum is placed in the first operand location regardless 17 of whether the branch is taken. In the Branch on Index 18 High, when the sum is high, the instruction address is 19 replaced by the target instruction address. In the Branch on Index Low or Equal, when the sum is low or 21 equal, the instruction address is replaced by the target 22 instruction address. The results of the comparison called 23 for are indicated on line 120, labeled B ;~ A.
24 In the Branch and Link instruction, the instruction counter value i5 stored as link information in the 26 general purpose register specified by Rl. Subsequently, 27 the next instruction is taken from the target instruction 28 address information. This instruction becomes conditional ~1~336~

1 as a result of the ability of a programmer to insert 0 2 in the R2 field of the BALR instruction. In this case, 3 the link information will be stored in the register 4 designated by Rl, but branching to the target address will not take place.
6 When utilizing conditional branch instructions, 7 of IBM System/360 or 370, the instructions are utilized 8 in such a way that a guess can be made whether the branch 9 condition will exist, and that the target instruction will be executed next. Further, a programmer can insert certain 11 ~it patterns in the instruction fields having mask bits, 12 or specify a general purpose register of 0, to cause the 13 branch instruction to always be successful or never 14 successful.
FIGURE 6 shows the logic by which the predictions 16 are made with regard to the success or failure of detecting 17 a particular branch condition. An OR circuit 131 will 18 provide an indication on line 132 indicating that the 19 branch will probably be successful. OR circuit 133 will provide a signal on line 134 where the coding is such 21 that it is kncwn that the branch is successful, and that 22 the target instruction address will be utilized. OR
23 circuit 135 will provide a signal on line 136 in those 24 situations where the programmer has inserted certain information in the instruction fields which will 26 invariably cause the next instruction in sequence after 27 the branch instruction to be executed. As shown at OR
28 circuit 131, when either of the Branch on Index D-PO~-77-005 -28-~1~`336~

1 instructions is decoded, it is assumed the branch will 2 be successful and therefore the target instruction 3 should be the next instruction executed. If the results 4 signalled on line 119, as to the contents of the B
register, are not as expected, then corrective action 6 must be taken. This will be discussed subsequently.
7 The Branch on Count instruction is also assumed 8 to create the need for the target instruction. In the 9 case of the Branch and Link instruction (BAL), this should be guessed as successful and in fact is utilized 11 at OR circuit 133 to indicate that it is known that 12 the target instruction should be obtained. and executed 13 next. As indicated previously, however, if the programmer 14 has inserted 0 in the R2 field of the BALR instruction, the link information will be stored, but a branch will 16 not be taken. AND circuit 137 in FIGURE 6 indicates 17 this situation, and provides an input to OR circuit 135 18 indicating that a branch is not to be taken. AND
19 circuit 138 detects the BALR instruction with the R2 field not equal to 0, and provides an output to OR
21 circuit 131 and OR circuit 133 indicating that it is a 22 known successful branch instruction.
23 AND circuits 139 and 140 examine fields of the 24 ~ranch on Condition (BC) instruction to determine whether or no~ the mask ~ield is all ones or all zeros. An 26 output from AND circuit 139 provides an output from O~
27 circuit 133 indicating a situation where a branch will 2~ always be successful. AND circuit 140, which detects D-PO9-77-005 -~9-3~

1 that the mask field is all zeros, indicates the 2 situation where the programmer has chosen not to 3 cause a branch with this instruction in any situation, 4 and therefore OR circuit 135 will indicate that this is a no branch situation. AND circuits 141, and 142, 6 and OR circuit 143, examine fields of the Branch on 7 Condition instruction (BCR). A mask field of all ones 8 or all zeroes, and zero or non-zero values of field R2, 9 will indicate those situations where there will not be a branch ever, the branch is known to be successful, or 11 a guess successful condition is indicated, and must await 12 actual execution of the instruction to determine whether 13 or not the guess was proper.
14 AND circuits 144 and 145 examine the fields of the Branch on Count instruction BCTR. If the R2 field equals 16 0, it is considered not to be a branch, and if the R2 17 field is not zero, OR circuit 131 will indicate that 18 this is a branch that will probably be successful.
19 FIGURE 7 represents the coding of branch status signals inserted in three bit positions of any of the 21 four registers of the Instruction Queue 42. A table 22 146 shows the coding of the bits 147, 148 and 149 which 23 will be inserted in the branch status bits of each 24 register of the Instruction Queue 42 in accordance with the type of instruction to be executed. For example, 26 the branch status bits will be coded "000" when the 2 7 instruction queue register does not contain an ~8 instruction, or the instruc~ion inserted is to be D-PO~-77-005 -30-1 Il, ;~369 1 considered a no-branch instruction, including branch 2 instructions in which the logic of FIGURE 6 has 3 determined that it is not to be considered a branch 4 instruction. The coding "010" will be inserted in the Branch status bits of the instruction queue register 6 which contains a Branch on Condition instruction.
7 Coding "011" will be inserted whenever OR circuit 133 8 f FIGURE 6 provides an output. The remaining code g combinations show the indications for various other conditional branch instructions.
11 The block 150, labeled Branch Result Decode contains 12 logic, to be described, which combines the branch status 13 information on lines 147, 148, and 149 contained in 14 the branch status bits of the instruction queue register of a branch instruction, with execution result signals 16 from the E-Function 23 on lines 118, 119 or 120, after 17 completing execution of the associated conditional 18 branch instruction.
19 The branch status information, instruction execution results signalled from the E-Function, and the binary 21 state of line 132 in FIGURE 6, indicating that a guess 22 successful or gue~s unsuccessful has been made, provides 23 inform~tion to the IPPF 20 which insures that the next 24 instruction transferred from the Instruction Queue 42 to the E-Function 23 is from the proper one of three 26 instruction streams. That is, either the next instruc-27 tion in sequence after the branch instruction, or 28 the target instruction which has been fetched utilizing 1 the address information in the conditional branch 2 instruction will be transferred. The outputs from the 3 Branch Result Decode lS0 include signals indicating 4 that the branch was successful, and that the guess was right or wrong, or the branch condition was found to 6 be unsuccessful, and the guess was right or wrong. These 7 various conditions are indicated on signal lines numbered 8 151 through 154 respectively.
9 FIGURE 8 shows detailed logic of the Branch Result Decode 150 of FIGURE 7. The branch execution result 11 signals 118, 119, and 120 are shown, as are the branch 12 status bits on lines 147, 148 and 149. The signals on 13 lines 155, 156, and 157 are the inverted binary value 14 of the signals on lines 118, 119, and 120. The detailed logic combines all of these various signals, and provides 16 the output signal lines 151 through 154 indicating whether 17 the branch was successful or unsuccessful and whether or 18 not the original assumption was right or wrong.
19 Returning now to a discussion of FIGURE 3A, reference will be made to the general problem encountered when 21 conditional branch instructions must be executed. Each 22 of the set of registers which make up the three Instruction 23 Buffers 31, 32, and 33 have a number of input gates and 24 output gates, such as shown at 3 6. Each also have a set of hardware triggers and logic which respond to the empty 26 or full status of the registers, and the present value of 27 the associated Instruction Address register 78, 79, and 28 80. These hardware sequencers coordinate instruction fetch \

11~33~

1 requests to the PSCF 21 for associated instruction 2 streams A, B, and C, and coordinate the transfer of 3 variable length instructions from the proper instruction 4 buffer register to the I-register 35. An Active trigger and a Busy trigger is also associated with 6 each of the Instruction Buffers 31 through 33. When 7 a conditional branch instruction is decoded in I-register 8 35, an instruction buffer which is not active or busy 9 will be identified and made active and busy, and the associated hardware triggers and logic will be 11 activated to make an instruction fetch request to the 12 PSCF 22. ~hen the target instruction of the conditional 13 branch is returned on the data bus 34, it will be gated 14 into the instruction buffer that has been activated.
At the time the execution control information 16 of the conditional branch instruction in I-register 17 35 is transferred to the Instruction Queue 42, a 18 guess will have been made in accordance with the logic 19 shown in FIGURE 6, as to whether or not the conditional branch will be successful or unsuccessful. Based on this 21 guess the next instruction to be transferred to the 22 I-register 35 will either be from the instruction 23 buffer containing the conditional branch instruction, 24 or from the instruction buffer which has received the target instruction stream. Instruction decoding will 26 then continue, and execution control information 27 transferred to the Instruction Queue 42. If a second 28 conditional branch instruction is decoded, and one of 11~336~

1 the Instruction Buffers 31, 32 or 33 is not active, 2 a third instruction fetch for a third instruction 3 stream may be initiated, and the same determination 4 as to the success of the conditional branch instruction made.
6 As execution result signals for conditional 7 branch instructions are returned to the IPPF 20 from 8 the E-function 23, and compared with the branch status 9 information contained in the Instruction Queue 42, in accordance with the showing in FIGURE 8, adjustments 11 may have to be made for having made a wrong guess as 12 to the success of the conditional branch instruction.
13 If the original guess as to the success of the 14 conditional branch was correct, instruction decoding and execution will proceed in accordance with that 16 guess. If the original guess was wrong, the execution 17 control information contained in the Instruction Queue 18 42 from subsequently decoded instructions will be 19 destroyed, and the next instruction from the proper instruction stream will be transferred to the I-register 21 35 for decoding.
22 FIGURE 9 shows the logic for responding to the 23 original guess, as to the success of a conditional branch 24 instruction, and the return of execution result signals, for thereafter insuring that execution control information 26 is transferred to the E-function in the proper sequence.
27 The coordination of the proper sequence of instruction 28 execution control information transferred to the D-~09-77-005 -34-il~3;~

1 E-function 23 from the Instruction Queue 42 of the 2 IPPF 20, is by means of four pointers, each of which 3 is comprised of two binary triggers. The decoding 4 of the pointers identify a particular one of the Instruction Buffers 31, 32 or 33 which are associated 6 with instruction streams A, B, or C respectively.
7 The two-bit pointers include a Decoding Pointer 8 158 which will energize signals on a line 159 to the 9 I-register In-gates 36 associated with the instruction buffer from which instructions are being transferred 11 to the I-register 35.
12 The Execution Pointer 160 identifies the instruction 13 stream A, B, or C which is the source of the instruction 14 execution control information which was last transferred to the E-function 23. The decoding of this information 16 will be utilized to enable the associated difference 17 register 81, 82, or 83 shown in FIGURE 3C, and this is 18 accomplished over a line labeled 161 and called Difference 19 Register Update.
The Next Target Stream Pointer 162 responds to the 21 setting of Busy triggers 163, 164 and 165 associated 22 with each of the instruction streams A, B and C, to 23 identify a particular one of the Instruction Buffers 24 31, 32 or 33 which is to be activated to receive the target instructions identified by a conditional branch 26 instruction. Depending on the success of conditional 27 branch instructions, the instruction buffers will be 28 made busy and not busy in various se~uences, and ii(~33~

1 therefore the set and reset state of Busy triggers 2 163 through 165 will be decoded, and a line 166 will 3 be effective to control the state of the next target 4 stream pointer 162.
A fourth pointer 167, labeled Target Buffer 6 Pointer is part of the execution control information 7 placed in each of the registers of the Instruction 8 Queue 42. When a conditional branch instruction has 9 been decoded, and the execution control information transferred to the Instruction Queue 42, the identity 11 of the instruction buffer which is to receive the 12 target instruction stream is transferred to the 13 associated Target Buffer Pointer. 167 14 The output of an A~D circuit 168 is effective to render the remainder of the logic of FIGURE 9 16 effective. Any time a branch instruction is decoded 17 in I-register 35, a line 169 will be enabled. One 18 interloc~ which is required to permit continued 19 decoding of a conditional branch in the I-register 35, is the recognition by an Inverter 170 and an AND circuit 21 171 that there is at least one instruction buffer which 22 i5 not busy, and can receive a target instruction stream.
23 The final input to AND circuit 168 is from an Inverter 24 172 which receives the signal on line 136 from FIGURE 6 indicating that the coding of the conditional branch 26 instruction in I-register 35 is such that it is to be 27 considered not a branch instruction. Therefore, 28 sequencing of instructions should continue in the same 29 instruction stream.

11~3369 1 As mentioned earlier, each of the three instruction 2 streams A, B, and C have an associated Active trigger 3 173, 174, and 175, which when set, will activate I-Fetch 4 Sequencers 176, 177, and 178. The I-Fetch Sequencers S are a set of triggers and logic which monitor the 6 associated Instruction Buffers 31, 32, and 33 which 7 are active, and determines the full or empty status 8 of the registers which comprise the buffers to 9 initiate instruction fetches as required. The state of the sequencers for each of the instruction streams 11 is used to control I-Buffer A, B, or C In-gates on 12 a line labeled 179.
13 When a conditional branch instruction has been 14 decoded and the execution control information trans-ferred to the Instruction Queue 42 of FIGURE 3A, the 16 output 180 of AND circuit 168 will be effective at 17 a gate represented at 181 to transfer the contents 1~ of the Next Target Stream Pointer 162 to the Instruction 19 Queue 42 register which receives the conditional branch execution control information, and will enter this information 21 into the Target Buffer Pointer 167 of the register.
22 At the same time, the contents of the Next Target 23 Stream Pointer 162 will be effective through lines 24 182 and 183 to turn on the Active trigger and Busy 2~ trigger associated with the Instruction Buffer 31, 26 32 or 33 which is to be activated to receive the 27 target instruction designated by the address infor-28 mation of the conditional branch instruction. Renderi~g il~3369 1 the Active trigger set will activate the proper I-Fetch 2 Sequencers to initiate instruction fetch for the target 3 instruction stream. The new state of the Busy triggers 4 163, 164, and 165 will update the Next Target Stream Pointer 162.
6 The output 18~ of A~D circuit 168 is also effective 7 at an AND circuit 184 and an AND circuit 185. If the 8 logic of FIGURE 6 indicates that the conditional branch 9 instruction is known to be successful, signal 134 will be effective at AND circuit 185 to cause the present setting 11 of the Decoding Pointer 158, through a gate 186, to turn 12 off the Active trigger of the Instruction Buffer 31, 32, 13 or 33 from which the conditional branch instruction was 14 obtained. This is possible because it is known that the next instruction to be executed is to come from the 16 target instruction stream.
17 In those situations where the logic of FIGURE 6 18 has provided a signal on line 132 indicating that 19 the conditional branch instruction will probably be successful (Guess Successful)/ AND circuit 184 will 21 provide an output and energize a gate represented at 22 187, to cause the setting of the Next Target Stream 23 Pointer 162, represented on line 182, to be effective 24 to set the Decoding Pointer 158 with the same value.
ThiS is required to indicate that the next instruction 26 to be executed after the conditional branch instruction 27 will probably come from the target instruction stream, 28 and should be transferred to the I-register 35 of li~

1 FIGURE 3A, and is controlled by the I-register In-gate 2 signal 159. If the logic of FIGURE 6 has not produced 3 the Guess Successful signal 132, then the Decoding 4 Pointer 158 is left in its present state and instruction decoding is continued in the same instruction stream 6 that contained the conditional branch instruction. This 7 is based on the assumption that the branch will not be 8 successful, and that instruction decoding should continue 9 in the same instruction stream. If the conditional branch is not of the known successful type, indicated on line 11 134, then the active trigger of the instruction stream 12 containing the conditional branch instruction is left 13 in an active state to continue instruction fetch 14 requests as required.
The Execution Pointer 160 identifies the 16 instruction stream from which instructions are being 17 transferred to the E-function 23 for execution. In 18 response to the execution result signals transferred 19 back to the logic of FIGURES 7 and 8, the Execution Pointer 160 must be set to the proper value identifying 21 the instruction stream to be utilized for further transfer 22 of instructions. Therefore, the energization of signal 23 lines 151 through 154 from the logic of FIGURE 8 have a 24 large effect on the setting of the Execution Pointer 160. The Execution Pointer 160 identifies the instruction 26 stream of the conditional branch instruction which caused 27 the signals on lines 151 through 154. If the Guess 2B Successful signal 132 was produced, the Decoding Pointer 29 158 was set to identify the target instruction stream.
~-PO9-77-005 -39-il~33t~

1 If signal line 154 is energized, indicating the 2 branch was unsuccessful (a wrong guess), a gate 3 represented at 188 will be enabled to transfer the 4 setting of the Execution Pointer 160 to the Decoding Pointer 158 on a line 189. This has the effect of 6 causing the instruction, next succeeding the conditional 7 branch instruction in the same instruction stream, to 8 be transferred to the I-register 35. Energizing gate 9 188 will also have the effect, on lines 190 and 191, of streams other than the instruction stream that contained 11 the conditional branch instruction and instruction next 12 succeeding it in the same instruction stream.
13 If it was assumed that the conditional branch 14 instruction would not be successful, the Decoding Pointer 158 would have remained set to identify the 16 instruction stream containing the conditional branch 17 instruction. If the branch proved to be successful, 18 (a wrong guess) line 152 from the logic of FIGURE 8 19 would be energized. This represents a situation where decoding should have proceeded from the target instruction 21 stream, and that execution of the next instruction by the 22 E-function 23 should be from the target instruction stream.
23 Therefore, line 152 ~ill be effective at a ~até represented 24 at 192, to cause the Target Buffer Pointer 167 contents, represented on a line lg3, to be effective on lines 1~4 26 and 195, to set both the Decoding Pointer 1~ and 27 E~ecution Pointer 160 to identify the target instruction ~1~33~

1 stream. The Decoding Pointer 158 will then indicate 2 that the target instruction should be transferred 3 to the Instruction Register 35 for decoding, and 4 that the next instruction to be transferred to the E-function 23 should come from the target instruction 6 stream identified by the Execution Pointer 160. The 7 enabling of gate 192 will also be effective on line 8 191 to deactivate all the Active and Busy triggers 9 for the instruction buffers, other than the instruction buffer containing the target instruction stream repre-11 sented by the Target Buffer Pointer 167.
12 Whether the original guess for a conditional 13 branch instruction was that it would be successful 14 or unsuccessful, and it is determined from the 1~ execution result signals that this guess was wrong, 16 either line 152 or line 154 will be enabled. These 17 lines will be effective on a line 196 to reset all the 18 instruction execution control information transferred 19 to the Instruction Queue 42 of FIGVRE 3A. This is required because the instructions decoded subsequent 21 to the conditional branch instruction, whether from the 22 same instruction stream or the target instruct1on stream, 23 will not now be executed by t~e E-function 23. Based on 24 the wrong guess, the Decoding Pointer 158 and Execution Pointer 160 will now identify the proper instruction 26 stream, and instruction decoding and execution from the 27 proper instruction stream can proceed.
28 If the conditiona~ branch instruction executed 29 was unsuccessful, and this was a correct guess, line 336~

1 153 from the logic of FIGURE 8 will enable a gate 2 represented at 197. This will cause the contents of 3 the Target Buffer Pointer 167, as represented on 4 lines 193, 198, and ultimately line 199, to cause the Active and 8usy triggers to be reset for the 6 Instruction Buffer 31, 32, or 33 which was activated 7 to receive the instructions fetched from the target 8 instruction stream. Although the instructions from 9 the target instruction stream were prefetched in anticipation of their possible use, they will not be 11 utilized, and since the original guess was that the 12 branch would be unsuccessful, the Decoding Pointer 158 13 and Execution Pointer 160 were not changed, and should 14 remain in their present state.
If the conditional ~ranch instruction executed 16 was successful, and this was a correct guess, line 151 17 will enable gates represented at 200 and 201. This 18 indicates that the next instruction that should be 19 transferred to the E-function 23 for execution, is the target instruction identified by the address information 21 of the conditional branch instruction. Therefore, the 22 instruction buffer represented by the Target Buffer 23 Po~nter 167 is ~he instruction buffer from which further 24 execution should proceed~ and this information is transferred from line 193 through gate 200, to line 202, 26 to set the Execution Pointer 160 to the same value. Prior 27 to setting the Execution Pointer 160 to correspond to the 28 setting of the Target Buffer Pointer 167, gate 201 will be 11(~33~

1 effective to cause line 199 to turn off the Active 2 and Busy trigger associated with the Instruction 3 Buffer 31, 32, or 33 which is the instruction buffer 4 that contained the conditional branch instruction.
Since the original guess as to the success of the 6 conditional branch instruction was correct, the 7 previous enabling of AND gate 184 and gate 187 would 8 have set the Decoding Pointer 158 to the value of 9 the target instruction stream buffer. Since the guess was correct, the Decoding Pointer 158 will 11 remain at this value for further instruction decoding.
12 In view of the fact that three sets of Instruction 13 Buffers 31, 32, and 33 have been provided in the IPPF
14 20, it is possible to decode a conditional branch instruction from instruction stream A, which will cause 16 instruction stream B to be fetched. Subsequent decodinq 17 of a conditional branch instruction from instruction 18 stream ~, can cause a target instruction stream C to be 19 fetched. It is also evident that since all of the pointers have two binary bits, it would be possible to add a fourth 21 set of instruction buffers, and thereby have the capability 22 of predecoding three conditional branch instructions. The 23 logic of FIGURE 9 is such that, as the execution result 24 signals of conditional branch instructions are returned to the IPPF 20, a proper sequence of execution control information 26 presented to the E-function 23 will be maintained.
27 FIGU~E 10 shows timing diagrams involved with 28 instruction fetch requests made by the IPPF 20 to the li(~3369 1 PSCF 21. The diagram at A shows the timing for 2 those operations where a Fetch request is made at 3 203, and the instruction requested is contained in 4 the high speed buffer, or cache, of the PSCF, so that data will be available on the bus at 205. The 6 instruction fetched will be available on the Data 7 Bus 34 of FIGURE 3A on the second cycle following the 8 fetch.
9 The wave form at B shows the timing if the PSCF 21 is unable to return an instruction on the second 11 cycle following the request. The PSCF 21 will return 12 a signal shown at 206, indicating Fetch Delayed, which 13 occurs 1-1/2 cycle after ~he Fetch request. This signal 14 is on for one cycle. When the PSCF 21 is ready to return the data at some later time, it will generate the Advance 16 signal 207, signalling the IPPF 20 that data will be on 17 the Data Bus 34, 2-1/2 cycles later.
18 The wave form at C occurs in situations where the 19 PSCF 21 must reject the fetch, and will turn on a trigger signal at 208 indicating that the Fetch request has 21 been Rejected. The IPPF 20 must then reinitiate the 22 operation after the delayed fetch. The state of a 23 No Delayed Fetch trigger is such that when it is off 24 as shown at 209, this indicates that the rejection has been because there is another delayed fetch in 26 progress. When an advanced signal is received at 27 210 from the previous request which had been delayed, 2~ the No Delayed Fetch trigger will be turned on at ~33~S~

1 210 signalling the IPPF 20 to reinitiate the instruc-2 tion Fetch at 211.
3 FIGURE 11 shows a state diagram and a table 4 representing the various settings of four sequence triggers shown generally at 212. These are the I-Fetch 6 Sequence Triggers 176, 177, and 178 of FIGURE 9 associated 7 with each set of Instruction Buffers 31, 32, or 33. These 8 triggers indicate status of any instruction fetch request 9 for a particular one of the instruction buffers, and indicate when the gates to the inputs of the registers 11 should be enabled to receive instructions from the Data 12 bus 34 shown in ~IGU~E 3A. The Cl cycles and C2 cycles 13 are cycles required for an instruction fetch when the 14 instruction is found in the high speed buffer, or cache, of the PSCF 21. The C2 cycle indicates the time at which 16 the Data Bus 34 should be sampled. The reference to 17 Dl and D2 cycles are with reference to cycles occurring 18 after return of the advance sign~l from the PSCF 21 when 19 a delayed instruction fetch has occurred. Reference to Dl (last) and D2 (last) cycles are those delayed fetch 21 request cycles that have been created because an 22 instruction fetch request required the instructions 23 to be transferred from main storage to the high 24 speed buff~r. In these situations, four double words, or a block of instructions~ will be returned to the 26 IPP~ 20. The signal E shown in the legend, will be the 27 indication from the PSCF 21 that the last double word 28 of a block instruction fetch is being returned. Through llC33~

1 all the various sequences of instruction fetches, 2 delayed fetches, rejections, etc., the sequence 3 triggers 212 will eventually reach a state where the 4 M trigger will be a binary 1. When the M trigger is a binary 1, and there is no reject or delay, the 6 Doubleword is on the Data Bus 34, and should be ingated 7 to the appropriate instruction buffer.
8 FIGURE 12 is a timing diagra~ relating to the 9 decoding of an instruction in I-register 35 of FIGURE 3A, and the transfer of the execution control 11 information to the Instruction Queue 42, followed by 12 transfer of this information to the Control Store 13 Address Register 125 of FIGURE 4 in the E-function 14 23. The Instruction Queue 42 has four register positions into which information is gated in response to the setting 16 of an Inpointer (INPTR) which steps in sequence from 17 register to register. The execution information is gated 18 out of the Instruction Queue 42, to the Control Store 19 Address Register 125 in response to the setting of an outpointer (OUTPTR). The inpointer is shown to be set 21 at position n at 213. When the instruction decode and 22 address formulation has been completed at 214, the 23 execution control information will be transferred at 24 215 to ~osition n of the Instruction Queue 42, and the inpointer will be set to the value of n+1. When 26 the instruction execution control information is 27 entered into position n, a busy trigger will be 28 turned on at 216. At 217, a trigger indicating that D-PO9-77-005 . -46-336~

1 the instruction is ready is turned on. As shown at 2 218, the OP code portion of the execution control 3 information in register n is constantly applied to 4 the input of the Control Store Address Register 125.
When the END OP signal 126 of FIGURE 4 is generated at 6 219, the OP code bits on line 128, and address bits 3 7 and 4 on lines 129 and 130 will be gated into the 8 Control Store Address Register 125. A trigger will be 9 set indicating that the OP code branch in the Control Store 121 has been taken. When this signal falls at 11 220, the outpointer will be changed to n+l at 221, 12 indicating the next of the registers of Instruction 13 Queue 42 to be gated to the E-function 23.
14 FIGURES 13A and 13B, when arranged in accordance with ~IGURE 13, depict the ingating and outgating 16 associated with Instruction Buffer 31 associated with 17 instruction stream A. Line 179, labeled In-gate Stream 18 A, corresponds to line 179 shown in FIGURE 9, which is 19 activated when instruction fetches are being made for Instruction Buffer 31. Each instruction buffer has 21 associated with it a two-bit Inpointer, bit positions 22 27 and 28 of which are initialized in accordance with 23 the setting of the corresponding Instruction ~ddress 24 register 78. Their settings, indicated on lines 222 and 223 respectively, when decoded in a Decoder 224, will 26 enable, for example, AND gates 225 through 228 when the 27 double word of instruction information received on 28 Data Bus 34 is to be entered into the first of the set 2g of registers making up Instruction Buffer 31. ~hat is, 33~

1 I-buffer A bit positions 0-63 shown in FIGURE 3A. As 2 instruction information is gated into Instruction Buffer 3 31 in accordance with the Inpointer bits 27 and 28, and 4 gated out of the instruction buffer as dictated by the variable length of instructions, the four double-word 6 registers of Instruction Buffer 31 will be filled in 7 sequence.
8 Decoders 229, 230, and 231, receive the binary 9 state of four triggers comprising an Outpointer for the corresponding instruction buffer. The Outpointer 11 is updated or modified in accordance with the length 12 of instructions transferred to I-register 35 shown in 13 FIGURE 3A. The representation of output gates at 14 36 in FIGURE 3A show the various combination of bits that should be transferred from a particular instruc-16 tion buffer register to I-register 35. For example, 17 if a two-byte instruction is transferred from bits 0 18 through 16 of the first register of Instruction ~uffer 19 31, the next instruction to be transferred will have its OP code starting at bit position 16 of the same 21 register. Therefore, bit position 0 of I-register 35, 22 which is the first bit of the OP code of any instruction, 23 may be gated from position 0, 16, 32, or 48 of any 24 particular one of the registers of an instruction buffer.
Each of the Instruction Buffers 31, 32, and 33 has 26 a set of OR circuits 232 through 237 which are enabled 27 by a series of four AND circuits, further enab~ed by the 2~ state o~ the instruction stream Outpointer, to provide , :,.",:, ~)`336~

1 an input to I-register 35 bit position 0 or bit 2 position 16, the two bit positions of I-register 35 3 shown in FIGURE 13B. OR circuits 238 and 239 provide 4 the final input to the I-register 35 bit positions 0 or 16. The final gating of information into I-register 6 35 from Instruction Buffer 31, representing I stream A, 7 comes from AND circuits 240 and 241.
8 When decoding has been completed of an instruc-9 tion in I-register 35, a signal Decode Successful on line 242 is generated, and corresponds to the time 11 shown at 215 in FIGURE 12. The combination of AND
12 circuits and OR circuits shown at 243 are effective 13 to indicate that I-register 35 does not contain any 14 information, and in the case of I-register 35 bit positions 0 through 15, an indication must be made 16 that the gating is not for the purpose of transferring 17 the final two bytes of a six-byte SS type of instruction 18 signalled on a line 244. The final two bytes of 19 instruction information for an SS type of instruction requires that this information be inserted in bit 21 positions 16 through 31 of I-register 35. AN~ circuits 22 245 and 246 are enabled by signals on lines 247 and 248 23 respectively, which correspond to line 159 of FIGURE 9 24 indicating that instruction stream A is the instruction stream for which decoding is to be effective.
26 If instruction decoding proceeds from instruction 27 stream A after decoding a conditional branch instruction, 28 instruction stream A is either the original instruction 29 stream or the target instruction stream. If the result D-PO~-77-005 -4g-~1~3;~

1 of a conditional branch is such that the original 2 guess was correct, indicated by a signal Not Guess 3 Wrong on lines 249 and 250, AND circuits 245 and 4 246 will be enabled to immediately transfer the next instruction to Instruction Register 35. AND circuit 6 251 responds in an opposite fashion, when the original 7 guess effected in accordance with the logic shown in 8 FIGURE 6 is wrong, and this is signalled on line 252.
9 Instruction stream A would previously have been designated as the alternate stream on line 253, indicating that 11 instruction stream A should gate the next instruction 12 to Instruction Re~ister 35 instead of the other instruc-13 tion stream, originally thought to have been the source 14 for instructions.
As mentioned previously, OR circuits 238 and 16 239 are the final input to I-register 35, and there 17 is shown a set of AND circuits associated with 18 instruction stream B and instruction stream C which 19 will be enabled by a line corresponding to that shown at lS9 in FIGURE 9 indicating that instruction 21 stream as ~eing the stream presently being decoded.
22 There has thus been shown the ability to transfer 23 instructions into one of three sets of registers making 24 up instruction buffers, when activated, and the controlling of the transfer of instructions from the 26 instruction buffers ~o an instruction decoding register 27 in accordance with the requirements of conditional branch 2B instructions encountered from the various instruction 29 streams. The sequence of the transfer of instructions for D-PO9-77-0~5 -50-11¢;~3~i~

1 execution to an E-function is monitored and controlled 2 such that more than one conditional branch instruction 3 can be predecoded and awaiting execution while main-4 taining the proper sequence of execution in the execution unit.
6 While the invention has been particularly shown 7 and described with references to preferred embodiments 8 thereof, it will be understood by those skil'ed in the 9 art that the foregoing and other changes in form and details may be made therein without departing from 11 the spirit and scope of the invention.

Claims (8)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. In a computer system having storage, instruction processor, and execution unit, said instruction processor including a plurality of instruction buffers with buffer selection and instruction fetching means, each instruction buffer being responsive to said buffer selection means to receive and store at least one instruction from an independent sequence of instructions from said storage, an instruction decoder, instruction gate means interconnecting said instruction decoder and a selected one of said instruction buffers, and an instruction queue comprised of a plurality of queue registers, each said queue register storing execution control information received from said instruction decoder for each instruction decoded, said execution unit including control means, responsive to said execution control information received from each said queue register, for performing the function called for by each said instruction, and providing to said instruction processor, result signals for certain of said instructions, instruction sequencing logic comprising:
branch signalling means, responsive to a branch instruction in said instruction decoder received from a first one of said instruction buffers, for controlling said instruction fetching means and said buffer selection means to transfer a target instruction from said storage to another of said instruction buffers;
instruction gate control means connected to said instruction gate means, for transferring a next instruction
1. CLAIM 1 (to be continued) to said instruction decoder after transfer of said execution control information of said branch instruction to said instruction queue;
   target buffer indicating means responsive to said branch signalling means, associated with each of said queue registers when storing execution control information of a branch instruction, for indicating said another of said instruction buffer means; and instruction selection means, responsive to said result signals from said execution unit in response to said branch instruction and said associated target buffer indicating means, for selecting the next sequential execution control information to be transferred to said execution unit.
2. 2. Instruction sequencing logic in accordance with Claim 1 wherein:
   said instruction processor includes at least three instruction buffers.
   CLAIM 1 (continued) and CLAIM 2
3. 3. Instruction sequencing logic in accordance with Claim 2 wherein said branch signalling means includes:
   a busy trigger, and instruction fetch sequencing means associated with each of said instruction buffers;
   next target stream pointer means responsive to all said busy triggers for indicating said another of said instruction buffers; and target instruction access means for generating an execute branch signal, connected and responsive to a branch instruction in said instruction decoder and connected to said next target stream pointer means, for setting said busy trigger and initiating said instruction fetch sequencing means of said another of said instruction buffers, and for transferring the indication of said target stream pointer to said target buffer indicating means associated with said queue register storing execution control information of said branch instruction.
4. 4. Instruction sequencing logic in accordance with Claim 3 wherein said branch signalling means includes:
   means connected and responsive to the set state of all said busy triggers, and connected to said target stream access means for inhibiting operation of said target stream access means.
   CLAIMS 3 and 4 5. Instruction sequencing logic in accordance with Claim 4 wherein execution of a target instruction fetched in response to certain of said branch instruc-tions is conditioned on the state of a result signal from said execution unit, and wherein said instruction selection means includes:
   branch result logic, including means connected and responsive to the state of said result signal, for generating either a branch successful signal or a branch unsuccessful signal; and means, responsive to said branch successful or said branch unsuccessful signal, for selecting the next sequential execution control information of an instruction to be transferred to said execution unit from either said another of said instruction buffers or said first one of said instruction buffers respectively.
5. CLAIM 5 6. Instruction sequencing logic in accordance with Claim 5 wherein:
   said instruction gate control means includes a decoding pointer for selecting and interconnecting one of said instruction buffers to said instruction decoder, and said instruction selection means further includes:
   an execution pointer for indicating which of said instruction buffers was the source of the execution control information transferred to said execution unit;
   means responsive to said branch successful signal for transferring the contents of said target buffer indicating means to said decoding pointer and said execution pointer to indicate said another of said instruction buffers, and resetting said busy trigger and said instruction fetch sequencing means of all other of said instruction buffers; and means, responsive to said branch unsuccessful signal for rendering said target buffer indicating means effective to reset said busy trigger and said instruction fetch sequencing means of said another of said instruction buffers.
6. CLAIM 6 7. Instruction sequencing logic in accordance with Claim 4 wherein execution of a target instruction fetched in response to certain of said branch instruc-tions is conditioned, and considered successful, based on a particular state of a result signal from said execution unit, and said instruction decoder includes means for selectively producing decode signals including a guess successful signal for those branch instructions normally successful, known successful signal for those branch instructions that will always be successful, no branch signal for those branch instructions that cannot be successful, and coded branch status information associated with each of said queue registers storing execution control information of a branch instruction for identifying the type of branch instruction and therefor the particular state of said result signal wherein:
   said instruction gate control means includes a decoding pointer for selecting and interconnecting one of said instruction buffers to said instruction decoder;
   said branch signalling means includes means responsive to said no branch signal for inhibiting operation of said target instruction access means; and said instruction selection means further includes, an execution pointer for indicating which of said instruction buffers was the source of the execution control information transferred to said execution unit, means responsive to said execute branch signal, said guess successful signal, and said next target stream pointer for setting said decoding pointer to indicate said another of said instruction buffers, branch result logic, connected and responsive to said coded branch status information and said result signal from said execution unit for generating first, second, third, or fourth control signals representing, respectively, branch unsuccessful/wrong guess, branch unsuccessful/right guess, branch successful/wrong guess, and branch successful/right guess, means responsive to said first control signal for resetting all of said queue registers and said busy triggers and said instruction fetch sequencing means of all said instruction buffers not indicated by said execution pointer, and for transferring the indication in said execution pointer to said decoding pointer, means responsive to said control signal for resetting said busy trigger and said instruction fetch sequencing means indicated by said target buffer indicating means, means responsive to said third control signal for resetting all of said queue registers, said busy trigger and said instruction fetch sequencing means of all said instruction buffers not indicated by said target buffer indicating means, and for transferring the indication in said target buffer indicating means to said decoding pointer and said execution pointer, and CLAIM 7 (Continued) means responsive to said fourth control signal for resetting said busy trigger and said instruction fetch sequencing means of said instruction buffer indicated by said execution pointer and for transferring the indication in said target buffer indicating means to said execution pointer.
7. CLAIM 7 8. Instruction sequencing logic in accordance with Claim 7 wherein said instruction selection means further includes:
   means, responsive to said known successful decode signal for resetting said busy trigger and said instruction fetch sequencing means of said instruction buffer indicated by said decoding pointer.
8. CLAIM 8