CA1109564A - Program loader for programmable controller - Google Patents

Abstract

PROGRAM LOADER FOR PROGRAMMABLE CONTROLLER
Abstract of the Disclosure A microprocessor based program loader is con-nected to the memory data bus and memory address bus of a programmable controller. It is responsive to commands entered through a keyboard to load and edit the programmable controller control program. A mode switch associated with the programmable controller pro-vides a number of selectable positions which determine the mode of operation of the programmable controller and the functions that can be performed by the program loader. One of the positions on this mode switch enables the program panel through a control line to assume control of the mode selection. The operator can thus control the mode of operation through the program loader keyboard which may be located remotely from the programmable controller.

Description

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The field of the invention is programmable con-trollers, and particularly, means for loading and editing programs for controllers such as that disclosed `
in U.S. Patent No. 3,810,118 entitled "Programmable Matrix Controller" and that disclosed in United States Patent No. 3,942,158 issued March 2, 1976 and entitled "Programmable Logic Controller."
Controllers such as those described in the above cited patents perform complex control jobs in accor~
dance with a stored programO The stored program i5 a set of instructions which directs the controller to examine the condition of various sensing, or input devices such as switches and photoelectric cells, com-pare these conditions to the conditions specified in the stored program, and accordingly, direc~ the controller to energize or deenergize selected output devices such as motors, solenoids and lights. Although suitable programs may be developed and loaded directly into the controller, in practice such initial programs must first ~e used on the job site to correct unforeseen problems which inevitably occur. To this end, program loaders such as that disclosed in U.S. Patent No. 3,798,612 en~itled "Controller Programmer" and that disclosed in U.S~ Patent No. 3,813,6~9 entitled "Controller Program Editor" have been developed to facilitate the loading and editing of such programs. Such program loaders are separate instruments which are temporarily connected to the programmable controller to allow the entry and manipu-lation of the control program instructions. When the pro grammable controller has been successfully programmed and .
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the controlled machine is operating properly, the program loader is disconnected therefrom and may be used to program another system.
As disclosed in U.S. Paten~ No. 3,997,879 issued on December 14, 1976 and entitled "Fault Processor ~or Programmable Controller ~ith R~mote I/O Interface Racks,"
programmable controllers are sometimes used in situations in which a large number of sensing devices and operating devices are located remotely from the controller processor.
In such situations one or more I/O interface racks may be located at the remote site and coupled to the controller processor as described in Patent No. 3,997,879. When editing the control program associated with these remotely located sensing and operating devices it is advantageous to observ~ their operation, particularly when control program editing is being done while the machine is operatins.
Accordingly, the program loader mu~t also be located re-motely from the controller processor which stores and executes the control program.
Also, even at installations where the controller processor is lacated immediately alongsid~ the machine being controlled, it is often desirable to perform the programming and editing functions from a remote location.
Such a remote location might be, for example, a clean, quiet room which is removed from the industrial environ-ment.
The present invention relates to a program loader for a programmable controller which can be located remotely from the controller processor and which can con~
trol the mode of operation of the system. More sp~cifically, ~ffl~

the present invention provides in a programmable controller having a memory which stores a control program and a processor for reading out the control program instructions and executing them to control operating devices on a controlled machine~ the combination comprising: a selector switch associ-ated with said controller processor and being manually operable to selective-ly generate control signals at a set of output terminals; mo~e control lines connected to said selector switch output terminals; a program loader pro-cessor coupled to said controller memory and controller processor and connect-ed to said control lines, said program loader processor including first means for sensing the logic state of each of said mode control lines, and second means ~hich is enabled by the logic signal on one of said mode control lines and is responsive to manually entered data to generate logic signals on selected other ones of said mode control lines; and means connected to said program loader processor for manually entering data indicative of the mode control lines upon which logic signals are to be generated.
The invention will generally allow one to enable mode selection from the program loader. The mode selection switch at the controller pro-cessor can be manually set to any one of the possible modes of operation.
In addition it can be set to a RUN/PROGRAM LOAD mode which enab~es the same ~O mode selections to be made from the program loader.
The invention will also allow one to control those who have access to enter and change the stored control program. The ability to enter pro-gr~lls, change programs, change stored data and monitor the operation of the system at the program loader is determined by the mode of operation. This can be controlled solely at the processor mode selector switch, or in the alternative, it can be controlled at the program loader by setting the processor switch to RUN/PROGR~ LOAD. Access to the processor mode selector switch can be controlled by locking the enclosure which houses it or by using a keylock switch.
3Q The invention ~ill also allow one to ena~le the user of a program loader to load and edit a control program ~rom a location which is remote from the controller processor and to enable the user to control the system's mode of operation from the remote location sr at the processor.
S In drawings which illustrate the embodiments of the invention, Fig. 1 is a block diagram of a programmable controller with attached program loader;
Fig. 2 is a block diagram of the program loader processor of Fig. l;
Fig. 3 is a schematic diagram of a portion of the processor front panel of Fig. l;
Fig. 4 is a schematic diagram of the interface control circuit which form~ part of the program loader processor of Fig. 2;
Fig. S is a schematic diagram of the de~ice selec-tion and control circuit which forms part of ~he program loader processor of Fig. 2;
Fig. 6 is a schematic diagram of the communications circuit which forms part of the program loader processor of Fig. 2;
Fig. 7 is a pictorial view of the keyboard which oxms part of the pxogram load~r of Fig. l; and Figs~ 8a-c is a flow chart o the keyboard and dis-2S play executlve routine which forms part of the processor of Fig. 2.
There are a number of commercially available pro-grammable controllers which operate to examine the con dition of various input devices, compare these conditions to the conditions speci~ied in the instructions of a \

stored program, and accordingly, energize or deenergi~e selected output devices. These controllers may vary in the number of input and output devices they ca~ control and in the number of operations which they can be dlrected to perform. Despite these many variations, all controllers include a stored program which is comprised of a series of instructions that are repeatedly read out of a memory in sequence. Each instruction includes an operation code which determines the function to be performed by the controller and an I/O address code which determines the particular input or output device concerned.
The preferred embodiment of the invention is incor-porated in a controller program loader for a programmable controller such as that described in the above cited U.S.
Patent ~o. 3,942,158 entitled "Programma~le Logic Controller."
Referring particularly to Fig. 1, the programmable controller includes a random access read/write memory l which has an eighteen-bit word length and which includes ~rom 4,096 to 12,288 separately addressable lines depending upon the size of the control program which it is to store~ Two bits in each word stored in the memory l are used or parity checking, and thus, sixteen data bits are stored on each line of the memory 1. An output image table 2 is stored in the fixst sixty-four lines of the memory l and each line is separately addressable with the oc~al addresses 000-077. An input image table 3 is stored on the next sixty-four lines o~ the memory 1 and each line is separately addressable with the octal addresses 100-177. Preset and accumulated values of counters and timers are stored on the next 128 lines of the memory l and are addressable with the octal address~s 200-377, and the remaining lines of the memory 1 contain a control program 4 in which program instructions are contained and are separately addressable with octal addresses of 400 or greater.
Selected data is read from the memory 1 by applying the proper octal address to a memory addrass bus 5 and applying a logic low voltage to a read/write line ~.
The memory 1 is cycled by applying a logic low pulse to a memory cycle line 7 and the addressed word is read out on a memory data bus 8. A word is loaded, or written into a selected line of the memory 1 by applying the octal address of that line to the memory address bus 5, applying a logic high voltage to the read/write line 6 and applying a logic low voltage pulse to the memory cylce line 7. The sixteen-bi~ data word appearing on the memory data kus 8 during the one-micros~cond cycle time of the memory 1 is written into the selected line of the memory 1.
~he control program 4 is executed by a controllex processor 9 which connects to the memory buses 5 and 8 and to the control lines 6 and 7~ In response to one-megahertz clock pulses generated by a polyphase clock 10, the controller processor 9 continuously and sequen-tially reads out the instructions of the control pro-gram 4 rom the memory 1, and in response to an operation code contained within each program instruction, it per-forms the operation necessary to carry QUt the controller unctions. Such operations include, for exampie, examining a status bit in the input image table 3 or setting a status bi~ in ~he output image table 2 to a desired state~

Each status bit in the output image table 2 corres-ponds with an operating device such as a motor starter or solenoid on a system being controlled, and each status bit in the input image table 3 corresponds with a sensing device such as a limit switch or a photoelectric cell on the controlled system. This correspondence is achieved by connecting all of the sensing and operating devices on the system being controlled to separately addressable input and output circuits in programmable controller in-terface racks, one of which is indicated at 18. Each status bit of the input image table 3 is periodically updated by coupling the status of the corresponding sensing device on the controlled system to the memory 1.
This is performed by an I/O scanner cixcuit 11 which also periodically updates the status of the output de-vices on the controllea system by coupling the current state of each status bit in the output image table 2 to the programmable controller output circuits. The I/O
scanner circuit 11 connects with the processor 9 thxough a set of control lines indicated collectively at 12 and it also connects directly to the memory data bus 8, the memory address ~us 5, and the read/write line 6. The scanner circuit 11 periodically couples the memory data bus 8 to an I/0 data bus 13 which connects to rack adap-ters 14 in interface racks 18. Each rack adapter 14 connects to eight separately addressa~le I~O slo~s 15, each of which includes sixteen addressable input or out-put circuits that connect to the operating and sensing devices on the controlled machine 16. An I/O address bus 17 connects the rack adapters 14 to the scanner circuit 11, and each rack adapter 14 includes decoding circui~ry which is responsive to three bits in the six-bit address code on the bus 17 to enable the interface rack when its rack number is detected. Each rack adapter 14 also in-S cludes decoding circui~.ry which is operable to enable one of the slo~s 0-7 in response to the three remaining ~its on the I/0 address bus 17.
The I/0 scanner circuit 11 periodically ~Isteals~
a memory cycle from the processor 9 to read a sixteen~bit word in the output image table 2 of the memory 1 and couple that word through the I/0 data bus 13 to a selected rack and slot which is identified by an address on the I/0 address bus 17. Also, the scanner circuit 11 periodi-cally reads the sta-tus of sixteen input circuits in an addressed slot 15 and couples the sixteen-bit data word to an addressed line in the input image table 3 o~ the memory 1. Thus, by periodically stealing a memory cycle from the processor 9, the I/0 scanner circuit 11 updates the input image table 3 with the current status of the sensing devices on the controlled machine 16, and periodi-cally updates the state of the operating devices on the controlled machine 16 by coupling the current status of the output image table 2 to the proper rack adapter 14. The I/0 ~canner 11 and rack adapter 14 may be constructed to allow the adapter 14 and associated I/0 circuits 15 to be located remotely from the other elements of the progra~0mable con~
troller as described in the above cited U.S. Patent No.
3,997~879.
The controller program loader interact3 with the controller processor 9 and the read~write memory 1 on a ' ~ . ' ':

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similar "cycle steal" basis. Referring particularly to Fig. 1, the controller program loader includes a program loader processor 20 which connects to ~he memory address bus 5, the memory data bus 8, the control lines 12 and the read/write line 6. As will be described in more detail hareina~ter, the program loader processor 20 in-cludes a micxoprocessor which operates in response to machine instructions stored in a read-only memory 21 to perform a number of func~ions.
One of the primary functions of the program loader processor 20 is to load the control program 4 into khe controller memory 1. The control program instructions are ~ntered through a keyboard 22 that forms part of a display terminal 23 which connects to the program loader pxocessor 20 through a cable 24. The display terminal 23 is a commercially available system su~h as that sold by TEC, Inc. under the trademark "Mini-Tec Data-Screen"
and in addition to the keyboaxd 22, it includes a CRT
display 25 and a communications module 26 which provides an EIA RS-232C compatible interface with ~he cable 24.
The keys on the keyboard 22 are marked with symbols typically used in program loaders as shown in Fig. 70 Controller program ins~ruction~ entered through ~he key-board 22 are coupled to the program loader processor 20 which converts them into the format disclosed in the a~sve cited U.S. Patent No. 3,942,158. After the conversion has been made, the program loader processor 20 interxupts the controller processor 9 for a one-microsecond memory cycle to load the program in~truction into the contxol program portion 4 of the read/write memory 1.

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The program loader processor 20 may also interrupt the controller processor 9 to perform other functions.
These include loading data into the memory 1 or reading out control program instructions or sixteen-bit data words. Status words read out of the image table 2 or 3 are converted to a form suitable for operating the CRT
display 25 and the operator is thus provided with a visual indication of the s~ate of the controlled machine 16. A particularly useful monitoring feature on the program loader is disclosed in U.S. Patent No. 4,070,702 which issued on January 24, 1978 and is enti~led "Contact H~stogram For ~rogrammable Controller."
The program loader processor 20 i9 located wi~hin the same enclosure as the programmable control~er elements, whereas the display terminal 23 is outside the enclosure and may be located remotely if desired.
Referrin~ to Figs. 1 and 3, the ~ront of the enclosure which contains the progxammable controller processor 9 includes a number of switches and indicators which are re~erred to collectively as the processor front panel 2~.
One of these switches is a single-pole, four position, mode selector switch 28 ~hich is manually opera~le to drive four mode control lines. These control lines connect to both processors 9 and 20 and they include a RUN/PROGRAM LOAD
Iine 29, a RUN~MONITOR line 30, a PROGRAM PANEL ENABLE
line 31, and an OUTPUTS OFF line 32O The movable con-tact on the selector switch 28 connects to a logic high voltage source 33 through a resistor 34 and this is applied through respective analog comparator circuits 40, 41 and 43 to the lines 29, 30 or 31 when the switch is set to the re-.
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spective RUN/PROGRAM LOAD, RIJN/MONITOR or P~OGRAM PANEL
ENABLE positions. The OUTPUTS OFF line 32 is driven through an inverter gate 35 by a flip-flop which is formed by a pair of NOR gates 36 and 37. One input of the NOR gate 36 is connected to the RU~I/MONITOR or RUN/
PROGRAM LOAD positions of the selector switch 28 by an OR gate 38, and one input of NOR gate 37 is connected to the TEST/MONITOR or PROGRAM PANEL ENABLE positions by an OR gate 39. The comparator circuits 40-43 ser~e to hold the control lines 29-32 at a logic low voltage until driven high by the selector switch 28 or the pro-gram loader processor 20. Table I indicates the logic state o~ the mode control lines as a function of selec~-tor switch position.

TABLE I

Mode Mode Mode Mode ~witch PositionLine 29 Line 30Line 31Line 32 RUN~PROGRAM LOADHIG~ LOW LOW HIGH
RUN/MONITOR LOW HIGH LOW EIGH
TEST/MONITOR LOW ~OW ~OW LOW
PROGRAM PANEL ENABLE LOW LOW HIGH ~OW

When the RUN/MONITOR control line 30 is.a-t a logic high voltage the controller processor 9 executes the control program 4 and operates the controlled machin~ 16.
When the RUN/MONITOR control line 30 i5 at a logic low voltage, the processor 9 reads out the control program 4, ~ut the read/write line 6 is held low so that data cannot .

be written into the memory 1 by the processor 9. The OUTPUTS OFF control line 32 couples to the I/O inter-face racks 18 and it serves to connect or disconnect all operatin~ devices on the controlled machine 16 depending on its logic state. That is, when ~he OUTPVTS
OFF control line 32 is low, the operating devices con-nected to I/O interface rack 18 are decoupled rom the programmable controller and are not controlled thereby.
Editing functions may thus be performed on the control program 4 without affecting the operation of the machine 16 until the made selector switch is changed to the RUN/
MONITOR mode. ~he PROGRAM PA~IEL ENABLE con~rol line 31 enables the program loader to per~orm its usual pro-gramming and editing functions on the control program 4 stored in the memory 1. Since the RUN/MONITOR control line 30 is low when the PRO&RAM PANEL ENABLE mode is selected, these program~ing and editing func~ions are performed "of-lineO"
One aspect of the present invention is that when ~he RUN/PROGRAM LO~D control line 29 is driven to a logic high voltage by placing -the selector switch 28 in the RUN/PRO~RAM LOAD mode, the logic state of the remaining control lines 30, 31 and 32 can be set through the pro-gram loader keyboard 22. This in essence enables the operator o~ the program loader to control the mode of operation of the programmable controller without operating the selector switch 28. If the selector switch i5 Locked in the RUN/PROGRAM LOAD mode, mode selection can only be made at the program loader keyboaxd 22 which may be located in a remote and secure location.

Referring particularly to Fig. 2, the program loader processor 20 includes an eigh~-bit microprocessor 45 such as that sola commercially by Zilog as the Model Z80. The microprocessor 45 is driven by a 2.5 mHz clock circuit 46 and is connected through an eight~bit bidirectional data bus 47 to a number of elements.
These elements include the 16K read-only memory 21 which stores microprocessor machine instructions that are read out in sequence ~o direct the microprocessor through its ~unctions and a lK random access memoxy 4g which stores data. The particular line from which data is read or into which data is written is dete~mined by the micro-processor 45 through a sixteen-bi~ address bus 4g.
Address bus leads AB0-A~13 also connect to a fifteen~bit address output buffer 50. The address output buffer 50 is comprised o hex bus dri~ers with 3-state output ter-minals that are connected to the respective leads in the programmable controller address bus 5. The control in-puts on these drivers are commonly connected to an ADD
~0 OUT control line 51. The output terminal of the ~ifteenth driver in the address output buffer 50 connects to the controller read/write line 6 and its input terminal is driven by a RD/WR con~rol line 52. The con~rol lines 51 and 52 are driven by an interface control circuit 53 to be described in detail hereinafter.
The microprocessor treats the programmable controller address bus 5 as an extension of its own address bus 49 and the controller memory 1 as an extension of its own memories 21 and 48. Table II indicates the a:ddresses which are generated on the address bus 49 to enable the various processor elements including the separate lines of the memories 21 and 48 and the sepaxate lines of the controller memory l.

TAB~E II

S ADDRESSED ELEMæNT ADDRESS (Decimal) ADDRESS (Hexadecimal) .
Read-Only Memory 21 0 H
to ko __________________________________________________,__ _ ~____ Random Access 64512 FCOO
to ~o Memory 48 65535 FFFF
_____________________.___________________________..____________ Controller Memoxy l 16384 to 61439 4000 to EFFF
________________________~___________ ___ _________~______ __ USART 81 Read data = 20 Reaa status = 21 Write data = 24 Write command = 25 __________________________________________ ________ __.._____ USART 82 Read data ~ 40 Read sta~us = 41 Write data = 44 Write command = 45 ______________ ______ __ ____.___________ _______.._~_~. ______ Counter Timer Channel 0 - 58 Circuit 83 Channel 1 = 59 Channel 2 = 6A
Channel 3 = 6B
______ _________ ____________.______ _ __________...____ ____ Data Multiplexer 94 Serial status ~ 74 8 Bit Control Input Port = 75 , :: :

Input Multiplexer 61 Channel 1 = 72 Channel 2 = 70 Channel 3 = 73 Channel 4 = 71 ______________________~_~_________ _______~________________ Mode Output Register 70 78 _______________________ ____________________________~________ Low Byte Storage 7C
& Mu1tiplexer 57 When the controller memory 1 is addressed, data is ei~her written into it or read from it through i~s 16-bit data bus 8. This memory data bus 8 is coupled tothe eight-bit data bus 47 of the program loader processor 20 by a pair of eight-bit data output buffers 54 and 55.
Tha data buffers 54 and 55 are comprised of hex bus drivers with 3-state output terminals that are connected 15 to the respective sixteen leads in the bus 8. Their con-trol terminals are commonly connected to an OUT EN control line 56 which is driven by the interface control circuit 53 . The eight inputs of the output buffer 54 connect to the respective leads DB0-DB7 in the data bus 47 and the eight inputs of the output buffer 55 con~ect to the out-puts of a low byte storage and multiplexer 57. The storage and multiplexer 57 is a pair of quadruple 2-input mul~
plexers with storage having one set of eight inputs con-nected to the leads DB0-DB7 in the data bus 47 and the other set of eight inputs connected to the eight least significant leads in the controller memory data bus 8.
A MUX SEL control line 58 determines through which of ~he two sets o multiplexer inputs data will be entered and stored and a signal on a MUX CL control line 59 clocks the data into the low byte storage and multiplexer 57.
The stored data is generated at its outputs and appears on an 8-bit bus 60.
To output a sixteen-bit word to the controller memory 1 r the eight least significant bits, or in other words, the low byte, is first stored in the low byt storage and mul~iplexer 57. The appropriate line in the memory 1 is addressed through address output buffer 50, the high byte is generated on the data bus 47, and ~he data output buffers 54 and 55 are then enahled through the OUT EN control line 56. The generation of the proper memory address and the proper data is accomplished by the microprocessor 45 under ~he direction of machine instructions stored in the read-only memory 21. The timing and sequence of operation of the outpu~ buffers 54 ~nd 55 is determined by the interface control circu.it 53 which also operates to steal a one microsecond memory cycle from the controller processor 9. During the one microsecond memory cycle the sixteen-bit word is trans-ferred to the memory 1 from the output buffe.rs 54 and 55.
Data is inputted to the program loader data bus 47 t.hrough an input multiplexer 61. The input multiplexer 61 is a set of four dual 4-line-to-1-line data multi-plexers with eight 3-state outputs which connect to the respective leads DB0-DB7 in the data bus 47. Four elght-bit input channels (l~a) are thus formed and the seIection o~
channels is made through a SEL A control line 62 and SE~ B
control line 63~ Data is inputted to the data bus 47 through a selected channel 1-4 when a logic high voltage appears at a MUX EN control line 64. The control lines 62-64 are all driven by a device selection and control circ~it 65 to be aescribed hereinafter.
The terminals of input channel 1 on input multi-plexer 61 connect to leads in the control lines bus 12 S and to the RUN/PROGR~M LOAD line 29. The terminals of input ~hannel 2 connect to eight output terminals on a hi by~e input register 66 and three of the eight ter-minals of input channel 3 connect to the respective mode control lines, RUN/~ONITOR 30, PROGRAM PAMEL ENABLE 31 and OUTPUTS OFF 32. The eight terminals of inpu~ channel 4 connect to the leads in bus 60 which are driven by the low byte storage and multiplexex 57. The hi byte register 66 is a pair of quadruple D-type flip-~lops having ~heir clock terminals commonly connected to a PLC IN control line 67. Their D inputs connected to the respective eight most signiicant leads in the memory data bus 8 and their outputs connect to channel 2 o multip1exer 61 as described above.
The operation of the inpu~ multiplexer 61, the hi byte input register 66 and the low byte multiplexer 57 are controlled by the device selection and control circuit 65 in response to machine instructions executed by the microprocessor 45. When a 16-bit word is to be inputted from the controller memory 1, for example, the MUX CL
line 59 and PLC IN line 67 are driven high to store the hi byte in register 66 and the low byte in storage 57.
As part of such a memory read machine instruction, channel

2 of the input multiplexer 61 is selected through the SEL A line 62 and SEL B line 63 and the hi ~-bi~ byte of the 16-bit memory word is coupled to the data bus 47. The : . .. : .- :- ~ : :- . . .- , . . . . . , -following machine instruction executed by the micro processor 45 selects channel 4 of the input multiplexer 61 and the low 8-bit byte of the memory data word is coupled to the data bus 47 rom the storage 57.
The program loader processor 20 can either read the state of the mode control lines 29 32, or under proper conditions it can drive the mode contxol line~ 30 32.
The RUN/PROGRAM LOAD line 29 is connected to input channel 1 of the input multiplexer 61 along with other control lines in the bus 12, whereas ~he RUN/MONITOR
control line 30, the PROGRAM PANEL ~NABLE control line 31 and the OUTPUTS OFF control line 32 connect to .input channel 3 of the multiplexer 61. By addressing the appropriate multiplexer input channel and executing a data input machine instruction, the logi.c state of the mode control lines 29-32 can be determined. The adclresses of the multiplexer input channels l-4 are indicated in Table II.
The logic state of the mode control lines 30-32 can be controlled by the program loader processor 20 through a mode output register 70. The mode output regis~
ter 70 is a hex ~-type flip-flop having a common clock terminal which aonnects through a WR STA~US control line 71 to the device selection and control circuit 65. Four inputs on the register 70 connect to the four least sig-ni~icant leads DB0-DB3 in the data bus 47 and ~hree of the correspondin~ outputs connect through ~uffers 72, 73 and 74 to the respective mode control lines 30, 31 and 32. A fourth output t~rm.inal connects through a FREEZE
control line 75 to the interface control circui~ 53 and indicator lights 76 and 77 connect to the fi~th and sixth register output terminals. The address of the mode out-put register 70 is indicated in Table II and by outputting the appropriate da~a ~o the register 70, the sta~e of the mode control lines 30-32, the FREEZE line 75 and the in-dicators 76 and 77 can be controlled.
Referring to Figs~ 1, 2 and 6, the progxam loader processor 20 communicates with the display terminal 23 through a communications circuit 800 The communications circuit connects to the eight leads DB0-DB7 in the data bus 47 and it connects to leads AB0, ABl, AB5 and AB6 in the address bus 49. The communications circuit 80 includes a pair of universal asynchronous receivex~
transmitters which are referred to hereinafter as USART
81 and USART 82 and a countex timer circuit 83. USART
81 and USART 82 are both connected to the data bus 47 and they receive and store an eight-bit data word when they are addressed through leads AB0, AB5 and AB6 and a USART WR control line 84 is driven high by the device selection and control circuit 65. This eight-bit data word is transmitted serially through respective line drivers 85 and 86 when clock pulses are received through respective inverter gates 87 and 88 from the counter timer circuit 83. Conversely, eight-bit data words may also be serially received at each USART 81 ancl 82 ~hrough respective line filters 89 and 90. The received clata words are ~oupled to the data bus 47 when the USART 81 or 82 is addressed and a USART RD control line 91 i.s driven high by the device selection and control circtlit 65.

The rate at which the USARTs 81 and 82 transmit serial data i5 controlled by the counter timer circuit 83 which in turn receives baud rate numbers rom the data bus 47. The counter timer circuit 83 is addressed through leads Aso and Asl and is enabled by the device selection and control circuit 64 through a CTC CE con-trol line 92. It stores a baud rate number for each of the USARTs 81 and 82 (channels 1 and 2) which can be changed by appropriate machine instructions stored in the read-only memory 21. The addresses of the various elements o~ the communications circui~ 82 are indicated in Table II.
The cable 24 from the display terminal 23 connects ~o line driver 86 and line filter 90 of USA~T 82. An ASCII character generated by the keyboard 22 is recei~ed serially at the USAR~ 82 and when all eight bits have been received, the USART 82 generates a "character pre-sent" status signal on the data bus 47 when its status is read. ~he received character i5 then inputted to the microprocessor 45 and its identity is determined. When transmitting ~SCII characters to the CRT display 25, the reverse procedure occurs. The ASCII character is written into the USART ~2 and serial transmission throuyh the line driver 86 is begun. The status of -the USART 82 is checked to determine khat transmission is complete before writing another character into it. The USA~T 81 operates in the same manner and the cable 93 which it drives may, for example, be connected to another programmable controller or to a digital computer. The cable 24 may be up to 1000 feet in length thus enabling the display terminal 23 to be located remotely.

The communications circuit 80 also includes an eight-bit data multiplexer 94 which serves as an eight-bit parallel data input port. The data mul~iplexer 94 is addressed as indicated in Table II and is enabled S through a RD CHAN PORT con~rol line 95 by the device selection and control circuit 65.
Referring particularly to Figs. 1, 2 and 4, the interface con~rol circuit 53 operates in response to a signal from the device selection and control circuit 65 to request a one microsecond memory cycle from the controller processor 9. When this memory cycle is granted, the control circuit 53 then operates to control the writing of a data word into the controller memory 1 or the reading of a data word from the controller memory 1. The signal which starts the sequence is received through an ENPORT control line 97 which couples through a NAND gate 98 to the preset terminal on a flip-flop 99. ~s a result, a Q output on the flip-flop 99 is set to a logic high voltage and this is inverted by a gate 100 and applied to an interrupt request con rol line 101 which connects to the controller processor 9. In addition, the Q output of flip-flop 99 also drives a ~AYT control line 107 through an OR gate 109~ The WAIT control line 107 connects to the microprocessor ~5 and it stops the execution o~ further machine instructions. As indicated in ~he above cited U.S. Pa~ent No. 3,942,158 the con-troller processor responds shortly with a logic high voltage on a GRANT line 102 and within the one micro-second which ~ollows, the memory data bus 8 and address 3Q bus S is relinquished to the program loader processor .

20. When this occurs, the microprocessor 45 is enabled again through the WAIT control line 107 to execute machine instructions.
The control circuit 53 i9 synchronized with ~he control processor 9 by a five-bit shift register 103 which has its clock terminal connec~ed to receive a five megahertz signal generated by the controller polyphase clock 10 through a line 104 and its input connected to receive a T4 timing signal from the colltrQller processor 9 through a line 105~ A logic high is shifted through the register once every microsecond in synchronism with a similar register in the controller processor ~ to divide the memory cycle into five two hundred nanosecond time periods, TO-~4.
The GRANT line 102 goes high during the T3 time period and remains high for approximately one-half micro-second. During the T4 time period which follows a flip-10p 106 is set and remains set for one microsecondO The Q output of the flip flop 106 goes high to enable the data output buffers through the OUT EN control line 56 and its Q output goes low to enable address output buffers 50 through the ADD OUT control line 51. The Q output also drives the WAIT control line 107 through the OR
gate 109 to stop the execution of further machine instruc tions during the remaining one microsecond time period.
An OR gate 108 is also enabled by the flip-flop 106 and its output connects to the RD/WR con~rol line 52 which drives the R/W cQntrol line 6 ~hrough the address output buffer 50. A second input on the OR gate 108 is driven by a RD EN control line 111 which connects to the device .. - . .. , . - - :

selection and control circuit 65. If a data word i5 to be reaa from the controller memory 1 auring ~he one microsecond time period, the RD/WR control line 52 is driven high and is coupled to the R/W control line 6.
Otherwise, it is driven low and a memory write function is performed.
The signal on the GRANT control line 102 which sets the flip-flop 106 also resets the flip-flop 99. Its Q
outpu~ is thus driven low to terminate the signal on the interrupt request line 101 and to disable an AND
gake 113 which drives the D inpu~ of flip-flop 106. As a result, when the next T4 time period is generated by the shift register 103, ~he flip-flop 106 is reset ~o terminat~ access ~o the controller memory 1.
The interfa~e control circuit 53 also connects to a grant enable input control line 114 and a grant enable output control line 115. These lines form a daisy chain with the I/O scanner 11 and controller processor 9 and ~hey are ~oupled toge~her by an AND gate 116. One input of ~he AND gate 116 is connected to the Q output o flip-10p 99 and the daisy chain is thus broken by the AND
gate 116 when the program loader processor 20 receives it~ one microsecond accass to the controller memory 1.
A similar gate is present in the I/O scanner 11 and in this m~nner it i5 certain th~t only one interrupt re~uest is granted at a time.
As indicated by the abovP description, the opexation of the program loader processor elements are controlled by the device selection and control circuit 65 which in turn is controllea by machine instructions stored in thP

-23~

read-only memory 21. Each machine instruc~ion which calls for the transfer of data to or from one of the processor elements includes an operand (either actual or implied) and an operation code. The device selec~
tion and control circuit 65 operates in response to -the operand which is generated on leads of the address bus 49 and the operàtion code which enables cer-tain processor control lines to enable the proper processor elemen~s.
These address lines and control lines which drive the device selection and control circuit 65 are indicated in Fig. 2 by the bus 120.
Referring particularly to Figs. 2 and 5, the device selection and control circuit 65 includes a 2-to-4-line decoder 121 which operates in combination with a set of lS logic gates to enable the read-only memory 21 or the random access memory 48 when they are addressed. The decoder 121 is enabled by a signal from the microprocessor 45 through an MREQ control line 122 which indicates that data is to be transferred to or from memory. The addresses of the memories 21 and 48 as well as the controller memory 1 are indicated in Table II. When the read-only memory 21 is addressed, a CS control line 123 is driven high by the decoder 121 as well as a RD control line 124 which eminates directly from the microprocessor 45. When the random access memory 48 is addressed, an enabling signal is generated on an END control line 125 and a read or a write operation is performed depending on the state of a WR control line 119 which eminates directly from the microprocessor 45. And finally, when the controller memory 1 is addressed, the decoder 121 and associated -~4-: - ' - . ' ' : , .

gates generate an enabling signal on the ENPORT control line 97 to the in~erface control circuit 53. As indi-cated above r this initiates an interrupt request and s~bsequent data transfer.
The least significant leads in ~he address bus 49 and mi~roproces~or control lines IORQ 126 and ~1 127 are decoded to enable ~he remaining elements o~ the processor 20. The decoding is accomplished with a 3-to-8-line decoder 128 and associated logic gates. The control lines which axe active in enabling ~he varlous processor elements are indicated in Table III.

TABLE III

__ _ ACTIVE CONTROL LINE PROCESSOR E~EMENT ENABLED

________________________~______ _~__________ ______________~_ ________________ _.____ _______ ___ __ ____ _ _ _ ___ __ _ ___._A~_ ~ _ _ _ _ __ CTC CE 92; RD 124 INPUT DATA FROM
CO~NTER TIMER 83 _ __ __ ._ __ __ __ __ _ _ _ _ __ _ _ ___ _ __ ___ _ __ ___ __ _ _ __ __ __ _ _ _ ._ _ _ _ . _ _ _ _ ___..__ _______________--__________________________~___________ USART RD 91 ~NPUT DATA FROM

_ _ _ _ _ _ :

__________ __ _____ ___ ____ .__ ________._____________ ______ INPU~ DATA FROM

ENPORT 97; ~D EN lll ~) INTERFACE CON~ROL

PLC IN 67 B) HI BYTE INPUT

MUX CL 59; MUX SEL 58 C) LOW BYTE STORAGE
& MUX 57 MUX EN 64; SEL A 62; SEL B 63 D) INPUT MULTIPLEXER 61 ___________ __________________._______________._______________ OUTPUT DATA TO CONTROL~ER

MUX CL 59; MUX SEL 58 A) LOW BYTE STORAGE
& ~UX 57 ENPOR~ 97 B) INTERFACE CONTROL
CIRCUI~ 53 OUT EN S6 C~ DATA OUTPUT

The abllity of ~he program loader 20 to outpu~ data to the controller memory 1 and display terminal 23 as well as its ability to dxive the mode control lines 30-32 is controlled by microprocessor machine instructions which direct the micropxocessor to issue commands that ar~ decoded by the device selection and contxol circui~ :
65. Si~ilarly, data is inputted from the controller memory l, display terminal 23 or mode control lines 2g~32 in response to microprocessor machine instruction~ stored ln the read-only memory 210 For a complete description of the instruction set fox the microprocessor 45 as well as a detailed description of the structure and operation of this microprocessor, reference is made to Z80-CPU Technical Nanual published in 1976 by Zilog.
The program stored in the read-only memory 21 is operable generally to input characters Erom the keyboard 22, decode them to oxm opexatox commands, and then to ~26~

,6~

carry out the command. With reference to Fig. 7, the following i5 a list of some of ~he commands which are possible.

FUNCTION CO~MANDS

TTY - Trans~r control of the program loader from the keyboard 22 to a TTY.
DISPLAY - Transfer control from TTY to th~ keyboard 22 or erase the screen and update rung diagram on CRT display 25. The CRT dis-play 25 is automatically updated to dis-play in xung diagram ~orma~ a portion of the control program stored in the controller memo~y 1.
CLEAR MEMORY 99 - Erase conkrol program 4 from ind.icated point to end.
CANCEL COMMAND - Cancel previous command.

EDIT COMMANDS

SEARC~ - Locate indicated control instruction in the control program 4 and display its 2~ rung on CRT display 2~.
SEARCH 8 ~ Locate all control instructions in the control program 4 with the same indicated I/O address and display its rung on CRT
display 25.

.
, SEARCH 9 - List errors and their memory addresses during cassette recorder verify opera-tion.
SEARCH 6 Contact his~ogram enabled to monitor status changes of a selected I/0 device or timer/counter~
INSER~ - Insert con~rol instruction into the control program 4 between existing contxol instructions.
REMOVE Delete indicated control instruction from the control program 4.
RUNG - Modifies insext and remove commands to insert or remo~e control instruc~ions representing an entire ladder diagram rung.
Mo~e CRT cursor left or right one ele~
~ ment in rung on di~play 25, display RUNG previous rung: display next rung. Each ~ element displayed on the C~T 25 corres RUNG ponds to a control program instruction in the memory 1 and it is through these cursor commands along with the SEARCH
command that the operator pages ~hrough the control program 40 The remaining keys on the keyboard 22 are employed to form control instructions such as those listed in U.S. Patent No. 3,942,158. The numeric keys may also be emplGyed to alter the data in the tirners and counters portion of the c~ntroller memory 1. The control lnstruc~
tion will be loadad into the control program 4 at the point indicated by the CRT cursor.

-28~

Referring to Figs. 8a-c, when the DISPLAY function command is entered, a keyboard and display executive pro~ram stored in the read-only memory 21 is executed by the microprocessor 45. The mode control apparatus of the pxesent invention is operated in part by machine instructions in this program which serv~ to establlsh the mode of operation of the programmable controller and which enable the mode to be changed through the keyboard 22.
The keyboard and display executive program is formed about a CRT display upda~e routine 135 which is executed after the start-up functions are completed. As is well known in the art, the control program stored in the memory 1 can be schematically represented by a ladder diagram, with each rung of the diagram representing a se~ of controller instructions related to a particular operating device on the controlled machine 16. Tha CRT
display update routine 135 reads a set of control program instructions out of the memory 1, converts them to a series of equivalent ASCII characters, and outputs those characters to the CRT display 25 to "paint" a picture of the equivalent ladder diagram rung. The operator controls which rung is displayed through the keyboard 22. As various changes are made in the control program by means of the editing commands, the corresponding rung displayed on ~he CRT 25 is changed to provide the operator with visual feedback of his actions.
Referring particularly to Fig. 8a, the system re-mains in a loop formed by the CRT display update routlne 135 and a decision block 136 until a character is received ~rom the keyboard 22. When a character is received it is analyzed to determine which command has been entered. This is accomplished by a series of instruc-tions represented collectively by the dashed line 137.
S Such commands may include the function commands of TTY, DISPLAY, CLEAR MEMORY, CANCEL COMMAND, or the EDIT com mands of INSERT or REMOVE listed above. In such case the system jumps to the proper routine for carrying out the indicated command. When the command has been executed, ~he system loops back to the CRT display update routine 135 and awaits the next keyboard command.
When a SE~RCH command is received, the system branches at decision block 138 and awaits the receipt of the n~xt character from the keyboard 22 as indicated by process block 139. If the received character is a CANCEL CO~ND
the system branches back to the CRT display update routine 135 as indicated by decision block 140. Otherwise, the character is analyzed by decision blocks 141 and 142 to determine if it is a SEARCH 59 or SEARC~I 5 command. If it is not, a SEARCH 6, SEARCH 7, SEARCH 8, SEARCH 9 or a SE~RCH command has been requested, and the system jumps to the appropriate routine for execution, as indicated collectively by proces~ block 143.
A S~ARCH 51 command is a request to make an "on-line" change of data stored in the cont~oller memory land a SEARCH 52 command is a request to make an l'on line"
change of the control program. Before these types of commands can be executed, however, the mode of operation must be checked~ Referring to Fig. 8b, to accomplish this the status of the de control lines 30-32 is first ~;6~

inputted to the processor 45 and the s~ate of the PROGRAM PA~EL ~NABLE li.ne 31 is checked to determine if it is high. If it is, as indicated by decision block 144, on-line editing cannot be performed and the system branches back to the CRT display and update routine 135. Otherwise, the next character is inputted from the keyboard 22 as indicated by process block 145, and it is evaluated to determine whether it is a "2" or a "1," as indicated by decision blocks 146 and 147.
If the colNmand is a SEARCH 52 the status o~ the RUN/PROGRAM LOAD line 29 is inputted to the processor 45. If it is not high, as indicated by decision block 148, on-line editing cannot be performed and the system branches back to the CRT display and update routine 135.
Otherwise, the status of the OUTPUTS OFF line 3? and ~UN/MONITOR line 30 are determined by decision blocks 149 and 150. If either control line 32 or 30 is high, the SEARCH 52 command can be executed and new controller instructions can be ~ormed and loaded into the controller memory 1 as indicated by process block 151. A mode status - register in the random access memory 48 is also se ~ to indicate that on-line editing of the control program can be performed so that numerous changes in the control program 4 can be made without reentering the SEARCH 52 command each time.
If the command is a SEARCH 51, the status of RUN/
MONITOR line 30 and OUTPUTS OFF line 32 are detexmined, as indicated by decision blocks 152 and 153. If either is high, the SEARCH 51 commands can be executed as in-dicated by process block 154. Access to the "timers and counters" por~ion of the controller memory 1 is thus possible in order to change the data therein. The status register in random access memory 48 is also set so that separate SEARCH 51 commands need not be entered for each change to the timers and counters data.
Referring ~o Figs. 8a and 8c, the SEARCH 590, SEARCH 591 and SEARCH 592 commands are mode change com~
- mands which set the state of mode control lines 30-32~
Before such a mode change can be made through the key-board 22, however, the state of the RUN/PROGRAM LOAD line 29 is inputted and evaluated as indica~ed by decision block 155. If it is not high, no mode changes can be made from the program loader and ~he system branches back to the CRT display and update routine 135. Otherwise, lS the next character (i.e~, 0, 1 or 2) is inputted from the Xeyboard 22 as indicated by process block 156 and i~
is evaluated as indicated by decision blocks 157-159. If it is a "0," a SEARCH 590 command is indicated and a mode status word i5 outputted to the mode output register 70 to drive the RUN/MONITOR line 30 and the OUTPUTS OFF line 32 high and the PROGRAM PANEI, ENABLE line 31 low. The RU~/
MONITOR mode is thus established as indicated by process block 160. If a SEARCH 591 command is entered, he OU~PUTS
OFF line 32 and PROGRAM PANEL ENABLE line 31 are driven low and the RUN/MONITOR line 30 is driven high by the mode status wordj as indicated by the process block 161. The TEST/MONITOR mode of operation is thus established.
Similarly, as indicated by process block 162, if the SEARCH
592 command is entered the PROGRAM PANEL EWABLE line 31 is driven high and the OUTPUTS OFF line 32 and the RUN/

-MONITOR line 30 are driven low to establish the PROGRAM
LOAD mode of operation.
A listing of the keyboard and display executive program illustrated in the flow chart of Figs. 8a-c appears in Appendix A.
It should be apparent from the above description that a mode selector switch is provided at the control-lex processor site which enables the user ~o select one of four possible modes of operation. Three of these modes of operation (RUN/MONITOR, TEST/MONITOR and PROGRAM PANEL ENABLE) directly determine the mode of operation of the programmable controller and they each determine what functions can be performed with the pro-gram loader through the keyboard 22. The fourth pOSi~iOll (RUNJPR~GRAM ~OAD) sets the mode of opPration to RUN/
MONITOR as the positlon is en~ered and it also enables the user to select the desired mode of opexa~ion ~hrough the program loader keyboard 22. This ~ourth selector switch position in essence transfers mode control from the selector switch at the controller processor site to the keyboard 22 at the program loader site.

APPENDIX A

SEARCH CO~A~ID PROGR~M

Label $nstructlon Comment CALL RCV~ Call subroutine for inputting data from }ceyboard 2 2 ~
CR 33Q Is it a c:ancel coi7snand9 JP Z ,DISPL If so, jump to display rou~ine 13g .
C:P 6SQ I~ character a " 5" ?
JR Z,SRC5-$ I so, jump to process~_ for SEARC~ S co~ands.

De~e~mine and exectlte o~her SEARCH commands~

SRC 5 I~ ~, (PLCSl) Xnput channel 3 of ir,put multiplexer 61 a~d load in microp_ocPssor ~ regi~tex.
~IT 7,A Check s~ate af P~OG~ PA~E~
ENAE3LE line 31.
JP Z, DISP~ If it is high, jump to display routine 135~
CAIL C~C:EL Otherwise, wait for next character from key}~oa~d 22 CP 610 Is ~e character a " 1" ?
JR Z,SRCSA-$ If so, jump ~o pxocess SE~RCH
51 command.
CP 62Q Is ~he character a " 2 " ?
JP NZ,SRC5B If not, jump to SRCSB .
I2~ A,(P1CS2) Input cha~nel 1 of input multipl~xer 61 and load in microprocasso~ A regis~er.
3I$ 4,A Is RUN/PROG~M LO~D line high?
NZ,DISPL If not, jump to display routine 135.
C~lL ~TCX Call subroutine to checX st~t2 or OUTPUTS OF~ and R~J~/~ONITO~
contxol lines.
LD ~L,FLAG Load mode status register into ~ and L registe~-s.
LD (~L),12Q Set mode status resister to S~RC~ S~ mode.
CALL C~CEL Wait ~or key~oard entr~J and c~ec~ ,or canc~l co~mand.
J~ LDRGl 3ump tc on-line ~rogr m load and edi~ rou~ine SRCS~ CP 63~ Is charac~er a "9"?
JP NZ,DISPL If not, jump to display routine 13~.
~P SRC ~9 Othe~ise, jump to SRC~.

.
~34 . .

SRC5A LD ~L,FLAG Load mode sta~us registex into ~ and L regis ,~rs .
LD (HL) ,llQ Se~ mode status register ~o SEARC~I 51 mode.
CALT RTC~ Call subroutine to chec:~
state c~ OUTPUTS OF~ and RUN control lines.
LD ~L, ~ hoad numeric f lag into ~D (HL), 61Q and I, register~ and sa~ ~o indicate numeric data can be entered .
CALL CNC:E~L Wait for keyboara en~ry and check for c~nce:l cornmand.
ID D,A Store da~a from keybaard.
JP NUMIC Ju~p ~o on-line numeric data entry rou~ine.
RTCK IN A, (PLCSl) Input channel 3 of inpu~
multiplexex 61 ~nd 102d in microproc:essar A reaist~r~
BIT 4 ,A Check s~ate of RUN/MONITOR
control line.
R~T Z If RUN/~ONITo~ line ls high return to calling routin~.
BIT 6 ,~ Check state ~f OUTPrJTS OF~
control line.
RET Z If OUTPU'rS OFF is hlgh return to calli~g routine.
~rP D~SPI. Otherwise, r eturll to CR~
display update routine.
SRCS9 I~ ~, (PLCS2) Input channel 3 o~ ~nput multiple~er 61 and load in m~croprocess~r ~ register.
BIT 4 ,A Chectc state of RUN/PROGRAM
LOAD control line.
JP NZ ,DISPL If it is low, return to CRT
display update rou~ine.
CALL C~CEL Wai~ ~or kevboard enl:ry and check for cancel command.
CP 6 OQ Compare key~c)ar~ 2ntry ~o determine if it is a z~roO
J~ Z ,SRC4A-$ If it is a zero jump to SRC~
CP 6 lQ Ccmpare keyboard er~xv to determ~rle if it is a OnQ.
J~ Z, 5~::4B--? If it is a one jump ~o SRC~3 .
CP 52Q Compars kev~oard ~ntry to determine i~ it is a two.
JP N2 ,DISPL If it is ~ot a two, ,~nP ~o the C~T display update routine.
I,D A, ~S~ATR) Lo d sta'cus con~rol regist~x into microprocessor A xegister.
Al~D 33 7Q Se~ PROG~ PAN:~L ~ BL bi~
high .:
I,D ~ST~R~ ,~ LGad updated status cont~ol register bac~c i nto rr.emor ~ a 8 .
OUT (STA~ ~ ,A Output statu~ control registex irl A rsgist~x to mode OUt~llt r~gister 7 0 .
JP DISPL Jump to C~T display update routine .

. . .
.. . . . . . . -\
i5~

SRC59A LD A,(STAT~) Load status controL register into microprocessor A register.
AND 357Q Set RUN bit highD
LD (STATR),A Load updatsd status control reyister back into memory 48.
OUT (STAT),A Output sta~us control register in A register to mode output register 70.
JP DISPh Jump to CRT display update routine.
SRCS9B LD A,(STATR) Load status control xegister into microprocessor A register~
AND 375Q Set OUTPUTS OFF line bit high.
LD ~STATR),A Load updated status control register back in~o memory 48.
OUT ~STAT),A Output statu~ control register in ~ xegister to mode output register 70.
~P DISPL Jump to CRT display ~pdate . routine.
CNCEL CALL RCVV Wait for character from key-board 22.
CP 33Q Check for cancel command~
RET Z If not a cancel command return to calling routine.
JP DISPL If a cancel command, jump to CRT display update routine.

" ~ " ~ , . ` . . . .

Claims (9)

The embodiment of the invention in which an ex-clusive property or privilege is claimed is defined as follows:

1. In a programmable controller having a memory which stores a control program and a processor for reading out the control program instructions and ex-ecuting them to control operating devices on a controlled machine, the combination comprising:
a selector switch associated with said controller processor and being manually operable to selectively generate control signals at a set of output terminals;
mode control lines connected to said selector switch output terminals;
a program loader processor coupled to said control-ler memory and controller processor and connected to said control lines, said program loader processor including first means for sensing the logic state of each of said mode control lines, and second means which is enabled by the logic signal on one of said mode control lines and is responsive to manually entered data to generate logic signals on selected other ones of said mode control lines;
and means connected to said program loader processor for manually entering data indicative of the mode control lines upon which logic signals are to be generated.

2. The programmable controller as recited in claim 1 in which an enabling logic signal is generated on said one mode control line by said selector switch in one of its selectable positions and a disabling logic signal is generated thereon when the selector switch is in its other positions.

3. The programmable controller as recited in claim 1 in which said means for manually entering data is a keyboard which is located remotely from said controller processor and said selector switch.

4. In a programmable controller having a memory which stores a control program comprised of a set of controller instructions, having a controller processor which is operable to sequentially read controller in structions out of said memory and execute them, and having an I/O interface rack which couples to said controller processor and which interfaces it with sensing devices and operating devices on a controlled machine, the improvement therein comprising:
a mode switch associated with the controller processor which has a plurality of manually selectable positions and associated output terminals, said mode switch being operable to generate a logic signal at the output terminal associated with the selected position, a set of mode control lines, one coupled to each of said mode switch output terminals and at least one coupled to said controller processor to effect its mode of operation; and a program loader connected to said mode control lines and coupled to said controller memory to read con-troller instructions out of said memory and to write con-troller instructions into said memory, said program loader including:
manual data entry means for entering commands into the program loader, means for determining the presence of a logic signal on each of said control lines, and means responsive to the presence of a logic signal on a selected one of said control lines and selected commands entered through said data entry means for genera-ting a logic signal on another one of said mode control lines.

5. The programmable controller as recited in claim 4 in which each of said selected commands is associated with one of said other mode control lines and said last named means is responsive to each of said selected commands to generate said logic signal on its associated mode control line.

6. The programmable controller as recited in claim 4 in which said program loader includes a microprocessor, said means for determining the presence of a logic signal on said control lines include an input multiplexer coupled to said microprocessor, and said last named means includes an output register coupled to said microprocessor.

7. The programmable controller as recited in claim 6 in which said manual data entry means includes a key-board which is coupled to said microprocessor.

8. The programmable controller as recited in claim 7 in which said keyboard is coupled to said microprocessor through a serial data link.

9. The programmable controller as recited in claim 4 in which one of said mode control lines is coupled to said I/O interface rack and the logic signal generated thereon operates said I/O interface rack to decouple opera-ting devices on the controlled machine from the programmable controller.