CA1111923A - Store and forward type of text processing unit - Google Patents

Abstract

STORE AND FORWARD TYPE OF TEXT PROCESSING UNIT
Abstract A store and forward unit having an output print station with convenience copying capabilities has connec-tions to diverse text signal sources and destinations.
Such diverse sources and destinations may have established textual format and control characters not necessarily shared with other sources and destinations. The store and forward unit, upon receiving a set of text signals, examines the text control characters. Based upon such examination, the store and forward unit processes such text without chang-ing the control characters provided that all destinations connected to such unit can use such control characters. If, on the other hand, the destinations cannot use such control character, the unit adds sufficient control characters for allowing the received text as modified by the additional characters to be transmitted without text processing analy-sis to any of the connected destinations. If desired, the control characters not usable or not recognized by a re-ceiving destination can be deleted prior to transmission to such destination. Accordingly, when received text is to be retransmitted to a plurality of diverse destinations, the store and forward unit text processes the received sig-nals but once and supplies the text processed signals to the diverse destinations with only deletions of control charac-ters.

Description

Background of the Invention The present invention relates to a store and forward unit for handling text type of data signals in a B

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1 communications environment which can include convenience copying capabili-ties interleaved with text processing func-tions and wherein the text processing can be repeated for a plurality of diverse destinations.
Automated editing and text processing is becoming a developed art. Computerization of such text processing is quite popular because of cost-performance considerations.
In the past, many of the text processing systems involving a plurality of diverse types of units have used a particular text control code unique to such aggregation of diverse units. Several manufacturers of text processing equipment have developed independent and different noncompatible text control characters, which provide greater facility for their respective apparatus and products, from those provided in other manufacturers' apparatus and products.
With the plurality of different types of text process-ing apparatus and the advent of enhanced communication sys-tems, interconnecting diverse types of text processing apparatus and systems having incompatible text control characters becomes highly probable and, in many instances, such interconnections are economically desirable. That is, a first text processing system at location A may wish to supply text signals via a communication network to a second text processing system at loca~ion B. The two text pro-,j cessing systems may require diverse types of text control characters. If the connection is merely a point-to-point , connection, then a single text processing procedure is necessary for conveying the text signals between the two locations. However, in i .,.~

9~3 1many communication systems, a plurality of such text pro-cessing systems can be interconnected in accordance with predetermined switching protocols. A diversity of text characters may be required; therefore, if location A wishes to transmit text signals to four different receiving text processing systems, then the text processing may have to be repeated up to four times. Such repeated -text process-ing on the same text detracts from text processing perform-ance of the transmitting unit.
10Other text processing systems may have diverse types of equipment connected thereto, each of which may require different text control characters. For example, a charac-ter generator supplying an image via a laser beam to an electrographic copy reproducing unit may require a first set of text processing control characters. A magnetic card automatic typewriter system may require a second set of control characters. A communication link of the Bysync type may require yet a third type of text control charac-ters. Yet further connections to the other apparatus may require yet further sets of text control characters. If a single text is to be transmitted to more than one of such utilization systems, reprocessing the same text for each of the receiving destinations or text processing sys-tems is required. Assuming that it is desired to minimize product cost, then such reprocessing detracts substan-tially from the performance of the text processing system.
Ac~ordingly, it is highly desirable that text processing capabilities be enhanced while minimizing product cost.

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. . -: ': , . . -1 Summary of the Invention It is an object of the present invention to provide a method of operating a store and forward unit of the text processing type wherein reprocessing of the same text destined for a plurality of diverse destinations is unnecessary.
A method in accordance with the present invention contemplates operating a store and forward device for supplying signals to one or more of a plurality of diverse destinations wherein the destinations require diverse sig-nal format. The store and forward device receives data indicating signals along with the control signals inter-leaved with the data indicating signals`fpr indicating functions to be performed with respect to the data indi-cating signals. The store and forward unit stores the data indicating signals and analyzes the received control signals. Such received control signals are modified by the store and forward unit by substitutions and additions to generate an entirely new set of control signals which ~ 20 includes control functions for all of the plurality of ;; possible destinations. Then the store and forward unit selects a destination and transmits the data indicating signals with the new control signals while deleting ones~ `
of the new control signals not usable o~ recognized by the selected destination with respect to the~transmltted data indicating signals.
The foregoiDg and other objects, features and advan-tages of the invention will be apparent from the follow-lng more particular description of preferred embodlments of the invention, as illustrated in the accompanying drawings.

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1 The Drawings FIGURE 1 is a block signal ~low diagram of apparatus incorporating the present invention.
FIGURE lA is a block diagram of a control system for operating the FIGURE 1 illustrated maehine.
FIGURE lB is a diagrammatic showing of a constructed machine using the arrangement shown in EIGURE 1.
FIGURE lC is a flow diagram illustrating the operation of the FIGURES 1 through ls indicated machine for operating on text in aecordanee with the present invention.

FIGURE 2 is a bloek signal flow diagram of a system eontroller usable with the FIGURE lA illustrated eontrol system.
FIGURES 3A and 3B are bloek diagrams that indieate the eonneetions between a eontrolling mieroproeessor and a eontrolled deviee within the FIGURE 2 illustrated eontroller.
FIGURE 4 is a bloek and signal flow diagram of a mieroproeessor usable in the FIGURE 2 illustrated controller.
' FIGURES 5 and 6 are charts showing the instruetion repertoire and an execution of eomputer instruetions by the FIGURE 4 illustrated mieroproeessor.

FIGURE 7 is an address space diagram illustrating the .;
; interaetions of the two microproeessors eontained within the FIGURE 2 illustrated controller.
FIGURE 8 is a sehematie diagram of apparatus for ~ logieally intereonneeting data signal transfer busses i;~ used in the FIGURE 2 illustrated controller.

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i 1~ BO9-76-053 -5-~' - , -1 FIGURE 9 iS a logic flow diagram illustrating opera-tion of the invention incorporated in a fixed logic sys-tem instead of a programmable system.
Detailed Description In the drawings, like numerals indicate like parts and structural features. FIGURE 1 illustrates apparatus incorporating the present invention. The apparatus is physically embodied in a copy production machine illustrated - and described with respect to FIGURE lB. In FIGURE 1, a system control processor SCP 60 contains programming utiliz-ing the present invention for adapting the FIGU~E lB illu-strated copy production machine 10 as a store and forward unit. SCP 60 includes a system text processor using a universal text format 60~ plus a communications adapter 60B which, under program control, connects a remote terminal connector RTC 17 with unit 60. RTC 17 includes a modem 17A
and a communications link 17B for communications with other ; units (not shown). Additionally, unit 60 includes recorder adapter 60C for connecting unit 60 to a local terminal LT
16, which may be a magnetic card automatic typewriter such as that manufactured by the International Business Machines ~ ~ Corporation, Armonk, New York. LT 16 includes a recording `~ channel 16A connected with a magnetic card reader/recorder 16B. Further, unit 60 includes a page memory 64, a semi-conductor random access memory. Memory 64 is connected not only to the processor 60A but also to an image genera-tor 12B for imposing images on a photoconductor drum later described with respect to FIGURE lB.

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1 Unit 12B includes an image processor 12BA and an image generator 12BB. Image processor 12BA receives image indi-cating signals from page memory 64 and converts them into a form for use by the image generator generating an opti-cal image to be produced.
Image indicating signals of the text type can be re-ceived from either RTC 17 or LT 16. RTC 17 and LT 16 each have their own unique set of control codes which are not compatible with each other. The received image indicating signals and control codes are processed through the adapter 60B or 60C to system text processor 60A. System text pro-cessor 60A, in accordance with the present invention, ana-lyzes the control code characters and modifies them to use the new modified code with any of the plurality of possible text destinations. Such text processed image indicating signals are stored in page memory 64 for use by laser input ; 12B and as a working memory in conjunction with system text processor 60A. If the text processed signals are to be retained for later transmission, such text processed signals are transferred from page memory 64 to nonvolatile store 19. From nonvolatile store 19 system text pro-~; cessor 60A can fetch the stored signals for retransmission to any of the illustrated links 17, 16 or 12B. In such a transmission system, the text processor 60A does not re-process the text signals. Rather, it only analyzes the control characters for deleting unwanted characters while simultaneously converting the code characters from one `:
code to another, i.e., from an internal code to a EBCDIC
code, for example.

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FIGURES lA and lB respectively show a copy produc-tion machine 10 constructed using the principles of the present invention and which may be advantageously employed in the FIG~RE 1 illustrated image communication network.
The copy production machine centers around a copy produc-tion portion CPP 13. CPP 13 is illustrated in FIG. lB as a transfer electrographic copy production portion although no limitation there~o is intended. A plurality of image inputs are provided to CPP 13. Such inputs, selectively denoted by numeral 12, include a document scanning opti-cal input in optical communication with a semiautomatic document feed SADF lI. SADF 11 includes a document glass on which an original document may be placed either manually by lifting a SADF lid (not shown), or via semiautomatic document feed from input tray ~not shown). The optical ima~e from SADF 11 is transmitted to CPP 13 using known optical techniques commonly found in convenience copiers of several types. Additionally, original input optics 12 include a laser input LI which receives word processing indicating signals for creating an optical image as an image input to CPP 13 via common input 23. The original input optics 12 include a SADF control OIC 12A as well as a laser input control 12B (FIG. lA).
The laser input can receive signals from a local terminal LT 16 (FIG. lB) which is a word processing termi-nal for receiving word processing signal bearing magnetic cards at input slot 16A and for ejecting such cards at output slot 16B. Signals from LT 16 are temporarily stored .~. .
in nonvolatile store NVS 19. Additlonall~, for communica-,~ 30 tion in an image BO9-76~053 -8-~, ~

1 communication network as shown in FIGURE 1, a remote terminal connector RTC 17 provides signal communication to various remote units, collectively denoted by numeral 13. In FIGURE lA, the numeral 18 indicates the remainder of the network as shown in FIGURE 1. The word process-ing signals from LT 16 or RTC 17 are initially stored in NVS 19. From NVS 19, multiprocessor machine controller MPMC 15 effects transfer of the signals to LIC 12B
(FIG. lA) for generating an image to be transferred to CPP 13, as will become more readily apparent. In one em-bodiment, print johs received by RTC 17 and LT 16 arealternated. A priority scheme could be employed if de-sired.
Copy production machine 10 also includes a copy output portion 14 having a plurality of copy receiving units.
When laser input LI 12 supplies images to CPP 13, the copies produced are directed toward output portion 14B as will be later more fully described. When SADF 11 is used as an input to optics 12, the copy production machine 10 is in what is termed a copy mode wherein the copies pro-duced by CPP 13 are directed either to copy exit tray 14Aor to copy collator 14C. The output unit 14B in a con-structed embodiment was reserved for copies produced in the print mode.
MPMC 15 controls all units in copy production machine 10. The various closely controlled units such as LIC
12B, NVS 19, RTC 17, and LT 16 are controlled by a pair of later described unidirectional busses collectively denoted by MIDI in FIGURE lA. The other units are those related to copy production and which are supervised by ` MPMC 15.

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1 Communication is by a bidirectional data bus IOC shown con-nected to the copier exit control OE C 15A, printer exit control PEC 15B, CPP 13, SADF control 12A. The interac-tions of the various units of copy production machine 10 will become apparent from a continued reading.

sefore proceeding further with the description of the invention, the operation of document reproduction por-tion 13 is described as a constructed embodiment of a so-called xerographic copy production machine. Photoconductor member 20 rotates in the direction of the arrow past a plurality of xerographic processing stations. The first station 21 imposes either a positive or negative electro-static charge on the surface of photoconductor member 20.
It is preferred that this charge be a uniform electrostatic charge over a uniform photoconductor surface. Such charg-ing is done in the absence of light such that projected optical images, indicated by dash line arrow 23, alter the electrostatic charge on the photoconductor member in pre-; 20 paration for image developing and transferring. The pro-jected optical image from original input optics 12 exposes the photoconductor surface in area 22. Light in the pro-jected image electrically discharges the surface areas of photoconductor member 20 in accordance with lightness.
With minimal light reflected from the dark or printed areas .~;
of an original document, for example, there is no cor-responding electrical discharge. As a result, an electro-static charge remains in those areas of the photoconductive :`
`` surface of member 20 correspondlng to ~ ~ 3o , :
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l~ Z3 1 the dark or printed areas of an original document in SADF lL

2 (semiautomatic document feed). This charge pattern is

3 termed a "latent" image on the photoconductive surface.
1 Interimage erase lamp 30E discharges photoconductor member 20 outside defined image areas.
6 The next xerographic station is developer 24 which 7 receives toner ~ink) from toner supply 25 for being deposited ~ and retained on the photoconductive surface still having an 9 electrical charge. The developer station receives the toner ln with an electrostatic charge of polarity opposite to that of 11 the charged areas of the photoconductive surface. Accordingly, 12 the toner particles adhere electrostatically to the charged 13 areas, but do not adhere to the discharged areas. Hence, t~ the photoconductive surface, after leaving station 24, has a .15 toned image corre~ponding to the dark and l~ght areas of an lG orig.inal document in SADF 11.
17 Next, the latent image is transferred to copy 1~ paper in transfer stati-on 26. The paper is brought to the 19 station 26 from an input paper path portion 27 via synchro-2C nizing input gate 28. In station 26, the copy paper is 21 brought into contact with the toned image on the photoconductive 22 surface resul'ting in a transfer of the toner to the copy 23 paper. After such transfer, the sheet of image bearing copy paper is stripped from the photoconductive surface for .1 .
transport along path 29. Next, the paper has the electro-; ~'6 statically carried image fused thereon in fusing station 31 27 for creating a permanent image on the copy paper. During ~8 such processing, the copy paper receives electrostatic .

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1 charges which can have an adverse affect on copy handling.
Accordingly, the copy paper after fusing is electrically discharged at station 32 before transfer to output portion 14.
Returning now to the photoconductor member 20, after the image area on member 20 leaves transfer station 26, there is a certain amount of residual toner on the photo conductive surface. Accordingly, cleaner station 30 has a rotating cleaning brush (not shown) to remove the residual toner for cleaning the image area in preparation for receiv-ing the next image projected by original input optics 12.
The cycle then repeats by charging the just-cleaned image area by charging station 21.
The production of simplex copies or the first side of duplex copies by portion 13 includes transferring a blank sheet of paper from blank paper supply 35 to trans-fer station 26, fuser 31, and, when in the simplex mode, directly to the output copy portion 14. Blank paper sup-ply 35 has an empty sensing switch 36 which inhibits opera-tion of portion 13 in a known manner whenever supply 35 is out of paper.
When in the duplex mode, duplex diversion gate 42 is actuated by the duplex controlling circuits 50 to the up-~ ~ ward position for deflecting single image copies to travel ,~ over path 43 to the interim storage unit 40. Here, the partially produced duplex c`opies (image on one side only) reside, waiting for the next subsequent single image run in which the copies receive the second image. Such copies ,;

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, )Z3 1 residing in interim storage unit 4~ are in an intermediate copy production state.
In the next successive single image run, initiated by inserting a document into SADF 11, the copies are re-moved one at a time from the interim storage unit 40, trans-ported over path 44, thence to path 27 for receiving a second image, as previously described. The two image duplex copies are then transferred into output copy portion 14. Switch 41 of interim storage uni~ 40 detects whether there are any copies or paper in interim storage unit 40.

If so, an intermediate copy production state signal is sup-plied over line 45 to later described control circuits.
The copy production machine has a control panel 52 having a plurality of lights and switches (most not shown), as well as a set of copier control circuits which operate the entire machine synchronously with respect to the move-ment of the image areas of photoconductor member 20. Bill-ing meter M of the copier control circuits counts images processed for billing purposes. For example, paper release gate 28 is actuated synchronously with the image areas moving past developer station 24. Such controls are well known in the art and are not described here for purposes of brevity.
A description of the operation of the document repro-duction mechanism 13 is included in United States Patent No. 4,086,658, assigned to the assignee of the present .i application.
The operation of the above-described machine when practicing the present invention is illustrated in the FIGURE lC flow chart. Details of such operations to fol-low with a more detailed description of the computer por-tion of the copy production machine 10. The FIGURE lC flow chart illustrates the operation of the system text processor 60A.

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1 Received text from either of the text sources 16 or 17 (Fig. 1) is first subjected to a text analysis at step 54. Imposed upon such analysis are text format constraints programmed into system text processor 60A. Such con-straints are typically generated by the respective sources 16, 17 through an operator control language (OCL) trans-mitted with the data indicating control signals as an initial set up card or set of signals. Such text format constraints include margins, tabulation settings, font selection, all as normally used in text processing. Fur-ther included in the text analysis is a comparison of the received control characters from sources 16, 17 with the control codes available. This is a table look-up opera-tion in that all of the legal codes receivable from sources 16, 17 are indexed to all of the codes usable in the en-tire FIGURE 1 illustrated system. System text processor 60A, using a computer program, adds, substitutes, or other-wise modifies the received control characters in accord-ance with the format constraints and the control codes available. An example of such modifications is set forth in Table I below for use with the illustrated FIGURE 1 machine for selected control characters, it being under-stood that other control characters will be subjected to other types of text processing functions similar to those illustrated in Table I.

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l Legend for 1'able_I
2 FT-II Forward Half Index 3 ~II Reverse l~alf Index

4 CIII Change Half Index RHT Re~uired E~orizontal Tab 6 NL New Line 7 PDLM Print Delimiter 8 SP Space 9 VT Vertical Tab EMF End Margin Fill 11 EOR End of Row 12 RFF Required Forms Feed 13 EOP End of Page 14 E~T Horizontal Tab SOF Start of Format lfi Dn Data or Control Information LP Line Feed 18 SCT Special Control Text . ?n Unknown (Random) Memory :~ :
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1 In the above Table I,the left hand column indicates 2 input text as received via input RTC 17. The alphabetic 3 characters represent control characters usable with Bysync 4 communications. The Greek alpha character represents inter-leaved text characters, the coding of ~hich is not pertinent 6 to the practice of the present invention. As a practical 7 matter, the universal text represented in the second column 8 is a conversion from the input text insofar as text char-g acters are concerned to an internal code. If, for example, the universal text was then returned to the RTC 17 for 11 retransmission to a remote unit the text coding would be 12 changed. This action ls a direct substitution, well kno~Jn 13 in text processing. For using RTC 17 as a destination, the 14 control characters of the universal text, FHI CHI, comparing with FHI would result in deletion of CIII while the second 16 control character RHI CHI would result in transmission of 17 only RHI. If the text corresponding with those control 18 characters were transmitted to diverse destination 12B, the 19 control characters would be CHI in both instances. If the text would be sent to I.T 16 the control characters would be 21 converted to FHI and RHI~ also again by deletion. The other 22 control characters using known input text formats are converted 23 as shown to the various adapted text.
24 From the text analysis the universal formatted text signals are stored in page memory 64 which serves as a 2~ buffer for the universal text. From buffer or page memory 27 64 the universal text is transmitted via system text pro-28 cessor 60A with the unwanted control codes being deleted at G

1 step 56. The deletion of the unwanted control codes re-sults in the adapted text being sent to utilization means which includes, of course, the three connections 12B, 16 and 17. Further, if the universal text is to be trans-mitted to additional destinations, the universal text is stored in nonvolatile store NVS 19 for later retrieval.
Before describing the computer programming for effecting such efficient text processing, the system hard-ware in which the programming resides is first described for a better understanding of programmed function and operations.

The multiprocessor machine controller MPMC 15 is shown in block diagram form in Figure 2. MPMC 15 includes a production machine controlling subsystem SCP 60 and a copy production machine controlling subsystem CMC 61. SCP
60 includes a system microprocessor SMP 62 which executes a set of control programs contained in ROS control store 63, and uses page memory 64 as a main or working store.
SMP 62 communicates with the other units in SCP 60 as well as peripheral units as later discussed, via a set of three unidirectional data transfer busses. The bus DI transfers data signals from the other units to SMP 62. In a pre-ferred constructed embodiment, DI was eight bits wide (one character) plus parity, while signals emanating from SMP 62 were carried over bus MI to all of the other units. Address signals selecting which units are to send or to receive signals with respect to SMP 62, as well as the other units are provided by SMP 62 over 16 bit wide address bus ADS. The above-described bus interconnections also provide signal .,1`~:, " lJ ~1923 1 communication between SCP 60 and the nonvolatile store 19, laser input 12B, local terminal LT 16, remote terminal con-nector RTC 17, and to CMC 61 via multiprocessor connector MPC 65.
CMC 61 is constructed similarly to SCP 60. It includes a copy microprocessor CMP 170 plus a ROS control store 171 containing programs for operating CPP 13, a working store 172 for use as a main memory, and input/output registers 173, 174. Signal communication between these units is via a bi-directional eight bit data bus IO under addressing con-trol from CMP 170 via 16 bit address bus ADC. C~P 170 sup-plies address signals over bus ADC for selecting the source and destination of signals with respect to CMP 170. Such selection includes an address to multiprocessor connector MPC 65. I/O bus is preferably one character wide (eight bits) while ADC is preferably two characters wide sixteen bits. CMC 61 via MPC 65 appears as an I/O device to the SCP
60 in the same manner as units 19, 12B, 16 and 17 appear as I/O devices. Processor intercommunication via MPC 65 requires a plurality of memorycycles in both SCP 60 and CMC

61. A clock 75 times SCP 60 and CMC 61 on a memory cycle synchronized basis. That is, page memory 64 and working store 172 have identical length memory cycles. The opera-tion of the memories are in synchronism under control of a two-phase clock, phase 1, and phase 2, supplied over lines 76a to all units within MPMC 15. Timing connections are not ~: shown for purposes of brevity. Additionally, clock 75 issues a series of S pulses, Sl through S5, for timing instruction execution within CMP 170 and SMP 62.

llll~Z3 1 Addltionally, it may be desired to interconnect, under program control, the busses MI, DI and ADS for enabling sig-nal transfers in later described desired paths. To achieve t:his result, bus select circuit 76 under SMP 62 control, provides communication between the various busses. For example, signals received from MPC 65 on bus MI can be transferred through bus select circuit 76 to bus DI for reception by SMP 62. Other permutations of signal trans-fers among the busses can be similarly accomplished.
FIGURE 3A shows the logical interconnections between SMP 62 and controlled units 63-65. All of the signals on the busses and individual control lines go to all units, the ADS and GP signals selecting which controlled unit is to respond for either receiving data signals or supplying data signals, respectively. SMP 62 supplies addressing sig-nals over bus ADS to all units. If the instruction supplied over bus GP indicates that data is to be transferred between SMP 62 and a controlled unit. Then a binary one on the I/O

line indicates signals are to be transferred to the micro-processor over DI and a binary zero indicates signals are to be transferred from the microprocessor SMP 62 over MI.
Write line WRT indicates to the page memory that signals are to be stored in the memory. A signal on the ITP line indicates an interrupt is in progress. In this situation, the microprocessor 62 program has been interrupted and microprocessor 62 is handling the interrupt. INT is the interrupt request signal, SDL is a signal received from system clock 75, meaning data latch and will be later `~ explained with respect to FIGURE 4. The symbol SX

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1 means sliver-killer and the line SK provides a control signal for eliminating extraneous signals commonly re-ferred to as slivers. These signals result in interac-tion between successively actuated bistable circuits termed latches. Other timing signals for coordinating operation of all of the units in the MPMC 15 (Fig. 1) are received from system clock 75. Additionally, power on reset circuit POR activates system clock 75 to send out timing signals and control signals for resetting all of the units to a reference state as is well known in the computer art.
In CMC 61 (Fig. 1), the decoding circuits and logic circuits which respond to the above-described signals are those normally used in conjunction with interconnecting controlling and controlled units. Since such circuits and design principles are well known, further description of these details are not provided.
Referring next to FIGURE 3B, the logical interconnec-tions between microprocessor 170 with controlled units 171-174 are shown. All of the signals on the busses and individual control lines go to all units, the ADC signals selecting which controlled unit 171-174 is to respond for either receiving data signals or supplying data signals, respectively, over bus IO. Control line I/O indicates whether CMP 170 is supplying or receiving signals over bus IO. When the I/O line has a binary one, signal data or instruction signals are to be transferred to the micro-processor 170 over IO. When it is a binary zero, micro-processor 170 supplies data signals over IO. Write line WRT indicates to .,~

il923 1 memory 172 that signals are to be stored in the memory.
The lines in Fig. 3B having similar designations as cor-responding lines in Fig. 3A perform the same function as described above in connection with Fig. 3A. Other timing signals for coordinating operation of all of the units 171-174 are received from system clock 75.
The Microprocessor 170 Both microprocessors SMP 62 and CMP 170 can be con-structed identically. CMP 170 is described in detail; it is understood that the description also applies to SMP 62.
The data flow of the microprocessor 170 is detailed in Fig. 4. The data flow and operation of SMP 62 is identi-cal. The sequence control circuits 180 are those logic cir-cuits designed to implement the functions performed in the timing context of the following description. Such sequence control circuits SCC 180 include instruction decoders, memory latches and the like, for sequencing the operation of the data-flow circuits illustrated in Fig. 4, , :

, lll~S~Z3 1 using two-phase clock signals, ~I and 02 from clock 75.
The processor contains an eight bit wide (one character wide) arithmetic and logic unit ALU 181. ALU 181 receives signals to be combined during a 02 clock signal and sup-plies static output signals over ALU output bus 182 during each 01. Operatively associated with ALU 181 is a six~een bit accumulator consisting of two registers. Low register ACL 183 has its output connections over eight bit wide bus 184 as one input operand to ALU 181. The second register of the accumulator is ACH register 185. When the micro-processor 170 operates with a two character or two byte word, the functions of ACL 183 and ACH 185 alternate.
That is, in a first portion of the operation, which requires two complete microprocessor 170 cycles, as later described ACL 183 contains the lower order eight bits of a sixteen bit word, while ACH 185 contains the upper eight bits of the sixteen bit word. ALU 181 first operates on the lower eight bits received over ACL bus 184 and supplies the re-sult signals over ALU output bus 182 to DB register 186.
During this same transferring action, ACH 185 is supplying the upper eight bits through DO register 187, thence over bus 188 to ACL 183. During the next ALU cycle, the upper eight bits are operated upon. In the preferred and con-structed embodiment, ALU 181 operates with two's comple-ment notation and can perform either eight bit or sixteen bit arithmetic as above described. Eight bit logical operations are also performed.
ALU 181 contains three indicating latches (not shown) which memorize the results of arithmetic and logical ~è~

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1 functions, such as conditional jumps or branches, and so-called input carry instructions, for use in later processor cycles. These three indicators are low, equal (EQ), and carry. Processor sequence control circuits 180 can con-trol a single level of interrupt and include an internal interrupt mask register (not shown) for disabling inter-rupts as i~ well known in the computer arts. The ALH regis-ter 190 (high order bits of the address) and ~LL register 191 (the low order eight bits of the address) are designated as work registers. These registers are divied into sixteen groups of sixteen, two byte registers. A portion of ALL
register 191 supplies GP signals for selecting which groups of registers are accessible by microprocessor 170.
As will be later detailed, microprocessor 170 requires two processor cycles for processing an I/O instruction.
The first cycle is a set-up cycle and the second cycle is a data transfer cycle. When an I/O operation requires a transfer of a succession of bytes, then the first cycle sets up a unit 171-174 for transferring a plurality of bytes such that the I/O operation appears as a set-up cycle fol-lowed by a plurality of data transfer cycles. The micro-processor 170 is designed to operate with a plurality of relatively slow acting devices, e.g., copy production machine 10. The time required for the microprocessor 170 to perform its functions is relatively short compared to '.

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~11119Z3 1 the time required by the controlled devices. Accordingly, under clock 75 control, the microprocessor 170 can be effectively turned off to allow a controlled device to have exclusive use of the IO bus.
From examination of FIGURE 4, it can be seen that all of the registers, being latches, will maintain their res-pective signal states whenever the clock phases, 01 and ~2, are not supplied. Therefore, upon an interruption of the microprocessor 170 by a controlled device 171-174, the sig-nal state of the processor 170 enables it to begin operat-ing again as if there had been no interruption.
The other registers in the microprocessor 170 are des-cribed with the instructions set for facilitating a better understanding of the interaction of these registers. The microprocessor employs instructions of variable length, 1, 2, or 3 bytes. The first byte of any instruction always includes the operation code and succeeding bytes, numbered 2 or 3, contain an address data or immediate operand data.

The fastest instruction execution requires one micro-processor cycle while the longest instruction requires six processor cycles. An interrupt requires ten cycles to process. In all designations, bit 0 is the least signi-ficant bit.
Instruction Repertoire The instruction repertoire is described in groups of instructions, all of which have defined instruction word formats. The instructions are defined by the title, mnemonic, ., '.

., ' .

. :.t .~, r~
~5 ~

~1~l1923 1 number of cycles required by the microprocessor to execute the instruction, number of operands (OP), and the number of bytes in the instruction word. Additionally, a break-down of the command structure of the first byte is given.
REGISTER ARITHMETIC
-Instruction Mnemonic Cycles OP Byt~s Add AR 3 Subtract SR 3 Load LR 3 Store STR 3 Load/Decrement LRD 5 Load/Bump LRB 5 The instruction byte is divided into two portions. The most significant four bits indicate the instruction code and the lower four bits indicate a register within a group of sixteen registers as the operand source. All operations are taken to the accumulator register. The Register Arith-metic is two-byte arithmetic.
BYTE ARITHMETIC
Instruction Mnemonic Cycles OP Bytes Add AB 3 1 2 Subtract SB 3 1 2 Load LB 3 1 2 Store STB 3 1 2 '~ Compare CB 3 1 2 `~ ~ And NB 3 1 2 Or OB 3 1 2 Xor XB 3 1 2 ,,~

: B

~li9Z3 1 The most significant five bits of byte one of the in-struction indicate the instruction command while the lower-most three bits indicate one of eight registers.
The second byte indicates one of 256 byte addresses in memory to be used in the arithmetic, i.e., difference between the register arithmetic and the byte arithmetic is that a byte arithmetic obtains the operand from memory.
IMMEDIATE ARITHMETIC
InstructionMnemonic Cycles OPBytes --Add AI 2 1 2 Subtract SI 2 1 2 : Load LI 2 1 2 Compare CI 2 1 2 And NI 2 1 2 Or OI 2 1 2 Xor XI 2 1 2 Group GI 2 3 2 The byte one format is the same as for byte arithmetic with the second byte being the operand data. In the last instruction, Group, (GI), the immediate data selects the registers in the register group as will become apparent.

ACCUMULATOR ARITHMETIC

InstructionMnemonic Cycles OPBytes Add 1 Al 2 0 Subtract 1 Sl 2 0 Shift Left SHL 2 0 Shift Right SHR 2 0 Clear CL~ 1 0 Transpose TRA 1 0 Input Carry IC 1 0 , ~ BO9-76-053 -27-~' 1~119Z3 1 All eight bits of byte one are used to denote the function to be performed. All operations are conducted within the accumulator. Transpose instruction, TRA, swaps the high and low order register contents of accumulator registers 183 and 185.
INDIRECTS
Instruction Mnemonic Cycles OP Bytes Store STN 4 Load LN 4 This is an indirect addressing set of instructions wherein the upper-most five bits indicate the function and the lower-most three bits signify which of eight registers is to contain the address in memory to be accessed.
BIT CONTROL
Instruction Mnemonic Cycles _ Bytes Test/Preserve TP
Test/Reset TR
The upper five bits of the instruction byte indicate the function and the lower three bits indicate a register to be accessed as a mask for testing the accumulator regis-ter.
INPUT/OUTPUT
InstructionMnemonic Cycles OPBytes Input IN 4 1 2 Output OUT 4 1 2 These two instructions use the first byte as a com-mand and the second byte to address one of the 256 addresses on the busses, MI, ~I, or IO.

BO~-76-053 -28-Instruction Mnemonic Cycles _ Bytes In the first three JUMP instructions, the three most significant bits indicate the function. A fourth bit indi-cates JUMP on plus or minus and the four lower order bits indicate the jump length. In one notation, the plus indi-cation is a binary zero and the minus indication is a binary one.

. ~ - . .
In the branch instructions, except for the BRANCH AND

LINK, the first four most significant bits together with the lower two significant bits indicate the functions. The middle two bits indicate plus or minus 256 address positions or ignore. The BRANCH AND LINK, a three byte instruction, selects one of four registers with the lower two bits of the command first hyte and uses the upper-most six ~its as a function indicator. The two bytes are a sixtten bit address for the address bus with the second byte being the eight least significant bits and the third byte being the eight most slgnificant bits.

,~

11115~3 1 The RETURN instruction is merely a one byte instruction having the same format as the BRANCH AND LINK command byte.
The interrupt is not an instruction, but a single signal received over interrupt line I.
ALU Condition Codes The table below indicates the condition code in the ALU-low, equal (EQ), or carry set as a result of the exe cuted class of instructions as set foxth in the table below.

., J.l O O
r~

C O '~ n J v ~I l .n ~ rrJ
O O ~ ~ -~ Q ~ ~ ~ ~ ~ O . o rn h ~ ~ .C.C .C ~ v rn v rn ~ C C C C C . ~J Q
rn ~ rn ~ r~S r~ rlS ~r~ ~ O t C ~ J ~ C C ~' ~~
o v v 3 ~ v ~ ~ ~ , 3 ~ ~ v ~ ~ h rn 3o ~ aJ
v rn o~ rn ~J ~I rn R~
o O O 0 ~1 ~ ~ C) S~ ~ a) ,S 3 ~J, n O ~ S :~ C
o o ru o ~ ~ ~ ~s~
O O ~ rl ~ ~ O JJ Q~ ~ C) V rn Y
Q ~1 r~ ,~ r~l ~ ~ ~ U rv -1 CY .,~ Q ~ R. o o ~ E
- ~1 rn rn .n ~: C rC ~ O rrS C U ~J ~ O
_ ~ ~ rn ~ rn ~ aJ rn rn ~ ~ 11 C ~ r~ L~
.r~ D rn rn- v- v ,1 s~ o O :~, o r-l .~ Q a~ rn ,~ rn ,~ o r-J O r~l Q nS ~ U ~ n rS r~ ~ n ~ nS rr ~n ,~ ~,C nS h E a) ~ rn ~a rn . r~ r~ O ~) a "~ ~ ~r, ~, o 0 a) o ~J o ~ m nS ~ nS ~ ~ C~ .Q ~ c::
r~ ~ ~I rlS O -~J h ~ rn O r-~
.r~ rn rrS ~ r~ r~S
rs ~ rn rn rn rn ~ v ~S
EO a) r" rS
U ~ O O O C ~ O U o ~ rS C ~ v ~ - U
'-~X ~ O Q X a) Q. rrS U rrS 0-~
~I r-l a) 1I rn E C U
1la) o ,~ ~a ,~ ~3 o ~ nS ~q ~ o IJ rn R rn ~q ~ a) rn nd rn coP:'. U ~:; v ,~
.,~ rn nS ~ ~ O r~ nS~
Qr~IJ r-l rl J-- 5~ C JJ lr~ rn ~ a) O -- . Q
QQ ,~ Q Q ,~ r- l tl) O r~~ Q ,~

5~ Q ~ n~ rn ~ Q n~Q n~ ~ Q rn ~: ~,C,~ o H ,~ rn ~1 a) H ~,q ~.~ 3 E t) ~ Q O nd .~O ~3 ~ ,~ r~ ~ r~ l a) r~l ~~ ~ rn O
,~ ~ ¢ O 11 ~ ,~ nJ ~; ~ O ,¢ Z b~ Q
rn C rn C
~ r~
~n U ~ rn ~a rq ~ Q ~ r rn Lq O ~ 5~ ~ ~
'~` ~ ~ U 0 ~1 0 ! u ~ ~ n ~ rd C) ~
`~~ rC P~ ~ ~ ~ n ~a R., 1 o ~ ~ o ~ c o o ~ ~ ~a .,~ ~ ~ x ~ ~ ~ c ~,: ~ ~ n~ n~ .C ~ C
`I: U C) ~ ~ nd c) H V r~ ~ ~a ~ n~
J Jl C O U r I n~ ~ C U
rn c) ~ ~ ,1 ts U ~ ~ ~ JJ ,~ ~-r~
~, ,~ a~ ~ ~ ~ '1 ~1 ~ Ql rn rn~a . rn C~ ~ Q E O ~ O C
* O C C E--~ O E~
mm cn cn ~ # 1~ H H V # #
, #
!~

. 1 .

i l923 1 A ~ump instruction does not modify the accumulator 183, 185 or indicator bits whether the jump is taken or not. The program counter has had one added to it since it addressed the jump instruction. The program counter 192 includes PCL register 192A and PCH register 192B. If the jump is taken, the low four bits of the instruction first byte replace the low four bits of the program counter 192 and the high eleven bits are modified if necessary. The range of the instruction address change is -15 to +17 bytes measured from the jump instruction address. If the destina-tion is within this range, it is only necessary to specify the low four bits absolutely of the destination address and a bit ~o describe which direction (0 for ~2 to +17 or 1 for -15 to +0; the +1 condition is not realizable). The +1 condition is not useful because the processor goes to +l if the jump is not taken. That is, if it was valid the processor would go to +l if the jump was taken or not).
In a branch instruction, the program counter 192 is incremented to point to the second byte of the branch in-struction word. The low eight bits absolute of the des-tination program address are coded in the data byte ~second byte). A code which describes how to modify the high eight bits is coded into the instruction byte to leave the high eight bits the same, to add one to the high eight bits, or to subtract one from the high eight bits.

Branch on Equal and Branch on Not Equàl test only ,~ the condition of the ALU 181 EQ indicator. Branch on Not Low tests only the condition of the Low indicator. Branch ,' 30 on High requires that both the EQ and Low indicators be ~, off.

'~
.

11~19;~3 1 The ~RANCH AND LINK (BAL) instruction is an uncondi-tional branch that specifies the sixteen bit absolute branch address of the program destination and a two bit number indicating a register to be used. The address of the next executable instruction (following the BAL) is stored in the register specified by the two bit number.
Interrupt is not a programmable instruction but is executed whenever the Interrupt Request line INT is acti-vated by an external device and an Interrupt mask in STAT
register 195 is equal to zero. Interrupt stops the execu-tion of the program between instructions, reads the new status (register group, interrupt mask, EQ, LOW, CARRY) from the high byte of the eighth register, stores the old status in the low byte of the eighth register, stores the address of the next instruction to be performed in the zero register, stores the accumulator in the fourth regis-ter (without altering the accumulator), and branches to the address specified by the contents of the twelfth regis-ter. The processor always specifies register group 0 for interrupt. Interrupt requires ten processor cycles to com-plete. Register groups will be later described.

Return is an unconditional branch to a variable ad-':
dress and can be used in conjunction with the BRANCH AND
LINK or to return to the main program after having been interrupted. Two bytes are read from the register speci-fied to define the absolute branch address. A return us-', ing register 0 of register group 0 is defined as a return i~ from interrupt. In this case the new status (EQ, LOW, CARRY, interrupt mask and register group) is read from the ~ 30 low order byte of the eighth register.

.
; BO9-76-053 -33-~119"3 1 Arithmetic Group instructions operate with the sixteen bit accumulator 183, 185 and eight bit arithmetic logic unit ALU 181 that are capable of performing various arithmetic and logical operations. Three condition indi-cators (LOW, EQ, CARRY) are set on the results of some operations. Two's complement sixteen bit arithmetic is performed except for byte operations and some immediate operations which are two's complement eight bit operations.
The high order bit is the sign bit. Negative numbers are indicated by a one in the sign bit position. Subtraction is accomplished by two's complement addition. Any arith-metic operation that results in a CARRY will set the CARRY
latch even though the accumulator may not be changed.
Double Byte Arithmetic is performed with registers 0-15 of the current group for the Add, Subtract, Load and Store instructions. Load Register and Bump (add ~1) uses registers 4-7 and registers 12-15. Load Register and Decre-ment uses registers 0-3 and registers 8-11. In the add register and subtract register instructions, AR and SR, respectively, the sixteen bits of the addressed or specified register are added to or subtracted from the accumulator and the result is placed in the accumulator. E~ is set if the result is all zeroes. Low is set if the high order bit is a one.
Load Register instruction LR loads sixteen bit signal contents of the specified register into the accumulator 183, 185. The contents of the addressed register are un-changed. The ALU 181 indicators are not altered. The Store Register instruction, STR, stores the sixteen bit contents of the accumulator BO~-76-053 -34-1 183, 185 into the specified register. The contents of the accumulator 183, 185 and the ALU 181 indicators are not altered.
In the Load Register and Bump, LRB instruction, and Load Register and Decrement, LRD instruction, an absolute one is added to or subtracted from the contents of the specified register, respectively. The result is placed in the accumulator 183, 185 and the specified register.

The indicators are updated as for an add or subtract, AR or SR.

Bytes 0-511 of memory 64 are addressable by the Byte Arithmetic instructions. The directly addressable memory 172 is divided into sections. Bytes 0-255 are address-able when register groups 0-7 are selected and bytes 256-511 are addressable when register groups 8-15 are selected. Bytes 512 to 767 and 768 to 1023 are two addi-tional groups. This sectioning yields 32 register groups in memory from which the processor operates.

In the instructions AB, SB, CB, LB and STB, the eight bit contents of the specified byte are added to, subtracted from, compared with, loaded into, or stored from the accumulator register ACL 183, respectively. The .:
high order byte of the accumulator in ACH Register 185 ~` is not disturbed. The ALU 181 condition indicators are . ~

set on the result of the single byte arithmetic: add, ` subtract, and compare. The results of all of the byte 1 ~ .
operations except compare CB and store STB are placed in ~ the accumulator register 183. Store alters the specified ; byte in the active byte group. Compare is a subtract i~ ~ 30 operation that does not ', ` Bo9-76-053 ~35~

1 alter the contents of the accumulator 183, 185. syte arithmetic is eight bit signed arithmetic.
In the byte NB, OB and xs instructions, the speci-fied byte is logically ANDed, ORed, or EXCLUSIVEORed with the accumulator register 183 contents, respectively. The result is kept in the accumulator register 183. The EQ
ALU 181 indicator is set:
for the AND operation if the result of the AN~ equals all 0's;
for the OR operation if the bits set by the OR were all 0's;
for the EXCLUSIVEOR operation if there is identity between the byte and accumulator (result = all 0's~. The LOW indicator is set:
for the AND operation if the preserved bits are all l's;
for the EXCLUSIVE-OR operation if the byte and accumu-lator are bit for bit opposites (result = all l's). The logical AND can test the mask selected to be all zeroes, all ones or mixed. The mask selected bits are indicated by ones in the corresponding positions of the byte used as the mask. The logical AND tests the bits that are preserved, and the logical OR tests the bits that are then set to one. If only one bit is selected then the logical OR does a test bit and set.
The Immediate Arithmetic instructions AI, SI, CI, LI, ~ NI, OI and XI are the same as the byte operations except j that eight bits of immediate data are used instead of the :: ' :~ ~'` ' 1 contents of an addressed byte and the Add and Subtract Operations are sixteen bit signed arithmetic rather than eight bit signed.
The Group Immediate instruction GI takes eight bits of immediate data to alter the contents of the status indicator register 195 to select register groups and en-able or inhibit interrupt. LOW, E~, and CARRY condition indicators in ALU 181 are not altered. The immediate data (byte two) is divided into five parts. BITS 0-4 are the new register group bits (new register group is coded in binary). BIT 5 is the command bit to put BITS 0-4 into the internal register group buffer if the command bit is a zero. BIT 7 is the new interrupt mask (a one masks out interrupts). BIT 6 is the command bit to put BIT 7 into the internal interrupt mask if the command bit is a zero.
The accumulator arithmetic instructions, Al and Sl, respectively add or subtract an absolute one to or from the contents of the accumulator 183, 185, and the result i5 left in the accumulator 183, 185. This is sixteen bit signed arithmetic and the ALU 181 condition indicators are set depending on the result.
The accumulator instructions SHL and SHR shift the signal contents of the accumulator 183, 185 left or right one digit position or binary place, respectively. For shift left, the high order bit is shifted into the CARRY
latch tnot shown) in ALU 181 and a zero is shifted into the low order bit except when the previous instruction was an input C~RRY. After an input CARRY, the CARRY latch condition before the shift is shifted into the low order bit. For ~ ? ~ ,,3 1 shift right, the low order bit is shifted into the CARRY
latch, and the state of the high order bit is maintained.
When SHIFT RIGHT is preceded by input CARRY, the state of the CARRY latch before the shift is shifted into accumu-lator 183, 185 Bit 15. EQ condition indicator of ALU 181 is set if a binary zero is shifted to the carry latch.
LOW condition indicator of ALU 181 is set if the result-ing contents of the accumulator 183, 185 is all zeroes.
The accumulator instruction CLA clears the accumulator 183, 185 to all 0's. Transpose TRA exchanges the low order register 183 with the high order byte register 185 signal contents. The ALU 181 indicators are unchanged.
The accumulator instruction IC transfers the signal state of signal contents of the CARRY latch to the low order bit of the arithmetic-logic unit 181 on the next following instruction if the next instruction is an add, subtract, bump, decrement, shift left, or compare opera-tion. CARRY is inputted to Bit 15 on a shift right.
Interrupt is inhibited by this instruction until the ~ next instruction is performed. The ALU 181 indicator Low is reset and EQ is set if the carry latch is a zero.
If the input carry precedes any instruction other than the ones mentioned above, it will have no effect on instruc-tion execution. If the instruction following the input carry changes the ALU 181 condition indicators, then the indicator information from the input carry is destroyed.

., The two Indirect Data Transfer instructions STN
and LN can access registers 8-15. Load Indirectly instruction :

~ : :

~,, . . ~ : :, .: . . :

1 accesses the specified register and uses lts contents as an address to fetch a byte of data ~ndload it into the low eight bits (register 183) of the accumulator without disturbing the high eight bits (register 185). Store Indirectly accesses the specified register and uses its contents as an address to store the low eight bits of the accumulator register 183 into the specified byte. The ALU 181 indicator is not altered.
The Bit Test or control instruction TR and TP take a specified bit of the low order byte of the accumulator register 183 for test. The ALU 181 condition indicator EQ is set if the bit is a 0. Concurrently, the bit is either reset or preserved in the accumulator, respectively.
The Input/Output instructions, IN and OUT, respect-ively transfer data to the accumulator register 183 from an I/O device (CPP 13, for example) and from the accumula-tor to an I/O device (CPP 13, for example). These instruc-tions are two cycle operations. The first cycle puts the modified device code on the data out lines, and the second cycle is the actual data transfer cycle; the low eight bits of the accumulator in register 183 are outputted to data in lines, and the device code is outputted on the address lines ADC. An OUT instruction does not change ~ the ALU 181 indicators. On an IN instruction, EQ is `~ set if the high order bit of the data inputted is a zero.
LOW is always reset. The Input/Output instructions can each specify 256 devices for data transfer. Generally, an I/O device will require more than one device address to specify different types of operations such as READ and TEST STATUS, etc.

~:

. ~

lJ 1~23 1 A power On Reset (POR) initialization places the processor in the following state:
Accumulator = 0 Register Group = 0 Interrupt Mask = 1 LOW, EQ, CARRY = X (unknown) The microprocessor 170 will begin operation by reading memory location 65,533.
Microprocessor Instruction Execution The processor 170 is pipelined to allow the memory 172 a full processor cycle for access time. To do this, the microprocessor 170 requests a read from memory several cycles ahead of when it needs a data byte. Several restric-tions are maintained throughout the instruction set.
1. Each instruction must fetch the same number of bytes as its uses.
2. Each instruction must leave the microprocessor with the next instruction in the INSTRUCTION BUFFER, IB register 196.
3. At "Phase Two Time" at the beginning of Sequence Two, as later described, the TEMPORARY BUFFER (TB) 197 must contain the byte following the current in-struction. (Note that this byte was fetched by the previous instruction.) 4. Each instruction decodes "TERM" (Terminate) as later described, which resets the instruction se-quence counter (not shown) in the clock for CMP 170 and a separate sequence clock (not : j : ' , - :. . - . :

1 shown) for crlP 170 to Sequence one, allows the next fetch to be done from the Is 196 and loads the next instruction into IR 198.
5. At "Phase Two Time" at the beginning of instruc-tion Sequence Two the low accumulator register 183 and the high accumulator register 185 must contain the appropriate signals.
- (Note that the previous instruction may have had other data in these registers during its execution.) Microprocessor 170 is built exclusively of latch logic. 02 signals are the output of latches (or static decodes using the output of latches) that are strobed (sampled or transferred by a clock signal called a strobe) at 02 time. 01 signals are the outputs of latches (or static decodes using the outputs of latches) that are strobed at 01 time. 01 signals are used as the inputs to 02 latches and 02 signals are used as the inputs to 01 latches.
The fetch decodes (memory references) are done from the IB register 196 to SEQUENCE 1 (SEQ 1) because the IR
register 198 is loaded at 01, SEQ 1 (FIGURES 7 & 8). At sequences other than SEQ 1, the fetch decode is done from IR register 198. The fetch decodes are 02 signals, and therefore, are strobed at 01. The output of the fetch decodes are strobed into registers ALL 191, ALH l9O, OL
2~00, and SCC 180. The program counter 192 is updated from registers AOL 201 and AOH 202 at a 02 time. The e~ecution , , !
, ~ ~ 30 ', Bo9-76-053 -41-:
.

, 1 and designation decodes are 01 decodes from the IR 198.
These decodes are strobed at 02 time into SCC 180 to set up the ALU 181 and DESTINATION strobes which occur at 01 time. The output signals of ALU 181 are strobed into DB 186, DO 187, or AOH 202 in accordance with the instruc-tion being executed. Then ACL 183 and ACH 185 are updated at 02 so another ALU 181 cycle can begin. It takes three processor cycles from the start of a fetch decode to the time that the accumulator 183, 185 is updated. A pipe-lined configuration means that in some cases a processor can be executing three separate instructions at the same time, as is known in the computer arts.
Instruction Sequences An instruction sequence chart in FIGURES 5 and 6 is a convenient shorthand catalog of the internal operation of the processor 170 (as well as SMP 62) during each se-~uence of each instruction. It can be a very useful tool in understanding the processor's operation. This glossary of terms provides the information necessary for proper interpretation of these charts.
General Information `: :
; The processor 170 is pipelined. While it is execut-ing one instruction, it reads the next two bytes from memory 172. The first byte is valid in IB 196 at the be-ginning of SEQ 1 and is used during SEQ 1 to provide three SEQ 1 decodes in SCC 180. At 01, SEQ 1, IB~IR where it remains until the next 01, SEQ 1. All remaining in-struction decodes are done from IR 198.
`~ .
, 30 ~' .~

, .

1 The second byte is in Ts 197 at the beginning of SEQ 2. This byte may contain immediate data for the cur-rent instruction or it may be a next instruction byte.
If it is a next instruction byte, then the current instruc-tion needs to read only one byte from memory to provide the required two bytes. This two byte read occurs for all one byte instructions.
All memory 172 accesses begin at 01. The memory data is valid in the data latch register DL 205 via bus IO for CMP 170 by ~2, i.e., one and a half instruction execution sequences later. In the table below, the memory timings for all instructions are set out with the register destina-tion (DEST) from data latch register 205.
MEMORY REFERENCE TIMING TABLE

INSTRUCTION START DEST START DEST START DEST

CI GPI LI

CB AB SB
LB XB OB

~; Al Sl SHL

~:

..~A ' 1 TRA CI,A
2 IC TBP TBR l TB
~ BAL 1 ACL 2 X 5 TB
4 RTN 1. TB 2 ACL 3 TB
j 4 TB
fi. B0~ IJO ] TB 2 TB- 3 TB
j ~ ~ IJO 1 TB 2 TB
1 INTERRUPT ]. TB 5 ACL 8 TB
'! 9 TB 10 TB
") BLI 1 TB 2 ACL 3 TB

l? BSI 1 TB 2 ACL 3 TB
l~ IN O~T 1 TB 3 ACL 4 TB
l~l *A bar over a jump or branch instruction indicates jump or 1~ branch was not taken.
lh Code Operation (Phase 2~ Decode 11 TB DL-~TB, ACL unchanged None 18 ACL DL-~ACL, TB unchanged TACL* or ITAL --.
l9 X None. ACL and TB are unchanged. NOTB* or TBNS
Data will be lost unless SDL on 21 ~ ].ine 206 is inhibited by DMA active 22 on line 207. AND circuit 208 blocks 2~ 02 from generating SDL signals on 24 line 206. DMA means direct memory ) 2S access as by registers 173, 174.
i~ ~.'6 If IR 198 still contains the current instruction ~7 byte, the decodes are static. If the.decode is for the .8 overlap cycle of SEQ 1 ~with the next instructicn byte in BO9?6.0$3 - 44 -i : ".~, . .;: ' . ' ~. . . - : . . . : , 1 IR 198), the ALU 181 condition latches are set during the last sequences(3-5) of the current instruction execution.
l`he designated register is decoded by SCC 180. This special case is shown on the instruction sequence charts, FIGURES
5 and 6 by the terms TBNS or ITAL in the ALU columns.
The operation of the processor 170 in each sequence is divided into two categories: Control Logic (CL) of SCC 180 and ALU and Destination (ALU). The position of these two blocks within the sequence, (i.e., left half or right half) has no meaning. Operations can occur at 01 or 02 in either category. 01 occurs in the middle of a se-quence. The 02 is always a sequence boundary.
Control Logic Glossary This is a list of terms which appear in the control logic CL columns.
WRITE - WRT
Indicates that a write into memory is initiated at Phase 1 rather than a read. A read is the default condition and requires no decodes. The WRT output line (FIGURE 5) is ac-tive when WRT appears in the chart.
OUTPUT lST I/O - OUT lIO
Indicates that the first cycle I/O code is placed on the output lines IO at 01. Address lines AL9 and ALll of ADC
are driven by the decode IOCl. I/O line is active (FIGURE 5).

-Indicates that the second cycle I/O code is placed on the output lines IO to 01. Address lines ALlO and ALll of ADS
are driven by IOC2. I/O line is active (FXGURE 5).

.

., `~J

, .
' ~ .

1 TB~IB
2 At each ~2, SEQ 1 of every instruction, the signal contents of Ts register 197 are transferrc~ to Is regis~cr ~ 196. The signal contents represent thc ne~t succcssi~e 'j instruction following the current instruction.
~- IB SET
i Same operation as TB~IB ~ut the intent is to sto~ IB l9fi ~! from following TB 197 rathcr than sa~e th~ COntentS o~ thc '` TB 197. It is followed at the next ~1 b~ IB SET lO "~R.~".
1(~ IB SET TO "TRA"
11 Indicates that the reset in~uts (not sho~n) on the I~
l,' 196 latches (not shown) are driven at ~1. CL.T OP~ PO~_~
l~ drives an overlapping set on bits 0, 3 and 5 E~rodu~ .3 a ~-1 "TRA" instruction code BAL, POR then e~ecute a ~RA to IrJ complete their respective operations.
fi (TE~I) ~i Indicates the end of the instruction. SEQ 1 begins 1~ at the line 220 on the chart. The sequence counter 1~ (not shown 51-S6) in clock 75 is reset by the decode TER~*.
2() PCI
21 Indicates a read from memory and a Program Counter Increment.
2.' This action is a default condition and no decodes arc nccded.
2~ 01: PC+l~AO
24 02: AO~PC
2~ PCNI
~fi A "NO OP". Same as PCI except the PC 192 is not updatcd at ,7 02. The next PCI reads the same location again as though 2~ the first read did not occur. It is used because the .;

. ` ' Bo976053 - 46 -'~.
, `
~,~
- ~
~. -l9Z3 1 processor lines signify something every ~1 and some instructions have no Read/Write or I/O requirements during ~ sequence 1. SPC (Set PC) is inhibited for the jumps and ,~ branc}lcs, for the shift instructions, and ~or ~1 and Sl ~j instructions.

r IBI., IRL, IRH
7 Indicates a memory access (read or write) to a register.

R IR (IB) means the register is specified by the low four q bits of IR ~IB). IB must be used during SEQ 1. IR 198 ~ is used during all other sequences. L means the access lL is to the low byte of the register, H ~specifies the high 1~ byte. The decode IRS~* (IR selected) controls the forma-,~ tion of the address at 01.

peration Control IB(0-3)-~0(0-3) IBX (SEQ 1 only) I r, IR~0-3)-~AO~0-3) IRX (all other sequences) l 7 L=O, H=l-~AO(4) ILH

18 GP(0-2)-~AO(5-7) RGX
19 GP(3)~AO(8) R3 ~o 0~AO~9-14) ~BIR

~ Indlcates a memory access using the contents of TB 197 as ,~ 73 the,address. The decode TBSL* (TB selected) controls the , i .
4 formation of the memory address at 01.

' ~ ~S~ Operation Control ,~, TB~0-7)-'Ao(0-7) TBX

GP(3)-~AO(8) R3 0-~AO(9-14) TBIR
.

:
~097605~ , : ~ .
:, l IRL_ > Same as IRL except l-~AOt3). It is used only in the RTN
~ instruction to read the new status from memory. A one is ,l plac~d on AL(3) '; CAL ~IGH BITS, TB-~AOL
___ _ ~i Indicates a memory access to a location being branched to.
The decodes TBSL* and AOSL* control address formation at Phase l. Thc high bits are calculated by the counter logic CL for PCH+l and PCH and by the ALU for PCH-l.
lj1 Phase l:
ll Operation Control TB ( O- 7) -~AO ( 0-7 ) TBX
ll PCH+l-~AO(8-14~AOSL*=l, sNF=l 1~ PCH~AO(8-14)AOSL*=l, BNF=0 I r, PC~ AO(8-14) AOSL*=0 i Phase 2: AO-~PC
I7 CAL HIGH BITS, IR~AOL
1 n Similar to TB~AOL above except only the low four bits of l~ the IR are used, and bits 4 through 7 are calculated by ,~
~0 the counter logic. The decodes IRSL* and AOSL* control 2l address formation by driving other control lines.
~% Phase 1:
; ~`2~ Operation Control ~ ?4 IR(0-3)-~AO(0-3) IRX
Z ~ CL(4-7)-~AO(4-7)None (default) 26 PCH+l-~AO(8-L4)AOSL*=l, JF8=l 7-~ PCH~AO(8-14)AOSL*=l, JF8=0 ~8 PCH~l~AO(8-14) AOSL*=0 29 Phase 2: AO~PC
. .

~ ~.

-, ~ , ~ -l9Z3 l OL, OH, ~L, 4~, 8L, 811, 12L, 1211 2 Indicates a memory access to a register direct1y specified .~ by the control SCC 180. Occurs only durin~ intcrrupt. L
4 indicates the low byte; H indicates the ~igh b;~te.
S ~hase l:
fi Operation Control Register~0~0-3) crl2~ C~13 L=O, H=l~0(4) ILH
" 0~0(5-13) TBIR
1~ l~AO(l4) R9 ll Update PC, ACL~A0~1, TB~AOL
J2 Indicates a memor~ 172 access to an address ~s~ecified b~
,; the contents of Ts and ACL. The address is also placed in L~ PC 192 at ~2. The address formation is control1ec1 ~y AOTB*
1'j which drives other control lines. ACL 183 go through ALU 181.
1~ Phase l:
17 Operation Control 1~ TB(0-7)~AO(0-7) T~X
19 ACL(0-6)~AO(8-14) SAO
2n Phase 2: AO-~PC
~l AC~AOH, T~AOL
2~ Same as above except PC 192 is not updated at Phase 2 ~ ~ Destination (Dest) Glossary :: ' Items with boxes around them (e.g., ACL to DO~ACL) 2~ do not always occur. On Branch or Jump taken7the boxed 2~ destination occurs only when PCH 192B must be decremented ~7 to produce the proper address. The decrement always occurs, an~

2~ is not loaded when not needed. On all other :' . '' .
' .
"
1~ -, --1 instructions the boxed destin~tion occurs if th~ instructio.
2 is also boxed.
.1 Items in parentheses are "don't care" conditions which .1 occur but are not part of the desired c~eration.
There are seven standard data transfers:
6Phase 1 Phase 2 D codes j1. ALU-~DO - rlo"e (default) ~2. ALU-~DO DO~ACL ~F3 n3. ALU~DB - DaDS*
I(!ACH~DO
114. ALU-~DB DB-~ACH BF2 1~5. ALU~AOH - AOT~*
llTB-~AOL DB~ACH
l~ACH-~DO DO~ACL
J56. PCL~DO - PCSL PSX
1 fi7 . STATUS~DO - STSL-PSX
l~ Any variations of these are decoded separately as exceytions.
It' MISCELLANEOUS OPERATIONS
n Update Status The new status (REG GROUP, ~Q, C~RR~', LO~ T ~SK) 21 which has been read from memory replaces the old status.
? ~peration Decode 23 (Phase 1) TB-~5TATUS UPST*, Cl~ST, C~ST*
(Phase 2) Clear ACL ~ ACH
~G ACL 182 ~ ACH lB5 are reset to zero by driving the reset ?7 inputs of the register latches (not shown).
~ (Phase 1) ~ .
29 (Phase 2) 0~ACL, 0'ACH CLAC

. ~ BO976053 - S0 -~ T ~

1111~23 .

1 Processor Forced to Execute T~
2 The IB 196 has been reset to a TP~ instru~tion.
1 The sequence counter (not shown) in the clock is reset to ~ SEQ 1 and the processor executes the TR~ ~for~ th~ ne~t r~ instruction from memory.
~; Interrupt is pre~ented from occurrin~ unti1 after ~he 7 TRA is completed.
~ AC7*--~Q
n The EQ indicator is set ~y AC7* (u~ed bv I,~o instructiotl), 1(: the bit 7 of ACL 183.
ll IC SETS IC
l2 The Input Carry instruction sets the IC l-~tch (not s~aown) I 1 .
!~1 "32"-tDo ~ DO(5). Part of POR code.

1~, ALU GLOSSARY
Ij This is a list of terms which appear in the ALU category.

X
ALU NO-OP. No ALU decodes are provided. ALU 181 output at 182 defaults to all l's.

~l ACL-TB
ALU 181 outpùt is either ACL 183 ~lus TB 197 or ACL 183 minus ~3 TB 197 depending on whether instruction was an ADD or a ,~ SU~TRACT.

~5 ACLxTB

2~ ALU output is some logical combination of ACL and T~

,7 which is dependent on the actual instruction.

; 29 ALU output is ACL.
' " . ' ' :~ i ~!

.923 ~. _ ALU output is TB.
~ ODIF) ,1 ALU output is modified in some manner depending on ~he ' instruction. Example: On an IN or OUT instruction, TB-~DO except for bits 5 and 6 which are modified to i reflect 0 and OUT respectively. ALU output is shown as ~ TB (MODIF).

ALU output is ACL plus 1 or ACL minus 1 depending on the 11 instruction.
I? PCH-l l~ ALU output is PCII minus 1.
l~ PCH-l+CR
___ I r` Same as PCH-l except carry is added.

16 TBNS, ITAL

l7 ALU WO-OP. The destination of data signals entering 1~ the processor at the end of Sequence 1 via register 105 l~ must be specified by the previous instruction (although ,'~ that instruction is no longer in the machine). To .'l accomplish this action, two sets of latches are necessary.

~2 The ALU latches are used as the first set. The ALU latches 2~ drive the second set, TBNS and ITAL.

~1 ITAL speci~ies the ACL as the destination. TBNS

,~'i specifies no destination. The default condition (no , 2fi decodes) specifies the TB as the destination.
,, ~ ~.7 CMP Working Store 172 ~ddressing , 28 Either SMP 62 or CMP 170 can access working store ~ .

1 172 as well as input and output registers 173, 174. SMP
62 accesses the working store 172, and registers 173, 174 via MPC 65 as will be later described. As shown in the FIGURE 7, the sixteen bit address for bus ADC, is not completely used for accessing the registers in store 172 or the input/output registers 173, 174. sit 12 of the CMP
address space selects whether working store 172 or regis-ters 173, 174 are accessed. When bit 12 is a binary 1 then registers 173, 174 are selected as represented by the I/O address space from addresses 4K to 8K. When bit 12 is a zero, the working store 172 address space from zero to 4K is selected. The lesser significant twelve bits select the address space within the two sections, using known address decoding techniques. For the I/O address ; space, bits 3 through 11 select which I/O semiconductive chips constituting the input and output registers 173, 174 are selected, while bits 0 through 2 select bit posi-tions within the chips forming the registers 173, 174 as will be later described. For working store 172, bit 0 through 11 represent a continuous address space.
SMP 62 addressing accesses working store 172 and registers 173, 174 in two segments. With eight byte group fetching for each access, i.e., the SMP 62 command '~ to MPC 65, minimum access is for eight bytes of signals `~ :
~ in CMC 61. The first segment corresponds to address space j~ of working store 172 and the second segment corresponds `~ ~ to the address space for registers 173, 174. In the :~

`:
:
:

, ~
~ ' . . :. .. .. .

1 address space, bits 0 to 7 of the ADS address bus from SMP 62 are used for controlling MPC 65. The upper four bits perform a device select and the lower four bits per-form a command select which selects the segment and groups for initializing MPC 65 for data transfer. The address space shown in FIGURE 7 for srqP 62 is for the first byte of a two-byte command, as will become apparent.
Bus Controls MPC 65 and bus select circuit 76 are both shown in FIGURE 8. Bus select circuit 76 includes decoder 104 responding to signals from SMP 62 via control lines 103.
Decoder 104 output signals in turn control a pair of AO
(AND-OR) circuits 105, 106 for selectively interconnect-ing the byte busses MI and DI as well as connecting page memory 64 to DI via AO 106. With these connections, SMP
62 completely controls the bus interconnections and hence the data flow in MPMC 15 under microcode or software con-trol. The lines 1~3 include CWRT which, when active, in-dicates that SMP 62 is supplying signals to be written either in page memory 64 or to input/output. Line POR sig-nifies that hardware circuits (not shown) are initiating a power on reset and that the bus connections are to be set up for initializing MPMC for operation. In general, POR control causes a write into page memory 64 from MI
A' as received from NVS 19. ADS 12 signal line signifies ~ ~ that the cycle of SMP 62 is in the address cycle; i.e., ; a memory address is being sent to page memory 64. DMACY
indicates that DMA 64A has access to page memory 64.
; 01XCC and 02DMAM are timing cycles .'' ' ` BO9-76-053 -54-lli~23 corresponding respectively to 01 and ,02 phases of the system clock. Additional gating for generating these signals are not shown for brevity. CHNSW carries a sig-nal defining the time that data on DI is valid during system clock 02. Lines INHDI and IN~IO are special test control signals for testing the circuits and, hence, are beyond the scope of the present description.
Decoder 104 responds to the various lines 103 signals to actuate the AOs 105, 106 as described. The Al input portion of AO 105 connects DI to MI because the other in-puts to the Al input terminals are DI and the output terminal is directly connected to MI. Similarly, A2 input portion of AO 105 interconnects DI to MI under DMA memory access control. Additionally, decoder 104 ascertains from SMP 62 control signals that it is all right to con-nect to DI.
AO 106 selectively connects IOX from MPC 65 to MI
or the output of page memory 64 to MI. The Al input por-tion passes the IOX receive signal whenever the IO in line from decoder 104 is active and that DI is in proper condition. Further, the A2 input portion is activated when decoder 104 signifies it is not IO, i.e., it is a memory reference.
With regard to the above statements, page memory 64 ; is continuously cycled and AO 106 selectively decouples its output signals from bus DI during input operations, i.e., when signals from IOX are to be transferred to MI.

MPC 65 is constructed using a similar design philo-sophy. Decode 110 responds to SMP 62 lines 103 signals BOg-76-053 -55-~` ~

. lil~3 1 as indicated in the drawing and to the ADS address sig-nals to activate AIID circuits 111 to pass signals from bus IO of CMC 61 to cable IOX for gating by AO 106 or AO
105. Similarly, decode 112 responds to the SMP 62 control lines 103 signals and to the ADS signals to activate AND
circuits 113 to pass the signals of bus DI to IO bus from CMC 61. In general, MPC 65 operates in two phases. The first phase is the addressing phase; the second phase is the data transfer phase. The address of the memory in CMC 61 which includes ROS control store 171, working store 172, plus registers 173, 174 is set in MPC register 114 at ADS 12 time from bus ADS. Additional control signals are supplied over DI. MPC register 114 supplies its out-put signals to bus ADC for addressing the above-mentioned modules in CMC 61. On the next and successive cycles, data is transferred through AND circuits 113 from DI to IO bus as indicated by the addresses supplied to ADC from MPC register 114.
MPC register 114 includes a control bit (not shown) that inhibits CMP 170 by supplying an inhibit signal over line 114A. This inhibit signal makes memory space of ` CMC 61 available to SMP 62 for exercising complete control, obtaining information, performing diagnostics, and load-ing programs.
A description of the MPMC 15 and a microprocessor suitable for executing the program according to the pre-sent invention is described in ~nited States Patent . ~
4,086,658 referred to hereinbefore.

A Microcode Implementation of the Invention i It is preferred that the above-described computer be microprogrammed to implement the present invention.
The source code instructions related to the above-des-cribed computer are set forth below for implementing major portions .

1 of the Table I examples. of course, in a practical machine, code would be included for a greater number of control characters which follow the teachings set forth below.
The code is arranged based on the universal text column.
The computer microcode is not organized such that each example is contained in but a single microcode sub-routine. Decoding the control character in the input text column results in calling microcode routines having em-bedded universal text control characters or symbols, i.e., such universal characters are embedded as constants within the called microcode routine.
The ''HTI' or "RHT" control characters of UniversalText are handled by the microcode set forth in Table II
and called by input text character decoding RHT or HT.
In all the tables LOC means memory location, OBJ means instruction operation definition, OPl and OP2 are operands and SOURCE STATEMENT is comment on the coding.

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1 In Table II above, the sranch and Link instruction, BAL, at 6354 and object coded 33E547 calls a microcode sub-routine not detailed herein by source code. The Table II source code for a tabulate function puts the first and last space in the tabulate movement. The called microcode subroutine "SPINS" is an interactive loop which adds the intermediate space symbols. For ex-ample, if a tabulate is for eight spaces, then the SPIN
subroutine has six iterations to add six space symbols to the first and last space symbol added by the Table II
illustrated source code. Since interactive loops are well known, that code listing is dispensed with.
LI, 12B, as constructed, has no tabulate function.
Accordingly, to achieve a tabulate function, space sym-bols equalling the tabulate distance are added to the ; text. In supplying such text to LT 16, the space symbols are deleted.
The Universal Symbol PDLM has a similar symbol RDLM.
PDLM pertains to LI 12B while RDLM pertains to LT 16.
Both actuate the respective units to effect similar re-sults. In Table III below the RDLM source code is shown, it being understood the complementary source code is ~ used for PDLM, Table III also includes the SOF microcode.

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`', 3 m z; ~ m :
i O ~ H
d ;j m Z, ~
j~ O
. ~ a ~ -. ~ ~4 ~ o a~ , :: p, ~ o o ~
o o o o o m r '`~ U
Z:' : : : o ,~ Lr In In In . ~ Z~
!~ :
:' I' ::: , :
1 ~ :
.
' ~Z
Z

Z ~ , .
BO9~76053 ~ - Zo8 -` Z
:~
:
, `. :

( : , ,~ .
':' ` :' ~ . : ' - ' g~

1 Table IV above shows LF code, Table V shows the EMF
code, Table VI, the VT code, and Table VII, the RFF source code. The code for deleting universal text is omitted as being straight forward.
ROM Type Text Processing A ROM type of encode-decode usable with the FIGURE lB
illustrated store and forwar~ unit in the form of a copy production machine is shown. The input text is received from either LT 16 or RTC 17 via a buffer (not shown). A
control 60D, which may be a computer program in SMP 62, selects a set of AND gates to receive text signals from either LT 16 or RTC 17 (FIG. 1), respectively, via AND
circuits 300, 302. The received text signals are trans-mitted a character at a time to a pair of ROMs 303 and 304. ROM 304 takes the text signals and supplies adjusted encoded text or data signals to universal text or page mem-ory 64. The control characters from RTC 17 are decoded in ROM 303. ROM decode 303 may contain one or more char-acters corresponding to each received RTC 17 control character. In the event additional control characters are to be added for the universal text, ROM decode 303 has a "hold-text" line 305 which supplies signals through OR
circuit 306 to a buffer (not shown) for delaying text un-;~ til the additional control characters can be suitably inserted in universal text memory 64. The line 305 sig-nal also actuates cycler 307 for providing additional ROM
cycles for reading out the additional control characters.
~OM decode 303 also has a memo~y field supplying signals over cable 308 to BO9-76-053 -~9-. :

~1~119;~3 1 cycler 307 indicatin~ the number of additional char-acters to be cycled from ROM 303 to universal text memory 64. Cycler 307 supplies timed readout signal pulses over line 309 along with address information over cable 310 for reading out such additional charac-ter signals. That is, the field supplied over cable 308 not only includes the number of characters to be read out but also includes the beginning memory address of the first additional control character to be read out.
Additionally, cycler 307 supplies a hold signal over line 311 until all additional characters had been read out of ROM 303. Upon removal of the hold signal from line 311, the buffer (not shown) continues to supply input text as aforedescribed. In this regard, it should be noted that universal text memory 64 also includes addressing cir-cuitry which includes an addressing incrementer (not shown) so that the received text as modified by ROMs 303, 304 is in a continguous portion of universal text memory 64. The transfer of the universal text process signals to NVS 19 is omitted for the purpose of brevity.
Text analyzer-modifier 60 CA for LT 16 operates identically to that just described for 60CB. The con-struction of ROMs 303, 304 are in accordance with nor-mal and known ROM construction techniques wherein the signal contents of the ROMs are made in accordance with that indicated for Table I, supra.
From the above, it is seen that the text process-ing for the control character control requires an addi-tional number of cycles than those required for pure transmission.

1 In this regard, all text processing requires such addi-tional cycles, thereby reducing throughput of a store and forward unit or a copy production machine.
The output portion of the ROM version of the inven-tion for supplying adapted text is shown as unit 56A
which includes a single ROM 315. The universal text mem-ory 64 under control of SMP 62 supplies the universal text to ROM decode 315 one character at a time. ROM de-code 315 is adapted for transmitting adapted text to one of the plurality of destinations, it being understood an additional ROM is provided for each destination. Each time a control character from the universal text is to be deleted, ROM decode 315 supplies a field of signals indicating the number of control characters to be deleted.
For example, if one control character is to be deleted, ROM decode 315 supplies a jump next signal to universal ; text memory for eliminating the readout of the next con-trol character. If five characters are to be deleted, the next five characters are not transmitted from memory 64, and so forth. Accordingly, the transmission of text from universal text memory 64 to the destination device will include a minimum number of cycles thereby maximiz-ing throughput of the store and forward unit in the trans-mission mode. This elimination of text processing cycles -.
~ is an important factor in providing maximum performance .~:
at minimum cost.

Examination of Table I will show that in some in-,:
stances the first received control character from the universal text is to be deleted. In such an instance, ROM decode 315 is programmed to substitute the second ~ ~ character : ' ~ BO9-76-053 -71-.
.

llli9;~3 I for the first control character and jump the second character even though that character is acceptable for the adapted text. For example, in the first line of Table I in going from the universal text control characters FHI C~I to pr:inter text, tlle control character CHI is to be used.
However, only one transmission character cycle is desired.
; Therefore, when ROM decode 315 is adapted for printer text .: transmission, the decode of FHI in ROM decode 315 causes , output of CHI during that first cycle, plus jumping one L) character position for deleting the transmission of the CHI

Il character from the universal text. The same procedure is 1 used in connection with deletions of other control characters.
In some instances the universal text may have a-variable ~l number of control characters for a given input character.
I~ In such ~ situation, the uni~rersal text includes a length ; field indicating the number of control characters. This 1, length field is decoded by ROM decode 315 for determining the actual number of characters to be jumped in the universal la text memory 64 output or transmitting mode.
.~() While the invention has been particularly shown ~1 and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that 2~ various changes in form and details may be made therein without departing from the spirit and scope of the invention.

, ~ I -s s , .

Claims (4)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A method for operating a message store-and-forward unit, coupled to a plurality of connected units, at least some of said connected units using some control signals which are different from control signals of other units but perform substantially the same function in each unit, comprising the steps of:
receiving a message from one of said connected units;
processing said received message by the steps of comparing each control signal received to control signals performing the same function in all other connected units, and inserting into said message those control signals which perform the same function in all other connected units and which are not the same as the control signals received; and transmitting the processed message to at least one of said connected units.

2. The invention as claimed in claim 1 wherein said transmitting step includes the step of:
deleting from said message those control signals which differ from those performing the same function in the one of said connected units to which said message is being transmitted.

3. A method for operating a message store-and-forward unit, coupled to a plurality of connected units, at least some of said connected units using differing control sig-nals, comprising the steps of:
receiving a message from one of said connected units in said store-and-forward unit, analyzing the control signals received from said one of said connected units, in said store-and-forward unit;
generating a new set of control signals which in-cludes control signals compatible with each of said connected units, selecting a destination connected unit for said received message; and transmitting said message and said control signals compatible with said selected unit to said selected unit.

4. The invention as claimed in claim 3 wherein after said destination connected unit is selected, the further step of deleting all control signals incompatible with said selected unit from said generated set of control signals to thereby provide said destination connected unit only with control signals recognizable by said destination connected unit.