CA1114494A - Video special effect generator - Google Patents
Video special effect generatorInfo
- Publication number
- CA1114494A CA1114494A CA303,651A CA303651A CA1114494A CA 1114494 A CA1114494 A CA 1114494A CA 303651 A CA303651 A CA 303651A CA 1114494 A CA1114494 A CA 1114494A
- Authority
- CA
- Canada
- Prior art keywords
- counter
- signal
- video
- output
- period
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/2622—Signal amplitude transition in the zone between image portions, e.g. soft edges
Abstract
A B S T R A C T
A video special effect generator for producing a wiped effect between two video signals uses presettable counters to define the boundary between the wiped and the wiping picture portions. The counter is clocked with pulses synchronised with the horizontal or vertical synchronising signal, depending on whether the picture is being wiped horizontally or vertically, is loaded with a preset count during each horizontal or vertical period as appropriate and produces a signal defining the boundary of the wipe when it overflows. Arrangements for both horizontal and vertical wiping are disclosed; the vertical presettable counter may be used to load the horizontal presettable counter to achieve diagonal wiping of the picture.
A video special effect generator for producing a wiped effect between two video signals uses presettable counters to define the boundary between the wiped and the wiping picture portions. The counter is clocked with pulses synchronised with the horizontal or vertical synchronising signal, depending on whether the picture is being wiped horizontally or vertically, is loaded with a preset count during each horizontal or vertical period as appropriate and produces a signal defining the boundary of the wipe when it overflows. Arrangements for both horizontal and vertical wiping are disclosed; the vertical presettable counter may be used to load the horizontal presettable counter to achieve diagonal wiping of the picture.
Description
r~4 THIS I~VENTlON relates to a video specia~ effect generatorO
There are already known various types of special effect generators, in which a composite video si.gnal is produced consisting of selected parts of two input video signals from two cameras by selectively switching the video signals. The conventional generator is provided with an analogue signal processing circuit including horizontal and vertical sawtooth or parabolic generators which generate analogue potentials proportional to the horizontal and vertical positioning of a scanning spotO Analogue comparators are thenarranged to compare various combinationq of these analogue signals, and the switching signals generated by the analogue comparators operate electronic switches which switch portions of t'he input video signals into a single output video signal under the control of the relative magnitudes of the combination signals which are being comparedO The horizuntal and vertical sawtooth or parabolic generators are usually constituted by integrating circuits comprising c,apacitance and resistance. As a result, the generatorg are prone to drift with temperature changes and : with the aging of componentsO
In order.to overcome the above-described defects, a digital special effect generator has been propose~ such as ~ shown ln UOSO Patent ~oO 3,821,468 and UO~O Patent NoO 3,941,925, ;~ 25 in which the genérator includes at l~ast a lever ~ounter, a ~ ~ horizontal (or vertical) counter and a digital co~parator.
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The lever co~lnter prod~ces a di~ital signal corresponding to the position of a manually operated potentiometer, while the horiæontal counter counts the predeterrnined number of pulses, for example, 512 pulses per horizontal line to provide the di~ital indication of the horizontal pGsition of the scanning lineO The contents of the lever counter and the horizontal counter are compared in the comparator which provides a transition signal when the count of the hori~ontal counter exceeds the value stored in the lever counterO This causes the output video signal to be switched in accordance with the position of the lever counter.
The above-mentioned construction of the generator requires the horizontal and vertical digital comparators to produce the switching signals for the horizontal and vertical wipe operation, respectively. It is apparent that the construction of the generator becomes more complex because of the addition of the comparators and it will be extremely difficult to exactly control the size and speed of the switching signal from the generatorO
According to the present invention, there is provided a .ideo special effect generator having a switching means :. ~ ' ' . .: :
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- 3a -to which a plurality of video signal~ are supplied for simllltaneously combining portions of said video signals into a single picture by controlling said switching means, said generator including at leaRt one circuit arrangement comprising, a counter, mean~ for ~upplying N clock pulses to said counter within a period of predetermined duxation, mean~3 for loading a preset count to said counter at each repeat of qaid period, and a flip-flop arrangement set by the output of said counter and reset at the end of each repeat of ~aid period of generating a control signal to be ~upplied to qai~ ~witching mean~
More p~rticul~rl~t there is provide~:
... : :~:_=,' ~ ~ideo special effects generator ha~ing switcher means to which a plural~ty of video signals are supplied and generator means for generating control signals, said control signals com~ining portions of said video signals into a singIe pictur~ ~y controllin~ said switcher means, said generator means compris~ng: a counter~ loading means for loading a variable preset count ~nto said counter, means for supplying N clock pulses to said counter within a period of predetermined durat~on, and latch means set at a time determined by when an output of said counter lndicates that . . .
said counter has attained a predetermined count va~.ue and re~et at the end of sa~d period for generating ~aid control . _ . . . _ _ slgnals .
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- 3b There is also pravided;
A video special effects generator having switcher means to which a plurality of video signals are supplied .
for comblning portions of said video signals into a single picture, and control signal genexating means for generating control signals which control said switcher means, said control signal generating means compirslng: first counter means for counting a first clock pulse train having a fre~uency such that at least N first clock pulse occur ~ithin one vertical period of the video signal, first loading means for loading a first preset count to said first counter means at the occurrence of at least one vertical s~nchron~zing period, first latch means set by an output generated w~en said first counter means counts N pulses of said first clock pulse train and reset ~y a vertical synchxonizing signal for generating a first control signal, second counter means for counting a second clock pulse train ~a~ing a frequency such that at least a predetermined number, M, of pulses occur within one horizontal period, second loading means for loading a second 2Q preset count to said second counter means during at least one horizontal synchronizing period, a second latch means set when said second counter means cou~ts M pulse.s of said second clock pulse and reset by a. horizontal synchronizing signal for generattng a second control signal, and means for com-bining said first and ~econd control signals to produce acomposite control signal b~ ~hich the switcher means is controlled.
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- 3c ~ ~ v3 There is also provàded:
A video special effects generator compris~ng:
switcher means ha~ing a plurality of video inputs and a single video output for switching one of sa~d plurality of input video signals onto said si:ngle video output while a control signal is produced, and control signal generating means having first counter means for counting N clock pulses within a period related to a video slgnal, loading means for loading a preset number into said first counter means lQ before said period, means for varying said preset number, said counter means being operative to generate an output signal when the sum of said preset num~er and the counted clock pulses equals N, and means responsive to said output signal for producing said controI si~nal at a time determ~ned by when said output signal is generated~
-Th~re is-- al50- proviaed~
/ A ~deo specia~ effects seneratox comprising: a wipe and key switcher having first and second video inputs ::
and one video output, said wipe and key switcher being operative 2a in response to a control signal to switch the signal connected to said ~ideo output between said first and second video inputs, a control signal generator for generating said control s~gnal, said control signal generator having ~irst and second 8-bit X counters, means svnchron~zed with a vi~eo synchronizing pulsefor loadins first and second preset numbers between O and 255 into said fi~st and second 8 bLt X counters, means for gene:rating a first clock frequency of 4.773 MHz, . .
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- 3d ~ 4w~4 means for permitting counting of said first clock frequency in said first and second 8-b~t X counters between horizontal synchronizing pulses, first and second latch flip-flops which are set by carry ~its from sa~d ~irst and second 8-bit X counters respect~vely and are reset by sa;~d horizontal synchroniz~ng pulses, said first: la~ich fl~p-flop having a set output for generating said control signal and said second fl;p-flop hav;ng a set output for terminating said control signal, first and second 8-bit Y counters, means synchronized with a vertical synchron~zing pulse for loading third and fourth preset numhers between O and 255 into said first and second 8-bit Y counters, means for permitting said first and second 8-bit Y counters to count horizontal s~nchronizing pulses between ~ertical synchronizing pulses, third and fourth latch flip-flops which are set by carry ~its from said first and second 8-bit Y counters respectively and are reset by said vertical synchronizing pulses, said third latch flip-flop ha~ing a set output for generating said con-trol signal and said ~ourth flip-flop having a set output for 2a terminating said control signal, means for generating a speed cIock frequency having a programmable frequency, a speed 8-bit counter operative to count s~id programmable frequenc~ for a fixed time period synchronized with video synchronizing pulses; the num~er stored in said speed 8-bit counter being equal to said third preset number and equal to the 2's complement of sa~d fourth preset n~ber, said first : preset number being selectable from one of sa~d speed 8-bit .~;
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counter and said first 8~bit ~ counter, and said ~econd preset number be~ng selecta~le from one of sa~d speed 8-bit counter and said second 8 hit counter, A preferred embodimenk of the present invention will now be descri~ed b~ ~ay of example and ~ith reference to the accompanying dra~ings, in whi.ch:
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.::, .. .: .:: -, . . . . . , :' '.. :, ' : ' . .. ' . ' Figure 1 is a block diagram showing a signal processing system in which the present inve~tion i~ employed, Figures 2A and 2B are diagrams used ~or explaining the effect on a television screen obtained by operating the signal processing system shown in Figure 1, Figure 3 is a circuit diagram showing an example of the practical circuit of the system shown in Figure 1, Figure 4 i9 a block diagram showing an example of the wipe (key) generator which is used together with the - 10 circuits shown in Figures 1 and 3;
Figures 5 and 6 are waveform diagrams used for explaining the operation of some elements used in the circuit 3hown in Figure 4;
Figure 7 is a diagram used for explaining a picture on a television gcrèen by the operation of the elements described in connection with Figure 5;
Figure 8 is a waveform diagram used for explaining the operation of the other element of the circuit shown in Figure 4, Figure 9 is a diagram used for explaining a tele-: vision picture by the operation of the element described in ; . connection with Figure 8, - ; Figures 10, 11, 12, 13, 1~, 15 and 15' are diagrams showing television pictures provided by changing the : 25 operating st~te o~ the circuit shown in Figure 4, Fi~ure 16 is~a diagram showing a television picture produced by the operatlon of a certain element of the . ~'.'! ' . ~ ' ' ' " ' ' . ' ' '' ~ . ' ', , , . : .' . '' . '' ' ' circuit shown ln Figure 4, Figures 17, 18 and :L9 are diagrams showing television pictures and waveform diayrams associated therewith used for the explanation of a certain element of the circuit ~hown in Figure 4, Figure 20 is a bloc]c diagram of the soft-edge generator, Figures 21, 22 and 23 are diagrams showing a circuit`which produces a signal fed to the circuit shown in Figure 4 and waveforms used for explaining the operation of the circuit, Figure 24 is a block diagr~n showing an example of the dissolve signal generator which is used together with the circuits shown in Figures 1 and 3, Figure 25 i~ a graph showing a waveform which is u ed for explaining the operation of a certain element of the dissolve signal generator shown in Figure 24, Figure 26 i8 a block diagram showing an example of the practical circuit of the element described in connection with Figure 25;
Figures 27 and 28 are waveform diagrams used ~or explaining the other elements of the ramp signal generator shown in Figure 24, Figure 23 is a blo~k diagram showing an example of the practic~l circuit of the elements described in connection with ~Figures 27 and 28 ~ .
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Fi~ure 30 shows the soft edge generator of Figure 20 in greater detail, and Figure 31 illustrates waveforms occurring in use of the generator of Figure 30,.
Fi~ure 1 is a block diagram showing the signa:L
processing system in which a video special effect generator according to the present invention is employed. In the figure, signal processing system 10 has two input terminals 12 and 14 and an output terminal 16. Video qignals to be 10 processed are fed to the input terminals 12 and 14, respectively. The signal processing system 10 also includes a wipe and key switcher 18 and a dissolve switcher 20. The first switcher 18 receives a wipe and key switching pulse applied to an input terminal 22 connected thereto, while the 15 second switcher 20 receives a dissolve control signal applied to an input terminal 24 connected thereto. The first switcher 18 also receives first and second video signals fed to the terminals 12 and 14 and has an output terminal connected ta a fixed contact 1 of a switch 28. A switch 26 20 is also provided which has one fixed contact 1 connected to the input terminal 12 directly and the other fixed contact
There are already known various types of special effect generators, in which a composite video si.gnal is produced consisting of selected parts of two input video signals from two cameras by selectively switching the video signals. The conventional generator is provided with an analogue signal processing circuit including horizontal and vertical sawtooth or parabolic generators which generate analogue potentials proportional to the horizontal and vertical positioning of a scanning spotO Analogue comparators are thenarranged to compare various combinationq of these analogue signals, and the switching signals generated by the analogue comparators operate electronic switches which switch portions of t'he input video signals into a single output video signal under the control of the relative magnitudes of the combination signals which are being comparedO The horizuntal and vertical sawtooth or parabolic generators are usually constituted by integrating circuits comprising c,apacitance and resistance. As a result, the generatorg are prone to drift with temperature changes and : with the aging of componentsO
In order.to overcome the above-described defects, a digital special effect generator has been propose~ such as ~ shown ln UOSO Patent ~oO 3,821,468 and UO~O Patent NoO 3,941,925, ;~ 25 in which the genérator includes at l~ast a lever ~ounter, a ~ ~ horizontal (or vertical) counter and a digital co~parator.
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L;~
The lever co~lnter prod~ces a di~ital signal corresponding to the position of a manually operated potentiometer, while the horiæontal counter counts the predeterrnined number of pulses, for example, 512 pulses per horizontal line to provide the di~ital indication of the horizontal pGsition of the scanning lineO The contents of the lever counter and the horizontal counter are compared in the comparator which provides a transition signal when the count of the hori~ontal counter exceeds the value stored in the lever counterO This causes the output video signal to be switched in accordance with the position of the lever counter.
The above-mentioned construction of the generator requires the horizontal and vertical digital comparators to produce the switching signals for the horizontal and vertical wipe operation, respectively. It is apparent that the construction of the generator becomes more complex because of the addition of the comparators and it will be extremely difficult to exactly control the size and speed of the switching signal from the generatorO
According to the present invention, there is provided a .ideo special effect generator having a switching means :. ~ ' ' . .: :
, ' : , , . . :
. . . ' - ~ . . .
~ ~4L~
- 3a -to which a plurality of video signal~ are supplied for simllltaneously combining portions of said video signals into a single picture by controlling said switching means, said generator including at leaRt one circuit arrangement comprising, a counter, mean~ for ~upplying N clock pulses to said counter within a period of predetermined duxation, mean~3 for loading a preset count to said counter at each repeat of qaid period, and a flip-flop arrangement set by the output of said counter and reset at the end of each repeat of ~aid period of generating a control signal to be ~upplied to qai~ ~witching mean~
More p~rticul~rl~t there is provide~:
... : :~:_=,' ~ ~ideo special effects generator ha~ing switcher means to which a plural~ty of video signals are supplied and generator means for generating control signals, said control signals com~ining portions of said video signals into a singIe pictur~ ~y controllin~ said switcher means, said generator means compris~ng: a counter~ loading means for loading a variable preset count ~nto said counter, means for supplying N clock pulses to said counter within a period of predetermined durat~on, and latch means set at a time determined by when an output of said counter lndicates that . . .
said counter has attained a predetermined count va~.ue and re~et at the end of sa~d period for generating ~aid control . _ . . . _ _ slgnals .
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- 3b There is also pravided;
A video special effects generator having switcher means to which a plurality of video signals are supplied .
for comblning portions of said video signals into a single picture, and control signal genexating means for generating control signals which control said switcher means, said control signal generating means compirslng: first counter means for counting a first clock pulse train having a fre~uency such that at least N first clock pulse occur ~ithin one vertical period of the video signal, first loading means for loading a first preset count to said first counter means at the occurrence of at least one vertical s~nchron~zing period, first latch means set by an output generated w~en said first counter means counts N pulses of said first clock pulse train and reset ~y a vertical synchxonizing signal for generating a first control signal, second counter means for counting a second clock pulse train ~a~ing a frequency such that at least a predetermined number, M, of pulses occur within one horizontal period, second loading means for loading a second 2Q preset count to said second counter means during at least one horizontal synchronizing period, a second latch means set when said second counter means cou~ts M pulse.s of said second clock pulse and reset by a. horizontal synchronizing signal for generattng a second control signal, and means for com-bining said first and ~econd control signals to produce acomposite control signal b~ ~hich the switcher means is controlled.
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- 3c ~ ~ v3 There is also provàded:
A video special effects generator compris~ng:
switcher means ha~ing a plurality of video inputs and a single video output for switching one of sa~d plurality of input video signals onto said si:ngle video output while a control signal is produced, and control signal generating means having first counter means for counting N clock pulses within a period related to a video slgnal, loading means for loading a preset number into said first counter means lQ before said period, means for varying said preset number, said counter means being operative to generate an output signal when the sum of said preset num~er and the counted clock pulses equals N, and means responsive to said output signal for producing said controI si~nal at a time determ~ned by when said output signal is generated~
-Th~re is-- al50- proviaed~
/ A ~deo specia~ effects seneratox comprising: a wipe and key switcher having first and second video inputs ::
and one video output, said wipe and key switcher being operative 2a in response to a control signal to switch the signal connected to said ~ideo output between said first and second video inputs, a control signal generator for generating said control s~gnal, said control signal generator having ~irst and second 8-bit X counters, means svnchron~zed with a vi~eo synchronizing pulsefor loadins first and second preset numbers between O and 255 into said fi~st and second 8 bLt X counters, means for gene:rating a first clock frequency of 4.773 MHz, . .
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. . .
. ' ' ' ~: "'' '' ' '. ... ' .' ~'" . .' " ~, ' ' ., . , . ~, . . . .
- 3d ~ 4w~4 means for permitting counting of said first clock frequency in said first and second 8-b~t X counters between horizontal synchronizing pulses, first and second latch flip-flops which are set by carry ~its from sa~d ~irst and second 8-bit X counters respect~vely and are reset by sa;~d horizontal synchroniz~ng pulses, said first: la~ich fl~p-flop having a set output for generating said control signal and said second fl;p-flop hav;ng a set output for terminating said control signal, first and second 8-bit Y counters, means synchronized with a vertical synchron~zing pulse for loading third and fourth preset numhers between O and 255 into said first and second 8-bit Y counters, means for permitting said first and second 8-bit Y counters to count horizontal s~nchronizing pulses between ~ertical synchronizing pulses, third and fourth latch flip-flops which are set by carry ~its from said first and second 8-bit Y counters respectively and are reset by said vertical synchronizing pulses, said third latch flip-flop ha~ing a set output for generating said con-trol signal and said ~ourth flip-flop having a set output for 2a terminating said control signal, means for generating a speed cIock frequency having a programmable frequency, a speed 8-bit counter operative to count s~id programmable frequenc~ for a fixed time period synchronized with video synchronizing pulses; the num~er stored in said speed 8-bit counter being equal to said third preset number and equal to the 2's complement of sa~d fourth preset n~ber, said first : preset number being selectable from one of sa~d speed 8-bit .~;
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counter and said first 8~bit ~ counter, and said ~econd preset number be~ng selecta~le from one of sa~d speed 8-bit counter and said second 8 hit counter, A preferred embodimenk of the present invention will now be descri~ed b~ ~ay of example and ~ith reference to the accompanying dra~ings, in whi.ch:
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.::, .. .: .:: -, . . . . . , :' '.. :, ' : ' . .. ' . ' Figure 1 is a block diagram showing a signal processing system in which the present inve~tion i~ employed, Figures 2A and 2B are diagrams used ~or explaining the effect on a television screen obtained by operating the signal processing system shown in Figure 1, Figure 3 is a circuit diagram showing an example of the practical circuit of the system shown in Figure 1, Figure 4 i9 a block diagram showing an example of the wipe (key) generator which is used together with the - 10 circuits shown in Figures 1 and 3;
Figures 5 and 6 are waveform diagrams used for explaining the operation of some elements used in the circuit 3hown in Figure 4;
Figure 7 is a diagram used for explaining a picture on a television gcrèen by the operation of the elements described in connection with Figure 5;
Figure 8 is a waveform diagram used for explaining the operation of the other element of the circuit shown in Figure 4, Figure 9 is a diagram used for explaining a tele-: vision picture by the operation of the element described in ; . connection with Figure 8, - ; Figures 10, 11, 12, 13, 1~, 15 and 15' are diagrams showing television pictures provided by changing the : 25 operating st~te o~ the circuit shown in Figure 4, Fi~ure 16 is~a diagram showing a television picture produced by the operatlon of a certain element of the . ~'.'! ' . ~ ' ' ' " ' ' . ' ' '' ~ . ' ', , , . : .' . '' . '' ' ' circuit shown ln Figure 4, Figures 17, 18 and :L9 are diagrams showing television pictures and waveform diayrams associated therewith used for the explanation of a certain element of the circuit ~hown in Figure 4, Figure 20 is a bloc]c diagram of the soft-edge generator, Figures 21, 22 and 23 are diagrams showing a circuit`which produces a signal fed to the circuit shown in Figure 4 and waveforms used for explaining the operation of the circuit, Figure 24 is a block diagr~n showing an example of the dissolve signal generator which is used together with the circuits shown in Figures 1 and 3, Figure 25 i~ a graph showing a waveform which is u ed for explaining the operation of a certain element of the dissolve signal generator shown in Figure 24, Figure 26 i8 a block diagram showing an example of the practical circuit of the element described in connection with Figure 25;
Figures 27 and 28 are waveform diagrams used ~or explaining the other elements of the ramp signal generator shown in Figure 24, Figure 23 is a blo~k diagram showing an example of the practic~l circuit of the elements described in connection with ~Figures 27 and 28 ~ .
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Fi~ure 30 shows the soft edge generator of Figure 20 in greater detail, and Figure 31 illustrates waveforms occurring in use of the generator of Figure 30,.
Fi~ure 1 is a block diagram showing the signa:L
processing system in which a video special effect generator according to the present invention is employed. In the figure, signal processing system 10 has two input terminals 12 and 14 and an output terminal 16. Video qignals to be 10 processed are fed to the input terminals 12 and 14, respectively. The signal processing system 10 also includes a wipe and key switcher 18 and a dissolve switcher 20. The first switcher 18 receives a wipe and key switching pulse applied to an input terminal 22 connected thereto, while the 15 second switcher 20 receives a dissolve control signal applied to an input terminal 24 connected thereto. The first switcher 18 also receives first and second video signals fed to the terminals 12 and 14 and has an output terminal connected ta a fixed contact 1 of a switch 28. A switch 26 20 is also provided which has one fixed contact 1 connected to the input terminal 12 directly and the other fixed contact
2 grounded. The switch 28 has the other fixed contact 2 connected to the input terminal 14 directly. Signals delivered to the mova~le contacts of the switches 26 and 28 25 are fed to inputs of the dissolve switcher 20 whose output is delivered to a fixed contact 1 of a switch 30. The :
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movable contact of the switch 28 is also connscted directly to the other fixed contact 2 of the switch 30. The movable contact of the switch 30 is connec~ed to the outpu-t terminal 16.
In the above signal processing system 10, when the movable contact of the switch 26 is connected to its fixed contact 2, the movable contact of the switch 2~ to its fixed contact 1 and the movable contact of the switch 30 to its fixed contact 2, the output from the switcher 1~ is delivered to the output tenminal 16, whereby the wipe (key) mode is set.
When the movable contact of switch 26 is connected to its fixed contact 1, that of the switch 28 to its fixed contact 2 and that of the switch 30 to its fixed contact 1, the output from the switcher 20 is delivered to the output terminal 16, whereby the dissolve (fade) mode is provided.
Furthermore, if the switches 26, 28 and 30 are connected with their respective fixed contact 1, as shown in Figure 1, key-in(or key-out) can be achieved, if the movable contact of the switch 26 is changed over to its fixed contact 2 from the switching condition of Figure l, the key-with-fade-: in(out) operation will be achieved.
Figure 2A shows a chart of the key-in (key-out3 operation on the screen. Firstly, the screen (a) imaging ~ only a picture A is dissolved to the screen (b) ~uperimposed ;: 25 a portion of picture B on the picture A, and then the key : screen (c) on which the partion of picture B is inserted in the picture A is obtained.~ The technique of a picture conversion from Figure ~A (a) to Fi~ure 2A (c) is called : ' ~. .: , . . . ..
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, ' ~ '' , ; ' ' '," ':, ' the key-in operation, while the technique of picture conver-sion from Figure 2A (c) to Figure 2A (a) is called the key-out operatlon. If the above technique iB achieved by the signal processing system 10 shown in Figure 1, the video signal which corresponds to the picture A is applied to input terminal 12 and the video s:ignal which corresponds to the picture B is applied to input terminal 14. In this case, the switcher 18 is operated to provlde a video signal which will produce the picture represented by Figure 2A (c).
At this time, the movable contacts of switches 26 and 28 are connected to their fixed contacts 1, respectively, so that the dissolve switcher 20 is supplied with the video signals corresponding to the pictures represented by Figure 2A (a) and (c). m e switcher 20 dissolves both the input video signals such that the video signal corresponding to the picture represented by Figure 2A (b~ is delivered to the output terminal 16 through the switch 30 whose movable contact is connected to the fixed contact 1 thereof.
Figure 2B is a chart showing pictures of the key-with-fade in (out) operation by operating the switches 26, 28 and 30 of the signal processing system 10 shown in Figure l. From a picture scre n which is initially black as shown in Figure 2B (a), a picture combined of the ~: picture portions~A~and B appears gradually as shown in :
~igure 2BI(b), and finally a picture combined of the `~ picture portions~A and B completely appears as shown on a ~:
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picture screen (c) in Figure 2B~ l~e technique that the combined picture of pictures A and B are faded-in in the order of (a), (b) and (c) as described just above is called the key-with fade-in operation, while the technique that the picture on the scre~n (c) of the key state is converted to the black picture on the screen (a) through the picture on the screen (b) is called the key-with-fade-out operation. The above effects on the televi~ion screen are achieved by connecting the movable contact of the first switch 26 to its fixed contact 2 and that of the second switch 28 to its fixed contact 1 and by dissolving the black video signal from the first switch 26 and the output signal from the wipe and key switcher 18 in the dissolve switcher 20.
Figure 3 is a diagram showing an example of the .
practical circuit of the signal processing system lO shown in Fiyure l. In Figure 3, transistors Ql and Q2 buffer ~:
the video signal applied to the input terminal 12, while transistors Q3 and Q4 buffer the video signal applied to the 20 - input terminal 14. Transistors Q6' Q7' Ql6' Ql7' Ql8 an ~ Ql9 ~orm -the wipe and key switcher 18, and transi~tors Qg, ; ~ Qlo' Qll' Ql2' Ql3 and QlL~form the dissolve switcher 20.
The other translstors Q5, Q8 and Q15 P
voltage balance or impedance conversion.
~: 25 Figure 4 is a block diagram showing an example of : :
circuit for gFnerating the key and wipe switching pulse g ~.
~:
,s :
: , ~ L~4 which is applied through the terminal 22 to the wipe and key swi.-tcher 18, In this example, a wipe (key) generator 32 includes an Xl counter 34, X2 counter 36, Yl counter 38, Y2 counter 40 and speed counter 42. ~he Xl and X2 counters S 34 and 36 are supplied with a clock signal fx applied to a terminal 44 and which has a frequency corresponding to 43 fsc ~fsc: frequency of chrominance subcarrier signal], prepared by multiplying the subcarrier Erequency (3.58 MHz) by 4 and counting-down the multiplied frequency by 1/3. The Xl and X2 counters 34 and 36 are also supplied at their load input terminale with a signal fy' fed to a terminal 46. This signal fy' consists of pulses of a narrow width which are formed from the half-H rejected horizontal synchronizing signal. The Yl and Y2 counters 38 and 40 are supplied at their clock input terminals with a signal fy applied to a terminal 48 and also at their load input terminals with a signal VBP fed to an input terminal 50, respectively. The signal fy is the half-H rejected horizontal synchronizing signal and the signal VBP is the vertical blanking pulse, respectivelyO The speed counter 42 is supplied at its clock input terminal with a speed pulse signal SP fed to a - terminal 52. As hereinafter described in detail, the speed pulse SP deternines the wipe speed.
Each of these counters 34, 36, 38, 40 and 42 2S comprises an 8-blt counter, so that they produce carry signal at a count of 256. Each of these counter~ has data :
, .
- : . . . :
. :.-: . , ~. ' . : , . - , ,, . ., - : . .
input terminals which receive data input signals of 8 bits.
The Yl and Y2 counters 38 and 40 and the speed counter 42 have data output terminals of 8 bits. These counters can be preset to a desired counting condition by applying data desired to be preset to their data input terminals at a time when a load signal having a level "0" is applied to their load input terminals.
As will be described later, the system consisting of Xl counter 34 and ~1 counter 38 can operate complementary to the system consisting of X2 counter 36 and Y2 counter 40. Accordingly, for the sake of simplifying the explanation, the system consisting of Xl counter 34 and Yl counter 38 is de~cribed, and thereafter the system consisting of X2 counter 36 and Y2 counter 40 will be described in connection with the syste~ consist7ng of Xl counter 34 and Y2 counter 38.
According to the standard of the ~TSC system, one frame of the video signal includes 525 video lines, each of which contains one horizontal synchronizing pulse, and hence,one field includes 262.5 video lines. ~ow, it is !
assumed that the speed counter 42 is in its cleared state and the data of 8 bits to the Yl counter 38 is "0".
The vertical blanking pulse VBP applied to terminal 50 has the waveform illustrated in Figure 5a, which comprises a 9H time period having a low level and the following 2$3.5H having a high level. When the vertical : `
.. . . .
,: .
:
L~l!~
blanking pulse VBP with the waveform shown on Figure 5a is fed to the Yl counter 38 at its load input terminal, it starts to count the signal fy fed to terminal 48 after the VBP pulse becomes "1". However, in the practical embodiment, the vertical blanking signal VBP is selected to be somewhat, shorter than 9H, for example 8.5H, as shown in Figure 5(b), and thereby the carry from the Yl counter is produced within the subsequent, vertical blanking pulse.
If the data "1" is loaded at the data input terminal of Yl counter 38 by speed counter 42, the carry is produced from the Yl counter 38 at the starting edge of the blanking pulse as shown in Figure 5c. Further, when the data "2" is loaded, the carry appears at the position before 2H from the front edge of the blanking pulse VBP. Thus, it is noted that if the data "n" (O < n ~255) is loaded at the data input terminal of the Y counter, the carry appears at a position before nH from the front edge of the blanking pulse. The carry ignal from the Yl counter 38 i9 applied to a D flip-flop 54 as a clock signaI. This D flip-flop 54 is supplied : .
~; ~0 at its clear input terminal with the vertical blanking signal VBP fed to terminal 50, Figures 6a, 6b and 6c show the vertical blanking pulse VBP, the carry signal which is produced from the Yl counter 38 when the data "n" is l~aded and a Q-output of the ~: .
D flip-f~lop 54, respective1y. The flip-flop 54 is tri~gered by the carry signa~ and reset by the pulse VBP, :::: :: :
:
~$.~
so that a Yl ~wi-tchlng signal shown in Figure 6C will be generated from the Q-outpu-t of the flip-flop 54. When this Yl switching signal is fed through a control circuit 56, a soft edge circuit 58 and an output terminal 60 to the terminal 22 shown in Figures 1 and 3 as the wipe (key) switching pulse, the picture A is selected during the low level of Yl switching signal and during the high level thereof the picture B is selected in the switcher 18.
Accordingly, such a picture as shown in Figure 7 will be produced on the television screen.
Now, if data "n" which increases at every vertical interval is loaded at the data input terminal of the Y
counter 38, the picture B is expanded or wiped upwards gradually as indicated by the arrows in Figure 7 and finally occupies the whole screen. On the contrary, if the data "n"
which decreases gradually at every vertical interval is loaded in the Yl counter, the picture portion A is expanded downwards and finally occupies the whole screen~ If the preset data from the speed counter 42 is fixed, the picture in the key state can be produced on the screen.
Next, the operation of Xl counter 34 will be explained with reference to Figure 8. m e Xl counter 34 is supplied with 8 bits of data from an exclusive OR~gate 62. Though only one exclusive OR-gate 62 is shown in Figure 4 for simpllcity, in a practiçal form of the , circuit there is a r.umber of OR gates corresponding to the '.
: ..
, ' ~ . , ' ' ': . ' ' ~ .
.. : .. . :.
. .
'.
.
.
number of bits, in this embodiment, 8 OR gates. One of the input terminals of OR-gate 62 is connected to the movable contact of a switch 64 whose one fixed contact 1 is connected to the 8-bits output terminal of a latch circuit 66 and whose other fixed contact 2 is connected to the 8-bits out-put terminal of the Yl counter 3~, respectively. Depending on whether a "1" or a "0" is applied to the ~econd inputs of the gates 62, the data from counter 38 is either inverted or uninverted.
~ow, it is assumed that the lnput data from speed counter 42 is "0" and the movable contact of switch 64 is connected to its fi~ed contact 1. As described previously, the frequency of the clock signal fx to the Xl counter 34 is selected to be the subcarrier frequency 3.58 MHz 43. The reason is that if the subcarrier ~requenc~ 3.58 MHz is selected as the clock signal fx the number of pulses to be counted in IH duration amounts to 227 and it is apparent that a number of pulses is lacking for generation of the carry in the 8 bit counter at every horizontal interval. Therefore, if the frequency of the clock signal f~ is selected to be
` - 6 -:, .. . .~.,.: . . : . ..
.: : : ., ;,: - , :, .. , . . . . ~ . .
~L$.~
movable contact of the switch 28 is also connscted directly to the other fixed contact 2 of the switch 30. The movable contact of the switch 30 is connec~ed to the outpu-t terminal 16.
In the above signal processing system 10, when the movable contact of the switch 26 is connected to its fixed contact 2, the movable contact of the switch 2~ to its fixed contact 1 and the movable contact of the switch 30 to its fixed contact 2, the output from the switcher 1~ is delivered to the output tenminal 16, whereby the wipe (key) mode is set.
When the movable contact of switch 26 is connected to its fixed contact 1, that of the switch 28 to its fixed contact 2 and that of the switch 30 to its fixed contact 1, the output from the switcher 20 is delivered to the output terminal 16, whereby the dissolve (fade) mode is provided.
Furthermore, if the switches 26, 28 and 30 are connected with their respective fixed contact 1, as shown in Figure 1, key-in(or key-out) can be achieved, if the movable contact of the switch 26 is changed over to its fixed contact 2 from the switching condition of Figure l, the key-with-fade-: in(out) operation will be achieved.
Figure 2A shows a chart of the key-in (key-out3 operation on the screen. Firstly, the screen (a) imaging ~ only a picture A is dissolved to the screen (b) ~uperimposed ;: 25 a portion of picture B on the picture A, and then the key : screen (c) on which the partion of picture B is inserted in the picture A is obtained.~ The technique of a picture conversion from Figure ~A (a) to Fi~ure 2A (c) is called : ' ~. .: , . . . ..
'' . ' : ' , ', . ~ '. .,: ~ ' '.
- ~ ~ , : . ' .
- , . .: :
, ' ~ '' , ; ' ' '," ':, ' the key-in operation, while the technique of picture conver-sion from Figure 2A (c) to Figure 2A (a) is called the key-out operatlon. If the above technique iB achieved by the signal processing system 10 shown in Figure 1, the video signal which corresponds to the picture A is applied to input terminal 12 and the video s:ignal which corresponds to the picture B is applied to input terminal 14. In this case, the switcher 18 is operated to provlde a video signal which will produce the picture represented by Figure 2A (c).
At this time, the movable contacts of switches 26 and 28 are connected to their fixed contacts 1, respectively, so that the dissolve switcher 20 is supplied with the video signals corresponding to the pictures represented by Figure 2A (a) and (c). m e switcher 20 dissolves both the input video signals such that the video signal corresponding to the picture represented by Figure 2A (b~ is delivered to the output terminal 16 through the switch 30 whose movable contact is connected to the fixed contact 1 thereof.
Figure 2B is a chart showing pictures of the key-with-fade in (out) operation by operating the switches 26, 28 and 30 of the signal processing system 10 shown in Figure l. From a picture scre n which is initially black as shown in Figure 2B (a), a picture combined of the ~: picture portions~A~and B appears gradually as shown in :
~igure 2BI(b), and finally a picture combined of the `~ picture portions~A and B completely appears as shown on a ~:
: ~
- - , . . : . .
~$~L~!f-~s~
picture screen (c) in Figure 2B~ l~e technique that the combined picture of pictures A and B are faded-in in the order of (a), (b) and (c) as described just above is called the key-with fade-in operation, while the technique that the picture on the scre~n (c) of the key state is converted to the black picture on the screen (a) through the picture on the screen (b) is called the key-with-fade-out operation. The above effects on the televi~ion screen are achieved by connecting the movable contact of the first switch 26 to its fixed contact 2 and that of the second switch 28 to its fixed contact 1 and by dissolving the black video signal from the first switch 26 and the output signal from the wipe and key switcher 18 in the dissolve switcher 20.
Figure 3 is a diagram showing an example of the .
practical circuit of the signal processing system lO shown in Fiyure l. In Figure 3, transistors Ql and Q2 buffer ~:
the video signal applied to the input terminal 12, while transistors Q3 and Q4 buffer the video signal applied to the 20 - input terminal 14. Transistors Q6' Q7' Ql6' Ql7' Ql8 an ~ Ql9 ~orm -the wipe and key switcher 18, and transi~tors Qg, ; ~ Qlo' Qll' Ql2' Ql3 and QlL~form the dissolve switcher 20.
The other translstors Q5, Q8 and Q15 P
voltage balance or impedance conversion.
~: 25 Figure 4 is a block diagram showing an example of : :
circuit for gFnerating the key and wipe switching pulse g ~.
~:
,s :
: , ~ L~4 which is applied through the terminal 22 to the wipe and key swi.-tcher 18, In this example, a wipe (key) generator 32 includes an Xl counter 34, X2 counter 36, Yl counter 38, Y2 counter 40 and speed counter 42. ~he Xl and X2 counters S 34 and 36 are supplied with a clock signal fx applied to a terminal 44 and which has a frequency corresponding to 43 fsc ~fsc: frequency of chrominance subcarrier signal], prepared by multiplying the subcarrier Erequency (3.58 MHz) by 4 and counting-down the multiplied frequency by 1/3. The Xl and X2 counters 34 and 36 are also supplied at their load input terminale with a signal fy' fed to a terminal 46. This signal fy' consists of pulses of a narrow width which are formed from the half-H rejected horizontal synchronizing signal. The Yl and Y2 counters 38 and 40 are supplied at their clock input terminals with a signal fy applied to a terminal 48 and also at their load input terminals with a signal VBP fed to an input terminal 50, respectively. The signal fy is the half-H rejected horizontal synchronizing signal and the signal VBP is the vertical blanking pulse, respectivelyO The speed counter 42 is supplied at its clock input terminal with a speed pulse signal SP fed to a - terminal 52. As hereinafter described in detail, the speed pulse SP deternines the wipe speed.
Each of these counters 34, 36, 38, 40 and 42 2S comprises an 8-blt counter, so that they produce carry signal at a count of 256. Each of these counter~ has data :
, .
- : . . . :
. :.-: . , ~. ' . : , . - , ,, . ., - : . .
input terminals which receive data input signals of 8 bits.
The Yl and Y2 counters 38 and 40 and the speed counter 42 have data output terminals of 8 bits. These counters can be preset to a desired counting condition by applying data desired to be preset to their data input terminals at a time when a load signal having a level "0" is applied to their load input terminals.
As will be described later, the system consisting of Xl counter 34 and ~1 counter 38 can operate complementary to the system consisting of X2 counter 36 and Y2 counter 40. Accordingly, for the sake of simplifying the explanation, the system consisting of Xl counter 34 and Yl counter 38 is de~cribed, and thereafter the system consisting of X2 counter 36 and Y2 counter 40 will be described in connection with the syste~ consist7ng of Xl counter 34 and Y2 counter 38.
According to the standard of the ~TSC system, one frame of the video signal includes 525 video lines, each of which contains one horizontal synchronizing pulse, and hence,one field includes 262.5 video lines. ~ow, it is !
assumed that the speed counter 42 is in its cleared state and the data of 8 bits to the Yl counter 38 is "0".
The vertical blanking pulse VBP applied to terminal 50 has the waveform illustrated in Figure 5a, which comprises a 9H time period having a low level and the following 2$3.5H having a high level. When the vertical : `
.. . . .
,: .
:
L~l!~
blanking pulse VBP with the waveform shown on Figure 5a is fed to the Yl counter 38 at its load input terminal, it starts to count the signal fy fed to terminal 48 after the VBP pulse becomes "1". However, in the practical embodiment, the vertical blanking signal VBP is selected to be somewhat, shorter than 9H, for example 8.5H, as shown in Figure 5(b), and thereby the carry from the Yl counter is produced within the subsequent, vertical blanking pulse.
If the data "1" is loaded at the data input terminal of Yl counter 38 by speed counter 42, the carry is produced from the Yl counter 38 at the starting edge of the blanking pulse as shown in Figure 5c. Further, when the data "2" is loaded, the carry appears at the position before 2H from the front edge of the blanking pulse VBP. Thus, it is noted that if the data "n" (O < n ~255) is loaded at the data input terminal of the Y counter, the carry appears at a position before nH from the front edge of the blanking pulse. The carry ignal from the Yl counter 38 i9 applied to a D flip-flop 54 as a clock signaI. This D flip-flop 54 is supplied : .
~; ~0 at its clear input terminal with the vertical blanking signal VBP fed to terminal 50, Figures 6a, 6b and 6c show the vertical blanking pulse VBP, the carry signal which is produced from the Yl counter 38 when the data "n" is l~aded and a Q-output of the ~: .
D flip-f~lop 54, respective1y. The flip-flop 54 is tri~gered by the carry signa~ and reset by the pulse VBP, :::: :: :
:
~$.~
so that a Yl ~wi-tchlng signal shown in Figure 6C will be generated from the Q-outpu-t of the flip-flop 54. When this Yl switching signal is fed through a control circuit 56, a soft edge circuit 58 and an output terminal 60 to the terminal 22 shown in Figures 1 and 3 as the wipe (key) switching pulse, the picture A is selected during the low level of Yl switching signal and during the high level thereof the picture B is selected in the switcher 18.
Accordingly, such a picture as shown in Figure 7 will be produced on the television screen.
Now, if data "n" which increases at every vertical interval is loaded at the data input terminal of the Y
counter 38, the picture B is expanded or wiped upwards gradually as indicated by the arrows in Figure 7 and finally occupies the whole screen. On the contrary, if the data "n"
which decreases gradually at every vertical interval is loaded in the Yl counter, the picture portion A is expanded downwards and finally occupies the whole screen~ If the preset data from the speed counter 42 is fixed, the picture in the key state can be produced on the screen.
Next, the operation of Xl counter 34 will be explained with reference to Figure 8. m e Xl counter 34 is supplied with 8 bits of data from an exclusive OR~gate 62. Though only one exclusive OR-gate 62 is shown in Figure 4 for simpllcity, in a practiçal form of the , circuit there is a r.umber of OR gates corresponding to the '.
: ..
, ' ~ . , ' ' ': . ' ' ~ .
.. : .. . :.
. .
'.
.
.
number of bits, in this embodiment, 8 OR gates. One of the input terminals of OR-gate 62 is connected to the movable contact of a switch 64 whose one fixed contact 1 is connected to the 8-bits output terminal of a latch circuit 66 and whose other fixed contact 2 is connected to the 8-bits out-put terminal of the Yl counter 3~, respectively. Depending on whether a "1" or a "0" is applied to the ~econd inputs of the gates 62, the data from counter 38 is either inverted or uninverted.
~ow, it is assumed that the lnput data from speed counter 42 is "0" and the movable contact of switch 64 is connected to its fi~ed contact 1. As described previously, the frequency of the clock signal fx to the Xl counter 34 is selected to be the subcarrier frequency 3.58 MHz 43. The reason is that if the subcarrier ~requenc~ 3.58 MHz is selected as the clock signal fx the number of pulses to be counted in IH duration amounts to 227 and it is apparent that a number of pulses is lacking for generation of the carry in the 8 bit counter at every horizontal interval. Therefore, if the frequency of the clock signal f~ is selected to be
3.58 ~ 43 MHz. The number of pulses to be counted in IH
period amounts to 303.3. As a result in order to count 255 pulses in IH duration it is'~ecessary that the~width of t~ oad pulse to the Xl counter 34 is selected about 10 ~S
(micro seconds). Thus, it is apparent that the load pulse ~ecomes equivalent to the horizontal blanking pulse. For ~ - 14 -: ' :
. - . . . ~ . .
::: : .: , . . . : .
.:--. , -. . . , : : ' . -.
- . . '. : ,: -' , .' .: ~: : ~ ., .. . . . .
, . ~ : . : : . . . .
; . : , ::
~ $~
this reason, the input terminal 46 is supplied, as the load input to the Xl counter, with the pulse fy' of a narrow width (shown in Figure 8a) which is produced from the half-H
rejected H synchronizing signal and which has a low level period of about 10 ~S. This period is equivalent to the period of ~9~3 pulses of the signal fx (Figure 8b) having the frequency 3.58 x 3 MHz. Accordingly, the period of signal fy' in high level corresponds to the peri.od of 254 pulses of the signal fx. Thus in the same manner as the Yl counter 38, the carriers can be obtained at the desired position in response to the corresponding preset value applied to the data input :terminal of the Xl counter 34. The carry signal therefrom is fed to a D flip-flop 68 as a clock input signal. The flip-flop 68 is supplied at its clear input terminal with the signal fy' fed to the terminal 46, so that it produces at its Q-output terminal : an X switching pulse shown in Figure 8d~ This X switching pulse is fed through the control circuit 56, soft edge circuit 58 and output terminal 60 to the terminal 22, shown in Figures 1 and 3, as the key and wipe switching pulse. In - this case, if the switcher 18 is such that the signal corresponding to the picture A is delivered during the low lever of the X switching pulse and the signal corresponding to the picture B is delivered during the high level of the X swltching pulse, on the television screen the picture portion B lS expanded to the left gradually as n increases ~, .
~ 15 ~ ' ~ . : . ; .-. . . ~, ' . .
. : ,. .. .. .
.
:. ......... ~ :
. ' : . ': . ' . .
.. . .
gradually with respect to the succeeding H blanking pulses as shown in Figure 9 and finally occupies the whole screen,~while the picture portlon A is expanded to the right gradually as n decreases gradually and finally S occupies the whole screen. When the input data value to the Xl counter 34 is fixed, the key state where the picture portions A and B are not changed is produced on the screen.
The above explanation represents the case where the movable contact of switch 64 is connected to its fixed contact l. If the movable contjact of switch 64 is turned to its other fixed contact 2, the Xl counter 34 is supplied with the 8 bit input data from the Yl counter 38.
If it is assumed that the output from the speed counter 42 is "0", the 8-bits output data from the Yl counter 38 15 iS loaded at the Xl counter 34 at every horizontal interval.
Since the Yl counter 38 counts the horizontal synchronizing pulse fy fed to terminal 48 during the high level period of the vertical blankin~ signal shown in Figure 5b, the output data from the Yl counter 38 increases by l at every H interval. This output data from the Yl counter 38 is loaded to the Xl counter 34 at the time when the load pulse fy' having horizontal synchornizing frequency is applied thereto and then the Xl counter 34 counts up the clock pulse fx from the load value. merefore, it i9 to be noted that the ~eneration of the carry output from the X1 counter 34 is shifted to the leEt by one pulse fx at every time when -- ; ~ ~ . . ................ . . . .
., . . ,, . ,, . ,: , : :
: ' ' " ' , : :' :.' ' ~ ' . , , ' . ~ ' : ' ', , , " , . : ' .
.. . ~ . .. . . . .
when the Q-outputs of the Yl counter 38 increases. That is to say, the output data from the Y1 counter 38 is "O" in the first horizontal interval, so that the carry output from the Xl counter 34 is fal;Len within the H blanking period. ~ext, when the outpul data from the Y1 counter 38 becomes "1", in the second horizontal interval, the carry output from the Xl counter 34 appears at the position of 1 pulse before the subsequent horiæontal sync signal which corresponds to the right upper side of the screen. In this manner, when the Yl counter 38 counts 254 H, the carry from the Xl counter 34 appears at the position of 254 pulses before the subsequent horizontal sync ~ignal which corresponds to the left down side of the screen. If the succeeding carry outputs from the Xl counter 34 which are formed in the above manner are used to set the D flip-flop 68 and in turn this D flip-flop 68 is reset by the clear pulse fy', the flip-flop 68 produces such X switching pulses that the picture on the television screen is diagonally divided with the picture portions A and B as ~0 shown in Figure 10.
If the speed counter 42 counts up at a cetain speed, the output from the Yl counter 38 is offset by an ~: amount corresponding the output data from the speed counter 42. Accord1n~ly, at every time when the speed counter 42 counts up, such as "0"; "l"..~.."n",~...."255"~ the : diagonal dividing line of the television picture moves -~ 17 -~`
. ~ ~ , . ,. ' , ~. ' - .'. ' - :
: ~ ' - : ~' . , , : : . - .
.
,, ~ . . .
period amounts to 303.3. As a result in order to count 255 pulses in IH duration it is'~ecessary that the~width of t~ oad pulse to the Xl counter 34 is selected about 10 ~S
(micro seconds). Thus, it is apparent that the load pulse ~ecomes equivalent to the horizontal blanking pulse. For ~ - 14 -: ' :
. - . . . ~ . .
::: : .: , . . . : .
.:--. , -. . . , : : ' . -.
- . . '. : ,: -' , .' .: ~: : ~ ., .. . . . .
, . ~ : . : : . . . .
; . : , ::
~ $~
this reason, the input terminal 46 is supplied, as the load input to the Xl counter, with the pulse fy' of a narrow width (shown in Figure 8a) which is produced from the half-H
rejected H synchronizing signal and which has a low level period of about 10 ~S. This period is equivalent to the period of ~9~3 pulses of the signal fx (Figure 8b) having the frequency 3.58 x 3 MHz. Accordingly, the period of signal fy' in high level corresponds to the peri.od of 254 pulses of the signal fx. Thus in the same manner as the Yl counter 38, the carriers can be obtained at the desired position in response to the corresponding preset value applied to the data input :terminal of the Xl counter 34. The carry signal therefrom is fed to a D flip-flop 68 as a clock input signal. The flip-flop 68 is supplied at its clear input terminal with the signal fy' fed to the terminal 46, so that it produces at its Q-output terminal : an X switching pulse shown in Figure 8d~ This X switching pulse is fed through the control circuit 56, soft edge circuit 58 and output terminal 60 to the terminal 22, shown in Figures 1 and 3, as the key and wipe switching pulse. In - this case, if the switcher 18 is such that the signal corresponding to the picture A is delivered during the low lever of the X switching pulse and the signal corresponding to the picture B is delivered during the high level of the X swltching pulse, on the television screen the picture portion B lS expanded to the left gradually as n increases ~, .
~ 15 ~ ' ~ . : . ; .-. . . ~, ' . .
. : ,. .. .. .
.
:. ......... ~ :
. ' : . ': . ' . .
.. . .
gradually with respect to the succeeding H blanking pulses as shown in Figure 9 and finally occupies the whole screen,~while the picture portlon A is expanded to the right gradually as n decreases gradually and finally S occupies the whole screen. When the input data value to the Xl counter 34 is fixed, the key state where the picture portions A and B are not changed is produced on the screen.
The above explanation represents the case where the movable contact of switch 64 is connected to its fixed contact l. If the movable contjact of switch 64 is turned to its other fixed contact 2, the Xl counter 34 is supplied with the 8 bit input data from the Yl counter 38.
If it is assumed that the output from the speed counter 42 is "0", the 8-bits output data from the Yl counter 38 15 iS loaded at the Xl counter 34 at every horizontal interval.
Since the Yl counter 38 counts the horizontal synchronizing pulse fy fed to terminal 48 during the high level period of the vertical blankin~ signal shown in Figure 5b, the output data from the Yl counter 38 increases by l at every H interval. This output data from the Yl counter 38 is loaded to the Xl counter 34 at the time when the load pulse fy' having horizontal synchornizing frequency is applied thereto and then the Xl counter 34 counts up the clock pulse fx from the load value. merefore, it i9 to be noted that the ~eneration of the carry output from the X1 counter 34 is shifted to the leEt by one pulse fx at every time when -- ; ~ ~ . . ................ . . . .
., . . ,, . ,, . ,: , : :
: ' ' " ' , : :' :.' ' ~ ' . , , ' . ~ ' : ' ', , , " , . : ' .
.. . ~ . .. . . . .
when the Q-outputs of the Yl counter 38 increases. That is to say, the output data from the Y1 counter 38 is "O" in the first horizontal interval, so that the carry output from the Xl counter 34 is fal;Len within the H blanking period. ~ext, when the outpul data from the Y1 counter 38 becomes "1", in the second horizontal interval, the carry output from the Xl counter 34 appears at the position of 1 pulse before the subsequent horiæontal sync signal which corresponds to the right upper side of the screen. In this manner, when the Yl counter 38 counts 254 H, the carry from the Xl counter 34 appears at the position of 254 pulses before the subsequent horizontal sync ~ignal which corresponds to the left down side of the screen. If the succeeding carry outputs from the Xl counter 34 which are formed in the above manner are used to set the D flip-flop 68 and in turn this D flip-flop 68 is reset by the clear pulse fy', the flip-flop 68 produces such X switching pulses that the picture on the television screen is diagonally divided with the picture portions A and B as ~0 shown in Figure 10.
If the speed counter 42 counts up at a cetain speed, the output from the Yl counter 38 is offset by an ~: amount corresponding the output data from the speed counter 42. Accord1n~ly, at every time when the speed counter 42 counts up, such as "0"; "l"..~.."n",~...."255"~ the : diagonal dividing line of the television picture moves -~ 17 -~`
. ~ ~ , . ,. ' , ~. ' - .'. ' - :
: ~ ' - : ~' . , , : : . - .
.
,, ~ . . .
4~
towards the top of the screen as shown in Figure 11. On the contrary, when the contents of the speed cownter 42 is counted down, such as "255",.. ,"n",.... , "1", "0", the diagonal boundary moves downwards. The 8-bit speed counter
towards the top of the screen as shown in Figure 11. On the contrary, when the contents of the speed cownter 42 is counted down, such as "255",.. ,"n",.... , "1", "0", the diagonal boundary moves downwards. The 8-bit speed counter
5 42 is supplied at its clock input terminal with the wipe speed pulse SP ~ed to the terminal 52 and also at its data input terminal with the key size data through a line 70. When a switch 72 is closed and hence the load input terminal of speed counter 42 is grounded, the content of 10 this speed counter 42 is fixed by the key data and the wipe (key) generator 32 is changed from the wipe generation mode to the key generation mode.
q~he data output from the speed counter 42 is applied to an exclusive OR-gate 74. Only one OR-gate 74 is shown 15 in Figure 4, but in practice the number of OR-ga-tes 74 corresponds to the bit number of the data outputs ~rom the speed counter 42. A control input terminal 74' is provided for the exclusive OR-gate 74. As well known, when the state of a control input to the control input terminal 20 74' is selectively changed to high or low, the speed counter ~2 can be operated as up-counter or down counter, respectively. For example, it is possible in the wipe mode of the composite television picture con~isting of the picture portions A and B shown in Figure 12 that if the 25 control input to the exclusive OR-gate 74 is changed, a wipe in the direction 76 or 78 (in Figure 12) can be - ... ~ . . , .. ... . . : , ,, , .- . , .,: , ; .,,. ., - -:. :. ,,: ':: ~' . ~ ' ' '. ' ' . : `. , , - ., :
-selectively carried out.
The exclusive OR-gate 62 is provided with a ~ontrol input terminal 62' which is operated similar to the control input terminal 74'~ The exclusive OR-gate 74 controls the whole operating direction of the wipe generator 32, while the exclus.ive OR-gate 62 merely determines the direction of the wipe operation in the horizontal direction. The levels of the control signals fed to the control input terminals 62' and 74' are controlled in response to the w.ipe pattern and key pattern desired.
me wipe (key~ generator 32 shown in Figure 4 is also provided with Y2 counter 40 similar to the Yl counter 38, X2 counter 36 3imilar to the Xl counter 34, exclusive OR-gate 84 similar to the exclusive OR-gate 62, switch 86 similar to the switch 64, D flip-flop 80 similar to D
flip-flop 54 which receives the carry output from the Y2 counter 40, and D flip-flop 82 similar to the D flip-flop 68 which receive the carry output from the X2 counter 36. m e 8-bit data output from the exclusive OR-gate 74 is applied directly to the Yl ~ounter 38 but through an ;: inv~rter-84 to the Y2 counter 40. This inverter 84 is used for complementary oper-ation of the Y2 counter 40 relative to the Yl counter 38. That is, if a co~posite Y switching pulse is formed from the Yl and Y2 switching pulses, there is produced a picture in which the upper and lower picture portions ~ are wiped over the picture portion , : . ' ~ : .
.. ~ ~ , . .
. .
A therebetween as shown in Figure 13a, or a ~icture in which the picture portion B between the upper ar.d lower picture portions A is wiped over the picture portions A as shown in Figure 13b. Similarly, if the movable contacts of switches 64 and 86 are connected to their fixed contacts 1, respectively, and the leve~sof the control inputs to the exclusive OR-gates 62 and 84 are different to each other ~a) composite X switching pulse of the Xl and X2 switching pulses produces a picture in which the left and right picture portions B are wiped to the picture portion A therebetween as shown in Figure 14a, or in which the picture portion B
between the left and right picture portions A is wiped over both the picture portions A as shown in Figu.re 14b. ~ext, if the movable contacts of switches 64 and 86 are lS connected to their fixed contacts 2, respectively, and ~e composite switching pulses are produced from the Xl, Yl -switching pulses and X2, Y2 switching pulses, pictures can be obtained in which the picture portions A and B are wiped as shown in Figures 15a, 15b, 15c and 15d, respectively.
In addition to the foregoing, if the conditions of the control inputs to the exclusive OR-gates 62, 74 and 84 are selectably changed, the switches 64 and 86 are controlled and the combination of Xl, X2, Yl and Y2 switching pulses lS selected in various ~anners, various wipe effects shown in Figure 15' can be obtained on the :~ ~ screen.
: : ' : - 20 -.
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.
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.... : . ~ , , -' '' ' ' : . . ~ .,:
... : . . : ' In F'igure 4, as described previously, there is provided a latch circuit 66 which receives at its data input terminal the 8 bit output data from the speed counter 42 through the exclusive OR-gates 74. This latch circuit 66 has a clock input terminal which receives the vertical blanking pulse VBP fed to the terminal 50, and a data output terminal from which the 8 bit data output is fed to the data input terminals of the Xl counter 34 and X2 counter 36 through the fixed contacts l of switches 64 and 86 and the exclusive OR-gates 62 and 84, respectively. The Xl and X2 counters 34 and 36 are loaded with the input data at every load pulse fy' having the.horizontal synchronizing frequency. If the latch circuit 66 is omitted, the Xl and X2 counters 34 and 36 are loaded with the data output from the speed counter 42 as it is.
m is means that the data of speed counter 42 may be renewed in the picture being reproduced in the television screen that is, during certain horizontal intervals other than t~e vertical blanking period. For this reason, the boundary between the two picture portions A and B does not become a straight line and the boundary line is terraced,~as shown in Figure 16a. In order to avoid the above : . disturbance on the screen, the output data from speed counter 42 is latched by the pulse VBP having the vertical synchroniz.ing frequency and held during one field period.
.
~ e held data in the altch circuit 66 is used as the preset ~;
:
-, data for -the Xl and X2 counters 34 and 36, so that the effect o:E the steps shown in Figure 16a diqappears and hence the boundary line between the picture portions A and B becomes straight, as shown in Figure 16b. In Figure 16, a numeral 90 designates the boundary line at the first ~ield and 92 designates the boundary line at the subsequent field, respectively. As the wipe speed becomes ~aster the distance between the boundary lines 90 and 92 becomes wider.
As to the Yl and Y2 counters 38 and 40, they are loaded with the output data from the speed counter 42 by the vertical synchronizing blanking pulse VBP, so that there is no need to provide such a latch circuit for the Yl and Y2 counters 38 and 40.
The control circuit 56 shown in Figure 4 is supplied with the Xl switching pulse from the flip flop 68, the Yl switching pulse from the flip-flop 54, the X2 switching pulse from the flip-flop 82., and the Y2 switching pulse from the flip-flop 80. This control circuit 56 is made of the combination of various gates and produces various types~of composite switching pulses in response to a control logic signal Sc applied thereto.
The soft edge circuit 58 shown in Figure 4 receives the composite switching pulse from the control : circuit 56 has a sharp rising adge as shown in Figure 17a, ~: 25 so that the border line between the picture portions A and B
is rapidly changed, as shown in Figure 17b. On the ,:
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contrary, if the compo~ite switchlncl pulse i~ formed wi-th a slope in a certain period on the border line as shown in Figure 17c, the signals correspondiny to the picture portion~
A and B are mixed with each other in that period. Accordingly, the boundary between the picture portions A and B becomes soft in view of visual sense a~ good for the viewer, as shown in Figure 17d. In order to obtain the soft edge effect on the border line, the ~ignals of -the picture portions A and B are multiplied in analogue manner in the well-known circuit. Therefore, the construction of the conventional circuit becomes complicated and hence expensive. In oxder to practice the same effect, there is provided with the soft edge circuit 58 which processes the composite switching signal from the control circuit 56 in digital manner. As shown in Figure 18b, the circuit 58 generates a series of switching pulses for the boundary area A + B of the picture portions A and B shown in Figure 18a. It should he noted that the mark to space ratio of the pulses in Figure 18c increases continuously. The mark to space ratio or duty cycle is low at the boundary portion A + B near the picture portion A but becomes high near the picture portion B. Accordingly, due to the visual integrating effect on the screen such a picture with a soft edge effect similar to that by the analogue method. Since the soft edge effect can be performed by the digital processing of the switching signal, the linearity on the boundary portion A ~ B is improved.
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- . - : , ' .' . ':.' ~ , . , ' :: ' :
In addition to the above soft edge effect in the vertical direction, it is possible that the soft edge effect in the horizontal direction is achieved by the manner similar to the above.
Figure l9a shows a screen in which the boundary portion A + B between the upper and lower picture porkions A and B is subjected to the so~t edging. In this case, the boundary portion A ~ ~ includes n~I lines. A line near the upper picture portion A is switched by the pulse whose duty cycle is low as shown in Figure l9b and the last line of n lines is switched by the pulse whose duty cycle is highest, as shown in Figure l9c. Thu9, the boundary portion A ~ B, which is soft-edged by changing the distxibution of the signals corresponding to the picture portions A and B at each line in time, can be obtained on the screen.
Figure 20 is a block diagram showing an embodiment of the soft edge circuit 58. The soft edge circuit 58 shown in Figure 20 consists of two 4-bit counters 100 and 1 --102 and an inverter 104. An integrated circuit type SN 74161 made by Texas Instruments Inc. can be used for each of the above counters. A clock signal fc applied to an input terminal 106 is fed to the first counter 100 at its clock ; input terminal. If no clear input signal is applied to the ::
~ counter 100 at its clear input terminal, because of switch : :
108 belng OFF, the counter 100 produces the carry output signal when it counts up the 15th clock pulse. The carry , , ,.
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f~
output signal is lnverted by an inverter 104 and then fed to the second counter 102 at its clock input termi.nal and also to the first counter 100 at its load inpu.t terminal. When the load input becomes low by the above load input, A, B, C and D i~puts of the first counter 100 P Y QA' QB' QC and QD outputs from the second counter 102. Upon the arrival of the first carry pulse, the second counter 102 produces the output of "0" and hence the first counter 100 is preset by this output "0".
Next, the first counter 100 is preset by the value "1" at the next carry output. In this manner, the first counter 100 is preset u~ to "15". As a result, at an output terminal 110, which is connected with the carry output terminal of the first counter 100, there is obtained a sub-pulse signal fOUT having a changing period which becomes narrower at the occurrence of each pulse of the clock signal fc. The composite switching signal with the soft edge effect will be obtained by suitably gating the composite switching signal from the circuit 56 with the pulse signal fOUT
Figure 30 shows a complete circuit diagram of the soft edge effect generator, the upper portion of which : corresponds to the circuit of Figure 20 that generates a series of pulses having different mark to space ratios at each cycle~ as described above. The series of pulses from :~ the terminal 110 are supplied to the lower portion of the .
. . :,, . , , . .: . ,, : :
.:: ' .. :: . ' ' . . : :
,:: - , circuit which is mainly composed of a counter 101 and a set of gate circuits. The switching signal from the gate circuit 56 (Figure 4) is supplied to the counter 101 which produces the switching signc~l A in itself and another switching signal B delayed by a predetermined time corresponding to the width of the soft edge region. The switching signals A and B are processed in the gate circuits in the manner shown in Figure 31. The signal F
thus obtained in the circuits is suppl.~ed -to the clear-terminals CL of the counters 100 and 102 to enable the counters while the signal F is high. Therefore, during the intervals, there will be obtained a series of pulses gradually reducing in mark to space ratio from the terminal 110, The series of pulses are supplied to exclusive OR
circuit 103 together with the signal C shown in Figure 31 C
so that the signal G shown in Figure 31 G, is generated from the circuit 103. The signal G is further supplied to a ~OR circuit 105 together with the signal D shown in Figure 31, so that the circuit 105 produces the signal H shown in Figure 31 H which should be supplied to the output 60. Asapparent from Figure 31 H, the signal H has an increasing duty cycle during a front soft edge region Tl and a .
decreasing duty cycle during a back soft edge region T2.
The signal H thus obtained is supplied to the wipe switcher 18 (Figure 30j and hence the video signals respectively suppliéd to the inputs 12 and 14 are finely switched in the ' ' .
; ' :
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. .- . . , : . ~ . . . . .. .
. .
,' ' , ' ' ' , .,'............ .: .
swltcher 18 during the regions ln response to the signal H.
The switched video signals are supplied to the television monitor to produce the image picture on the screen and the finely switched areas o:E the picture are softly edged owing to the integrating ef:Eect of human eyes.
Further, it is noted that when the switching signal to the counter 101 iS the horizontal switching signal from the X-counter, the clock signal fc has a relatively high frequency, for example 50 MHZ and the counters lOl and 102 are constituted by the ~-bit counter.
However, in case of the vertical switching signal from the Y-counter, the clock signal fc has a horizontal synchronizing frequency and the counters 101 and 102 are constituted by the 2-bit counter.
As described above, the elements which form the wipe generator 32 shown in Figure 4 are all digital elements. Therefore, it is desired that the circuit which generates the above signals fy and fy' and VBP from the vertical and horizontal synchronizing signals separated from the composite video signal is also constituted by a digital circuit. Conventionally, in order that the : vertical synchronizing signal is derived from the composite ~ ~ synchronizing signal, an anak~ecircuit is employed in which .
::~ an integrating circuit is used. In the system described below, the vertical synchronizing signal is extracted in digital manner by counting out the 3.58 MHz subcarrierO
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.
-.' ' , . ~. . - . ~ ..
, . . .. . . . . . .
A~ shown in Figure 21, the waveform of the composite synchronizing signals of the video signal comprises the f horizontal ~ynchronizing ~ignal having a pulse width of about 4 ~ ~econds and the vertical qynchronizing signal having a pul~e width of about 30 qeconds. Figure 22 i3 a block diagram showing a circuit which will produce a pulse representing the vertical synchroni~ation by u~ing the above difference between the pul~e widths of the horizontaL and vertical ~ynchronizing pul~e~. The vertical synchroniziny separating circuit ~hown in Figure 22 consi~t~ o~ two 4-bit counters 112 and 11~ which are connected in a look-ahead connection manner to form an 8-bit counter~ A Texas In~trument Inc. S~ 74161 integrated circuit can be employed as the counters 112 and 114. The clock input- terminals of the first and second counters 112 and 114 are connected to a terminal 116 to receive the subcarrier ~ignal of 3.58 M~z fed thereto, and the clear input tenminals of the ~irst and second counter~ L12 and 114 and the count enable input tenminals P and T of the fir~t counter 112 are connected to a terminal 118 through - -an inverter 120 to receive the composite synchronizing signal which i5 lnverted by the inverter 120. The carry output terminal of the first counter 112 is connected to ~:~ - the count enable lnput terminal P and,T of the second counter 114, and a Q7-output terminal of the second counter ~:
114 i3 co~mected to an output terminal 122 i.e. the 7-bit .:
.,~ -' : . . :, i output signal of the 8~bit counter :is delivered to the output terminal 122.
According to -the circuit described just above, the 8-bit counter counts abc~ut 15 pulses of the clock signal having frequency 3.58 MHz during the horizontal synchronizing pulse period, while the counter counts more than 100 pulses during the :Low level period in the vertical synchronizing pulse period. Accordingly, the vertical synchronizing pulse can be distinguished by detecting the output of the 7th bit of the counter s.ince the count value 15 is indicated by (1111) in binary number and the count value 100 is indicated by (1100010) in binary number.
Figure 23a is a waveform diagram showing the composite synchronizing signal and Figure 23b is a waveform diagram showing a waveform which is derived from the 7th bit output terminal of the counter. The pulse thus produced i9 shaped suitably and then can be used as the signal VBP
. fed to the terminal 50 of Figure 4.
The ramp signal fed through the tenminal 24 to :~ the dissolve switcher 20 shown in Figures 1 and 3 is : ; produced by a ramp signal generator 130 shown in Figure ; : 24. The diseolve switcher 20 differentially combines :~ the video signals A and B fed thereto through the terminals 12 and 14" This means that the output level~ of both the ~ video signals thus combined are always constant. The : - 29 - .
- . ...... - ...... .. . . . :. . . . . .................... .
:: . .: . ' . : :
picture appearing when the vldeo signal,s A and B are combined half and half is called a mix ef~ect, while the fade effect is a kind of di~solve effect, in which one of the video signals to be combined is of the black burst form. If the other video signal is gradually emphasized, this effect is called a fade-in, whLle if the black burst signal is empha,sized gradually and finally the screen becomes a blank picture, this effect is called a fade-out. Further, the dis~olve period is especially called the "duration". This dissolve effect is controlled by the ramp signal applied to the kerminal 24.
The ramp signal generator circuit 130 shown in Figure 24 receives the frame pulse at its input terminal 132. The generator circuit 130 includes a phase comparator lS 134, a voltage controlled oscillator (VC0) 136 and a feed-back path 138 which form a PLL (phase locked loop) circuit.
If the frequency of the frame pulse is taken fv, the output frequency of the BLL circuit is applied to a programmable counter 140 having the frequency dividing ratio of l/n, in which the output frequency of the PLL
circuit is frequency-divided by the duration value n to be set. me frequency-divided signal from the counter 140 is fed to a first signal processor 142 which has a start control input terminal 144 and a stop control input terminal 146 and also output lines 150 and 152 connected to up and .
down input terminals of a counter 148 respectively. The : ' .
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- . . :
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output signal from the counter 1~0 is also supplied to the terminal 52 of the speed counter 70 a~ the speed pulse SP. A most significant bit (MSB) outputs o~ the couner 148 is applied through a line 154 to the first signal processor 142. The outputs of the counter 148 are fed to a D-A converter 156 which converts the digital output from the counter 148 into an analogue ramp signal. The analogue ramp sign~l from the converter 156 is fed through a second signal processor or ramp signal generator 158 and an amplifier 160 to an output terminal 162. At this output terminal 162 there appears the ramp signal which is applied to the ramp control signal input terminal 24 shown in Figures 1 and 3.
By use of the ramp signal generator 130, a desired duration from 0 to 255 trames can be set and accordingly it is possible to set the duration from 0 to 8.5 seconds. In the prior art c~rcuit which provides various slopes up to a constant ~mplitude value, a clock of a constant frequency, such as the frame frequency, is fed to an n-bit counter, the counter output is D-A
converted, and the analogue output signal therefrom is amplified by an amplifier whose gain is varied in response to the duration. In order to obtain a linear analogue output signal within a desired range it is necessary to use a counter and a D-A converter, having a relatively large number of bits. Further, in order to provide ramp .
.
. .
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, :. ',', , ", " ' ., ' ~ ~ .
signals with various slopes, it is necessary to control the ampllfication factor of the anlogue amplifier over a relatively wide range. Increasingly steep slopes encounter non-linearity difficulties while the minimum slope is limited by the number of bits of the counter and D/A converter.
The ramp signal generator 130 shown in Figure 24 overcomes the above defects effectively. ~ith this generator 130, the signal synchronized with the vertical synchornizing signal in the video signal i.e. the frame pulse signal fv is converted to a signal wi-th a frequency of 256 fv by the PLL circuit which consists of the phase comparator 134, the voltage controlled oscillator 136 and the feedback path 138. The frequency 256 f~ is divided in ~e progra~nable counter 140 by the desired dissolve duration value n and then the divided frequency signal is counted by the 8-bit counter 148. The time TD in which the 8-bit counter 148 counts up 256 pulses is expressed as follows:
n TD = 256 fv . 256 = f - . n Accordingly, the time TD is in proportion to the set duration value n. The output from the counter 1~8 is conve~ed by the D-A converter 156 tG the corresponding analogue value, and then amplified by the amplifier 760 having a constant amplification factor. m e ramp signal delivered to the output tenninal 162 has the gradient corresponding to the desired~duration value.
: .
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.
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If a relatively long duration is desired by the control of the dissolve and fade, it would be necessary -to increase the number of bits of the counter and D-A
converter. However, the increase in bit ~umber results in increase of cost. To avoid such a defect, the first signal processor 142 is provided. The processor 142 carries out the ordinary operation as long as the duration n satisfies the condition 1 <n <255, while when n > 256, the processor 142 operates to produce a ramp siynal with the same gradient as that in n ~ 255 and temporarily halts its operation at n = 128~ Thereafter, it will start the operation thereof in accordance with a re-start command signal.
Figure 25 is a waveform diagram showing an output ramp signal produced at the output terminal 162 of the ramp signal generator 130 by the above operation. In the graph of Figure 25, the ordinate represents a voltage level in VO and the abscissa represents the time in the frame unit.
In the graph of Figure 25, the solid line curve 164 indicat~
the output ramp signal when the number of bits of the counter and D-A converter are selected to make a~gentle gradient of the ramp signal which is substantially s~raight up to a predetermined value n. Over the value n the output voltage s saturated as indicated at 166. By uslng the first signal process circuit 142, the output ramp signal waveform rises up with the same gradient as thati~of n = 255 from a start - : . . . : -, - . . , : : . .
. . . : . . . .. .
position 168, as indicated at 170. At the time when n =
128, the gradient becomes 0 and hence the output voltage becomes constant, as shown at 172. The output ramp signal waveform starts to rise again at a position 174 in S response to the re,start command signal and then arrives at the predetermined saturation voltage, as indicated at 166. By this system, the duration of the dissolve will be expanded over a wide range using an 8-bit counter 140. It is of course possible for the various examplified values to be changed and also for the frequency of the clock pulse to be selected other than the frame frequency of 30 Hz.
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.
Figure 26 i8 a bLock diagram ~howing a practical embodiment of the first signal processor 142 shown in Figure 24. In Figure 26, the .~tart command signal is fed to a terminal 144 and the stop command si.gnal is fed to a terminal 146, respectivelyn Strictly i.t is incorrect that this latter signal is cal:Led the stop command signal.
As described later, the stop command signal is used for starting the count-down operat:ion of the counter 148 from the saturation level 166 to the zero level 162 in Figure 25.
The frame pulse is applied to a terminal 1~30, the speed pulse from the programmable counter 140 is applied to a terminal 182, and a reset signal is applied to a terminal 184, respectively. The signal processor 142 includes five V flip-flop 186, 188, 190, 192 and 194 and two AND-gates 196 and 198. The output from the A~D-gate 196 is fed through the lead line 150 to the up-count input terminal of the counter 148. and the output from the AND-gate 198 is fed through the lead line 152 to the down-count input terminal of~the counter 1~8. The.128 count is most significant but output from the 8-bit counter 148 is fed f : through the line 154 to the clock input terminal of the flip-flop 194. ~ext, the operation of the circuit shown in Figure 26 wi~l be explained with reference to ~igure 25.
~: ~ow assuming that several parameters, such as duration and start time, are stored~, in a computer (not shown), a start signal having high level "1" is applied to the .input : .
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35 - :
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.. , . . ~
144 at the time preqet by t'he computer. Therefore, the "Q"
output signal of the flip-flop 186 will be obtained at the time when the frame pulse is supplied to the clock terminal CK thereof, and thus the start signal SRT will be synchronous with the frame pulse. Further, the "Q"
output signal from the flip flop 186 i8 applied to t'he D-terminal of the flip-flop 190, in which the former signal is in synchronism with the speed pulse supplied to the clock terminal of the flip-flop 190. The ~ynchronizing "Q" output signal from the flip-flop 190 is further supplied to the AND gate 196, and thereby the gate 196 is opened to supply the speed pulse to the up-terminal of the count~r 1480 When the counter 148 fini3hes counting the 128 speed pulse3, the MSB (most significant bit) output 158 of the 8-bit counter 148 becomes "1". The MSB output 158 is supplied to the clock terminal CK of the flip-flop 194. so that the Q-output thereof generates t'he clear signal "1", because an input signal having high level "1"
~0 from the "128" counts to the restart point is supplied to the D-input terminal 200 under control of the computer.
The clear signal is supplied to the clear terminàl CK
of the'flip-flop 186, so that the Q-output thereof bècomes "0". As a~result of the "0" outputs of the flip-flops 25 186 and 190, the speed pulse SP from the counter 140 is not applied to the counter 148, and hence the output from ,, .~
~: , , .: . .. ..
., - . .. .: , -~, ' ' .,' ' '. , . ' . : : , . , . , ~ ~ ': . .
- , .. . . ..
' ~ ' ' ' the D-A converter 156 keeps cons-tant, as indicated by the broken line 172 of Figure 25.
At the restart point 174 the reset siynal PST from the computer is supplied to the clear terminal CL of the flip-flop 194, so that the Q-output thereof becomes "O".
Accordingly, the Q-output of the flip~flop 186 again becomes "1" at the time when the subsequent frame pulse fv is applied to the clock terminal CK of the flip-flop 186.
The Q-output of the flip-flop 190 also becomes "1" owing to the Q-output "1" of the flip-flop 186. As a result, the speed pulse i9 again applied to the up-terminal of the counter 148 and hence the output from the D/A converter 156 goes up linearly~ Thus, it is apparant that when the counter 148 counts to tis full scale, the output of the D/A converter 156 reaches the saturation level 166.
Then, the counter 148 generates a carry output which is used for resetting the start signal SRT.
On the contrary, when the output signal obtained from the terminal 162 is dissolved from the saturation level to the zero level, the stop command signal is 3upplied to the input terminal 146 and the circuit compri~ing the flip-flops 188 and 192 and the AND gate 198 : opexates in the same manner as the circuit of the flip-flops 186 and 190 and the AMD gate 1960 However, it is noted that the speed pulse from the A~D gate 198 is supplied to the down-terminal of the counter 1480 In this case, : ~ :
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the flip-flop 194 is formed of an integrated circuit of the SN 7474 type, flip-flops 186 and 188 are each formed of an integrated circuit of the 5N 74175 type, and flip-flops 190 and 192 are each formed of the SN 74175 type, similarly.
The counter 148 shown in Figure 24 consists of an octal reversible counter which i~ made by connecting two integrated circuits of SN 74193 type in cascadeO The output terminal of the counter 148 is aonnected to the input terminal of the octal D-A converter 156 whose analogue output is processed by the second signal processor 158 and then delivered through the amplifier 160 to the output terminal 1~2.
If the level of the video signals A and B fed to the dissolve switcher 20 are controlled as shown in Figure 27a by this dissolve switcher 20 and if the dissolve switcher 20 is controlled by a ramp signal with the waveform shown in Figure 27b, the video signals will be switched in a time pexiod T from a time tl when the 2Q dissolve operation starts and to a time t~ when the dissolve operation terminates. Accordingly, in the period ~ the ; signals A and B are mixed with a voltage ratio of the gradient of the ramp signal and the levels of the signals A and B are changed gradually from high to low and from low to high, respectively. However, it is noted that the duration period T gives an impression of a shorter ~' ~. ,.. , . .. .- .
.
.
. . -dissolve than the actual set time duration T. The reason is that a lower portion x of the ramp signal (up to a voltage level vl) and ~n upper portion y of the ramp s.ignal (up to a voltage level v2) are dead zones where no movement i9 sensed by a viewer's eyes. As a re~ult, the time period in which the viewer can perceive the dissolve effect becomes a shorter time period T' as shown in Figure 27b.
The second signal processor 158 i~ provided ko make the set time period T equal to the time perio~ T' in which the viewer recognizes the effect on the screen to improve the property of the dissolve operation. For this purpose the signal processor 158 operates such that the whole amplitude V' of the ramp signal is made V-(Vl+V2) as shown in Figure 28 by a solid line. That is the ramp signal is increased by the voltage level Vl at the start time tl and at the same time t2 the ramp signal is decreased by the voltage level V2 to coincide the time period T w,ith the effective time period T'.
Figure 29 shows a circuit diagram of the second signal processor 158, in which the output from the D/A
~ converter 156 i~ added to an input 202 of operational :~ amplifier 201 consituting the amplifier 160, t~e output : terminal of which is connected with the output 162.
The processor 158 is provided with a first elec-tronic switching device 218 having two switch elements Sl andS2 .
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.
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, v~
which are controlled by output Y0 and Yl from a second switch device 219. The'~ovable arms" of the switch elements Sl and S2 are connected through respective resistors with the input of the amplifier 201, while the "fixed contacts" thereof are connected with D.C. voltage terminals 224 and 220, to which the respective DC voltages corresponding to the voltage levels V1 and V2 are supplied.
The second switching device 219 includes four switch elements T0, Tl, T2 and T3 having a first set of terminals Y0, Yl, Y2 and Y3 and a second set of terminals A0-B0, Al-Bl, A2-B2 and A3-B3, and which is controlled by a control signal from terminal 216. The terminals of the first set are connected with respective ones of the terminals of the second set while the control signal being "1", while the terminals of the first set are connected with respective ones of the terminals of the second set while the control signal being "~".
When the control signal is high ("1") and the start signal is supplied to a start command signal input : 20 terminal 204, the start signal is supplied through the switch element T3 to clock terminal CK of D-type flip-flop 211, and thereby the Q-output of the flip-flop 211 becomes "1" which is further supplied through the switch element T0 to control terminal Cl of the switch element Sl.
Accordingly. the switch Sl becomes 0~ and hence the voltage at the terminal 224 is applied to the input of the amplifier ~ .
' : ..
. . . :
.
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201. As a result, the output voltage at the output 162 rapidly rises up by the voltage Vl. From this condition, the output siynal from the D/A converter 156 will be gradually applied to the input of the amplifier 201, so that the voltage at the output 162 rises linearly as shown in Figure 28.
When the counter 148 counts to its full scale, that is, the output of l:he D/A converter reaches the saturation level at the tirne t2, the counter 1~8 generates the carry signal to supply the latter signal to a terminal 208. The carry signal is further supplied through the switch T2 to clock terminal CK of the flip-flop 213, so that the Q-output of the flip-flop 213 becomes "1" owing to 'high ~evel at the D-terminal thereof. The Q-terminal of the flip-flop 213 is applied through the switch Tl to control terminal C2 of the : switch S2. As a result, the switch S2 becomes ON and ; , hence the voltage at the terminal 220 is applied to the input of the amplifier 201. 'rhen, the output voltage appeared at the output 162 rapidly goes up by the voltage V2 at the time t2, as shown in Figure 28.
: Thus, the dissolve signal shown in Figure 29 is ;~ formed in the circuit 130 and the dissolve operation by the signal is performed in the dissolve switcher 20.
On the ~ontrary, when the dissolve operation shown in the dot-dash line of Figure 28 is desired, the : : - 41 -~:
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control signal from the terminal 216 becomes low. Therefore, the terminals of the switches TO to T3 are switched over the respective terminals AO to A4, so that the Q-outputs of the flip-flop 211 and 213 having high levels at the initial time tl are respectively supplied through the switches TO and Tl to the control terminals Cl and C2 of the switches Sl and S2. As a result, both the switches Sl and S2 become ON and hence both the voltages Vl and V2 from the terminals 220 and 224 are supplied to the input of the amplifier 201.
When the start signal (stop command signal) is applied to terminal 206 at the time tl, the former signal is supplied through the switch T3 to the clock terminal CK of the flip-flop 211 and hence the Q-output thereof becomes "0", which is further supplied through the switch Tl to the control terminal C2 of the switch S2. As a result. the switch S2 becomes OFF and hence the output voltage at the terminal 162 decreases rapidly by the voltage V2 at the time Tl.
Thereafter, the output voltage from the D/A
converter is linearly decreasing until the time t2. When the counter 148 is counted down until 1l0l', it generates a borrow signal which is supplied to a terminal 210.
~he borrow signal is supplied through the switch T2 to the clock terminal CK of the flip-flop 213 and thereby the Q-output of the flip-flop 213 goes down to the low level "O"
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4~v4 which is further supplied through the switch TO to the control terminal Cl of the switch Sl. Consequently, the switch Sl becomes OFF, so that the voltage from the terminal 224 applied to the input of the amplifier 201 is cut-off. Accordingly, the output voltage at the output terminal 162 rapidly decreases by the voltage Vl at the time t2.
Thus aq described above, a ramp signal as sh~wn in Figure 28 is obtained which is controlled in the di~ital manner.
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q~he data output from the speed counter 42 is applied to an exclusive OR-gate 74. Only one OR-gate 74 is shown 15 in Figure 4, but in practice the number of OR-ga-tes 74 corresponds to the bit number of the data outputs ~rom the speed counter 42. A control input terminal 74' is provided for the exclusive OR-gate 74. As well known, when the state of a control input to the control input terminal 20 74' is selectively changed to high or low, the speed counter ~2 can be operated as up-counter or down counter, respectively. For example, it is possible in the wipe mode of the composite television picture con~isting of the picture portions A and B shown in Figure 12 that if the 25 control input to the exclusive OR-gate 74 is changed, a wipe in the direction 76 or 78 (in Figure 12) can be - ... ~ . . , .. ... . . : , ,, , .- . , .,: , ; .,,. ., - -:. :. ,,: ':: ~' . ~ ' ' '. ' ' . : `. , , - ., :
-selectively carried out.
The exclusive OR-gate 62 is provided with a ~ontrol input terminal 62' which is operated similar to the control input terminal 74'~ The exclusive OR-gate 74 controls the whole operating direction of the wipe generator 32, while the exclus.ive OR-gate 62 merely determines the direction of the wipe operation in the horizontal direction. The levels of the control signals fed to the control input terminals 62' and 74' are controlled in response to the w.ipe pattern and key pattern desired.
me wipe (key~ generator 32 shown in Figure 4 is also provided with Y2 counter 40 similar to the Yl counter 38, X2 counter 36 3imilar to the Xl counter 34, exclusive OR-gate 84 similar to the exclusive OR-gate 62, switch 86 similar to the switch 64, D flip-flop 80 similar to D
flip-flop 54 which receives the carry output from the Y2 counter 40, and D flip-flop 82 similar to the D flip-flop 68 which receive the carry output from the X2 counter 36. m e 8-bit data output from the exclusive OR-gate 74 is applied directly to the Yl ~ounter 38 but through an ;: inv~rter-84 to the Y2 counter 40. This inverter 84 is used for complementary oper-ation of the Y2 counter 40 relative to the Yl counter 38. That is, if a co~posite Y switching pulse is formed from the Yl and Y2 switching pulses, there is produced a picture in which the upper and lower picture portions ~ are wiped over the picture portion , : . ' ~ : .
.. ~ ~ , . .
. .
A therebetween as shown in Figure 13a, or a ~icture in which the picture portion B between the upper ar.d lower picture portions A is wiped over the picture portions A as shown in Figure 13b. Similarly, if the movable contacts of switches 64 and 86 are connected to their fixed contacts 1, respectively, and the leve~sof the control inputs to the exclusive OR-gates 62 and 84 are different to each other ~a) composite X switching pulse of the Xl and X2 switching pulses produces a picture in which the left and right picture portions B are wiped to the picture portion A therebetween as shown in Figure 14a, or in which the picture portion B
between the left and right picture portions A is wiped over both the picture portions A as shown in Figu.re 14b. ~ext, if the movable contacts of switches 64 and 86 are lS connected to their fixed contacts 2, respectively, and ~e composite switching pulses are produced from the Xl, Yl -switching pulses and X2, Y2 switching pulses, pictures can be obtained in which the picture portions A and B are wiped as shown in Figures 15a, 15b, 15c and 15d, respectively.
In addition to the foregoing, if the conditions of the control inputs to the exclusive OR-gates 62, 74 and 84 are selectably changed, the switches 64 and 86 are controlled and the combination of Xl, X2, Yl and Y2 switching pulses lS selected in various ~anners, various wipe effects shown in Figure 15' can be obtained on the :~ ~ screen.
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... : . . : ' In F'igure 4, as described previously, there is provided a latch circuit 66 which receives at its data input terminal the 8 bit output data from the speed counter 42 through the exclusive OR-gates 74. This latch circuit 66 has a clock input terminal which receives the vertical blanking pulse VBP fed to the terminal 50, and a data output terminal from which the 8 bit data output is fed to the data input terminals of the Xl counter 34 and X2 counter 36 through the fixed contacts l of switches 64 and 86 and the exclusive OR-gates 62 and 84, respectively. The Xl and X2 counters 34 and 36 are loaded with the input data at every load pulse fy' having the.horizontal synchronizing frequency. If the latch circuit 66 is omitted, the Xl and X2 counters 34 and 36 are loaded with the data output from the speed counter 42 as it is.
m is means that the data of speed counter 42 may be renewed in the picture being reproduced in the television screen that is, during certain horizontal intervals other than t~e vertical blanking period. For this reason, the boundary between the two picture portions A and B does not become a straight line and the boundary line is terraced,~as shown in Figure 16a. In order to avoid the above : . disturbance on the screen, the output data from speed counter 42 is latched by the pulse VBP having the vertical synchroniz.ing frequency and held during one field period.
.
~ e held data in the altch circuit 66 is used as the preset ~;
:
-, data for -the Xl and X2 counters 34 and 36, so that the effect o:E the steps shown in Figure 16a diqappears and hence the boundary line between the picture portions A and B becomes straight, as shown in Figure 16b. In Figure 16, a numeral 90 designates the boundary line at the first ~ield and 92 designates the boundary line at the subsequent field, respectively. As the wipe speed becomes ~aster the distance between the boundary lines 90 and 92 becomes wider.
As to the Yl and Y2 counters 38 and 40, they are loaded with the output data from the speed counter 42 by the vertical synchronizing blanking pulse VBP, so that there is no need to provide such a latch circuit for the Yl and Y2 counters 38 and 40.
The control circuit 56 shown in Figure 4 is supplied with the Xl switching pulse from the flip flop 68, the Yl switching pulse from the flip-flop 54, the X2 switching pulse from the flip-flop 82., and the Y2 switching pulse from the flip-flop 80. This control circuit 56 is made of the combination of various gates and produces various types~of composite switching pulses in response to a control logic signal Sc applied thereto.
The soft edge circuit 58 shown in Figure 4 receives the composite switching pulse from the control : circuit 56 has a sharp rising adge as shown in Figure 17a, ~: 25 so that the border line between the picture portions A and B
is rapidly changed, as shown in Figure 17b. On the ,:
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contrary, if the compo~ite switchlncl pulse i~ formed wi-th a slope in a certain period on the border line as shown in Figure 17c, the signals correspondiny to the picture portion~
A and B are mixed with each other in that period. Accordingly, the boundary between the picture portions A and B becomes soft in view of visual sense a~ good for the viewer, as shown in Figure 17d. In order to obtain the soft edge effect on the border line, the ~ignals of -the picture portions A and B are multiplied in analogue manner in the well-known circuit. Therefore, the construction of the conventional circuit becomes complicated and hence expensive. In oxder to practice the same effect, there is provided with the soft edge circuit 58 which processes the composite switching signal from the control circuit 56 in digital manner. As shown in Figure 18b, the circuit 58 generates a series of switching pulses for the boundary area A + B of the picture portions A and B shown in Figure 18a. It should he noted that the mark to space ratio of the pulses in Figure 18c increases continuously. The mark to space ratio or duty cycle is low at the boundary portion A + B near the picture portion A but becomes high near the picture portion B. Accordingly, due to the visual integrating effect on the screen such a picture with a soft edge effect similar to that by the analogue method. Since the soft edge effect can be performed by the digital processing of the switching signal, the linearity on the boundary portion A ~ B is improved.
.
- . - : , ' .' . ':.' ~ , . , ' :: ' :
In addition to the above soft edge effect in the vertical direction, it is possible that the soft edge effect in the horizontal direction is achieved by the manner similar to the above.
Figure l9a shows a screen in which the boundary portion A + B between the upper and lower picture porkions A and B is subjected to the so~t edging. In this case, the boundary portion A ~ ~ includes n~I lines. A line near the upper picture portion A is switched by the pulse whose duty cycle is low as shown in Figure l9b and the last line of n lines is switched by the pulse whose duty cycle is highest, as shown in Figure l9c. Thu9, the boundary portion A ~ B, which is soft-edged by changing the distxibution of the signals corresponding to the picture portions A and B at each line in time, can be obtained on the screen.
Figure 20 is a block diagram showing an embodiment of the soft edge circuit 58. The soft edge circuit 58 shown in Figure 20 consists of two 4-bit counters 100 and 1 --102 and an inverter 104. An integrated circuit type SN 74161 made by Texas Instruments Inc. can be used for each of the above counters. A clock signal fc applied to an input terminal 106 is fed to the first counter 100 at its clock ; input terminal. If no clear input signal is applied to the ::
~ counter 100 at its clear input terminal, because of switch : :
108 belng OFF, the counter 100 produces the carry output signal when it counts up the 15th clock pulse. The carry , , ,.
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f~
output signal is lnverted by an inverter 104 and then fed to the second counter 102 at its clock input termi.nal and also to the first counter 100 at its load inpu.t terminal. When the load input becomes low by the above load input, A, B, C and D i~puts of the first counter 100 P Y QA' QB' QC and QD outputs from the second counter 102. Upon the arrival of the first carry pulse, the second counter 102 produces the output of "0" and hence the first counter 100 is preset by this output "0".
Next, the first counter 100 is preset by the value "1" at the next carry output. In this manner, the first counter 100 is preset u~ to "15". As a result, at an output terminal 110, which is connected with the carry output terminal of the first counter 100, there is obtained a sub-pulse signal fOUT having a changing period which becomes narrower at the occurrence of each pulse of the clock signal fc. The composite switching signal with the soft edge effect will be obtained by suitably gating the composite switching signal from the circuit 56 with the pulse signal fOUT
Figure 30 shows a complete circuit diagram of the soft edge effect generator, the upper portion of which : corresponds to the circuit of Figure 20 that generates a series of pulses having different mark to space ratios at each cycle~ as described above. The series of pulses from :~ the terminal 110 are supplied to the lower portion of the .
. . :,, . , , . .: . ,, : :
.:: ' .. :: . ' ' . . : :
,:: - , circuit which is mainly composed of a counter 101 and a set of gate circuits. The switching signal from the gate circuit 56 (Figure 4) is supplied to the counter 101 which produces the switching signc~l A in itself and another switching signal B delayed by a predetermined time corresponding to the width of the soft edge region. The switching signals A and B are processed in the gate circuits in the manner shown in Figure 31. The signal F
thus obtained in the circuits is suppl.~ed -to the clear-terminals CL of the counters 100 and 102 to enable the counters while the signal F is high. Therefore, during the intervals, there will be obtained a series of pulses gradually reducing in mark to space ratio from the terminal 110, The series of pulses are supplied to exclusive OR
circuit 103 together with the signal C shown in Figure 31 C
so that the signal G shown in Figure 31 G, is generated from the circuit 103. The signal G is further supplied to a ~OR circuit 105 together with the signal D shown in Figure 31, so that the circuit 105 produces the signal H shown in Figure 31 H which should be supplied to the output 60. Asapparent from Figure 31 H, the signal H has an increasing duty cycle during a front soft edge region Tl and a .
decreasing duty cycle during a back soft edge region T2.
The signal H thus obtained is supplied to the wipe switcher 18 (Figure 30j and hence the video signals respectively suppliéd to the inputs 12 and 14 are finely switched in the ' ' .
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swltcher 18 during the regions ln response to the signal H.
The switched video signals are supplied to the television monitor to produce the image picture on the screen and the finely switched areas o:E the picture are softly edged owing to the integrating ef:Eect of human eyes.
Further, it is noted that when the switching signal to the counter 101 iS the horizontal switching signal from the X-counter, the clock signal fc has a relatively high frequency, for example 50 MHZ and the counters lOl and 102 are constituted by the ~-bit counter.
However, in case of the vertical switching signal from the Y-counter, the clock signal fc has a horizontal synchronizing frequency and the counters 101 and 102 are constituted by the 2-bit counter.
As described above, the elements which form the wipe generator 32 shown in Figure 4 are all digital elements. Therefore, it is desired that the circuit which generates the above signals fy and fy' and VBP from the vertical and horizontal synchronizing signals separated from the composite video signal is also constituted by a digital circuit. Conventionally, in order that the : vertical synchronizing signal is derived from the composite ~ ~ synchronizing signal, an anak~ecircuit is employed in which .
::~ an integrating circuit is used. In the system described below, the vertical synchronizing signal is extracted in digital manner by counting out the 3.58 MHz subcarrierO
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A~ shown in Figure 21, the waveform of the composite synchronizing signals of the video signal comprises the f horizontal ~ynchronizing ~ignal having a pulse width of about 4 ~ ~econds and the vertical qynchronizing signal having a pul~e width of about 30 qeconds. Figure 22 i3 a block diagram showing a circuit which will produce a pulse representing the vertical synchroni~ation by u~ing the above difference between the pul~e widths of the horizontaL and vertical ~ynchronizing pul~e~. The vertical synchroniziny separating circuit ~hown in Figure 22 consi~t~ o~ two 4-bit counters 112 and 11~ which are connected in a look-ahead connection manner to form an 8-bit counter~ A Texas In~trument Inc. S~ 74161 integrated circuit can be employed as the counters 112 and 114. The clock input- terminals of the first and second counters 112 and 114 are connected to a terminal 116 to receive the subcarrier ~ignal of 3.58 M~z fed thereto, and the clear input tenminals of the ~irst and second counter~ L12 and 114 and the count enable input tenminals P and T of the fir~t counter 112 are connected to a terminal 118 through - -an inverter 120 to receive the composite synchronizing signal which i5 lnverted by the inverter 120. The carry output terminal of the first counter 112 is connected to ~:~ - the count enable lnput terminal P and,T of the second counter 114, and a Q7-output terminal of the second counter ~:
114 i3 co~mected to an output terminal 122 i.e. the 7-bit .:
.,~ -' : . . :, i output signal of the 8~bit counter :is delivered to the output terminal 122.
According to -the circuit described just above, the 8-bit counter counts abc~ut 15 pulses of the clock signal having frequency 3.58 MHz during the horizontal synchronizing pulse period, while the counter counts more than 100 pulses during the :Low level period in the vertical synchronizing pulse period. Accordingly, the vertical synchronizing pulse can be distinguished by detecting the output of the 7th bit of the counter s.ince the count value 15 is indicated by (1111) in binary number and the count value 100 is indicated by (1100010) in binary number.
Figure 23a is a waveform diagram showing the composite synchronizing signal and Figure 23b is a waveform diagram showing a waveform which is derived from the 7th bit output terminal of the counter. The pulse thus produced i9 shaped suitably and then can be used as the signal VBP
. fed to the terminal 50 of Figure 4.
The ramp signal fed through the tenminal 24 to :~ the dissolve switcher 20 shown in Figures 1 and 3 is : ; produced by a ramp signal generator 130 shown in Figure ; : 24. The diseolve switcher 20 differentially combines :~ the video signals A and B fed thereto through the terminals 12 and 14" This means that the output level~ of both the ~ video signals thus combined are always constant. The : - 29 - .
- . ...... - ...... .. . . . :. . . . . .................... .
:: . .: . ' . : :
picture appearing when the vldeo signal,s A and B are combined half and half is called a mix ef~ect, while the fade effect is a kind of di~solve effect, in which one of the video signals to be combined is of the black burst form. If the other video signal is gradually emphasized, this effect is called a fade-in, whLle if the black burst signal is empha,sized gradually and finally the screen becomes a blank picture, this effect is called a fade-out. Further, the dis~olve period is especially called the "duration". This dissolve effect is controlled by the ramp signal applied to the kerminal 24.
The ramp signal generator circuit 130 shown in Figure 24 receives the frame pulse at its input terminal 132. The generator circuit 130 includes a phase comparator lS 134, a voltage controlled oscillator (VC0) 136 and a feed-back path 138 which form a PLL (phase locked loop) circuit.
If the frequency of the frame pulse is taken fv, the output frequency of the BLL circuit is applied to a programmable counter 140 having the frequency dividing ratio of l/n, in which the output frequency of the PLL
circuit is frequency-divided by the duration value n to be set. me frequency-divided signal from the counter 140 is fed to a first signal processor 142 which has a start control input terminal 144 and a stop control input terminal 146 and also output lines 150 and 152 connected to up and .
down input terminals of a counter 148 respectively. The : ' .
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output signal from the counter 1~0 is also supplied to the terminal 52 of the speed counter 70 a~ the speed pulse SP. A most significant bit (MSB) outputs o~ the couner 148 is applied through a line 154 to the first signal processor 142. The outputs of the counter 148 are fed to a D-A converter 156 which converts the digital output from the counter 148 into an analogue ramp signal. The analogue ramp sign~l from the converter 156 is fed through a second signal processor or ramp signal generator 158 and an amplifier 160 to an output terminal 162. At this output terminal 162 there appears the ramp signal which is applied to the ramp control signal input terminal 24 shown in Figures 1 and 3.
By use of the ramp signal generator 130, a desired duration from 0 to 255 trames can be set and accordingly it is possible to set the duration from 0 to 8.5 seconds. In the prior art c~rcuit which provides various slopes up to a constant ~mplitude value, a clock of a constant frequency, such as the frame frequency, is fed to an n-bit counter, the counter output is D-A
converted, and the analogue output signal therefrom is amplified by an amplifier whose gain is varied in response to the duration. In order to obtain a linear analogue output signal within a desired range it is necessary to use a counter and a D-A converter, having a relatively large number of bits. Further, in order to provide ramp .
.
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signals with various slopes, it is necessary to control the ampllfication factor of the anlogue amplifier over a relatively wide range. Increasingly steep slopes encounter non-linearity difficulties while the minimum slope is limited by the number of bits of the counter and D/A converter.
The ramp signal generator 130 shown in Figure 24 overcomes the above defects effectively. ~ith this generator 130, the signal synchronized with the vertical synchornizing signal in the video signal i.e. the frame pulse signal fv is converted to a signal wi-th a frequency of 256 fv by the PLL circuit which consists of the phase comparator 134, the voltage controlled oscillator 136 and the feedback path 138. The frequency 256 f~ is divided in ~e progra~nable counter 140 by the desired dissolve duration value n and then the divided frequency signal is counted by the 8-bit counter 148. The time TD in which the 8-bit counter 148 counts up 256 pulses is expressed as follows:
n TD = 256 fv . 256 = f - . n Accordingly, the time TD is in proportion to the set duration value n. The output from the counter 1~8 is conve~ed by the D-A converter 156 tG the corresponding analogue value, and then amplified by the amplifier 760 having a constant amplification factor. m e ramp signal delivered to the output tenninal 162 has the gradient corresponding to the desired~duration value.
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If a relatively long duration is desired by the control of the dissolve and fade, it would be necessary -to increase the number of bits of the counter and D-A
converter. However, the increase in bit ~umber results in increase of cost. To avoid such a defect, the first signal processor 142 is provided. The processor 142 carries out the ordinary operation as long as the duration n satisfies the condition 1 <n <255, while when n > 256, the processor 142 operates to produce a ramp siynal with the same gradient as that in n ~ 255 and temporarily halts its operation at n = 128~ Thereafter, it will start the operation thereof in accordance with a re-start command signal.
Figure 25 is a waveform diagram showing an output ramp signal produced at the output terminal 162 of the ramp signal generator 130 by the above operation. In the graph of Figure 25, the ordinate represents a voltage level in VO and the abscissa represents the time in the frame unit.
In the graph of Figure 25, the solid line curve 164 indicat~
the output ramp signal when the number of bits of the counter and D-A converter are selected to make a~gentle gradient of the ramp signal which is substantially s~raight up to a predetermined value n. Over the value n the output voltage s saturated as indicated at 166. By uslng the first signal process circuit 142, the output ramp signal waveform rises up with the same gradient as thati~of n = 255 from a start - : . . . : -, - . . , : : . .
. . . : . . . .. .
position 168, as indicated at 170. At the time when n =
128, the gradient becomes 0 and hence the output voltage becomes constant, as shown at 172. The output ramp signal waveform starts to rise again at a position 174 in S response to the re,start command signal and then arrives at the predetermined saturation voltage, as indicated at 166. By this system, the duration of the dissolve will be expanded over a wide range using an 8-bit counter 140. It is of course possible for the various examplified values to be changed and also for the frequency of the clock pulse to be selected other than the frame frequency of 30 Hz.
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Figure 26 i8 a bLock diagram ~howing a practical embodiment of the first signal processor 142 shown in Figure 24. In Figure 26, the .~tart command signal is fed to a terminal 144 and the stop command si.gnal is fed to a terminal 146, respectivelyn Strictly i.t is incorrect that this latter signal is cal:Led the stop command signal.
As described later, the stop command signal is used for starting the count-down operat:ion of the counter 148 from the saturation level 166 to the zero level 162 in Figure 25.
The frame pulse is applied to a terminal 1~30, the speed pulse from the programmable counter 140 is applied to a terminal 182, and a reset signal is applied to a terminal 184, respectively. The signal processor 142 includes five V flip-flop 186, 188, 190, 192 and 194 and two AND-gates 196 and 198. The output from the A~D-gate 196 is fed through the lead line 150 to the up-count input terminal of the counter 148. and the output from the AND-gate 198 is fed through the lead line 152 to the down-count input terminal of~the counter 1~8. The.128 count is most significant but output from the 8-bit counter 148 is fed f : through the line 154 to the clock input terminal of the flip-flop 194. ~ext, the operation of the circuit shown in Figure 26 wi~l be explained with reference to ~igure 25.
~: ~ow assuming that several parameters, such as duration and start time, are stored~, in a computer (not shown), a start signal having high level "1" is applied to the .input : .
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144 at the time preqet by t'he computer. Therefore, the "Q"
output signal of the flip-flop 186 will be obtained at the time when the frame pulse is supplied to the clock terminal CK thereof, and thus the start signal SRT will be synchronous with the frame pulse. Further, the "Q"
output signal from the flip flop 186 i8 applied to t'he D-terminal of the flip-flop 190, in which the former signal is in synchronism with the speed pulse supplied to the clock terminal of the flip-flop 190. The ~ynchronizing "Q" output signal from the flip-flop 190 is further supplied to the AND gate 196, and thereby the gate 196 is opened to supply the speed pulse to the up-terminal of the count~r 1480 When the counter 148 fini3hes counting the 128 speed pulse3, the MSB (most significant bit) output 158 of the 8-bit counter 148 becomes "1". The MSB output 158 is supplied to the clock terminal CK of the flip-flop 194. so that the Q-output thereof generates t'he clear signal "1", because an input signal having high level "1"
~0 from the "128" counts to the restart point is supplied to the D-input terminal 200 under control of the computer.
The clear signal is supplied to the clear terminàl CK
of the'flip-flop 186, so that the Q-output thereof bècomes "0". As a~result of the "0" outputs of the flip-flops 25 186 and 190, the speed pulse SP from the counter 140 is not applied to the counter 148, and hence the output from ,, .~
~: , , .: . .. ..
., - . .. .: , -~, ' ' .,' ' '. , . ' . : : , . , . , ~ ~ ': . .
- , .. . . ..
' ~ ' ' ' the D-A converter 156 keeps cons-tant, as indicated by the broken line 172 of Figure 25.
At the restart point 174 the reset siynal PST from the computer is supplied to the clear terminal CL of the flip-flop 194, so that the Q-output thereof becomes "O".
Accordingly, the Q-output of the flip~flop 186 again becomes "1" at the time when the subsequent frame pulse fv is applied to the clock terminal CK of the flip-flop 186.
The Q-output of the flip-flop 190 also becomes "1" owing to the Q-output "1" of the flip-flop 186. As a result, the speed pulse i9 again applied to the up-terminal of the counter 148 and hence the output from the D/A converter 156 goes up linearly~ Thus, it is apparant that when the counter 148 counts to tis full scale, the output of the D/A converter 156 reaches the saturation level 166.
Then, the counter 148 generates a carry output which is used for resetting the start signal SRT.
On the contrary, when the output signal obtained from the terminal 162 is dissolved from the saturation level to the zero level, the stop command signal is 3upplied to the input terminal 146 and the circuit compri~ing the flip-flops 188 and 192 and the AND gate 198 : opexates in the same manner as the circuit of the flip-flops 186 and 190 and the AMD gate 1960 However, it is noted that the speed pulse from the A~D gate 198 is supplied to the down-terminal of the counter 1480 In this case, : ~ :
::
,, - , , . . , , :.: . - " .:
, , . :: ,: . -. , : ., : , .
.. - : - . - . .. .
,, . . - . : . . .. . ....
, .. . . . . . .
the flip-flop 194 is formed of an integrated circuit of the SN 7474 type, flip-flops 186 and 188 are each formed of an integrated circuit of the 5N 74175 type, and flip-flops 190 and 192 are each formed of the SN 74175 type, similarly.
The counter 148 shown in Figure 24 consists of an octal reversible counter which i~ made by connecting two integrated circuits of SN 74193 type in cascadeO The output terminal of the counter 148 is aonnected to the input terminal of the octal D-A converter 156 whose analogue output is processed by the second signal processor 158 and then delivered through the amplifier 160 to the output terminal 1~2.
If the level of the video signals A and B fed to the dissolve switcher 20 are controlled as shown in Figure 27a by this dissolve switcher 20 and if the dissolve switcher 20 is controlled by a ramp signal with the waveform shown in Figure 27b, the video signals will be switched in a time pexiod T from a time tl when the 2Q dissolve operation starts and to a time t~ when the dissolve operation terminates. Accordingly, in the period ~ the ; signals A and B are mixed with a voltage ratio of the gradient of the ramp signal and the levels of the signals A and B are changed gradually from high to low and from low to high, respectively. However, it is noted that the duration period T gives an impression of a shorter ~' ~. ,.. , . .. .- .
.
.
. . -dissolve than the actual set time duration T. The reason is that a lower portion x of the ramp signal (up to a voltage level vl) and ~n upper portion y of the ramp s.ignal (up to a voltage level v2) are dead zones where no movement i9 sensed by a viewer's eyes. As a re~ult, the time period in which the viewer can perceive the dissolve effect becomes a shorter time period T' as shown in Figure 27b.
The second signal processor 158 i~ provided ko make the set time period T equal to the time perio~ T' in which the viewer recognizes the effect on the screen to improve the property of the dissolve operation. For this purpose the signal processor 158 operates such that the whole amplitude V' of the ramp signal is made V-(Vl+V2) as shown in Figure 28 by a solid line. That is the ramp signal is increased by the voltage level Vl at the start time tl and at the same time t2 the ramp signal is decreased by the voltage level V2 to coincide the time period T w,ith the effective time period T'.
Figure 29 shows a circuit diagram of the second signal processor 158, in which the output from the D/A
~ converter 156 i~ added to an input 202 of operational :~ amplifier 201 consituting the amplifier 160, t~e output : terminal of which is connected with the output 162.
The processor 158 is provided with a first elec-tronic switching device 218 having two switch elements Sl andS2 .
. . . .
.
':~ '...... , ' ~
, v~
which are controlled by output Y0 and Yl from a second switch device 219. The'~ovable arms" of the switch elements Sl and S2 are connected through respective resistors with the input of the amplifier 201, while the "fixed contacts" thereof are connected with D.C. voltage terminals 224 and 220, to which the respective DC voltages corresponding to the voltage levels V1 and V2 are supplied.
The second switching device 219 includes four switch elements T0, Tl, T2 and T3 having a first set of terminals Y0, Yl, Y2 and Y3 and a second set of terminals A0-B0, Al-Bl, A2-B2 and A3-B3, and which is controlled by a control signal from terminal 216. The terminals of the first set are connected with respective ones of the terminals of the second set while the control signal being "1", while the terminals of the first set are connected with respective ones of the terminals of the second set while the control signal being "~".
When the control signal is high ("1") and the start signal is supplied to a start command signal input : 20 terminal 204, the start signal is supplied through the switch element T3 to clock terminal CK of D-type flip-flop 211, and thereby the Q-output of the flip-flop 211 becomes "1" which is further supplied through the switch element T0 to control terminal Cl of the switch element Sl.
Accordingly. the switch Sl becomes 0~ and hence the voltage at the terminal 224 is applied to the input of the amplifier ~ .
' : ..
. . . :
.
: - ~ . .
201. As a result, the output voltage at the output 162 rapidly rises up by the voltage Vl. From this condition, the output siynal from the D/A converter 156 will be gradually applied to the input of the amplifier 201, so that the voltage at the output 162 rises linearly as shown in Figure 28.
When the counter 148 counts to its full scale, that is, the output of l:he D/A converter reaches the saturation level at the tirne t2, the counter 1~8 generates the carry signal to supply the latter signal to a terminal 208. The carry signal is further supplied through the switch T2 to clock terminal CK of the flip-flop 213, so that the Q-output of the flip-flop 213 becomes "1" owing to 'high ~evel at the D-terminal thereof. The Q-terminal of the flip-flop 213 is applied through the switch Tl to control terminal C2 of the : switch S2. As a result, the switch S2 becomes ON and ; , hence the voltage at the terminal 220 is applied to the input of the amplifier 201. 'rhen, the output voltage appeared at the output 162 rapidly goes up by the voltage V2 at the time t2, as shown in Figure 28.
: Thus, the dissolve signal shown in Figure 29 is ;~ formed in the circuit 130 and the dissolve operation by the signal is performed in the dissolve switcher 20.
On the ~ontrary, when the dissolve operation shown in the dot-dash line of Figure 28 is desired, the : : - 41 -~:
,~ .
~ ~ ' : - - .. - . . : ' . . :. . .. . ': : .: . ' ... .. . .
control signal from the terminal 216 becomes low. Therefore, the terminals of the switches TO to T3 are switched over the respective terminals AO to A4, so that the Q-outputs of the flip-flop 211 and 213 having high levels at the initial time tl are respectively supplied through the switches TO and Tl to the control terminals Cl and C2 of the switches Sl and S2. As a result, both the switches Sl and S2 become ON and hence both the voltages Vl and V2 from the terminals 220 and 224 are supplied to the input of the amplifier 201.
When the start signal (stop command signal) is applied to terminal 206 at the time tl, the former signal is supplied through the switch T3 to the clock terminal CK of the flip-flop 211 and hence the Q-output thereof becomes "0", which is further supplied through the switch Tl to the control terminal C2 of the switch S2. As a result. the switch S2 becomes OFF and hence the output voltage at the terminal 162 decreases rapidly by the voltage V2 at the time Tl.
Thereafter, the output voltage from the D/A
converter is linearly decreasing until the time t2. When the counter 148 is counted down until 1l0l', it generates a borrow signal which is supplied to a terminal 210.
~he borrow signal is supplied through the switch T2 to the clock terminal CK of the flip-flop 213 and thereby the Q-output of the flip-flop 213 goes down to the low level "O"
- ~2 -.
, - - , . , - ., .,~,, ~', , :' .- ~ ', ,:' . .
~ .. ~' ', ~ ' . ' . .
: . . , . .
4~v4 which is further supplied through the switch TO to the control terminal Cl of the switch Sl. Consequently, the switch Sl becomes OFF, so that the voltage from the terminal 224 applied to the input of the amplifier 201 is cut-off. Accordingly, the output voltage at the output terminal 162 rapidly decreases by the voltage Vl at the time t2.
Thus aq described above, a ramp signal as sh~wn in Figure 28 is obtained which is controlled in the di~ital manner.
:
:
, . .
, -:
, .. .. .,. . . .: : , .-.. .,. .. ,. . ,.. : .
; .:. :.,,:-. . .. - , . . . . : .. : .,,. .. .. . :.. ,.,. .", ., . , . : .. : . . . .. .
.. . ,, ,... : , . . ..... .~ .. . .. .. ,. ... .. ,.,, ,., - . . ... . . .. . ..
.'''" ' ' .'' ' "'''" ', ', ' ' " ' '' '' " "' ''. ' .' ,'',''' '''' '' ',".' "' '., ',, ,. '', ' ' ''' ' ' ." '' ' ','', ', ',', . '',',' ' '` ' . :' ,' ' "' ' . '' '., '' . ', ' ' " ,: ' , ' ' ' ' ' ' '' ' ' " ' ' ', , ' ' , ' ,' :' ~ ' . -. '.' ' ''.'' . . .' ' ' " ,'' :' ,' ' ' ', ' , . ' .: . . ' . . ' . . , ' , . . .
Claims (26)
1. A video special effects generator having switcher means to which a plurality of video signals are supplied and generator means for generating control signals, said control signals combining portions of said video signals into a single picture by controlling said switcher means, said generator means comprising: a counter, loading means for loading a variable preset count into said counter, means for supplying N clock pulses to said counter within a period of predetermined duration, and latch means set at a time determined by when an output of said counter indicates that said counter has attained a predetermined count value and reset at the end of said period for generating said control signals.
2. A video special effects generator according to claim 1, further comprising means connected with said loading means for progressively changing said preset count between successive periods.
3. A video special effects generator according to claim 2, in which said preset count changing means includes second counter means connected with said loading means, programmable means for generating a second clock signal having a controllable frequency, said second counter means counting said second clock signal and said second counter means being operative to progressively change said preset count by an amount proportional to the said controllable frequency.
4. A video special effects generator having switcher means to which a plurality of video signals are supplied for combining portions of said video signals into a single picture, and control signal generating means for generating control signals which control said switcher means, said control signal generating means comprising: first counter means for counting a first clock pulse train having a frequency such that at least N first clock pulse occur within one vertical period of the video signal, first loading means for loading a first preset count to said first counter means at the occurrence of at least one vertical synchronizing period, first latch means set by an output generated when said first counter means counts N pulses of said first clock pulse train and reset by a vertical synchronizing signal for generating a first control signal, second counter means for counting a second clock pulse train having a frequency such that at least a predetermined number, M, of pulses occur within one horizontal period, second loading means for loading a second preset count to said second counter means during at least one horizontal synchronizing period, a second latch means set when said second counter means counts M pulses of said second clock pulse and reset by a horizontal synchronizing signal for generating a second control signal, and means for com-bining said first and second control signals to produce a composite control signal by which the switcher means is controlled.
5. A video special effects generator according to claim 4, further comprising a third counter means in said control signal generating means for varying said first and second preset counts supplied to said first and second counter means, said third counter means being arranged to count a train of third clock pulses.
6. A video special effects generator according to claim 5, wherein said first and second preset counts are loaded during the occurrence of vertical synchronizing signals.
7. A video special effects generator according to claim 5, further comprising means for selectively invert-ing the input count of said third counter means, whereby up-counting of outputs of said third counter means is effective-ly converted to down-counting thereof.
8. A generator according to claim 5, further comprising means for latching the output count of said third counter means supplied to said second loading means during at least one vertical period.
9. A generator according to claim 5, further compris-ing means for supplying the output count of said first counter means to said second loading means.
10. A generator according to claim 9, in which said supplying means includes a switch for selectively supplying the output count of the first or third counter means to said second loading means.
11. A generator according to claim 9, and including means for selectively inverting data loaded into the first counter means.
12. A video special effects generator according to claim 5, in which said first counter means includes first and second counters, said second counter means includes third and fourth counters, said first latch means includes first and second flip-flops set respectively by the outputs of said first and second counters, said second latch means includes third and fourth flip-flops set respectively by the outputs of said third and fourth counters, said first and second loading means are operative to load said third counter from said first counter and said fourth counter from said second counter, and are arranged as two parallel circuit arrangements, said third counter means is common to said two circuit arrangements.
13. A video special effects generator according to claim 12, wherein data from said third counter means is inverted for delivery to said second counter and uninverted for delivery to said first counter.
14. A video special effects generator comprising:
switcher means having a plurality of video inputs and a single video output for switching one of said plurality of input video signals onto said single video output while a control signal is produced, and control singal generating means having first counter means for counting N clock pulses within a period related to a video signal loading means for loading a preset number into said first counter means before said period, means for varying said preset number, said counter means being operative to generate an output signal when the sum of said preset number and the counted clock pulses equals N, and means responsive to said output signal for producing said control signal at a time determined by when said output signal is generated,
switcher means having a plurality of video inputs and a single video output for switching one of said plurality of input video signals onto said single video output while a control signal is produced, and control singal generating means having first counter means for counting N clock pulses within a period related to a video signal loading means for loading a preset number into said first counter means before said period, means for varying said preset number, said counter means being operative to generate an output signal when the sum of said preset number and the counted clock pulses equals N, and means responsive to said output signal for producing said control signal at a time determined by when said output signal is generated,
15. The video special effects generator according to claim 14, wherein said period is a horizontal line period.
16. The video special effects generator according to claim 14, wherein said period is a frame period.
17. The video special effects generator according to claim 14, wherein said period is a field period.
18. The video special effects generator according to claim 14, wherein said loading means includes second counter means.
19. The video special effects generator according to claim 18, further comprising a programmable means for gen-erating a variable clock signal having a programmable frequency and which is applied to said second counter means, said second counter means being operative to change the number stored in said first counter means before said period in response to the frequency of said variable clock signal.
20. The video special effects generator according to claim 14, further comprising second counter means for counting M second clock pulses within a different period related to a video signal, second loading means for loading a second preset number into said second counter means before said different period, said second counter means being operative to generate a second output signal when the sum of said second preset number and said second clock pulses equal M, and other means responsive to said second output signal for producing said control signal.
21. The video special effects generator according to claim 20, wherein said period is a video field and said different period is a horizontal line.
22. The video special effects generator according to claim 20, further comprising variable frequency means for generating a variable clock signal frequency, third counter means for counting said variable clock signal frequency for a fixed time period and for thereafter storing the variable number counted, and means for loading a number related to the variable number stored in said third counter means into said first and second counter means, said related number being the first mentioned preset number and said second preset number.
23. The video special effects generator according to claim 20, in which said first counter means includes first and second counters, said second counter means includes third and fourth counters, said first counter is operative to switch from a first video input to a second video input and said second counter is operative to switch from said second video input to said first video input within one horizontal line, and said second counter is operative to switch from one of said first and second video inputs to the other thereof and said fourth counter is operative to switch from said other to said one video input within one field.
24. A video special effects generator comprising: a wipe and key switcher having first and second video inputs and one video output, said wipe and key switcher being operative in response to a control signal to switch the signal connected to said video output between said first and second video inputs, a control signal generator for generating said control signal, said control signal generator having first and second 8-bit X counters, means synchronized with a video synchronizing pulse for loading first and second preset numbers between 0 and 255 into said first and second 8-bit X counters, means for generating a first clock frequency of 4.773 MHz, means for permitting counting of said first clock frequency in said first and second 8-bit X counters between horizontal synchronizing pulses, first and second latch flip-flops which are set by carry bits from said first and second 8-bit X counters respectively and are reset by said horizontal synchronizing pulses, said first latch flip-flop having a set output for generating said control signal and said second flip-flop having a set output for terminating said control signal, first and second 8-bit Y counters, means synchronized with a vertical synchronizing pulse for loading third and fourth preset numbers between 0 and 255 into said first and second 8-bit Y counters, means for permitting said first and second 8-bit Y counters to count horizontal synchronizing pulses between vertical synchronizing pulses, third and fourth latch flip-flops which are set by carry bits from said first and second 8-bit Y counters respectively and are reset by said vertical synchronizing pulses, said third latch flip-flop having a set output for generating said con-trol signal and said fourth flip-flop having a set output for terminating said control signal means for generating a speed clock frequency having a programmable frequency, a speed 8-bit counter operative to count said programmable frequency for a fixed time period synchronized with video synchronizing pulses; the number stored in said speed 8-bit counter being equal to said third preset number and equal to the 2's complement of said fourth preset number, said first preset number being selectable from one of said speed 8-bit counter and said first 8-bit Y counter, and said second preset number being selectable from one of said speed 8-bit :
counter and said second 8-bit counter.
counter and said second 8-bit counter.
25. The video special effects generator according to claim 24, further comprising controllable gating means for inverting the first and second preset numbers before they are loaded into said first and second 8-bit X counters.
26. The video special effects generator according to claim 25, further comprising second controllable gating means for inverting the third and fourth preset numbers before they are loaded into said first and second 8-bit Y counters.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5930677A JPS53144622A (en) | 1977-05-24 | 1977-05-24 | Video signal processing system |
| JP59306/77 | 1977-05-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1114494A true CA1114494A (en) | 1981-12-15 |
Family
ID=13109547
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA303,707A Expired CA1116288A (en) | 1977-05-24 | 1978-05-18 | Soft-edged video special effects generator |
| CA303,651A Expired CA1114494A (en) | 1977-05-24 | 1978-05-18 | Video special effect generator |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA303,707A Expired CA1116288A (en) | 1977-05-24 | 1978-05-18 | Soft-edged video special effects generator |
Country Status (11)
| Country | Link |
|---|---|
| US (1) | US4199788A (en) |
| JP (1) | JPS53144622A (en) |
| AT (2) | AT378639B (en) |
| AU (2) | AU516735B2 (en) |
| CA (2) | CA1116288A (en) |
| DE (2) | DE2822720C2 (en) |
| FR (2) | FR2392561A1 (en) |
| GB (2) | GB1585954A (en) |
| IT (2) | IT1095911B (en) |
| NL (2) | NL7805640A (en) |
| SE (2) | SE438401B (en) |
Families Citing this family (48)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5558868A (en) * | 1978-10-21 | 1980-05-01 | Takeshi Harada | Video reproducing unit |
| NL7903241A (en) * | 1979-04-25 | 1980-10-28 | Philips Nv | TELEVISION KEY SIGNAL SWITCH. |
| GB2063616B (en) * | 1979-11-16 | 1984-06-20 | Quantel Ltd | Multiple picture image manipulation |
| JPS5718168A (en) * | 1980-07-09 | 1982-01-29 | Toshiba Corp | Key signal generation device |
| US4392156A (en) * | 1981-05-04 | 1983-07-05 | Ampex Corporation | Video key edge generator for increasing the size of an associated border, drop shadow and/or outline |
| US4533952A (en) * | 1982-10-22 | 1985-08-06 | Digital Services Corporation | Digital video special effects system |
| GB8405947D0 (en) * | 1984-03-07 | 1984-04-11 | Quantel Ltd | Video signal processing systems |
| JPS6194479A (en) * | 1984-10-15 | 1986-05-13 | Mitsubishi Electric Corp | Display device |
| US4827344A (en) * | 1985-02-28 | 1989-05-02 | Intel Corporation | Apparatus for inserting part of one video image into another video image |
| JPH0638652B2 (en) * | 1985-12-28 | 1994-05-18 | ソニー株式会社 | Television receiver |
| JPS62159582A (en) * | 1986-01-06 | 1987-07-15 | Sony Corp | Television receiver |
| JPS62159989A (en) * | 1986-01-08 | 1987-07-15 | Sony Corp | Television receiver |
| US5732186A (en) * | 1986-06-20 | 1998-03-24 | Canon Kabushiki Kaisha | Image signal recording/reproducing apparatus having special-effects-processing capability |
| JP2794661B2 (en) * | 1986-09-20 | 1998-09-10 | ソニー株式会社 | TV receiver |
| US4752826A (en) * | 1986-10-20 | 1988-06-21 | The Grass Valley Group, Inc. | Intra-field recursive interpolator |
| US4887159A (en) * | 1987-03-26 | 1989-12-12 | The Grass Valley Group Inc. | Shadow visual effects wipe generator |
| DE3732789A1 (en) * | 1987-09-29 | 1989-04-06 | Thomson Brandt Gmbh | METHOD FOR TIMELY REPRODUCTION OF A RECORDED IMAGE SIGNAL CONSISTING OF SINGLE IMAGE SEQUENCES |
| US4954898A (en) * | 1988-05-07 | 1990-09-04 | Sony Corporation | Wipe pattern generator |
| US4970596A (en) * | 1988-09-07 | 1990-11-13 | North American Philips Corp. | Pseudo line locked write clock for picture-in-picture video applications |
| US5117226A (en) * | 1989-06-27 | 1992-05-26 | Samsung Electronics Co., Ltd. | Circuit for generating a scroll window signal in digital image apparatus |
| DE3935447A1 (en) * | 1989-10-25 | 1991-05-02 | Broadcast Television Syst | METHOD AND CIRCUIT FOR CHANGING THE POSITION OF A DIGITALLY GENERATED ANIMAL |
| US5022085A (en) * | 1990-05-29 | 1991-06-04 | Eastman Kodak Company | Neighborhood-based merging of image data |
| US5185808A (en) * | 1991-06-06 | 1993-02-09 | Eastman Kodak Company | Method for merging images |
| JP3163690B2 (en) * | 1991-11-25 | 2001-05-08 | ソニー株式会社 | Editing device |
| US7644282B2 (en) | 1998-05-28 | 2010-01-05 | Verance Corporation | Pre-processed information embedding system |
| US6912315B1 (en) * | 1998-05-28 | 2005-06-28 | Verance Corporation | Pre-processed information embedding system |
| US6737957B1 (en) | 2000-02-16 | 2004-05-18 | Verance Corporation | Remote control signaling using audio watermarks |
| EP1552454B1 (en) * | 2002-10-15 | 2014-07-23 | Verance Corporation | Media monitoring, management and information system |
| US20060239501A1 (en) | 2005-04-26 | 2006-10-26 | Verance Corporation | Security enhancements of digital watermarks for multi-media content |
| US8020004B2 (en) * | 2005-07-01 | 2011-09-13 | Verance Corporation | Forensic marking using a common customization function |
| US8781967B2 (en) * | 2005-07-07 | 2014-07-15 | Verance Corporation | Watermarking in an encrypted domain |
| US8259938B2 (en) | 2008-06-24 | 2012-09-04 | Verance Corporation | Efficient and secure forensic marking in compressed |
| US9607131B2 (en) | 2010-09-16 | 2017-03-28 | Verance Corporation | Secure and efficient content screening in a networked environment |
| US8923548B2 (en) | 2011-11-03 | 2014-12-30 | Verance Corporation | Extraction of embedded watermarks from a host content using a plurality of tentative watermarks |
| US8682026B2 (en) | 2011-11-03 | 2014-03-25 | Verance Corporation | Efficient extraction of embedded watermarks in the presence of host content distortions |
| US8615104B2 (en) | 2011-11-03 | 2013-12-24 | Verance Corporation | Watermark extraction based on tentative watermarks |
| US8533481B2 (en) | 2011-11-03 | 2013-09-10 | Verance Corporation | Extraction of embedded watermarks from a host content based on extrapolation techniques |
| US8745403B2 (en) | 2011-11-23 | 2014-06-03 | Verance Corporation | Enhanced content management based on watermark extraction records |
| US9323902B2 (en) | 2011-12-13 | 2016-04-26 | Verance Corporation | Conditional access using embedded watermarks |
| US9547753B2 (en) | 2011-12-13 | 2017-01-17 | Verance Corporation | Coordinated watermarking |
| US9571606B2 (en) | 2012-08-31 | 2017-02-14 | Verance Corporation | Social media viewing system |
| US8726304B2 (en) | 2012-09-13 | 2014-05-13 | Verance Corporation | Time varying evaluation of multimedia content |
| US8869222B2 (en) | 2012-09-13 | 2014-10-21 | Verance Corporation | Second screen content |
| US9106964B2 (en) | 2012-09-13 | 2015-08-11 | Verance Corporation | Enhanced content distribution using advertisements |
| US9262793B2 (en) | 2013-03-14 | 2016-02-16 | Verance Corporation | Transactional video marking system |
| US9251549B2 (en) | 2013-07-23 | 2016-02-02 | Verance Corporation | Watermark extractor enhancements based on payload ranking |
| US9208334B2 (en) | 2013-10-25 | 2015-12-08 | Verance Corporation | Content management using multiple abstraction layers |
| EP3117626A4 (en) | 2014-03-13 | 2017-10-25 | Verance Corporation | Interactive content acquisition using embedded codes |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3598908A (en) * | 1968-08-30 | 1971-08-10 | Ampex | Digitally controlled lap dissolver |
| US3821468A (en) * | 1972-03-22 | 1974-06-28 | Sarkes Tarzian | Digital special effects generator |
| US3758712A (en) * | 1972-03-27 | 1973-09-11 | Sarkes Tarzian | Digital special effects generator |
| US3941925A (en) * | 1975-03-10 | 1976-03-02 | Sarkes Tarzian, Inc. | Digital soft edge video transition system |
-
1977
- 1977-05-24 JP JP5930677A patent/JPS53144622A/en active Granted
-
1978
- 1978-05-18 CA CA303,707A patent/CA1116288A/en not_active Expired
- 1978-05-18 CA CA303,651A patent/CA1114494A/en not_active Expired
- 1978-05-23 SE SE7805897A patent/SE438401B/en not_active IP Right Cessation
- 1978-05-23 AU AU36386/78A patent/AU516735B2/en not_active Expired
- 1978-05-23 AU AU36384/78A patent/AU516734B2/en not_active Expired
- 1978-05-23 SE SE7805899A patent/SE438403B/en not_active IP Right Cessation
- 1978-05-23 IT IT23718/78A patent/IT1095911B/en active
- 1978-05-23 IT IT23717/78A patent/IT1095833B/en active
- 1978-05-23 FR FR7815321A patent/FR2392561A1/en active Granted
- 1978-05-23 FR FR7815320A patent/FR2392560A1/en active Granted
- 1978-05-23 US US05/908,768 patent/US4199788A/en not_active Expired - Lifetime
- 1978-05-24 NL NL7805640A patent/NL7805640A/en not_active Application Discontinuation
- 1978-05-24 AT AT0380778A patent/AT378639B/en not_active IP Right Cessation
- 1978-05-24 DE DE2822720A patent/DE2822720C2/en not_active Expired
- 1978-05-24 GB GB22093/78A patent/GB1585954A/en not_active Expired
- 1978-05-24 NL NL7805644A patent/NL7805644A/en not_active Application Discontinuation
- 1978-05-24 AT AT0380878A patent/AT378640B/en not_active IP Right Cessation
- 1978-05-24 GB GB22091/78A patent/GB1585952A/en not_active Expired
- 1978-05-24 DE DE2822785A patent/DE2822785C2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2392560A1 (en) | 1978-12-22 |
| ATA380878A (en) | 1985-01-15 |
| AU516734B2 (en) | 1981-06-18 |
| SE438403B (en) | 1985-04-15 |
| FR2392561B1 (en) | 1984-01-20 |
| IT1095911B (en) | 1985-08-17 |
| GB1585954A (en) | 1981-03-11 |
| SE7805897L (en) | 1978-11-25 |
| IT7823718A0 (en) | 1978-05-23 |
| JPS6122509B2 (en) | 1986-05-31 |
| AT378640B (en) | 1985-09-10 |
| US4199788A (en) | 1980-04-22 |
| AU3638678A (en) | 1979-11-29 |
| DE2822720C2 (en) | 1985-06-20 |
| DE2822720A1 (en) | 1978-12-07 |
| NL7805644A (en) | 1978-11-28 |
| AU3638478A (en) | 1979-11-29 |
| NL7805640A (en) | 1978-11-28 |
| FR2392560B1 (en) | 1984-03-09 |
| IT1095833B (en) | 1985-08-17 |
| CA1116288A (en) | 1982-01-12 |
| IT7823717A0 (en) | 1978-05-23 |
| AU516735B2 (en) | 1981-06-18 |
| FR2392561A1 (en) | 1978-12-22 |
| SE7805899L (en) | 1978-11-25 |
| DE2822785A1 (en) | 1978-12-07 |
| DE2822785C2 (en) | 1986-03-27 |
| JPS53144622A (en) | 1978-12-16 |
| SE438401B (en) | 1985-04-15 |
| AT378639B (en) | 1985-09-10 |
| GB1585952A (en) | 1981-03-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |