CA1119327A - High frequency refresh system for gas display panel - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A plasma discharge display device is operated at a high frequency above the response range of the inherent wall charge storage phenomenon and utilizes a refresh buffer. The vertical drive selection includes a pair of shift registers operated in parallel into which data from the host or associated controller is loaded, with an individual driver associated with each register stage.
The horizontal lines are addressed through associated shift registers in an even-odd interlace sequence to generate a display on a horizontal scan basis. The horizontal drivers are referenced at the level and frequency of the high frequency energizing signals, while the vertical drivers are selectively set to ground or a positive a.c. voltage according to the state of associated register cells. By using the high frequency signal in the horizontal axis as a floating reference and unique selection techniques, the display is operated by low voltage signals. The normal sustain and erase operations associated with conventional plasma discharge devices are eliminated, while the write operation does not require either the precise timing or logical considerations associated with the selective operation of conventional plasma discharge display devices. The low voltage drive requirements permits use of low voltage driver circuitry which is susceptible to low cost monolithic fabrication techniques.

Ki9-76011

Description

3~

IIIGH FREQUENCY REFRESH SYSTEM FOR GAS DISPLAY PANEL

BACXGROUND OF THE ~Mn~NTlON~

Conventlonal a c pls~ma dl~c~arge di~play p~nel-consl~t of two gls~ plate~ upon e w h of whlch has baen formed an array of parallel conductors oYer whlch transpsr~nt gla~s dlelectric and secondary emissive coating~ have been applled The plateJ are as~ombled with the conductor arrays ~l~po~ed substan-tially orthogonal to each other, the lnner plate surface-spaced at a unlform dl~tanco de~ignsted the dl~charge gap over the entire surface and perlmeter ~e~led into an onv~lope whlch 18 then evacuated, bac~filled with the appropriate gnJ mixture snd permanently ~ealed By selective manlpul~tlon of tho conductor array~, cell~ positloned at the lnter~ectlon~ are ionl~ed to ~orm a dl~play WhLle the m~nufacturing technique~ for fabrlcatlng a c pla~ma panel~ have been devoloped, they remaln relAtivoly expen~lve to fsbrlcate becau~e o~ requlred close tolerance~ ln physlcal and electrlcal parameter~
Such ~ c plasma panels po6~e~ an lnher~nt storage or memory functlon ln which alscharge particles, lon~ and electron~, are alternately sttractsd to oppo~lt~ walls oP tho cells a~ the polarlty of the drlvlng volt~ge L~ succe~slvely rever~ed Ho~ver, ~` '

-2-the lnhsrent memory r~quira~ hat 3u~t~1n ~lgn~l~ b~
cont~nuou~ly appl~ed ~o all c~ o~ the pan~l to repetit~Yely z~ioni~e ths c3113 to maintaln the diIIplay~ re~ul~lng ln rela~ ly complex logic requ$r~-S menta to ccmbin~ ~electl~e write and erase operatlon~wlt:h ~he non-selectl~e 3uataln. In addltlon, rolntlvely hlgh voltnge writa nnd ~r~ dri~er~ whlch are not auacep-t~ble to econom~cal low voltage monollthic circult ~a~rl-cat~on are required in con~entlonal pla~ma dl3charge dl~play devlces. Prec~ae write, era~e ~nd ~ustain tlme~
are requlred in noxmal a.c. pla~ma operation. Furth~r, c~rtnln electrical parameter~ such a~ the opersting margln, l.e., the dif~erence batween the maxlmu~ and minimum ~ustAlA volt~ge (V~ max. - V~ min.) are extremely critical, and may vary bsyond llmlts elther during or a~t~r te~t, nece~ltatlng elther rejectlon or field repl~c~ment o~ ~he panel wlth the a~oclAted co~t involved.

Xi9-76011 '~ 9~Z~
l SUMMARY OF THE INVENTION
The instant invention overcomes certain limitations inherent in conventiona1 plasma display panel systems by providing in combina-tion, a plasma display device comprising a pair of glass plates having dielectrically coated orthogonally related conductor arrays disposed thereon in which the intersections of said orthogonal conductors define gaseous display cells. High frequency signal generating means is provided to generate signals having a frequency above the response time of the wall charge of said plasma display device. First and second selection circuits are provided. The system also includes means responsive to said first selection circuits for conditioning selected conductors on one of said arrays in response to the binary data applied thereto, and means associated with said second selection circuits for scanning the display device along the other of said arrays. The scanning means applys low voltage signals to said frequency signal to said selected line whereby the combined signals produce ionization of selected cells by coincidence of drive signals on said first and second conductors.
The system of the invention operates in what is herein designated as "scan" mode in which the gas panel is operated at very high frequency such that the inherent memory characteristic of the panel is effectively eliminated. In the preferred embodiment, a refresh driving method such as that used in conventional CRT display devices is employed to refresh the display where desired. Since the normal use of the invention would be in a display terminal environment associated with a host processor, the host or host interface may pro-vide refresh of the display in the same manner as conventional raster scan CRT displays. In operational terms, the frequency at which the invention is operated may be varied from 500 kilocycles to 2 mega-cycles, or higher as compared to a nominal 50 KC rate for conventional a.c. plasma devices, in which frequency range the wall charge char-acteristic of the plasma discharge device is eliminated. The invention .3Z~
1 does not require close tolerances in physical or electrical para-mel;ers inherent in conventional plasma displays, while the associated logic ;s simplified and adapted for integrated circuit packaging.
There is no specific time format for a write operation, while the erase and sustain operations together with the margin requirements inherent in conventional plasma panels are completely eliminated. The entire display should be refreshed at a frequency to eliminate or avoid any flicker problems which would be disturbing to the viewer, at least 40 complete scans per second, while the time to load data which tends to reduce display intensity is minimized. The invention permits the use of low voltage drivers, while the logic and driving circuitry are designed for high density integrated circuit packaging.
The plasma panel structure utilized with the instant invention can correspond to those used in conventional X-Y matrix addressed plasma display devices including panels which would tend to fail standard testing techniques applicable to matrix addressed plasma panels. The embodiment of the instant invention utilizes a horizontal line scan-ning technique, such that maximum benefit is provided for displays having a high aspect ratio, i.e., the ration of vertical to horizon-tal conductors.

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, ~RI~F DESCRIPTION OF ~E DRAWINGSs Figure 1 i9 a block logic diagram of a pre~erred embodiment of the ~nqtant lnventlon.

Flgure 2 1~ a block schematlc dlagram o~ a preferred embodiment of the instant invention.

Figure 3 1~ A block r~pre~entation of a vertical ~election and drlve module.

Flgure 4 18 a schematic dlagram o~ the horlzontal driver conflguratio~.

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- ~ -Referring now to the drawlng~ and m.ore particu-larly to Fig. 1 thareof, tha lnstant lnventlon wlll be de~crlbed ln term~ of a preferred pla~ma dl~play ~ystem lnclud~ng panel as~embly 10 hnvlng 60 horl~ont~l line~ labeled Y0-Y~9 and 240 vertlc~l lln~ labeled X0-X239, the llne~ belng dlvlded lnto groups of odd or even llnes, both the vertlc~l and horizontal line groups belng drlven ~rom oppo~lt~ ~ido3 of the pnnel. Such a con~lguratlon could provlde a ~lx llne 40 character per line dl~play or 240 5 x 7 dot char4cters. ThQ horl-~ontal llne3 are drlven by group~ ln an interlaced pattern nlmllar to conventlonal ~V dl~play~, ~hlle the vertlcal llnes X0-X239 are condltloned by thelr as~oclAted ~hl~t regl~ter ~tages and drlven or ~canned s~multaneously on a horlzontal llne by line ~a~is. It should b¢
noted thst u~ng the ba~lc ~can technlque, all of the dot or llne ~egments must be cont1nuously refreshed by the host or through An as~oclated bu~er. Such technlques are well known ln the dl~play termlnal art, and ~uch detalls hnve accordlngly boen omltted ~rom the ln~tant appllcatlon.
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The panel a~sembly 10 and s~soclated drlve and control clrcultry are shown to the rlght o~ llne 11, which ls used to lllustrate the ~eparatlon o~ the ~ser Inter~ace ~rom the panel assembly. The user lnt~r~ace ;

32~

of th~ preferred ~nbod~ent con~iat3 of nlne control llne~ Lncludlng a logic ground ~hlch are ln~eled by ~unctlon. The vertlcal lnput llnew are d~slgnated by X DATA ODD and ~ 3ATA ~V~N ~nput~, whlle the horizontal llne~ design~ted ara d~vlded lnto two lnterlaced groups de~ignated ~ DATA ODD and Y DAT~ EVEN. Serl~l d~tn comprl~lng tha odd X lmage d~ta wlll ~e lo~ded on th~ 8 llne to the top vertlcal arlvers wlth a data sequenc~
o~ hlgh order (Xl) b~t ~lrst. The even X ~mage d~ta, which ia prenented ln parallel with the odd X lmage data, wlll b~ loaded to the bottom vertlcal driver~ wlth a data ~equenc~ o~ h~gh ord~r (X0~ blt flrst. Ioglc control llne~ ~n tha User Interface wlll be as~umed to orlglnate from the ho~t or display controller, both of which are well known ln the art, the detall~ of whlah are beyond the scope of and unnecessary for an under-standlng o~ the instant lnventlon.

The panel a~embly 10 lllustrated ln the preferred embodiment of Flgure 1 13 an ~PA (All Polnts Addressable) devlce ln whlah the d~plAy cell~, located botween the orthogonal conductor array~ dlsposed on oppo~lte nldes o~ the panel, are lndlvldually and selectlvely addr~ss-able. Refresh 18 provlded on A horlzontal scan ba~i~
by ~cce~slng the host or controller uslng conventlonal re~re~h technlques. Eoth the horlzontal and vertical conductors are dlv~dod lnto alternate groups of odd and even llne~, the odd line groups belng drlven from one side of the panel, the even line groups being drlven from the oppo~ite ~ide. Two parallel data load path~
for the X axl~, X DATA ODD and X DATA E~EN, are provided ln order to reduce load tlme, whlls, as prevlou~ly noted, the X odd and X even dnta are presented ln parallel.
The ratlo of the load tlme to the dl~play time in a refresh drlven dlsplay a~ect~ the dlsplny inten~lty, ~o that lt i8 desixable to minlmize the load time portlon o~ a di~play 3equence. Accordingly, the x Odd and x Ev~n ~h~ reqi3ter3 15 and 19 are loaded ~n parallel at a high data r~te from the respectlve X
D~TA ODD ~nd X D~ VEN linee 13 and 17 re~pectively.
Thlo de~lgn ~llo~ flexlbility in programm~ng character ro~w po~ltlonlng, ch~ractar ~lze and charactar ~ont through m~nlpulation of the horlzontal addres~ data.
The horizont~l clock lina 45 l~beled X Data Clock shlfts thl~ data through t~.e horizontal ~hi~t regi3ters in such manner that the evcn then o~d llnes are scanned sequentially ln an interlace technlque. Serl~l data on this line 1~ loaded to the Y dr~vers to latch the addressed horlzontal scan llnes. Y aadress ~equencing 18 YO~ Y2, Y4. . .Y58 followed by Yl, Y3, ~5. . .Y59.
Data to YO i8 a logical "l~ ~o latch the YO scan line.
All suhsQquent data to Y are logical ~o n ~ ~ through Y59 to cause precesslon of the loqical Ul" through all horlzontal addre~ses. Only one loglcal "l" in the Y
axi~ 1~ permis~ible at any tlme. Shift registers 15 and l9 associated wlth X Odd Drlve 21 and the X Even Drlve 23 respectlvely includ0 an lndlvldual ~hlft r~qi~tex cell ~e~ocl~ted with each of the drlve llne~, e~ch cell ln turn boing controlled by the blnary state of its as~ociated ~hi~t reglster ~tage. Thus each of ~hlft reqlstere 15 and l9 lnclude 120 cells asHoclated with the respective 120 odd and 120 even ~ertlcal line~.
Basically, the operation of the device entalls setting the selected X Odd and X Even lines at ground reference through thelr respectlve cells, and applylng a burst of hlgh frequency ~ignal~ to the selected Y llne, these signals comprl~ing sinusoidal voltaqe3 of 220 volts peak-to-peak applled to all Y lines. An addlt~onal write eignsl of +25 volts ie applled sequentially to the Y even lines and then the Y odd llne~, and the celle located at the intersect~on of the ~elected X and Y line~
and recelving the 245 volt potential will be ionized.

Xl9-760~1 2~

The Y axls al30 lncludes ~hlft regl3t~rs 27 and 29 and th~ir a3~0ciated odd and even drlvQrs 31 and 33 respectlvely, one driv2r for each llne. I~ach Y
drive i~ refexenced to ths high fraquency slnusold ~rom high voltage and power osclllator 35, which ls connectod through llne 37, 37' and 37 " to the respectlvc Y Odd and Even Drive~ 31 and 33. ~o a~old the problem of high voltage shlf'lng, the hlgh frequency signal 10 applied directly to all odd and even llne~, 80 that effectlvely all Y llnes have a 220 volt potential thereon, a voltag~ level lnauf~cient to lonlze a cell. As descrlbed above, the Y even ~hlft reglster 29 has a "one" blt applled from Y data llne 47 ln ~he U~er Interface to the zero ~tage of the Y even shl~t regi~ter 29, th~ "~ne~ blt ~erving to identify the selected Y llne durlng each wrlte cycle. The selected Y even drive 33 utillzes the hlgh frequency sinusold ~lgnal a~ a reference, and applles an addltional pulse of 25 volt~ to tbe selected Y line whlch, comblned wlth the 220 volt hlgh fre~uency reference, provlde~ a potentlal o 245 volt3 acron~ ~elected cells, whlch ~8 ~dequate to lonize tho~e cells whereln the X select level 1~ set at ground a~ prevlou~ly de~crlbed.
~Jriting 18 done by horlzontal ~cannlng of the Y llnn~
ln an lnterlaced mode a~ shown, ln whlch the one bit 1~ shlfted through the 30 even ~tages of ~hlft regl~ter 29. The output stage 58 of even ~hlft regl~ter 29 1~
connected vla line 43 to the lnput stage of the odd shlft reglster 27, and 18 then ~hlfted through the 30 stages : 30 of the odd shlft register in the idsntlcal manner as in the even shlft register, thereby completlng one interlaced horlzontal scan ~equence.
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Shlfting of the x odd and X even shift reglsters 15, 19 i3 provided by the shl~t signal on line 45 whlch : 35 origlnate6 from the X Data Clock ln the U~er Interf~ce, wh~le 3hlftlng ~or the Y shlft registers i8 provlded Xi9-76011 --io--by the Y data c~ ock 3ignal on llna 41 al~o orlglnatlnq ~n the U?~er Tnterface. ~u~ to the dl~rence ln slgn~l levela b~tween the control 3ignala ln the URer Inter-~ace ~nd the high fre~u~ncy dr~ve ?~ignals, optlcal coupler~ 42, ~8 provlde coupllng and laol~tlon b~twoen the two dlfferent level8 or the Y Dat~ ~nd Y Data Clock Qlgnal?3. Tha Y ?~cannlng ~equence utllize~ the lnterlace technlque in wh~ch scannlng o~ ~11 the even lines O through 58 15 ~ollowed by scannlng of the odd llnsfi 1 through 59. Th~ 3 lnterlace sequence effQct-lvely improves the intenslty and prevents any fllcker problem whlch could result lf the lines were scanned sequentlally on a non-interlace basis.

O~erating at 3 MXZ u~ing a 1.5 MHz slnusoid, for example, the write period per llne 1~ approximately 400 microsecond~, whlle the load tlme for loadlng the X odd and X even shl~t reglsters is approxlmately 40 mlcroseconds operatlng at a frequency of 8 MHz. The X re~erence ~ignnls are effectively referenced at ground level for the selected vertlcal line~, or at 25 volts a.c. ~or the deselected lines. The output from th~ X shl~t rogieters 15, 19 on llnes 53 and 55, returned to the U3er ~nter~ace on llnee labeled X
Data Odd Out and X Data ~ven Out, are not functlonally r~quired but are uscd or dlagnostic purpo~es. The write llne on l~ne 5~, al80 origlnatlng ln the U~er Interface, 18 applled to logic and control circuit 35 to lnitiate the wrlte cycle hereto~ore described, whlle the logic ground control llne ~hown at the Vser Inter~ace merely provides 8 ground reference ~or the logic clrcultry. ~rlte 18 8 command ~lgnal caus~ng the latchQd driver?a in X and Y to be drlven and the assoclated image data wrltten to the panel. ~rlte iB
held actlve for the duration of the wrlte cycle ~or ; 35 ~can llne, 516 micros~cond~, a period determined by the tlme/lntenalty raquir~m~nt~ ln the lnterlace operation of the lnstant ~nYQntlon. Wrlta lo~lcally trlgger~ an a.c. drlve whlch m~i.ntaln~ drlvln~ potsnt~al on all 3elected X/Y drlvere.

Whlle the inv~ntion han b4en broadly de0crib~d wlth re~er~nce to the block dl~gram of Ylg. 1, a moro detailed block schomatlc o~ th~ inventlon 19 lllu~trated ln Fig. 2. Referring now to Fig. 2, there i~
lllustrated a ~lmpli~ied 3chematlc of the ecan panel eystem. The prlmary purpos~ o~ the horlzontal and vertical drlver~ 18 to lncrea~e tho peak-to-peak voltage acrosn each capacitlve el~ment ~cell~ by about 50 volts, whlch ln turn accompllshe~ selectlon. Thl~ 18 provlded in the ln~tant ~nventlon, however, utillzlng low voltage clrcuit3 not exceedlng 25 volts. ~lgh frequency drlver lOl 18 connected to the prlm~ry wlndlng o~ a transformer 103 which develops 180 volts peak-to-peak at nod~ lOS, u~lng a portlon o~ the secondary wlnding, and 205 volts peak-to-peak uslng the ~ull socondary wlndlng of trans~ormer 103 at nodo 107. Re31~tor lO9, cnp~citor lll ~nd dlod~ 113 compri~ a voltage doubler clrcult whlch cau~o~ node 115 to reach a maxlmum n~atlve potentlal of 25 volt~, neglectlng diode dropa, wlth respect to node 105. The ~5 volt and -l volt power ~upplle~ and ll9 re~pectively ~or th~
horlzontal modules float on the node 115 potontlal~
further, optical couplerJ 42, 45 (Flg. 1) ~rovlde the Y clock and data slgnal~ to the horlzontal module~ a~
more fully de~crlb~d herelnafter. The -l volt power ~upply 119 re~erenc~s the chlp eubstrate At -1 ~olt.
The above de~crlbed clrcultry 18 the common horlzontal clrcultry for generatlng ~nd applylng the Y drlve to the s~lected llnes. Indlvldual horlzontal drlver clrcultry 18 assoclat~d wlth each o~ the llne~ l.e., 18 dupllcated for each horlzontal drlve lln~.

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X~9-76011 In operatlon, ~he data i3 propogat~d aerlally thro~gh th~ ahl t ra~l~tsr c~ll 121, .~hlch may bs packaged ln monollthlc clrcu1try, and then to other serlally conn~cted modula~ aa descrlbsd wlth respect to Flg. 3, depending on dlsplay ~ize. Once the data i~
turned on, and ~ull voltage~ are applled to the driver module~. Thl3 prqvont~ all BVCEO bxeakdown of the drivers whlch would occur 1~ the drlver~ wer~ r~qulred to swltch the requlred increment ln pe~k-to-peak voltage (about 250 volt~). oparatlon of the vertlcal drlvers 1B 8im~ lar and the componants are ~lmllarly ~dentl~ied wlth a prime deslgnatlon, except that the optlcal couplers are not requlred, and the cloc~ frequency i8 h~gher since there are more vertlcal llnes which must be loaded ln the ~ame tlme lnterval. ~?orizontal clock frequency i9 about 200 ~æ, whereas vertlcal clock frequency ls about 5 MHz. It ~hould be noted that the dlsplay lntensity varles AB a functlon of the frequency of the trans~ormer driver lOl, and the maxlmum frequen~y ~0 is about 1.5 MHz. When the horlzontal drlver lOl 18 off dlode 123 sources current to the output node 125, wh~le dlode 127 slnk~ current ~rom the same node. When the horlzontal drlver 18 on, an addltlonal 25 volt~ in the negatlve dlrect~on le applled to node 125, since the output node 125 18 essentlally connected to the volt~ge doubler buss at node 115 through tran~l~tor 129 and dlode 123. When the vertlcal drlver 1~ off, dlode 123 clamp~
; output node 131 to ground, ~hlle diode 133 clamp~ node 131 to about +25 volts orlginatlng at voltage source 135. Wlth the vertlcal drlver on, output node 131 1~ held to ground. A~ a consequence, activatlon of elther the vertical or horlzontal drlver cau~e~ an addltional 25 volts to occur acro~s the ~elected cells. ~olncldence Ri9-76011 of both vertlcal ~nd hori~ontal Jelectlon place~ an Addltional ;0 ~tolt3 acro~ the aelect~d cell~ ~hich cau8e th~ 3elected cella to av~lanche. For a large pl~m~ display panel, a paak current o~ about 20 m~ ~mpJ mu~t be ~ourced and 3inked by the hori~ontal drlver~. Because of the 50~ duty cycla, th~ 20 m.a.
pellk corre~pond~ to about 7 m.a. R~S~ con~e~uently, lO
m.a. devlces can bQ u3ed for dlode~ 123, 127 and po~ibly tran~l~tor 129. ~hQ vertlcal current dem~nd 0 i8 cons~derably less- ~he details o~ the specific drlve circults utili~ed for the horl20ntal and vertical driver~ are sho~n and described with respect to Flg. 4.

Referring now to Fig. 3, there 1~ illustrated ln bloc~ schematic form a slngle module of the x Odd 15 Shl~t Regi~ter 15 and associated x Odd nrive 21, notlng that the x Even ~rive 23 and as~oclated X ~ven Shlft Regl~ter 19 are ldentical both ln structure and operation. The circuitry ~hown ln ~lgure~ 2-5 18 ad~pted ~or lntegrated clrcuit pac~aglng, each module 20 lncluding a plurallty o~ circult~, although obvlou~ly discrete components could be employed. While the number of circults per module varies aQ the pa~kaging technology employed, the circultry utillzed in the pre~erred embodlment wa~ packaged ln group~ of 16 ~hift reglst~r 25 ~tages and a~sociated drlver3, plus an lnput buffer and an output buffer for ench module. ~ number of such ; modules are intsrconnected in accordance wlth the size of the dlsplay to be provlded, 80 that the horlzontal modules can be consiaered as one large serial shlft 30 register with parallel output drlvers, one driver per blt or per cell. The specific circuit implementat~on of the driver~ are shown and described in detail hereinafter.

Assuming the module repr~ents the flr~t 16 ~lts of ; 35 the X shift regist~r ~nd as~oclated drlve, the X Data .
' ~i9-76011 ~19~32~

Odd Llne 13 de~ignat2d DAT~ ~n la connected to input buf~ar ~1, which g~nerate~ t~o output~, an output on llne 73 de~ignated DATA ~ndlcat~ng the presenc~ o~
positlve data or a b~.nary 1 condltion on the data lnput, an output on llne 75 designated DATA indlcating the ~b~ence of data or a blnary O condltlon. Th~
outputs 73 and 75 are connected to the ~irst 3tagQ o~
shlft register 15 ahown as 3hlft reglster cell 77, the DATA and DATA outputs of whlch are connected via llne~
10 81 and 79 to the associatud ariver 83 of X Odd Drive 21, which producea an output on line 85, which output~
are normally applied as drive signals to their associ~ted panel drivs lines. ~ach 3hift register essentially comprise~ a series of trlggers which are logically 15 interconnected to form a shift regi3~er in a manner well known to those skilled in the art. In the configuration chown in Fig. 3, only the first and sixteenth ~tages, ce}l~ 77, 89 of the shift reglster and their as~oclated driver~ 83, 91 are illustrated by way of example, all 20 interconnecting ~hift reqister and driver stages bein~
idcnt~cal. The output 85 from driver ~3 de~ignated D OUT
represents output drive line Xl from the X Odd Drive 21, (Fiq. 1), and each driver stage has an a~sociated reference level VCL of +25 volts such a~ output termln~l 25 87. qhe +25 volts repre~ents a clamp voltage which prevents the output rom exceeding 25 volt~ damaging the module. The individual ~tages of the shi~t regi~ter are coupled together ln succes~ive palrs to transfer information from the first stage to the last, and when 30 filled, the one or zero condltion of the re~pective stages produces a ground reference or a 25 volt a.c.
potential applied to each of the stage~ such that the select or write signal from the Y drivers either select~
or deselect~ individual cell~ on the ~elect line in 35 accordance with the contents of the X shift register.

Since the device~ ara pack~ged ln a ~erle~ of .3~7 modules, each module lncludo~ an lnput aAd an output buf fer to drlve the ~ucceeding module to malntaln tha prescrlbed olgnal levol ~8 ~lgnal~ ~rc sequence~ or propogated through the entlre shl~t reglster. Utll~zing S A 16 clrcult per module packaglng arrangement a8 descrlbed, a total of 15 moduleo would be requlred to drive 240 X vertlcal llnes, one of the modules being ~harQd by elght odd ~nd elght even shlft regl~ter and dr$ver clrcu$t~. This sharing arrangement would lO obvlously be utlllzed only lf moro convenlent than utlllzlng elght ~hlft registers for odd and even respectlvely.

Referring now to Fig. 4, there 1B illu~trated a clrcuit schematic of the horizontal driver ~hown ln 15 block ~chematic form in Flgures 1-3. In the preferre~
embodiment, Fig. 4 18 an off-chlp drlver who~e inputs are the true nnd complement outpùts of the associated shlft reglster cell marked DATA and DATA and whose output wlll sink current through tran~lstors 141 and 20 143 to ground when data 1~ positive with re~pect to DAI~. r.xam~natlon of ~oth vertlcal And horlzontal clrcult requlro~ents reveal~ that the same circult can ~e u~ed ~or ~oth functlon~, provldlng the additional output capac$tance o~ the larger horizontal output 25 deYiceg can be tolerated ln the vertlcal ~unctlon, since too large an output cspacltance could prevent the 25 volt clamp from operatlng.

The average value of DATA and DATA 18 positlve, oo that a current of approx~mately 250 mlcroamps always 30 flows through the reslstor 145 when DATA is oo~ltive wlth respect to nATA, and thl~ current i8 dlverted through transi~tor 141. ~hls current flows into the base, turning translstor 141 on. Current through transistor 141 also turns on translstor~ 141 and 143 in ~5 thlo stage whlch are lnterconnected ln a conventlon~l -~19-76011 Darll~gton coupled ~ran~l~tor ~lr conflguratio~, which i~ p~rt~cularly ~ult~ble ~or monollthic fabrication.
~he current galn with re~pect to output node 151 1~ tha product of the current galns of devices 141 and 143.

~Yhen DATA ~3 poslt~ve wlth re~pect to D~TA, the 250 mlcroamps 1~ d~vertod thsough tran~lstor 153. The collector of tranelstor 153 ri~e~, and current i8 drlven lnto the ba~es of translstors 155 and 157 through re~i~tors 159 and 161 respectlvely. Device~ 155 and 10 157 pull down the bases of transistors 141 and 143 to ground, pre~entlng a low b~e lmpedance for devlce~ 141 - and 143 respectlv~ly. The low base ~mpedance i8 import nt because the breakdown voltage requlred 18 the open emltter brenkdown voltage, as opposed to the open base breAkdown ~oltage.
,:, Variable re~lstor 163 come~ lnto operation when the DATA and DATA nodes are reversed in ~ense or polarity.
~e~i~tor 163 functlon~ to hold translstor~ 155 and 157 off durlng the on condltlon of the drlver. It ls ~
~urther ~y~tem requlrement that the output drlver be ~rotected ~rom brea~down condltlon, and dlode 165 1 provlded ~or thls functlon. In the event that the drlver 1~ drlven from tho load to a potentl~l more po~tlve than ~ts specifled brea~down of 25 volt~, dlode 165 wlll conduct, preventlng the breakdown conditlon from happenlng. Also ln the preferred embodlment of the lnstant lnventlon, lt 18 requlred that the devlce be able to source current from ground. Th~ requlrement iB met through dlode 167.

The above descrl~ed clrcult con~lgur~tlon is a circu~t wlth enough drive to h~ndl~ horlzontal llnes on falrly large panels. For lower load vertlcal drlver3 as ln the pre~erred embodlment, the clrcult can ~e ~lmpllfled. Instead of a Darllngton conflguration ., 32}~

using transi~tors 141 and 1~3, transl~tors 143 and 157 can be ellmlnated, and ~he emitter of tran~iRtor 141 connected to ground. wlth thi~ qimpllcatlon, the o~f-chip driver provlde~ only about one~ th to ona-S tenth the driv~ current a~ compar~d to the ~arllngtonimplement~t~on, which current requlrement i8 adequate for the vertical driver~ in the prefcrred emboclimcnt.

The above described invention thus provide~ a novel method of operating a pla~ma display with low voltage drlving circultry, non-complex ~electlon and drive circuit adapted for generating a dlsplay uslng a scanning technique. The ~tructure and techniques used therein are well developed in the display art, ~o that the overall co~t and complexity o such displays $8 su~tantially reduced. Further, by eliminating certain operat~onal parameters assoclated with conventional a.c. pla~ma display device~, panels whlch do not operate within these parameters may be employed $n the present ;, invention.

Wh~le we have illustrated and de~cribed the pre~erred embodlments o~ our lnvention, it i9 to be understood that we do not limit ourselves to the preclse constructions herein disclosed and the right is re~erved to all changes and modifications coming within the scope of the invention a~ defined in the appended claim.

Claims (9)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A refresh buffer plasma display system comprising in combination, a plasma display device comprising first and second glass plates, said plates being sealed under pressure and containing an ionizable gas, said first and second plates having first and second dielectric coated arrays of parallel conductors respectively formed thereon, said first and second conductor arrays being orthogo-nally disposed with respect to each other whereby the intersection of said orthogonal conductors define a matrix of gaseous discharge cells, a high frequency signal source having a repetition rate above the wall charge response time of said gaseous discharge cells to prevent the accumulation of wall charge on said cells during operation of said device, first and second drive-selection circuits associated with said first and second conductor arrays, means responsive to control signals applied to said first drive-selection circuits for selectively conditioning conductors on one of said arrays in response to data signals applied thereto, and means responsive to control signals applied to said second drive-selection circuits for selectively and sequen-tially scanning a plurality of conductors in said second array with said high frequency signal source and applying drive signals referenced to said high frequency signal source to selected lines whereby selected cells in said array are ionized by coincidence of said conditioning and said scanning signals.

2. A system of the type claimed in claim 1 wherein said high frequency signal is applied to all conductors on one of said arrays.

3. A system of the type claimed in claim 1 wherein said first and second selection circuits comprise vertical and horizontal selection circuits respectively.

4. A system of the type claimed in claim 1 wherein said conditioning means is applied to a vertical axis and said scanning means is applied to a horizontal axis.

5. A system of the type claimed in claim 3 wherein said vertical selection circuits comprise interleaved shift registers connected to conductors alternately terminated on opposite sides of the panel.

6. A system of the type claimed in claim 3 wherein said horizontal selection circuits comprise serially connected interlaced shift registers operated as a ring counter for providing an interlaced display.

7. A system of the type claimed in claim 5 wherein said vertical shift registers are loaded and operated in parallel to reduce data load time.

8. A device of the type claimed in claim 3 wherein said first drive-selection circuits apply a pulse signal to selected vertical lines while a similar signal referenced to said high frequency signal is applied to said horizontal conductors whereby a horizontal slice of data is simul-taneously generated for display.

9. A device of the character claimed in claim 8 wherein said horizontal and vertical drive-selection circuits include shift register means for entering and shifting data to control the operation of drivers associ-ated with each row and column in said matrix display.