CA1126873A - Multi-configurable cache store system - Google Patents

Abstract

ABSTRACT

In a data processing system which includes a plurality of system units such as a central processing unit (CPU), main memory, and cache memory all connected in common to a system bus and communicating with each other via the system bus, and also having a private CPU-cache memory interface for permitting direct cache memory read access by the CPU, a multi-configur-able cache store control unit for permitting cache memory to operate in any of the following word modes:
1. Single pull banked;
2. Double pull banked;
3. Single pull interleaved;
4. Double pull interleaved.
The number of words read is a function of the main store configuration and the amount of memory interference from I/O controllers and other subsystems.
The number ranges from one to four under the various conditions.

Description

~31 2~73 ~ACKGROUND OF TIIE INVENTION
Field of the Invention This invention relates generally to minicomputing systems, and particularly to storage hierarchies having high speed low capacity storage devices coupled via a system bus to lower speed high capacity storage devices, and more particularly to a private CPU-Cache Memory Interface.
Description of the Prior Art The storage hierarchy concept is based on the phenomenon that individual storage programs under execution exhibit the behavior that in a given period of time a localized area of memory receives a very high frequency of usage. Thus, a memory organization that provides a relatively small size buffer at the CPU interface and the various levels of increasing capacity slower storage can provide an effective access time that lies somewhere in between the range of the fastest and the slowest elements of the hierarchy and provides a large capacity memory system that is "transparent" to the software.
This invention takes advantage of a word organized memory.
Prior art was limited to storing the requested data word with its address in hardware registers. ~hen the need came about for expanded size low cost buffers, the prior art utilized a block organization. If a particular word was requested by the CPU, the block containing that word was stored in a high speed data buffer. This had the disadvantage of bringing into the high speed buffer words with a relatively low probability of usages.
Assuming a four word block, if word ~ is requested, the entire block lncluding words 1, 2 and 3 which have a relatively low probability of usage, are brought into the high speed buffer. To optimize the usage of the memory hierarchy, the operating system must organize memory in such a manner that software submodules and data blocks start wi-th word 1 of the block. To overcome tilis difficulty, the prior art utilized a "block look ahead".
en one block was in the high speed buffer, a decision was made during the processing of a da~a word in that block to bring the ne~t block into the high speed buffer.
Some typical patents indicative of this philosophy are as follows:
United States Patent No. 3,231,868 issued to L. Bloom, et al, entitled "Memory Arrangement for Electronic Data Processing System" discloses a "look aside" memory which stores a word in a register and its main memory address in an associated register.
To improve performance, United States Patent No. 3,588,829, issued to L.J. Boland, et al, discloses an eight-word block fetch to the high speed buffer from main memory if any word in the eight-word block is requested by the CPU.
An article by C.J. Conti, entitled "Concepts for Buffer Storage" published in the IEEE Computer Group News, March 1969, describes the transfer of 64-byte blocks as used on the I~M
360/85 when a particular byte of that block not currently in the buffer is requested. The *IBM 360/85 is described generally on pages 2 through 30 of the IBM System Journal, Vol. 71, No. 1, 1968. United States Patent No. 3,820,078 issued to Curley, et al, entitled "Multilevel Storage System Having a Buffer Store with Variable Mapping Modes" describes the transfer of blocks of 32 bytes or hold blocks of 16 bytes from main memory to the high speed buffer when a word ~4 bytes) of the block or half-block is requested by the CPU. United States Patent No. 3,896,419 issued to Lange, et al~
entitled "Cache Memory Store in a Processor of a Data Processing System" describes the transfer of a four word block from main *Trademark - 4 -memory to the high speed bu~fer when a word o-~ that block is requested by -the CPU. Unitecl States Patent No. 3,898,62~ issued to Tobias entitled "Data Processing System with Variable Prefetch and Replacement Algorithms" describes the prefetching of the next line (32 bytes) from main memory to the high speed buffer when a specific byte is requested by the CPU of the previous line.
In minicomputers, particularly those minicomputers which are organized in such a fashion that a plurality of system ~mits are connected in common to a system bus, the prior art systems present a number of problems all having to do with reducing the throughput of the minicomputer. The prior art sends back to cache from main memory, the entire block of words in which the requested word is located. This includes words with addresses preceding the requested word and words with addresses following the requested words. In most cases the CPU will require as the following cycle the word in the next higher address. This re-sults in words with high probability of being used as well as words with lower probability of being used being transferred, into cache. To overcome this problem, the prior art requires that the programmers on the operating system optimi~e their programs to start sequences off with words at the first address of each block. Another problem in the prior art is that a block of words transferred from main memory to cache comes over in successive cycles, for example, a 32 byte block may be trans-ferred in 8 cycles, ~ bytes at a time. In the minicomputer bus architecture system this would greatly reduce the throughput of the system.

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~3.2~B'73 To improve l)erformance in-terleavecl main memorics are utili~ecl. (See United States Patent No. 3,796,996 issued March 12, 197~1, entitled "Main Memory Reconfiguration"). Interleaving main memory modules permit the cache memory Imit to perform contiguous read requests for acljacent words in main memory without waiting for the first word to be delivered before re-questing the second word. This is possible with main memory modules when the adjacent locations -reside in separate modules.
This is accomplished by having all even addresses reside within one or more memory modules and all odd addresses are within an equal number of modules.
Howeverl interleaving of cache memory to reflect the inter-leaving of main memory, and more particularly, in a system where communications is via a system bus is not, to the applicants' knowledge, found in the prior art.
Additionally, a product that has greater diversity of options is a more saleable product. Accordingly, it is de-sirable to not only have an interleaved mode of operation, but a banked mode of operation, as well, and that each mode of cache memory operation be capable o:E operating in either single pull or double pull operation.
What was needed, therefore, was a cache memory system which not only communicated to main memory via a bus system, and to the CPU via a private bus system, but could operate in any of the following word modes:
l. Single pull banked;

2. Double pull banked;

3. Single pull interleaved;

4. Double pull interleaved.

J~ 73 OBJECTS OF TIIE INVENTION
l-t is an objcct of the invention to providc an improved cache mcmory system.
It is another object of the invent.ion to provide an im-proved cache ~emory system for use i.n a computer system of the type utilizing a bus architecture.
It is still another object of the invention to provide improved transfer of information between cache memory and main memory and from cache memory to CPU.
It is a further object of the invention to provide a multi-configurable cache store unit which operates in any of the following word modes:
1. Single pull banked;
2. Double pull banked;
3. Single pull interleaved;
4. Double pull interleaved.
SUM~RY OF THE INVENTION
In a data processing system which includes a plurality of system units such as a central processing unit CPU, main memory, and cache memory all coupled to a system bus and communicating with each other via the system bus, and also having a private CPU-cache memory interface for permitting direct cache memory read access by the CPU, a multi-configurable cache store unit for permitting cache memory to operate in any of the following word modes:
1. Banked Single Pull A request from cache memory reads one address to : a banked word-organized main memory, and receives in response one data word from that address of main memory.

2. Banked Double Pull A request from cache memory reads one address to a banked word-organizhd main memory, and receives in response two data words from consecutive adjacent word addresses.
3. Interleaved Single Pull Two successive adjacent address requests are sent from cache memory, one address to each of two modules of main memory, and the cache memory receives in response two words, one word from each module.
4. Interleaved Double Pull Two successive address requests are sent from cache memory, one address to each module of two modules of main memory, and the cache memory receives in response a total of four words, two words each Erom each module.
In response to the first request, the words from a first and third address are received from the first module; whereas in response to the second request the words from a second and fourth address are received from the second module.
The number of words read is a function of the main store configura-tion, and the amount of memory interference from I/0 controllers and other subsystems. The number ranges from one to four under the various configura-tions.
In accordance with the present invention, there is provided in a data processing system which includes at least one central processing unit (CPU), at least one main memory, and at least one cache store all coupled to a system bus for communicating with each other via said system bus, a portion of said main memory being partitioned in modules, predetermined ones of said modules being word-organized in banked mode wherein words are stored sequential-ly at numerical addresses 0 to n, and predetermined others of said modules being word-organized in interleaved mode wherein pairs of modules wherein a first of said pairs of modules has the even numerical addresses and a second of said pairs of modules has the odd numerical addresses, and said words are stored sequentially at said even and odd addresses alternating between said pairs of modules, a multi-configurable cache store unit for permitting cache memory to read words from said main memory in any of a plurality of word modes, ~2~;~373 said multi-conLigur~ble cache store comprising:
a. first means responsive to said cache store Eor reading one word from a selected one of said bankecl word-organized modules in said main memory;
and, b. second means respons-lve to said cache store for reading two successive adjacent words from a selected pair of interleaved word organized modules of said main memory, one word being read from said first of said pairs of modules and another word being read from said second of said pairs of mod-ules of said main memory.
Brief Description of the Drawings The manner in which the apparatus of the present invention is constructed and its mode of operation can best be understood in the light of the following detailed description, together with the accompanying drawings, in which:
Figure 1 is a general block diagram for one type of communication bus utilized by the cache memory, main memory and CPU.
Figures la and lb illustrate the format of the address bus and data bus of the bus system of Figure 1.
Figure 2 is a general block diagram of another type of bus utilized by the main memory, cache memory and CPU.
Figures 2a-2d illustrate the format of various information transfer-red over the bus of Figure 2.

- 8a -3'73 Figure 3 is a general block diagram of the present invention.
Figure ~ is a general block diagram of the system bus interface units.
Figure 5 is an illustration of a timing diagram of the operation of the bus of the present invention.
Figures 6a and 6b are logic block diagrams of a portion of the input/output IOM bus interface.
Figure 7 is a block diagram illustrating the transfer of the de-vice address information from the data bus to the address bus.
Figures 8a-8d illustrate the format of various information during a read cycle.
Figure 9 is a detailed logic block diagram of the bus interface to a typical device controller coupled to the bus.
Figure 10 is a detailed logic block diagram of the bus interface with a typical memory controller.
Figure 11 is a detailed logic block diagram of a typical system bus interface.
Figure 12 is a diagramatic representation of the private cache memory CPU interface.
Figure 13 is a detailed logic block diagram of the private cache memory CPU interface.
Figure 1~ is a detailed block diagram of CPU serviee logic.
Figure 15 is a cache/clock timing diagram.
Figures 16a and 16b are schematical representations of banked and interleaved configurations respectively.
Figure 17a is a schematic diagram showing the main memory to cache mapping.
Figure 17b is a schematic diagram showing the CPU/cache absolute main memory addressing concept.
Figures 18a and 18b are schematic drawings of the CPU read request cachc~ mallagCment Ullit.
Figure 18c is a schematic diagram of the memory select switches.
Figure 19 is a logic block diagram of the cache memory system .igure 20 is a logic block diagram of the read request logic.
Figure 2l is a logic block diagram of the cache system bus con-trol logic.
Figures 22a and 22b are logic block diagrams of replacement address file (RAF).
Figure 23 is a second cycle RAF mode timing diagram.
Figure 24 is a third cycle RAF mode timing diagram.
Figure 25 is a fourth cycle RAF mode timing diagram.
Figure 26 is a logic block diagram of the data counter.
Figure 27 is the logic symbology for symbols where utilized in this application.
DETAILED DESCRIPTION OF T~IE PREFERRED EMBODIMENT
The data processing bus of the present invention provides one com-munication path between two units in a given system. Figure 1 illustrates one type of bus wherein the controllers are coupled on the same bus as the memories and the processors. The bus utilizes 24 bits for addressing and 20 bits for data -- 18 bits including an A and B bit and 2 additional bits for parity This type of bus is described in detail in the above-referenced allowed United States Patent Application 591,964, filed June 30, 1975 and now issued into ~nited States Patent No. 39993,981 and assigned to the same assignee as the instant inventioll and included herein by reference. It should be noted that Figure 1 of the referenced application includes more devices attached to the bus than shown on Figure 1 of the instant applica-tion. It should be understood, however, that any number of devices up to the maxim~ for which the bus was designed may be coupled to the bus.
Another bus is illustrated in Figure 2 wherein the basic bus sys-tem is divided into 2 buses, an I/O bus and a system bus separated by an ~.r~;

37;3 input/o~ltput multiplexor (lOM) 11. In this type of bus system, the l/O bus interfaces all the I/O controllers whereas the system bus interfaces the memories and processors. A typical word format of the bus system of Figure 2 is shown on Figures 2a-2d wherein Figure 2a is the address portion of the bus and Figures 2b and 2d are data formats. It should be understood that other formats with clifferent word lengths can also be used. Although a few typical controllers are shown coupled to the I/O bus, it is designed to have up to 46 connectible ~mits. However, the number of I/O devices support-ed on a single I/O bus may be greater than this number because many of the units support several I/O devices at the same time. Similarly, although 2 memory devices and one processor are shown connected to the system bus of Figure 2, several such units may be connected up to their maximum allowable for any system, including subsets of memory such as cache memory, pages, etc.
A main feature of these types of buses is that communication may be established directly between units on a bus such as for example, between N~IL memory 1 and NML controller 3, or between HNP controller 5 and HNP mem-ory 9 without any intervention from a central processing unit.
Referring to Figure 1 and to the above-referenced patent no.
3,993,9~1, a typical NML bus system includes a multi-line bus l00 coupled with an NML memory 1 and an NML memory 2. Also, on the same bus there is shown a typical NML controller 3 for communications, a typical NML controller 3a, an NML processor 4, a typical CPU 4a and a typical cache memory la. Also connected on the bus may be included, for example, a scientific arithmetic unit and various controllers which in turn are themselves coupled to control other peripheral devices such as unit record or tape peripheral devices.
NML controller 3 may be used to provide communications control via modem devices. (See above referenced patent no. 3,993,981).
Referring now to Figure 2, the HNP bus 200 is shown with some typ-ical units connected thereto. It should be understood that according to the design, many units beyond those shown can be coupled thereto, although for ~

~Z~ 73 the purposes of disclosing this invention, the typical Imits shown herein suffice. The HNP bus 200 is comprised of the I/O bus 201 and the system bus 202. As previously noted, the controllers are coupled to the I/O bus 201 such as HNP controllers 1 through N, 5, 6 and NML controller 7. On the system portion of the bus 202, typical HNP memories I through ~, ~, 9 and typical HNP processor 10, a typical CPU 12 and a typical cache memory 13 are coupled. Also coupled to the system bus 202 may be included for example, a scientific arithmetic unit (not shown) and various peripheral devices such as mass storage devices, tape devices, and unit record devices (also not shown). The input/output multiplexor (IOM) 11 provides a path for data and control information between components attached to the HNP system bus such as the main storage units or the central processors ~nd the I/0 controller (sometimes referred herein as channels) attached to the HNP I/O bus 201.
The IOM consists of four major units -- the input/output bus inter-face, the system bus interface, a data pump, and an I/O processor. However, since these units are not necessary to the practice of the instant inven-tion, only that portion of the IOM on Figures 6a and 6b are shown and de-scribed.
The HNP bus 200 permits any two units on that bus to communicate with each other. Any unit wishing to communicate, requests a bus cycle (see Figure 5) described further infra. When that bus cycle is granted, that ~-~ unit ~the source) may address any o~her unit (the destination) on the bus.
j~ Information transfers during that specific bus cycle are in one direction only which is from source to destination. Some types of bus interchange re-quire a response ~read memory, for example). In that case, the requestor indicates that a response is required and identifies itself. When the re-quired information is available, the original destination becomes the source for an additional bus cycle which supplies the information to the requesting unit. This completes the interchange which has taken two bus cycles in this case. Intervening time on the bus between these two cycles may be used for '~

-~2~373 other additional systems trafic.
A source may address any other unit on the bus as a destination.
The address of each unit is identified by a channel number with the excep-tion of the memory type units which are identified by their memory address.
A channel number is assigned for each such device. Full duplex devices as well as half duplex devices may utilize two channel numbers; some HNP full duplex channels, however, require only one number. Output only or input only devices use only one channel number each. Channel numbers are usually variable and accordingly one or more hexadecimal rotary switches (thumb-wheel switch) may be utilized for each such unit connected with the bus toindicate or set to the unit address. Thus, when a system is configured, the channel number may be designated for the particular unit connected to the bus as may be appropriate for that particular system. Units with multiple input/outpùt (I/0) ports generally require a block of consecutive channel numbers. By way of example, a four port unit:-may use rotary switches to assign the upper seven bits of a channel number and may use the lower order three bits thereof to define the port number to distinguish input ports from output ports. A source ~sometimes called a master unit in this applica-tion) addresses a destination (sometimes called a slave unit in this appli-~ 20 cation) by placing a destination address on the address leads of the address -~ bus. There are 24 address leads which can have either of two interpreta-` ~ tions depending on the state of an accompanying control lead, called memory reference (BSMREF-). When a master unit is addressing a slave unit and that slave unit is a memory, the ormat of Figure 2a is utilized. ~his is indi-cated by having the memory reference signal BSMREF true. However, when the master unit is addressing a slave unit, which is not a memory, then the mem-~ ory reference signal BSMREF is false and the format of Figure 8c is utilized.
; When a source or master unit requires a response from the destina-; tion or slave unit, such as in a read operation, it indicates this to the destination by a control bit signal named Response Required (BSRSVP+). In '' , 1~2~73 addition, the source provides its own identity to the destinat;on by pro-viding its ch~nnel number comprising generally ten bits on the data bus along ~ith the address on tlle address bus; addltional control information is also provided on the data bus on the lowest order six bits. When a re-sponse is required, tllerefore, by a source from a destination, the address is provided on the address bus and will take the format of Figure 2a or Fig-ure 8c depending on the type of destination being addressed -- memory being addressed by the format of 2a and other type units by the format of Figure 8c. Moreover, when a response is required from the destination being ad-dressed, the source additionally provides its own address, i.e. channel num-ber on the first high order ten bits of the data bus and also provides con-trol information on the six low order bits of the address bus. This latter operation is provided in two bus cycles.
Referring now to Figures 2a-2d, there is shown some typical ad-dress and data formats of the HNP bus system 200. The first five bits of the address format of Figure 2a including the P, I, S, F and RFU bits. The only bit required to practice the invention is the F bit or format bit.
This bit will be described in greater detail infra. Bits 5 through 23 are utilized to address a memory Iocation. Figure 2b illustrates the way the data is formatted on the data bus of the HNP bus system. It was previously shown that the data bus format of the ~L bus system of Figure 1 had the format of Figure lb; that is, there were two contiguous bytes each byte con-sisting of 9 bits each plus 2 parity bits -- a total of 20 bits. The format of Figure 2b, on the other hand, also has 20 bits and includes an A bit on the high order side, a B bit between bits 7 and 8 and 2, 8-bit bytes com-prised of bits 0-7 and bits 8-15. The format of Figure 2c is utilized when data from the NML bus having the format of Figure lb is to be utilized as data in the HNP bus. Since the HNP bus has a data format as shown on Figure 2b comprising a total of 20 bits, the data of the NML bus with a format of Figure lb must be realigned to a format as shown on Figure 2d. This fo~nat ''`~:.

has a zero in tlle highest bit position and also anot}ler zero between bits 7 and 8. Accordingly, bits 0-7 o Figure lb occupy bits 0-7 of Figure 2c and bits 8-15 of Figure lb occupy bit position 8-15 of Figure 2c. This transformation is easily accomplished as clescribed in Canadian Patent Ap-plication 288,344 entitled "Automatic Data Steering and Data Formatting ~lechanism", filed October 7, 1977, and assigned to the instant assignee.
Referring to Figure 4, of Serial No. 288,344 application there is shown connections for driver/receiver A and driver/receiver B. Driver/receiver A
has connections for bits in accordance with the format of Figure 2c while driver/receiver B has connections in accordance with the format of Figure lb. It will be seen that the A and B bits of driver/receiver A is coupled to an X terminal on driver/receiver B. The X indicates that that position is always zero. Hence, with this simple interconnection, formats of Figure lb may be transformed to formats of Figure 2c and vice versa.
Figure 2d illustrates still another word format utilized by the HNP bus 200 when storing certain types of information into the memory unit connected to that bus. In that format, the A and B bits occupy the two high order bit positions with two, eight bit bytes being stored contiguously in the remaining low order bit positions.
~ 20 As previously noted, the formats of Figures 8a-8d are utilized ; when a source addresses a destination and expects a reply. As previously noted, Figures 8a and 8c illustrate the formats of the address bus when the source is addressing a memory type device and any other type device respec-tively. Figure 8b is the format of the data bus when a source is addressing a destination and is expecting an answer, and hence is providing its own address ~i.e. the channel member) on the data bus. Referring to Figure 8a, bits O through 23 may be utilized for addressing a particular word in mem-ory. An alternative format is shown on Figure 2a where a smaller memory is being addressed and the high order bits are utilized as control information.
Referring to Figure 8c, the first 8 bits may be utilized for varying uses.

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Bits 8 through 17 are the channel number o-f the destination being addressed, whereas bits 18 through 23 are control bits. Rcferring to Figure 8d, one data format of an ~INP memory is shown and includes the A and B bits in the high order bit positions with 2, 8-bit bytes in the low order positions.
Figure 8d and Figure 2d are similar; however, the format has also been in-cluded in this second grouping, because it will facilitate the explanation of a read cycle to be later more fully discussed.
Referring to Figures 6a and 6b, there is shown the circuits for generating the selector code for selecting the appropriate format. NAND
gates 26, 27 and 16 generate the signals ISLRDO + 00, ISLRDl + 00, and ISLRD2 + 00 respectively, and these same signals form the selection code shown on the right hand edge of block 300 of Figure 3 of the Serial No.
288,344 reference supra. In order to select, for example, BIDI (1-8, 10-17) 305, the code 011 must be generated. This means that the signal ISLRDO + 00 must be low or binary zero whereas the signal ISLRDl + 00 and ISLRD2 + 00 ;~ must be high or binary one. Hence, referring to Figures 6a and 6b, NAND
gate 26 must provide a low OT a binary zero signal and NAND gates 27 and 16 respectively must provide high or binary one signals. In order for NAND
gate 26 to be low, both input signals to NAND gate 26, ISLRDO + OA and ISLRDO + OB must be high. The ISLRDO + OA signal is the signal that con-~ trols placing of I/O bus data on the system data bus ~when logic one); or ;~ placing channel number and format control bits of the data bus ~when logic zero); and the ISLRDO + OB is the signal used only by the IOM Processor ~not shown) when it is reading or writing the external I/O or System Bus. In order for the ISLRDO + OB signal to be high, at least one input signal to NAND gate 31 must be low, such as the IOPCYC + 00 signal or RSLR18 + 00 sig-nal. The IOPCYC + 00 signal is low if the IOM processor ~not shown) within the IOM is not accessing an extarnal I/O bu~ or System Bus; it is high if the IOM processor is accessing an external I/O or System Bus. Similarly, the RSLR18 + 00 signal is utilized to indicate that the IOM processor (not .

.g ~' ~

~lZ~ 3'73 shown) is accessing a bus when it is high.
In addition to inyut signal ISLRDO + OB being high, the input sig-nal ISLRDO + OA to NAND gate 26 must also be high in order to have output sivnal IS~RDO + 00 low. The ISLRDO -~ OA signal will be high when both in-put signals to NOR gate 28 are low. Both input signals through NOR gate 28 will be low when the output signals from AND gates 29 and 30 respectively are also low. The output signals from AND gates 29 and 30 will be low when at least one of the input signals to each of AND gates 29 and 30 is low.
Accordingly, input signal IOMCYC + 00 or input signal BMREFD-10 to AND gate -~ 10 29 must be low or both must be low for a low output signal on AND gate 29.
SimilarlyJ input signal IOMCYC + 00 and input signal BIACOL-10 to AND gate 30 or both must be low for a low output signal from AND gate 30. Signal IOhlCYC + 00 is low when a transfer from the I/O bus 201 to the system bus 202 is not taking place. Signal BMREFD-10 is low when a direct memory reference from the I/O bus 201 to any memory module 8 or 9 on the system bus 202 is not taking place. Similarly, the IOMCYC + 00 signal on AND gate 30 may be low as previously described; and signal BIACOl-10 will be high when a re-sponse cycle is not required of the system bus. With these conditions met, a lo~Y output signal will be generated on AND gate 26. This represents the .:
high order bit of the selector code and for this example is a binary zero.
The next highmost order bit of the selector code is provided at the output of NAND gate 27 as signal ISLRDl + 00. For this same example, it is re-quired that this signal be high. This signal will be high when either in-put signals ISLRDI + OA or IOMCYC-OO to NAND gate 27 or both are low. The ISLRDI + OA signal is low when IOM Processor ~not shown) is reading I/O
bus 201. The IOMCYC + 00 signal is low when no transfer from the I/O bus 201 to the system bus 202 is taking place and conversely it is high when a ; transfer from the I~O bus to the system bus is taking place. One input sig-nal to NAND gate 27 is low when the output signal of NAND gate 32 is also low, and this is low when either of the input signals or both to NAND gate .~

~ .

32 is high. The input signal IOPCYC + 00 to NAND gate 32 is high if an IOM
processor ~not shown) withill the IOM is accessing an external I/O or system bus; and conversely, it is low if the IOM processor (not shown) in the IOM
is accessing an external I/O or system bus. The RSLRl9 -~ 00 signal is high when the IOM processor ~not shown) is accessing the I/O bus; and conversely, it is low when an IOM processor is accessing the system bus. Accordingly, it has been shown how the next most high order bit of the selector code is generated. Finally, to generate the lowest order bit of the selector code, NAND gate 16 must be high for this particular example where we are selecting element 305 having selector code 011. Output signal ISLRD2 + 00 on NAND
gate 16 is high when either or both of its input signals are low. Accord-ingly, output signals from NOR gates 17 and 18 must either be both low or at least one low for this particular example. Output signal ISLRD2 + OA
from NOR gate 17 is low when either or both of its input signals are high.
High input signals to NOR gate 17 are applied when high output signals result from AND gate 19 when both input signals are high. Similarly, a high output signal will result from AND gate 20 when both its input signals are high. The IOPCYC + 00 signal is high when the IOM processor is accessing an external I/O or system bus register (not shown). The RSLR20 + 00 signal is high when IOM processor is reading the external I/O or system bus reg-isters ~not shown). Similarly, input signal BMWRTD + 10 is high when there is a direct memory write operation from the I/O bus 201 to the memory on the system bus 202. This high signal is generated when the output of AND gate 23 is high and accordingly all input signals to AND gate 23 must also be high. Input signal IOMCYC + 00 is high if a transfer from the I/O bus 201 to the system bus 202 is taking place. Input signal BMREFD + 00 is high if a transfer of information is taking place from the I/O bus 201 to any memory 8, 9 on the system bus 202. The input signal BIACOl + 00 is high when a response cycle is not required ~e.g. writing memory by the I/O bus). With these conditions true, a high signal ISLRD2 + 00 will be generated and this ` .
;

., ~ .

';t3 will be the low order bit of the tllree bit selector code. A hlgh output signal ISLRD2 + 00 from NAND gate 16 may be similarly selected utilizing the same reasoning by following the alternate path utilizing AND gates 25, 21 and 22 and NCR gate 15. Table I below identifies the various signals utilized by Figures 6a and 6b and also their function. Accordingly, any person of ordinary skill in the art may construct the apparatus to generate the selector code signals to select a predetermined format required.
TABLE I

Signal Source of Destination Function of Name Signal of Signal Signal IOhlCYC+OO I/O Bus Interface Internal Bus High if a transfer of information from I/O bus to system bus is taking place.

Bh~EFD+OO " " " " " High if information from an I/O bus to a memory module on the system bus is taking place.

BIACOl+OO I/O Bus System Bus High when a response cycle is not required Oe the system bus.

IOPCYC+OO IOM Processor Internal Bus High if an IOM pro-cessor is aCCessillg an external I/O or system bus.

RSLR18+ " " " " A read operation on storage bit 18 only used when IOM pro-cessor is accessing ~ a bus.

; RSLRl9+00 " " " " Read operation on storage bit 19 only when IOM processor is accessing a bus.

RSLR20+00 " " " " Read only storage bit M 20 when IOM processor is accessing a bus.

BMWRTD+10 I/O Bus Inter- Internal Bus Direct memory write face from I/O bus to system bus.

, ~Z~ 73 TABLE I (CONT.) Signal Source of Destination Function of Name Signal of Signal Signal BIAI03+00 I/O Bus System Bus The format bit on the I/O bus which indicates refor-matting must take place when it is:
= 1 with write select 305 (Figure 3).
= 0 with write s01ect 304 (Figure 3).
= X with read select 309 - ~Figure 3).
~I21~00 System Bus I/O Bus Format bit from memory on BSSHBC
when:
;~ = 1 and SHBC code is 303-= 0 and SHBC code is 302.
SYSCYC+00 System Bus Internal Bus System bus to I/O
Interface ~ bus transfer.
ISLRDO+OA I/O Bus Interface ~; ISLRDO+OB IOM Processor " ";
ISLRDl+OA
ISLRDl+00 Internal Bus ~ Signal for the~
high order bit of the selector code.
ISLRD2+00 " " " " Signal for the low order bit of the selection~code. ~ `
It can be readily seen from the prevlous discussion that requeses for data from another unit or for transfer of data, etc., are made via issu~
ing predetermined signals. C:ombinations of these signals~automatically~gen-erate a code which is utilized to automatically select the proper format for the particular operation being performed or requested. Normally, transfer :
': .

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1~2~iE37';~

Gperations involve information being transEerred From the I/O data bus 201 to tlle system bus 202. Accorclingly, a transfer from the I/O bus 201 to the system ~us 202 will include in its path tile IOM ll. Information may also be transferred from tlle system bus 202 which comes into the IOM together with the control signals) to the I/O bus 201 which accepts information from the IO~I on the control signal. ~lowever, t-ransfers of information between CPU and memories are performed over the system bus lO0, 202.
Referring now to ~igure 5, the timing diagrams of the HNP bus sys-tem will be discussed in detail. ~For detailed timing of the cache memory see application no. 318,~76, entitled "~ligh Speed Buffer Memory System with Word Prefetch", and assigned to the same assignee). In every bus cycle there are three identifiable parts; more particularly, the period ~7-A to 7-C) dur-ing which the highest priority requesting device wins the bus, the period ~7-C to 7-E) during which the master unit calls a slave unit, and the period ~7-E to 7-G) during which the slave responds. When the bus is idle, the bus request signal ~BSREQT-) is a binary one. The bus request signal's negative going edge at times 7-A starts a priority net cycle. There is an asynchronous delay allowed within the system for the priority net to settle ~at times 7-B) and a master user of the bus to be selected. The next signal on the bus is the BSDCNN- or data cycle now. The BSDCNN- signal's transition to a blnary ; zero at time 7-C means that use of the bus has been granted to a master unit,.
Thereafter, the second phase of bus operation means the master has been se-lected and is now free to transfer information on the data, address and con-trol leads of the bus 200 to a slave unit that the master so designates.
The slave unit prepares to initiate the third phase of bus opera-tion beginning at the negative going edge of the strobe of BSDCND- signal.
` The strobe signal is delayed, for example, 60 nanoseconds from the negative going edge of BSDCNN- signal via a delay line ~not shown). Upon the occur-rence of the negative going edge of the BSDCNN- signal at times 7-D,; the slave unit can now test to see if this is his address and if he is being .~

called to start the decision-making process of what response it is required to generate. Typically this will cause an acknowledge signal ~BSACKR~) to be generated by the slave unit or in the non-typical cases a BSNAKR- or BSWAIT- signal or even no response at all (for the case of a non-existent slave) may be generated as herein described. The negative going edge of the acknowledge signal at time 7-E when received by the master unit, causes the master~s BSDCNN- signal to go to a binary one at time 7-F. The strobe sig-nal returns to the binary one state at time 7-G, which is a delay provided by a delay line (not shown) from time 7-P. Thus, in the third phase of bus operation, the data and address on the bus are stored by the slave unit and the bus cycle will begin to turn off. The ending of the cycle, i.e. when BSDCNN- goes to a binary one, dynamically enables another priority net resolution. A bus request signal may at this time, be generated and if not received, this means that the bus will return to the idle state, and accord-ingly the BSREQT- signal would go to the blnary one state. If the bus re-quest signal is present at that time, i.e. a binary zero as shown, it will start the asynchronous priority net selection process following which another negative going edge of the BSDCNN- signal will be enabled as shown by the dotted lines at time 7-I. It should be noted that this priority net resolu-tion need not wait or be triggered by the positive golng edge of the acknow-ledge signal at time 7-H, but may in fact be triggered at time 7-F just fol-lowing the transition of the bus to an idle state if thereafter a unit de-sires a bus cycle, this process repeats in an asynchronous manner. The in-formation which is transferred by this type of bus cycle may include 51 sig-' ~
nals which break down as follows:
` a) 24 address bits;
b) 16 data bits;
c) 6 control bits;
d) 5 integrity bits.
Having thus far described the structures and function of the bus ' ',:
.

llZ~ 3 system to which different types of system units may be connected, including main memories, and w:ith which they communicate with each other, let us focus our attention on the interface between the system bus and the bus interface unit of the cache memory 301 and a CPU 303 as shown on ~igure 3. This will be done in conjunction with Figures 3 and 7 through 11.
Referring first to Figure 3 there is shown a block diagram of CPU 312, and the cache memory unit 313 each coupled to the system bus 302 via bus interface units 301 and 303, to be described in detail infra. A
; private interface 311, also to be described in detail infra, connects the cache memory unit to the central processor unit, allowing main memory 8, 9 requests, addresses and data to be communicated between the central pro-cessor unit CPU 312 and the cache memory unit 313. The cache memory unit is disclosed in detail in Canadian Application No. 318,474, entitled "Non Block Oriented Cache Store" and assigned to the same assignee as the instant invention. The cache memory unit is comprised of four major logic units, the bus interface 301 ~to be described infra), the private interface 311 ~to be described infra) the replacement and update logic unit 314, and the cache - directory and data buffer unit 315, both described in detail in the above-referenced Canadian Application No. 318,474, entitled "Continuous Updating ; 20 of Cache Store".
The cache directory and data buEfer unit 315, determines whether ` or not the requested main memory word is present in the cache random access memory ~RAM) 313. The cache RAM 313 typically provides intermediate high-speed storage for 2,048 to 4,096 words that have been read from main mem-ory, 2 to supply data or instructions to the CPU.
The replacement and update logic unit 314 provides the hardware necessary to access main memory 1, 2 and be able to perform monitor func-tions. The monitor function checks and evaluates all main memory writer references ~i.e. from the CPU 312, 4a, 12 or the IOM 11) and replaces data in any currently active cache memory location with the data from the system .
: - 23 -'~"
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.

bus 202, 302.
The bus interface unit 301, connects the cache memory unit 313 to the system bus, enabling the cache memory unit 313 to access a main memory 1, 2 via the system bus 302 and to read out central processor unit required information not in the cache 313. Also the bus interface unit 303 connects the CPU 312 to the system bus 302 and provides logic for communication to other system units also connected to the system bus 302. The bus interface is comprised of the following: ~a) system bus interface; (b) request and priority logic; (c) address generator logic; and, (d) replacement address filed logic, all described in detail infra and in Canadian Patent Application No. 318,477, entitled "Continuous Updating of Cache Store", referenced supra and in United States Patent Nos. 4,030,075 and 3,993,981.
The CPU 312 is comprised of subsystems well known in the art such as the arithmetic and logic unit ALU 312, and the control store unit 31~.
The portion of the CPU 312 which is pertinent to the~instant invention is the bus interface unit 303, ~or control unit) to be described in detail infra also with respect to Figures 7-11.
Referring now to Figure 4 there is shown a typical system bus interface unit BIU400. Main memory requests, addresses, and data are sent and received via the CIU transmitters and receivers 401-404. (For details see Figures 7, 9-11 and description infra).
In brief, the central processor CPU 312 unit service cycle starts when the CPU simultaneously sends a memory read address ~i.e. absolute main memory address) with the Read Request Signal to address generator 406 via :
the private cache/CPU interface 311 to the cache memory unit 313. ~For de-tails of private interface 311 see Figures 12, 13, and 15, and description infra). If the cache is not in an update or replacement cycle ~i.e. the information in main memory is not being updated or the information in cache is not being replaced and replacement and update logic 408 is not activated) the CPU memory read address sent is switched into a cache directory ~not ~2 ' ,... . .

llZ~il3'73 shown) where a search and select operation is performed, generating an address ~lit or No llit indication. (Por details of cache directory see above-referenced Canadian Application No. 318,474, entitled "Non Block Oriented Cache Store").
If the searched CPU memory read address is present ~i.e. a Hit), the associated data in cache memory is sent to the CPU 312 over the private interface 311.
If the searched CPU memory read address sent was not present in the cache directory ~i.e. a No Hit), the CPU memory read address is switched to the cache memory unit address out register 405 and a No Hit main memory fetch is initiated, and the system bus is activated to obtain the faulted word. Accordingly, the main memory requests, addresses, and data are sent and received by the bus interface unit BIU 400 via BIU transmitters-receivers 401-403 and bus request and response logic 404. ~Por ~urther details see Figures 7, 9-11 and description infra). All copies of the absolute address sent to main memory are stored in the cache replacement file 407. (Details of replacement and update logic unit 408, are disclosed in Canadian Applica-tion No. 318,477, entitled "Continuous Updating of Cache Store").
Referring now to Figures 7 and 8a-8d, a source unit on I/O Bus 201 requiring a memory readout provides a memory address on the Address Bus 701.~
This memory address has the format of Figures 8a or 2a, depending on the size of the memory. At the same time the requesting or source unit on the I/O bus 201 of Figure 2 provides its address i.e. channel number and some control bits on the Data Bus 702. The information has the format shown on Flgure 8b.
The memory address from Address Bus 701 is stored in Memory Address Reglster 36 while the channel number and control bits are stored in Channel Register ; 34 and Control Bit Register 35. The memory location in memory 38 addressed by Memory Address Register 36 is read out and the data stored on Data Out Register 33. The data is then placed on the data bus when the necessary tim-ing ~see Figure 5) to complete the handshake operation of the data bus is 1~.2~ 73 complete, and a requesting unit now transformed into the receiving unit, acknowledges that it is ready to receive the data; the second bus cycle be-gins and the data from Data Out Register 33 is placed on data bus 702 and at tlle same time the channel number and control bits from registers 34 and 35 are placed on Address Bus 701 in accordance to the format of Figure 8c. (It should be noted now that this is the address format when addressing a unit other than a memory unit). Accordingly, the address i.e. channel number, is placed on the Address Bus 701 on bit positions 9-17 whereas the control bits are placed on the Address Bus 701 on bit positions 18-23. However, as pre-viously mentioned, the only bit of interest to this invention is bit 21 whichis the formatting bit. This is recogni~ed by the logic circuitry of Figure 6a as signal MMAI21+00. ~hen this bit is true, reformatting of the data is required and the type of reformatting will depend on the other signals repre-senting others requests for operations that are present. It should be also noted that Figure 6a is also responsive to formatting bit number 3 of the for-mat shown on Figure 2a and is identified as signal BIAI03+00 on Figure 6a.
It should be further noted that the format of Figure 8b corresponds to the - -format 308 in multiplexor 301 of IOM 300. Accordingly, when a read cycle is requested by a source unit from a memory unit, the data bus is automatically reformatted by the invention as previously discussed in detail with respect to other types of examples.
Referring now to Figure 9 there is shown a typical controller ad-dress logic. This logic is exemplary of controllers particularly those types having up to four subunits or peripheral devices connected thereto. Element 70 includes line receivers, one for the memory reference signal ~BSMREF-), and the others, one each, for the bus address BSAD08- to BSAD14-. Because this logic in Figure 9 is for a non-memory controller, a memory reference sig-nal is a binary one, both at the input of element 70 and the output of invert-er 71.
A switch 72 is coupled to receive the address leads as well as the ~ 26 -.,, inversion thereof vla inverters 78. This switch is located in most device controllers connected to the bus 200 and is set to the address of the par-ticular unit. The ~us address leads at the input side of element 70, are a binary zero for those bits which reflect the proper address of the desired unit. Accordingly, with the inversion provided by element 70, binary one signals are provided at the non-inverted inputs of switch 72 for those bits of the address which were received on bus 200 as binary zeroes. Similarly, the output leads from the inverters 78 ~there being as many inverters as there are leads) have binary ones for those positions in which the address bits are binary ones on the incoming address bits on bus 200. With the sig-nals at the two inputs of switch 72 the complements of each other, the switches therein, which may be a hexadecimal switch or a plurality of toggle switches, more particularly a non-ganged seven pole, two position switch, are set so that for the correct device address, all binary one signals appear at the output terminals of switch 72. Thus, gate 73 will receive all binary one signals and will provide a binary zero at its output if this is the proper device address and if this is not a memory cycle as shall be ex-plained. It can be seen that the switch 72 is arranged so as to provide a comparator function and eliminates the need for at least one level of gating ; 20 and accordingly the associated propagation delay therefor. Further, the sNitch provides an easy means for changing the address of a particular unit ; thereby simplifying the manner in which a system may be configured.
The output of gate 73 is referred to as the MYCHAN- signal and will be a binary zero for the selected slave. The MYCHAN-signal is coupled to one input of each of the three NOR gates 74, 75 and 76 and, as shall be seen, is utilized to generate the ACK, WAIT, or NAK signal. The other in-puts to gates 74, 75 and 76 are received as follows.
Multiplexor 77 is coupled to receive four signals ~although a greater or lesser number may be utilized) from respectively up to four sub-units or peripheral devices connected with the particular controller logic _ 27 -''".
,, ' ' ~. '' 112~;~37~3 as shown in Figure 9. These signals received at the inputs of multiplexor 77 indicate respectively whether or not the particular subunit is present i.e. installed in the system. That is, one or more of such subunits may be connected. If only one is so connected, the only one of such signals will indicate the presence of a subunit. These signals indicating that the subunits are present are indicated as the h~DEVA-, MYDEVB-, MYDEVC-, and the h~DEVD- signals. Multiplexor 77 as well as multiplexor 88 to be here-inafter discussed may be that device mamlfactured by Texas Instruments hav-ing part number 74S151. The binary zero state of such signals indicates that the subunit is present in the system. The multiplexor 77 is enabled by the address signals BSAD15+ and BSAD16+ received from the bus 200 via inverting amplifiers or receivers not shown. The same two address signals are coupled to enable multiplexor 88. These two bits indicate which one of the, by way of illustration, up to four subunits or devices is being ad-dressed. The output of multiplexor 77 is the MNDEVP-signal which, when a binary zero, indicates that the device addressed is present. Thus, each of the gates 74, 75 and 76 receive the output from multiplexor 77 and accord-ingly a response from a particular controller is governed by the presence of the controller's channel number and the fact that the controller actually has the subunit attached and present in the system. As shall be discussed hereinafter, this arrangement allows continuity in addresses between ane subunit to the next in a manner to be more particularly discussed with ref-erence to the memory address logic. In general, however, with more than one basic device controller 5-7 as shown in Figure 2 in the system, and with ; each such controller 5-7 coupled to control different types of peripheral devices, or with all such controllers 5-7 coupled to control the same type of peripherals by selectively arranging such peripherals with the controller, the addresses for each such subunit or peripheral may be contiguous. Fur-ther, such addresses may be configured so that no matter how large or small the system, a particular address may have any type of peripheral device .` .

- ~ : .

~Z~il373 associated therewith.
The other multiplexor 88 is coupled to receive indications from any one of the four sub~mits, for example to indicate that in ~act such subunit is ready to receive or send data. Thus, the ready signals received by multiplexor 88 are different from the presence signals received by multi-plexor 77. Whereas the presence signals indicate whether or not the par-ticular subunit or peripheral device is installed and present in the system, the ready signal indicates dynamically whether the associated subunit is ready and capable of sending data or receiving data. These ready signals are referred to as MYRDYA-, hlYRDYB-, h~YRDYC- and hlYRDYD-.
The output of multiplexor 88 labelled hlYRDYS-, when a logical zero, enables the generation of either a IVAIT signal or the ACK signal de-pending upon the state of the ot'ner signals received at the gates 74, 75 and 76. If a binary zero is generated at the hlYRDYS+ output of multiplexor 88, a NAK signal will be generated thus indicating that the addressed sub-unit is not in fact ready.
Gates 75 and 76 receive other signals, gate 75 receiving the BDRBSY- signal as shall be explained hereinafter and gate 76 receiving the h~ACKA- signal from the output of gate 84. These two s'ignals are explained with reference to the functions provided by flip-flops 80 and 81. In each controller, *here is a buffer or register which accepts the data from the bus system 200. I this data buffer is busy, that is, it already has in-formation stored therein which cannot be lost, then there will be an indi-cati~n that the buffer is busy and this will be received at the D input of D-type flip-flop 80, whose D input will be reflected at the Q output thereof upon receipt of the clock signal which in this case is the BSDCNN+ signal received via a driver from the bus. Thus, at the time the data cycle now signal i.e. the BSDCNN- signal, goes to the binary zero state as shown in ~ Figure 5, if the buffer associated with this particular controller is in ; 30 fact busy, then the Q output of flip-flop 80 i.e. the BDRBSY+ signal will ' ' .

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be a binary one wllich via NAND gate 85 will be a binary zero. This binary ~ero state coupled to tl~e input of NOR gate 84 will generate a binary one at its output, which will then inhibit gate 76 from generating an ACK sig-nal. However, the Q output of flip-flop 80, i.e. the BDRBSY- signal will be binary zero which will be provided at one input of gate 75, which if all the inputs are binary zeroes, will generate a WAIT signal. Thus, if the buffer is not busy and other conditions exist, an ACK signal will be gen-erated. If the buffer is busy, then either a WAIT signal or a NAK signal, depending upon the other conditions, will be generated.
The flip-flop 81 is used to indicate whether or not this is a sec-ond half read cycle operation. As discussed hereinbefore, the BSSHBC- sig-nal is used by the master to indicate to the slave that this is the infor-mation previously requested. From the time a pair of devices coupled with the bus has started a read operation (indicated by RSWRIT-) until the sec-~
ond cycle occurs to complete the transfer, (indicated by BSSHBC-), both de-vices may be busy to all other devices on the bus. Thus, looking at the in-puts of flip-flop 81, the MYDCNN+ signal clocks the flip-flop, such signal coupled to and being the logical equivalent to the Q outpùt of the grant flip-flop 22 of the device which has become the master. Received at the D
input of flip-flop 81, is the MYWRIT- signal which means that this was the particular device which started the memory read cycle and that such device is now waiting to read from the memory and that such particular dsvice is expecting a second half read cycle to be later generated by the memory as the memory completes the cycle.
The second half read cycle history flip-flop 81 has as its reset inputs, the MYACKR+ and the BSMCLR+ signals, both coupled to the reset in-put via NOR gate 82. The BSMCLR+ signal acts to reset flip-flop 81 as dis-cussed hereinbefore for various other flip-flops and the MYACKR+ signal in-dicates that the second half read cycle is complete. Thus, if the flip-flop 81 is set, this set condition is coupled from the O output of flip-flop ~ z~ 73 81 to partially enable one input of AND gate 83. In order to fully enable AND gate 83, the BSS~IBC+ signal must be generated by the memory, indicating that this is the information previously requested. Thus, with the data coming from memory via the bus, this signal is activated and via NOR gate 84, the negative going edge of the MYACKA- signal is generated which per-mits the particular device to acknowledge this bus cycle by the enabling of gate 76 and via element 79, generating the ACK signal via driver 90. In addition and as indicated hereinbeore, an ACK acknowledgement may also be generated if in fact this is not a second half bus cycle and the buffer is not busy. This indication is provided by gate 85 through gate 84 in order to generate the ACK signal.
Thus, if the particular controller is waiting for a bus cycle, having had its second half read history flip-flop 81 set, then only the receipt of a second half bus cycle signal (BSSHBC+) can be responded to for this particular device. If this par~icular device is not busy, i.e. if there is no longer any useful information in such buffer, then an ACK signal may be generated.
In addition, the second half bus cycle signal ~BSSHBC+) is re-ceived at one input of gate 74 as well as gate 75. When the second half read cycle flip-flop 81 has been set, the only output that can be obtained if this is the correct channel number, etc. as indicated by the inputs at gate 76, is an ACK signal. This is independent of whether or not the buffer is busy as indicated by flip-flop 80. Thus, a NACK signal or a WAIT signal will be generated by gates 74 and 75 only if this is not a second half bus cycle signal i.e. that the signal BSSHBC+ is a binary ~ero. In further ex-planation, a second half bus cycle received by the controller can come, only from the controller's point of view, from a memory and when the memory is ready to return the data to the controller, neither a NAK nor a WAIT signal can be generated, but rather only an acknowledge signal can be generated.
~hus, if the BSSHBC+ signal is a binary one, then neither the NAK nor the :

~6l~3'73 WAIT signals can be generated.
As indicated hereinbefore, when information is being transferred from the memory, the memory can never receive a NAK or WAIT signal. This is because of the inherent priority arrangement of the apparatus of the present invention. The memory is the highest priority device. If a unit has asked memory to send it information, then the unit can expect the in-formation at some point in time. If the unit generates a WAIT or NAK sig-nal to the memory, then because the memory is the highest priority device, the memory could keep trying to gain access to the particular controller which requested the data transfer and could hang up the bus i.e. it could because the memory is the highest priority device, cause the bus to effec-tively disable further data transfers until the data is accepted by the par-ticular controller which had previously asked for it. Thus, only an acknow-ledge signal can be made in response to a request from memory to accept data. A controller, however, is allowed to generate a NAK or l~AIT signal to another controller or a central processor. In addition, a general rule is that if one controller requests information from a controller of higher priority, the requesting controller must be read to accept the information, and accordingly must respond with an ACK signal.
With respect to the ready multiplexor 88, as indicated herein-before, if the device is not ready, then the NAK signal, other conditions being met, will be generated. The reason the NAK signal is generated rather than the WAIT signal is because of the fact that typically, if a controller such as controller 210, is busy, the terminal will be busy more than just a few microseconds, but rather will be busy for milliseconds. Thus, cycle time would be wasted if the indication to the master is that the master keep trying. Rather, the indication should be that the requesting unit go on with data processing rather than unnecessarily using bus cycles thersby de-laying the overall response of the system. All the requesting unit has to do is at its convenience retry the destination unit.

~ ' , 1~68~73 As indicated hereinbefore, the strobe input of multiplexor 88 re-ceives a signal from gate 86 identified as the MYFC01+ signal. This signal is a combination of the function code of the signals received at the input of NOR gate 86, such control bit or function code shown specifically in 8c, and identified as bits 18 through 22 with bit 23 not used. Within these bits, the function code is indicated so that the various units connected to the bus may recognize certain codes and commands, as hereinbefore discussed.
In summary, the NAK signal ~BSNAKR-) is generated via driver 92 from the respective D-type flip-flop of element 79, by the full enabling of gate 74, and when BSDCND+ signal clocks such flip-flop. Gate 74 is fully enabled when the channel number is received, the device address provides an indication that it is in fact installed, that such device is not ready and that this is not a second half bus cycle. The WAIT signal (BSWAIT-) is pro-vided on the bus via driver 91 from its D-type flip-flop inciuded in element 79 when gate 74 is fuily enabled. Gate 75 is fully enabled when the channel number is received, the device address provides an indication that it is in fact installed and that it is in fact ready, that there is an indication that this is not a second half bus cycle and that the buffer is busy. The acknowledge (BSACKR-) signal is provided on the bus by means of driver 90 in response to the D-type flip-flop included in element 79 when gate 76 is fully enabled. Gate 76 is fully enabled when the correct channel number is re-ceived, an indication that the device address as installed is provided, that ~- such device addressed is in fact ready and that the buffer is not busy. How-ever, should a second halE read cycle signal be received, then an ACK~acknow-ledge signal will be generated independent of whether or not the buffer is busy or not. Each of the flip-flops in element 79 is cleared in response to the BSDCNB- signal received from the output of gate 26 shown in Figure 8, via inverter 89.
Having described a typical controller's address logic, such as con-trollers 5-7, typical address logic for a memory controller shall now be ~' ~
.
. .
.

1~26l~3'73 discussed. The memory controller logic of Figure 10 is in many ways similar to the logic of Figure 9. The address signal received by element 40 from the bus, is transferred as the bus address signals BSADOO+ through BSAD07~
in the format shown in Figure 8a. The address signals from receiver 40 are also received at the inputs of parity checker 47. The address signals from receiver 40 and also those at the output of inverters 41 are received by a switch 42 in the same manner as indicated for Figure 9. If the memory ref-erence signal ~BSMREF+) is a binary one, and the address compared by switch 42 generates all binary ones at the output of switch 42, then NAND gate 43 Will be fully enabled to provide a binary zero signal on the MYMADD- line which is received at one input of each of the three NOR gates 44, 45 and 46 which are utilized to generate the NAK, WAIT and ACK signals respectively.
The memory cannot be address unless in fact the BSMREF+ signal is in the correct binary state.
As indicated, the addressed bits are received at the inputs of parity checker 47 which in addition receives the BSAPOO+ bit which is the address parity received over the bus. Parity checker 47 makes a nine bit parity check and generates at its Q output, a signal labelled MYMADP-, which if a binary zero partially enables the gates 44, 45 and 46, thereby indicat-ing that the parity is correct.
A third input to the gates 44, 45 and 46 is received from the multiplexor 48 which is analogous to multiplexor 77 of Figure 9. Multiplexor 48 receives by way of example, four inputs labelled MYMOSA- through MYMOSD-which indicate whether or not any one or all of the memory modules connected to this particular controller are actually present in the system. This allows a memory to either have a full memory module array or allows it to have a partial array, that is, only one of such memory modules may be con-nected in the system. These four memory modules are further addressed, and via multiplexor 48 are tested to determine if they are installed by means~of the two bus address signals BSAD08+ and BSAD09+.

1~2t.1~3~73 Thus, for differently configured systems, there may be one memory module connected to one particular memory controller and there may be two such modules connected to another such controller and in fact the different memory modules connected to the different controllers may be of different types. For example, in this manner a semiconductor memory may be connected to one controller whereas a magnetic core memory may be connected to another.
Further, different size, i~e. more or less storage capacity, memory modules may be used. Further, by arranging the memory modules in different control-; lers, then different speed memories may be used thereby increasing the speed of system response. Also, for any given controller there is normally only agiven power support and timing capability and in the normal case, that con-troller establishes the personality of the memories that may connect to it.
Accordingly, for example, if there are different types of memory speeds or different types of timing required such as for example between core and semiconductor memory, then a different controller must be utilized for each type. Further, by use of different controllers, the memories can be run faster since in fact they can be run essentially parallel in time with each other, even though they are connected to the same bus, however, only one transfer can take place at a time on a bus, the point being that the infor-mation will be read in the memory without any access time required since infact the access time has already taken place.
As indicated hereinbefore, each controller whether it be for mem-ory or another peripheral device, generally has its own specific address.
- Thus, for different memory controllers having a full complement of memory modules connected thereto, contiguous memory addresses may be provided.
More specifically, assuming that each memory controller has four memory modules coupled thereto, and that each such module has the capability of about 8,000 words of storage, then each such memory controller will be able to provide access to 32,000 words of storage. With a full 32,000 words of storage coupied in the system for each memory controller, the addresses of .~ ~
. ~ ... .

3'73 the memories are contiguous. From an operations point of view, contiguous memory address is important not only for purposes of system addressing, but also for increased response in the system. As mentioned before, typically the memory controller can only provide service for a memory of a certain characteristic, i.e. a magnetic core memory cannot be coupled to the same memory controller as a semiconductor memory because of the basic timing dif-ferences associated therewith. The same is normally true for memories of different speeds or power requirements. Thus, assuming again that each mem-ory controller may provide service for 32,000 words of memory, if only 16,000 Nords of memory are to be used for low speed memory and another 16,000 words are to be used for high speed memory, this means that two mem-ory controllers must be used. However, this would typically mean that the - memory addresses between the high speed and the low speed memory would not be contiguous because the memory controller addresses are 32,000 words apart.
In this case, it is possible to provide contiguous memory addresses by allow-ing both of the memory controllers to have the same address. However, this would also mean that the respective memory module positions of the two con-trollers could not be both occupied in the same location in each such con-troller. More specifically, the first controller would utilize two 8,000 word storage locations in memory module positions A and B as indicated by the MYMOSA- and MYMOSB- signals. Thus, these two controllers appear in the system as if they were one controller. By way of further example, one such controller may have simply ~,000 words of one such memory coupled therewith in the form of one module, whereas the other memory module with the same address may have coupled therewith up to three such memory modules in the ~ other three positions to accordingly provide 24,000 words of memory storage.
; This arrangement need not necessarily be limited to different types of mem-ories, but in fact may address the problem of defective memory modules cou-pled with a controller. For example, a redundant memory module may be pro-vided coupled with another controller whose device address may be set as may ~ .
. . I

13~Z613~3 be appropriate upon detection of a failure in such memory module.
Referring again to the enabling of gates 44, 45 and 46, each of such gates in order to be enabled and allow a response from this particular memory controller, must receive its memory controller's address, an indica-tion that the module addressed exists in the system, and that the address parity is correct, as indicated by parity checker 47. The other inputs to the NOR gates are serviced from a combination of busy logic and lock history logic as presently described.
The memory controller busy signal is provided by flip-flop 49 and indicates that any one of the memory modules connected to this controller is in fact busy. This D-type flip-flop 49 is clocked by the BSDCNN+ signal.
If a memory module is busy, then a WAIT signal will be generated. Thus, if the MYBUSY- signal at the Q output of flip-flop 49 is a binary zero, this enables, if the other conditions are met, gate 45 to be fully enabled and to set the associated flip-flop in element 56, it being noted that this is done when the BSDCN+ signal is received at the clock input of element 56. At this point, it is noted that this flip-flop element 56 is cleared via in-verter 63 when the BSDCNB- signal is received as was the operation for ele-ment 79 of Figure 9. The acknowledge signal will be generated when a binary zero is generated at the Q output of flip-flop 49 as indicated by the ;;
MYBUSY+ signal coupled to one input of gate 46. It is again noted that the WAIT signal means that there will be a very short delay since the memory is still busy.
The other condition which indicates which of the ACK, NAK or WAIT
signals is to be generated, is the lock signal which as indicated herein-before comprises a multi-cycle bus transfer whereby a device can access a specific memory location without any other locked unit being able to break into the operation. The effect of this locked operation is to extend the busy condition of the memory controller beyond the completion of a single cycle for certain kinds of operations. Devices attempting to initiate a l~Z~B'73 lock operation before the last cycle of the sequence is complete will re-ceive a NAK signal. The memory will, however, still respond to a memory request as shall be presently explained. It is noted that the intervening time between these cycles may be used by other units not involved in the transfer. A locked operation is used primarily where it is desirable for two or more units or devices to share the same resource, such as memory for example. The locked operation which can include any number of bus cycles is unlocked by the particular unit or device which has had control of the shared resource. While the shared resource is locked, other units desiring to access the shared resource will be locked out if such other units present the lock control signal. If the lock control signal is not presented, it is possible for such other unit to gain access to the shared resource such as for example to process an urgent request or procedure. Before any unit presenting the lock control signal gains access to the shared resource, it tests the resource ~o see whether it is involved in a locked operation and then during the same bus cycle, if the resource is not involved in a locked operation, it may gain access to the resource.
Thus, it can be seen that the locked operation for sharing a resource is one that is effective between those unlts which issue the ap-propriate controls i.e. the lock control signal~ and may be used for examplein sharing a portion of memory in which a table of information may be stored. Further, if one of the units desires to change information in the shared resource, other units may be locked out so that they do not gain access to only partially changed information, but rather are allowed access only after all such changes have been made. A read modify write operation may be involved in such case. By use of the locked operation, it can be seen that a multiprocessing system may be supported. For example, with two central processing units connected to the same bus system 200, both may share the memory units connected to the bus without interference if the locked operation is used.

:` ~

- 112~ci8~

It is noted that the BSSHBC- signal for the locked operation, as shall be seen, is used in a somewhat different manner than has been hereto-fore discussed. During the locked operation, the BSS~IBC- signal is issued by the unit attempting to share a resource both to gain access to the shared resource by means of a test and lock procedure and to unlock the shared resource when it has completed its locked operation.
Thus, as can be seen by Figure 10, a lock history flip-flop 50 is provided, which if set, indicates that a locked operation is in process, thereby enabling a NAK signal to be issued to a requesting unit via driver 59. Assuming that the logic of Figure 10 represents the bus system 200 interface logic for the shared resource, the BSLOCK+ signal (binary one state) is received by both AND gate 52 and flip-flop D3 of element 56. Ele-ment 56 thereby generates the MYLOCK+ signal which is received at one input of AND gate 51. If the lock history flip-flop is not set, the NAKHIS+ sig-nal will be a binary zero thereby, independent of the state of the other two inputs to gate 52, generating a binary zero at one input of gate 46. If all inputs of gate 46 receive a binary zero, thereby indicating that the current address for this unit and device were received, and that the common element or buffer is not busy, then an ACK signal will be generated via element 56 .: . .
and driver 61 in response to the BSLOCK+ signal. The ACK signal will fully enable AND gate 51 to set the history flip-flop 50 in response to the binary one state of the BSSHBC- signal at the D input thereof which is received with the binary one state of the BSLOCK+ signal at the commencemen~ of the locked operation. Thus, a test and lock operation is performed during the same bus cycle.
If flip-flop 50 had already been set at the time of the receipt of the binary one state of the BSLOCK~ and BSSHBC- signals, then a binary one signal will be generated at the output of AND gate 52 thereby generating a binary zero state at the output of inverter 58 so as to enable AND gate 44, all other conditions having been met, to generate the NAK signal. Thus, the .

Z687~

test and lock operation would have produced a NAK response inhibiting another unit from using the shared resource.
Once the unit using the shared resource is through with its oper-ation, it must unlock the resource. This is done by receipt from the user unit of the binary one state of the BSLOCK+ signal and the binary zero state of the BSSHBC- signal. This enables the logic of ~igure 10 to provide an ACK response, enabling gate 51 and thereby effectively resetting history flip-flop 50 because of the binary zero state of the BSSHBC- signal. The shared resource is now free to make an ACK response to other units.
It can be seen that the shared resource will only lock out other units which present the binary one state of the BSLOCK+ signal. If a unit, for example, desires to gain access to a shared resource which had its his-tory flip-flop set so that the NAKHIS+ signal is a binary one, then, if the BSLOCK+ signal is a binary zero, the output of AND gate 52 will be a binary zero, thereby disabling a NAK response and enabling, dependent upon other conditions, either a WAIT or ACK response. Thus, a unit may gain access to a shared resource even though it is involved in a locked operation.
Thus, it can be seen that the generation of a WAIT signal from any one of the controllers, allows a device or controller of higher priority to break into the sequence of the bus cycles and use the bus as necessary. If .~
there is not a higher priority unit which is requesting service, the partic-ular master/slave arrangement will be maintained until the acknowledge is received by the master thereby ending the WAIT condition. Following this, another user is allowed to use the bus. Thus, the BSDCNN+ signal allows a slave to generate any one of three responses, either the NAK, WAIT or ACK
signals. At the end of any one of these responses, a new priority net cycle occurs and this particular device gains access to the bus or another higher priority device wins the bus.` It should be understood at this point that signal states on the bus are the inverse in binary state to those signaIs shown internal to the units. For example, the memory reference signal is g . ~ ~

~6Z373 referred to on the bus, between for example7 drivers 59, 60 or 61 and re-ceivers 40, to be in one state and in the opposite state in the controllers themselves. Further, as indicated hereinbefore, a fourth response between any of the controllers connected on the bus is that there is no response at all. Thus, if one of the masters is calling for service from the memory and this memory is not installed in the system, a time out element, well known in the art, will generate a signal after a certain period of time, such as for example, five microseconds, thereby genersting a ~AK signal.
At that point, a central processor may take action such as by an interrupt or trap routine.
Referring again to ~he operation of the memory busy flip-flop 40, the data input is coupled to receive the MOSBSY+ signal which is asynchron-ous to the bus operation. This signal may be received at any time regardless of the operation which is occurring on the bus for any controller. When the BSDCNN+ signal is received from the master at the clock lnput of flip-flop 49, a history is stored as to the state of the memory, i.e. whether it is busy or not at that time. Thus, this eliminates confusion in the response to the bus cycle. Without the history retention provided by flip-flop 49, it would be possible to start out the bus cycle in a WAIT condition and end up with the same bus cycle in the state which generates an ACK condition.
Thus, both responses would be made during the same bus cycle which would ~hus be an error condltion. By use of history flip-flop 49, the responss is fixed as to the condition which the controller was in at the time the BSDCNN+ signal is received, thereby allowing an asynchronous response and regardless of the tolerance or difference in memory speed.
Now referring to the typical central processor bus coupling logic of Figure 11, the signals are received from the bus by means of the receivers included in element 99. The memory reference slgnal BSMREF+ is received by one of such receivers and inverted by means of inverter 100 and provided to one input of comparator 103 so as to enable such comparator if the address .

' ~L~26~ 3 being received is not a memory address. One of the inputs for comparison by comparator 103 are the data processer address bits which in this case by way of example are four in number and are indicated as the BSAD14+ through BSAD17+ signals. This address received at one input of comparator 103 is compared with the address set by, for example, the hexadecimal switch 101 in the data processor itself. When the received address and the switch 101 provided address are compared and found to be equal, then comparator 103 generates ITSMEA+ signal which partially enables gates 106 and 107.
Further, address bits BSAD0~ through BSAD13+ are received at the inputs of comparator 104 which determines whether or no~ these bits are all zeroes. If they are all zeroes, then the ITSMEB+ signal is generated to also partially enable gates 106 and 107. Enabling of further ilipUt of either gates 106 or 107 will effectively set a respective flip-flop in element 113.
The other input to gate 106 is a second half bus cycle BSSHBC+
~ signal which is coupled to gate 106 via inverter 116. The second half bus ; cycle is also received at one input of AND gate 109. The other input to gate 109 is from the Q output of the second half read history flip-flop 110. The second half read history flip-flop is utilized to remember that the data pro-cessor issued its MYDCNN+ signal i.e. the setting of this device's grant flip-flop 22, and that the central processor also sent the signal entitled MYNRIT-, which implies that the data processor is expecting a response cycle from the slave. Thus, with such a two cycle operation, the second such cycle presents the expected data to the central processor, and the flip-flop 110 will identify this data as being that which the central processor requested by the fact that the history flip-flop 110 has generated the MYSHPH+ slgnal at the Q output thereof. Fllp-flop 110 is reset via NOR gate 111 if the bus clear signal BSMCLR+ is received or if the second half bus cycle has been completed as indicated by the MYSHRC+ signal. The MYSHRC+ signal is derived from one of the outputs of element 113 to be hereinafter discussed.
Thus, AND gate 107 will be fully enabled if two of the inputs ~' l~Z6l373 thereto indicate that this is the addressed device and that from the other input thereof, that there has been a second half bus cycle as indicated via AND gate 109 from history flip-flop 110. Thus, by the enabling of AND gate 107 the MYS~lRC-signal will be generated and will be coupled to one input of NOR gate 114. NOR gate 114 will provide an ACK signal, (BSACKR-) via driver 115.
Gate 106 will be fully enabled when the proper unit address is re-ceived and if this is not a second half bus cycle, which thereby generated a positive pulse labelled as the MYINTR+ signal at the output of the respec-tive flip-flop included in element 113. The MYINTR+ signal causes the logic of Figure 11 to determine whether or not an ACK or a NACK signal will be generated. ~hich one of such signals is generated will depend on the inter-rupt level that is presently operating in the system as compared to the inter-rupt level of the device seeking processing time.
This decision regarding whether or not the interrupt level is suf-ficient is determined by means of comparator 117, which is a comparator for determining whether or not the A input is less than the B input. The A in-put of comparator 117 receives the BSDT10+ through BSDT15+ signals, is a not;
the interrupt level of the device coupled with the bus which is seeking data processing time. There are a plurality of interrupt levels provided in the system. Interrupt number level 0 receives the highest possible accessib1lity to data processing time and accordingly is non-interruptable. Thus, the lower the interrupt level number, the less chance there is that such device's on-going processing will be interrupted. Thus, if the level number received at the A input of comparator 115 is less than the current level operating in the data processor as indicated by the level number in block 118, then the device seeking to interrupt as indicated by the signal received at input A
will in fact be able to do so. If the A input is equal or greater than the B input, then the LVLBLS+ signal will not be generated and a NAK signal will be provided by the driver 108 and flip-flop 120 as shall be hereinafter 26~373 described.
Thus, if the interrupt level received at input A, of comparator 117 is less than that received at input B, the LVLBLS+ signal will be a binary one and will be coupled to the D input of both flip-flops 120 and 121, it being noted that the D input of flip-flop 120 is an inversion. If the A signal is equal to or greater than the B signal as indicated by com-parator 117, then a binary zero signal will be generated for the LVLBLS+
signal which will be recieved at the negation input of flip-flop 120. This t will generate the NAK signal if the MYINTR+ signal is received at the clock 10input of flip-flop 120 by the setting of the respective flip-flop in element 113. If the level was sufficient i.e. if the A input was less than the B
input as indicated by comparator 117, then a binary one will be generated at the LVLBLS+ signal and accordingly the MYINTR+ signal will clock this to the`Q output of flip-flop 121 into one input of NOR gate 114 which via driver 115 will generate the ACK signal. Thus, if the MYNAKR+ signal is a binary one, then the NAK signal will be generated and if the MYINTF- signal is a binary zero, an ACK signal will be generated. The flip-flops in element 113 are clocked and cleared by inverter 125 in the same manner as previously discussed for similar flip-flop type elements. It should be noted that an 20ACK signal will be generated independent of the lndication by compara~or 117, if in fact this is the second part of the second half bus cycle. In such event, the ~SHRC- slgnal in one of the fiip-flops of element 113 is coupled in the binary zero state to the other input of NOR gate 114 so as ~ to generate the ACK signal thereby overriding any indication from flip-flop ': `
121.
As indicated hereinbefore, the BSDCNB- signal via inverter 125 resets flip-flop 121 and in addition sets flip-flop 120, thereby initializ-ing the flip-flops following the bus cycle. In addition, flip-flop 120 is reset by the logic associated with flip-flop I27 which generates a BTIMOT-signal indicating a time out condition, i.e. that a non-existent device was 3'73 addressed and that in fact no response, neither a NAK, an ACK or a WAIT has been generated by any potential slave device. Accordingly, there is provid-ed a one-shot multivibrator 126 which may be set to have a five microsecond period for example. This multivibrator 126 is triggered by the receipt of the BSDCND+ signal i.e. the strobe signal, which is received at the input of buffer ll9. Since the timing of the multivibrator 126 is in motion, if a BSDCNB~ signal is not received which signal indicates the end of the bus cycle, then after the period set by multivibrator 126, the BTIMOT- signal is generated at the Q output of flip-flop 127 via the clocking of the BSDCNN~
signal received at the D input of flip-flop 127, it being noted that the BSDCNN+ signal indicates that the bus cycle is still in process. The BTIhlOT- signal operates on flip-flop 120 to generate a NAK signal. If on the other hand, the BSDCNB~ signal terminates before the end of the period set by multivibrator 126, the timing of multivibrator 126 is terminated and flip-flop 127 is prevented from generating the signal BTIMOT-.
It is noted that the data processor logic in Figure 11 generates either a NAK or ACK signal, however, a WAIT signal is not so generated by the dàta processor logic. The reason for this is that the data processor always has the lowest priority and accordingly, if it generates a WAIT sig-nal, the other devices generating their request to the data processor forservice will possibly experience a hang-up on the bus, if for example, a higher priority device was the master to which the central processor re-sponded with a WAIT signal. Thus, just because the higher priority device is waiting for the lowest priority device, i.e. the central processor, other devices will be disabled from using the bus.
In further explanation of the present invention, it can be seen that the integrity of information transferred over the bus may be insured without the necessity of adding a parity bit for each byte of information transferred on the bus. This integrity may be provided for any units which transfer information therebetween. More particularly, this may be facilit-i~i2~

ated in those cases where a master unit in its request expects a response from a slave unit. Thus, the integrity of such data transfers may be best facilitated in those situations where two bus cycles are utilized in a bi-lateral bus transfer. This is particularly advantageous for example in a memory read operation wherein the master requests information from the mem-ory and, during a later bus cycle, receives such information. It has been found, for example, that a substantial number of data transfers occur be-tween the memory and another device during a read operation which requires two bus cycles and accordingly the data integrity feature of the invention is particularly important in such case.
Basically, the integrity apparatus takes advantage of the fact that when a master addresses another unit, which may be for example, a mem-ory or a tape or disk peripheral unit, for information, the master places the address of the slave unit on the address leads on the bus and its own address and function code on the data leads of the bus. When the slave responds and in so responding is the master, the slave then places the re-questing unit's address on the address leads and the data on the data leads.
Thus, the requesting unit's address is received back on address leads as opposed to the transfer thereof initially on the data leads. The requesting device then compares its address i.e. the addresses transferred on the data leads with the address now received on the address leads, and if they com-pare, this insures that in fact at least its device address was received ` properly by the slave and that in addition, if the op-code is also received back, the op-code was received satisfactorily. Thus, for 16 bits of infor-mation as shown in the format of Figure 4, up to 2 parity bits are elimin-ated while maintaining the integrity of the data transfers in the system.
CPU/CACHE PRIVATE INTERFACE SYSTEM
; Referring to Pigure 12 there is shown a block diagram of the priv-ate interface between the CPU 1201 and the cache memory unit 1202. There are 43 signal lines that permit: (1) the CPU 1201 to send the address of ~' : ' .
. , .

.` . ' . :

~LlZ~i873 the next word required for execution, and ~2) the cache memory unit 1202 to return the contents of that word to the CPU accompanied by the conditions associated with that word or address. The private cache/CPU interface sig-nal are defined as follows:
1. Absolute Address: ~BAOR 05-22). These 18 signals transport the absolute address of the word that the CPU requires for program execu-tion.
2. Read Request: ~CACHRQ~00). This signal informs the cache memory unit that the absolute address signals have been encoded and that the cache memory unit is to proceed in reading that word.
3. Data: (CADP 00-l9). These 18 signals transport the request word to the CPU for the CPU supplied absolute address.
4. Data Parity: These 2 signals carry odd parity for each byte of the requested word. The parity received from the system bus in response to a main memory read is treated as data in the cache memory unit (i.e. not regenerated or checked) and is passed on to the CPU.

5. Out of Range (CNOMEM-OO). This signal indicates that the address requested does not exist in the current system configuration. The out of range signal is returned to the CPU when the cache memory unit does not find the requested word within the cache memory and receives a Negative . . -Acknowledge (NAK) signal from the BIU in response to a main memory reference System Bus Cycle.

` 6. Cache Data Valid: (CYCADN-00). This signal indicates to the CPU that the information on the data and data parity signals may be ready for the CPU.

7. Cache Present: (CACHON-00). This signal indicates that the cache memory unit is installed in functioning ~i.e. has passed its Q~T).

8. CPU ID: This signal informs the cache memory unit of the CPU

Identity that is attached to it.

9. Cache Red: This signal informs the CPU that the requested .

.. : .

;~Z6t3~3 word from main memory has an uncorrectable read error.
10. Cache Parity Check Time: This signal informs the CPU that the result of the parity checker is available for strobing into the parity error flop (not shown).
The llardware logic block structures for generating these signals ; and for the CPU service cycle logic are disclosed in detail below in connec-tion with Figures 13, 14 and 15.
Referring again to Figures 14 and 15 the CPU service cycle logic will be described. Figures 14 and 15 are drawn so that when a person of ordinary skill knows what the blocks represent he can ascertain the struc-ture and function by the pnemonics of the various signals. For example, it has previously been shown in connection with Figure 12 that the pnemonic for the read request signal is (CACHRQ). Attached to that pn~monic there can be ; either a plus sign or a minus sign followed by 2 integers. The plus sign following the pnemonic of a signal indicates that the signal in this instance the read request, is true when the signal is high; whereas a minus sign fol-lowing the phemonic of the signal again in this case the read request is true when the signal is low. The first of 2 integers following the plus or minus signal indicates when it is zero that it is the first occurrence of the signal in performing its function, and when it is one, it is the second occurrence and so on. For example, the signal may be first encoun~ered on a flip-flop which in turn passes through an AND gate, which in turn passes through an inverter, a total of 3 occurrences of that signal. The second integer following the high order first integer is generally utilized eor special conditions for example, to indicate that the signal is to apply to the reset of a flip-flop in which case it would be an R. Accordingly, with this as background let us now describe the CPU service cycle logic of Pigure 14 and the pertinent CPU service cycle of cache block timing diagram Figure 15.
The CPU SERVICE CYCLE begins when the Cache Request (CACHRQ~00) signal is logically ANDed with the cache busy signals via AND gates 1401, 1402, and flip-flop 1403. Barring any cache activity a CPU Service Request (CPUREQ-OD) is generated at the output of AND gate 1401 and sent to 100-nanosecond delay timing network 1~04, 1405. This network is variable and provides an adjustable delay timing for the phasing of the cache and the CPU clocks. ~Computer timing clocks are well known and are not shown here but a typical clock is shown and disclosed in Canadian Patent No. 1,084,630, issued August 26, 1980 and entitled "Stretch and Stall Clock" by Thomas F.
Joyce, et al). Referring at this point to Figure 15 under the CPU service cycle the timing of various signals generated by the CPU service cycle logic of Figure 14 is shown. When the CPU SERVICE REQUEST (CPUREQ) is true and the FIFO Not Empty (FEMPTY) signal remains true, the FEMPTY output signal ~FEMPTY-20) goes low, generating the clock signal CLOCKO~OA high and the Cache Clock (CLOCKO+OO) signal low. The Cache Clock (CLOCKO+OO) going low drives the delay line, and thus a predetermined delay time later the delay signal CDLY40+00 goes low and the Cache Clock (CLOCKO~OO) signal goes high.
The Block Request flip-flop 1403, which is controlled by the Cache Clock (CLOCKO+10) signal, blocks or resets the CPU Service Request (CPUREQ) signal and the Cache Clock Control Logic returns to the Idle State. As a result of the Block Request flip-flop 1~03 setting, further CPU Service Requests are inhibited. The Block CPU Request flip-flop 1403 remains set until the CPU Service Cycle terminates and the CPU Service Request (CACHRQ+OO) signal in the CPU is reset. During the CPU Service Cycle, the cache performs the following internal operations.
1. The cache reads the cache directory and data buffer 315 (i.e.
a HIT and a NO HIT).
2. If a HIT occurs, the data/instructions are sent to the CPU 312 from cache memory unit 313.
3. If a NO HIT results, the Memory Request (MEMREQ+OO) state is entered and the data requested of main memory 1, 2.

~Z~i873 ~ en the information requested by the CPU is not in the cache directory and data buffer~ a Memory Request MEMREQ signal is generated and applied to flip-flop 1409. On the next Clock Cycle CLOCKO+10 the one out-put terminal of the MEMREQ+00 goes true and the cache memory enters the mem-ory request state. If the information requested by the cache memory of the main memory, the out of range signal CNOMEM-00 is generated and applied to NAND ga~e 1410 which in turn applies a hlemory Request Reset Signal MEMREQ-lR
to the reset terminal of flip-flop i409 via NOR gate 1411, thus resetting the zero terminal of flip-flop 1409 and terminating the Memory Request Mode.
The CPU Service Cycle terminates when the CACHE/DONE signal ~CYCADN+00) is set and applied to set flip-flop 1413 via delay network 1414, 1415 and inverter 1416. The Cache Done Signal (CYCADN+00~ is set by any of the following conditions:
1. The data requested is in the cache data buffer (i.e. a HIT) which is enabled onto the CPU data bus.
2. The data requested is retrieved from main memory and the cache FIFO buffer is enabled onto the CPU data bus (i.e. replacement cycle~.
3. The data location address sent to the cache from the CPU is for a memory location outside the range of the configured memory (i.e.
CNOMEM+OO).
The CPU uses the leading edge of the Cache Done (CYCADN+00) signal to strobe the CPU data bus into its internal data-in register, start its clock and reset the CPU CACHE REQUEST (CACHRO+00) flip-flop. The CACHE
DONE signal (CYCADN+00) resets appro~imately 60 seconds after the CPU CACHE
REQUEST (CACHRO+00) signal is removed because of the delay network 1415, 1416.
Accordingly, the FIFO EMPTY SIGNAL (FEPTY-20) signal is true (i.e.
low) at the output of clock start flip-flop 1406 and is inverted in inverter 1408 to a high signal which is then applied to Block Request Flip-Flop 1403 to inhibit the CPU cache request signal by providing the low block request i8'73 signal (BLKRE~-OO to one input of NAND gate 1401). Thus, further CPU
service requests are inhibited so long as this signal remains low as one input of NAND gate 1401. The Block CPU Request flip-flop 1403 remains set until the CPU service cycle terminates and the CPU service request signal (CAC~IRO+OO) in the CPU is reset.
During the CPU service cycle, the cache performs the following internal operations:
1. The cache reads the cache directory and data buffer 350 (i.e.
a hit, a no hit).
2. If a HIT occurs, the data/instructions are sent to the CPU.
3. If a NO HIT results, the memory requests state (MEMREQ+OO) is entered.
The CPU service cycle terminates when the CACHE DONE signal (CYCADN+OO) is set on flip-flop 1413 by any of the following conditions.
1. The data request is in the cache data buffer (i.e. a HIT), which is enabled onto the CPU data bus.
2. The data reques~ed is retrieved from main memory and the cache FIFO buffer (not shown) is enabled onto the CPU data bus (i.e. replacemènt cycle).
3. The data location address sent to the cache from the CPU is for a memory location outside the range of the configured main memory ~i.e.
CNOMEM+OO).
These different cycles and the hardware of the cache memory are described in greater detail in the above-mentioned co-filed patent applica-tion entitled "FIFO Activity Queue for a Cache Store".
The CPU uses the leading edge of the CACHE DONE signal (CYCADN+OO) to strobe the CPU bus into its internal data-in register, start its clock, and reset the CPU CACH~REQUEST flip-flop ~CACHRQ+OO), all described in the previous referenced patent application. The CACHE DONE signal ~CYCADN+OO) resets approximateLy 60 nanoseconds after the CPU CACHE REQUEST signal .~

8~3 ~CACHRQ-~OO) is removcd.
The CPU service cyclc is also shown on Figure 15 in relation to the timing signals applied to the CPU service CYCLE logic hardware o Fig-ure 14. Referring now to the CPU SERVICE CYCLE of Figure 15, it is shown tha~ when the CPU SeRVICE REQUEST signal (CPU REQ) is true and the FIFO NOT
EhlPTY signal (FEMPTY) remains true, the FEMPTY output signal ~FEMPTY-TO) goes low, generating the CLOCKO+OA signal high and the CACHE CLOCK signal ~CLOCKO+OO) low. The CACHE CLOCK signal ~CLOCKO+OO) going low drives the delay line and accordingly typically 40 nanoseconds later drives signal 10 CDLY40+00 low and the CACHE CLOCK signal ~CLOCKO+OO) high. The Block Request Flip-Flop"~lhich is controlled by the CACHE CLOCK signal ~CLOCKO+10), blocks or resets the CPU SERVICE REQUEST signal ~CPUREQ) and the cache con-trol logic returns to the IDLE state.
Referring to Figure 13 there is shown the high speed logic for the private interface between the processor and the cache memory. The CPU uti-lizes this private interface to obtain information from cache or place in-formation back in-to cache. If the information is not available in cache memory, then cache memory must go into main memory, obtain the information, place it into cache memory and also provide it to the CPU. When there is a 20 memory lock-on or lock-off operation, then the CPU obtains information directly from main memory. Upon a "hit" in cache memory ~i.e. the word addressed is located in cache memory) and the subsequent parity error checks and provision to the CPU of the data requested the cache memory is reset.
If the CPU provides an illegal address to the cache memory, then an illegal store op-fault results.
Reviewing the logic block diagram oE Figure 13 in detail, a cache read request signal CACHRQ+OA is generated ak the output of AND gate 1302 are high. The cache read request input signal CACHRQ+lB to AND gate 1302 is generated via exclusive OR gate 1315 and inverter 1316. It is high when both input signals BRESRV+OO and MYRESV+OO to exclusive OR gate 1315 are either high or low. It will be noted that when input signal BRESRV+OO from the CPU, which is a bus reservation signal, is high, and when input signal ~RESV+OO to exclusive OR gate 1315 is also high, the output from exclusive OR circuit 1315 will be low which then will be inverted in inverter 1316 and provide a high output CACHRQ+lB. Similarly, when the two input signals BRESRV+OO and ~RESV+OO are low, the OUtpllt of exclusive OR gate 1315 is also again low which again is inverted in inverter 1316 providing a high output signal CACHRQ+lB. With both input signals to exclusive OR gate high, there is an indication that the cache request signal generated is in the maintain mode. On the other hand,when both input signals BRESRV+OO and ~RESV+OO are low, there is an indication that the CPU is in the not-set lock mode operation. If either one of the input signals to exclusive OR
gate 1315 are high while the other one is low, there is an indication that CPU is in the set-lock now or reset-lock now mode.
Another input signal to AND gate 1302 that must be high in order to generate the cache request signal CACHRO+OA is the cache-on signal CACHON+OO. This signal is generated when the cache memory is attached to the CPU via the private interface and is turned on. The cache test and ver-ification logic 1317, (see Canadian Application No. 318,149, entitled "Out of Store Indicator for a Cache Store", by T. Joyce, et al, and assigned to the same assignee as the instant application), senses that the cache memory is attached and provides a low input signal to inverter 1301 which in turn pro-vides a high input signal CACHON+OO to an input terminal of AND gate 1302.
Finally, for the cache read request signal CACHRQ+OA to be high the third input signal BMSTRR+OO on AND gate 1302 must also be high. This is a signal provided by the CPU which indicates that a main store read is to be performed when it is high. Accordingly, the following conditions must be true in order to generate the cache read request CACHRQ+OA signal which is applied to the D terminal o:E flip-flop 1303:

~26~ 3 1. Main memory is not being locked or wIlocked, and this is indicated by the CACIIRQ+lB signal being high;
2. The cache is attached and is on which is indicated by the in-put signal CACIION~00 being high; and, 3. A main memory read is being performed which is indicated by BMSTRR~00 signal being high.
As noted previously, the CACHRQ+OA signal is applied to the D in-put terminal of flip-flop 1303. With this signal high, flip-flop 1303 will set when the clock pulse signal MYCLOK+00 is applied to clock terminal CK.
Accordingly, the Q terminal of flip-flop 1303 will go high and generate the CACHRQ+00 signal which is applied to the cache clock control 1304 (see Canadian Application No. 318,476, entitled "High Speed Buffer Memory System with Word Prefetch", by T. Holtev, et al, and assigned to the same assignee as the instant application), and is also applied to the D and R terminals of flip-flop 1307.
Flip-flop 1307 is the cache request reset flip-flop which is reset by flip-flop 1303 when the cache request signal CACHRQ-OR, which is applied to the inverted R terminal of flip-flop 1307, is low. Flip-flop 1307 will reset on the clock pulse CACHDN+00 applied to input terminal CK of flip-flop 1307 and is generated via inverter 1306 and cache hit logic 1305. (See Canadian Application No. 318,476, entitled High Speed Buffer Memory System with Word Prefetch and assigned to the same assignee as the instant inven-tion) . The rising edge of the CACHDN+00 pulse on the CK terminal of flip-flop 1307, clocks the CACHRQ~00 on the D input terminal of 1307, so that the CACHRQ+OR signal on the Q terminal of flip-flop 1307 is high and the cache request signal CACHRQ-OR on the Q terminal of flip-flop 1307 is low. This low signal is applied to the reset terminal of flip-flop 1303 and causes flip-flop 1303 to set on the rising pulse of the cache done CACHDN~00 sig-nal. It is thus seen that although the cache done CACHDN~00 signal remains high for a duration, flip-flop 1303 can be reset immediately on the rising . , .

pulse and be utilized almost immediately again and thus actually recycle the next request with this type of logic within a typical time period of 40 nanoseconds. It should be noted that when cache request signal CACHRQ+00 was generated and was applied to the cache clock control 3104, it was also applied to an input terminal of NAND gate 1314 which caused the clock signal CLOC~O+OD signal to go low and thus stall the processor's clock. (see Canadian Patent No. 1,084,630 issued August 26, 1980, entitled "Stretch and Stall Clock", and assigned to the same assignee as the instant application).
The processor's clock remains stalled until data is delivered either from memory to the cache or from the cache directly back to the CPU. The CPU
clock stalls on a low signal and starts on high.
Since the CACHRQ-~00 signal on NAND gate 1314 is normally high when a request is being made to cache, and since the CACHRQ-~OR signal is normally high until a CACIIDN+00 signal on flip-flop 1307 clocks it low, the output signal of NAND gate 1314 goes low when the input clock timing pulse CLOCKO~OF
on NAND gate 1314 goes high, thus stalling the CPU clock. The advantage of stalling the CPU clock rather than permitting it to run is that if informa-tion is available to be delivered from cache to the ,CPU in the middle of a CPU clock cycle, it cannot be delivered until the end of that cycle and ac-cordingly time is wasted. By stalling the clock, it may be immediately re-started when information is available and there is no wasted cycle time. Ac-cordingly, when information is available for the CPU, the CACHDN+00 signal is generated via CACHE HIT LOGIC (see Canadian Patent Application No.
318,476, entitled "High Speed Buffer Memory System with Word Prefetch" and assigned to the same assignee as the instant invention) which causes the . CACHRQ-OR signal to go low at the Q terminal of flip-flop 1307, which in turn is applied to one input terminal of NAND gate 1314, causing its output to go high, thus restarting the CPU clock (not shown).
~ When there is a "hit in the cache memory" (i.e. the word addressed as in cache memory) in addition to stalling the processor clock it is nec-~fi~373 essary to check the data for parity and strobe it into the processor's data registers ~not sho~n) when it becomes available. This is performed by ap-plying the CYAC~DN-ll signal to one input of NAND gate 1308 which generates the bus end read slgnal BENDRD-00 and strobes data from the cache into a register (not shown) of the CPU. Approximately 80 nanoseconds later after the generation of the cache done signal CACIIDN+00 AND gate 1310 is enabled by input signal CAPCKT-00 and BSS~IBH-ll which provides a signal BENDRD+00 for checking parity.
Assuming that the CPU makes a request for a word from the cache which is not in the cache and the cache in turn requests the word from mem-ory which again is not in memory, then a CYCADN-00 is set and CNOMEM-00 sig-nal 1311 is generated and applied to AND gate 1312. AND gate 1312 sets sig-nal IIS000+1A of flip-flop 1313 which remains set until reset by signal IRESET+10. Signal IIS000+lA causes the CPU to abort the current instruction and process the no-memory fault signal and reset IIS000-~lA signal via signal IRESET+10.
DETAILED DESCRIPTION OF MULTI-CONFIGURABLE CACHE ORGANIZATION AND LOGIC
.
: Referring to Figures 16a and 16b there is shown a diagramatic rep-resentation respectively of a single or double module banked main memGry and a single or double module pair of interleaved main memories. In a conven-tional banked main memory organization words of any memory module 1601-1603 are organized sequentially from top to bottom or vice versa as shown. In the single pull mode of operation a request from cache memory addresses one word from a given module and receives in response thereto one data word from that address in main memory. In the double pull mode of operation, a re-quest from cache memory reads one address to any module 1601-1603 and re-ceives in response thereto two data words from consecutive adjacent word addresses in a module, as for example, address 0 and address 1 of module 0.
~See Canadian Application No. 319,202, filed January 5, 1979 and entitled System Providin~ Multiple Fetch Bus Cycle Operation).

, , .

~Z~B'73 In the interleaved mode of addressing as shown on Figure 16b, the modules of main memory are addressed in pairs such as module pair 0 and mod-ule pair 3 of Figure 16b, and one module is organized to hold the even ad-dresses such as module 1611 and another module is organized to handle the odd addresses. In addressing an interleaved organized in the single pull mode, two successive adjacent address requests are sent from cache memory, one address to the first module 1611, for example, and the other address to the second module 1612, for example, of the typical module pair 0. Cache memory then receives in response thereto two words, one word from module 1611 and another word from module 1612. In the double pull mode of address-ing, two successive address requests are sent from cache memory, one ad-dress to each module of a module pair. For example, the cache memory sends one address to module 1611 and another address to module 1612. In response to these addresses, the cache memory receives two words from module 1611 and two words from module 1612. The words from module 1611 come from any two adjacent addresses such as from address 0 and 2 or from address 2 and 4 and similarly the two words from module 1612 also come from any two adjacent addresses.
A typical total main storage address range is from 0 to 1,048,575-words. As shown on Figure 17a, the entire main memory system can be viewed,conceptually, as a square array comprised of 1,024 columns and 1,024 rows of word locations. Correspondingly, a 20-bit address is typically utilized in a processor request to address main memory and can be considered equivalent to a 10-bit row number concatenated with a lO-bit column number of the word location to be accessed. (See Figure 17b).
The random access cache memory 1702, on the other hand, has a total typical capacity of either 2048 or 4096 words and can be considered to be an array of 2 or 4 rows and 1024 columns. Because the column number portion of the processor request address is used to access the cache, there is an exact correspondence between columns in the cache memory 1702, and the ,~, columns of the location in main memory 170l that can have copies of their contents in the cache memory. Because there is no similar direct fixed cor-respondence between the rows in main memory and the cache, the rows of the cache word matrix are referred to as levels to avoid confusion. The cache 1702 has typically 2 or 4 levels by 1024 columns of word storage locations.
Each column of 1024 words in main memory has either 2 or 4 corre-sponding cache random access memory locations in which copies can be stored for immediate access by the processor. The directory entries 1812-1815, Figure 18a, for a specific column of cache indicate the main memory row num-bers of the words stored in each level. The row numbers of the words stored in any particular column of cache are completely independent of their own numbers of the words stored in any other column of the cache. ~Of course, it should be recogni~ed that any number of columns and any number of rows either in main memory or cache and any number of bits may be utilized to practice this invention).
In operation, the column number portion of the processor request address 1702, 1860 in Figures 17b and 18a respectively is used to access one of the 1024 locations in each of the cache random access memory levels 1808-- 1811 and in each of the 4 corresponding directories 1812-1815. A comparison 20 is made in comparators 1801-1804 between the row number portion of the pro-cessor request address and the row number stored in each directory at the specified column. If there is equality with the row number stored in the directory for any one of the 4 levels, the data from the corresponding cache memory level is transmitted to the central processor via a selector (typ-ically a multiplexor) 1805. To illustrate the above procedure, consider the following example:
EXAMPLE
Processor Request: Location 4608 Decimal.
In Cache in Column 512: Row Numbers from Directories.
.
Level 0 - Location 2560 2 ~row 2/column 512) " .

EXAMPLE CONT'D
Processor Request: Location 4608 Decimal In Cache in Column 512: Row Numbers from Directories Level 1 - Location 5632 5 (row 5/column 512) Level 2 - Location 4608 4 ~This is the requested word) (row 4/column 512) Level 3 - Location 8704 8 ~row 8/column 512) Hence, it is seen that there is a comparison for the requested address from main memory, a copy of which is also located in row 4 column 512 of cache memory. If there is no comparison, a copy of the requested word is not presently in the cache and must be fetched from main memory;
this is known as a "no-hit" condition. Upon receipt of the word from main memory by the cache, it is transferred to the processor and also stored in the cache with the expectation that the processor will request access to the same word again. Because the cache, after initialization, is always filled to capacity, the insertion of a new word always causes the removal of an-other word. An important aspect of the design of the replacement logic (See Canadian Application No. 318,475, entitled Round Robin Replacement for Cache Store) is to select, for removal, the words in the cache that have the low- t est probability of reference by the processor. The contents of any column in the cache is managed independently of any other column and is determined by the column number field 1702, 1806 of the Processor Request Address PRA.
To implement the management of each column of the cache 1850 of Figure 18b, the replacement logic has a 2-bit counter for each column of the cache 1851, 1852, 1853 -- one for all 4 levels of each column. (See also 1950, 1951 of Figure 19). The counter for each column is an indicator for the level in which the next new data word IS to be stored in the column. Each time a new word is placed in cache at the level indicated by the counter, it is incre-mented so that the succeeding word in the same column will be placed in the iB'i'3 next higher level of the cache. Ihe coun-ters increment from O through 3 then back again; tllus, the cache is effectively a set of 1024 4-level first, first-out arrays witll a separate array for each column -- first-out, in this context, referring to cadidacy for replacement rather than access by the processor.
Referring to Figure 18c, there is shown a schematic drawing of the switches utilized to configure main memory into either banked interleaved configuration. Switches No. 1 and No. 2 respectively F19 and El9 are eight position rocker switches. Each switch is for a different module, and each position of the switch permits the access of certain designated space as shown in Exhibit I infra. In effect cache which addresses various blocks of contiguous space in main memory.
EXHIBIT I
. ~ _ SWITCH
NUMBER POSITIONS CO~ENTS
. -- . , . ,_ _ 2 1 through 8 0-32KW = 10101010 ~El9) 32-64KW - 10101010 64-96KW = 10100110 128-160KW = 10011010 192-224KW = 10010110 224-256KW = 10010110 1 1 through 8 0-32KW = 10101010 (F19) 32-64KW = 01101010 64-96KW = 10101010 96-128KW = 01101010 128-160KW = 10101010 160-192KW = 01101010 192-224KW = 10101010 224-256KW = 01101010 . ' . .~A. . __.
E18 1 through 8 E18 = 10000101 E17 1 through 8 E17 = 01010100 E16 1 through 8 E16 = 10101001 Switches E16, E17 and E18 are utilized for configuring main memory in the interleaved mode. ~See United States Patent No. 3,796,996, issued March 12, 1974 and entitled "Main Memory Reconfiguration for Implementation of Various Interleaved Configurations").

~26~373 With respec-t -to switching to the barked or interleaved mode Eor cache memory, details are shown in Canadian Application No. 318,~76 entitled "A lligh Speed Bufer ~lemory System Witil Word Prefetch", by Thomas F. Joyce, et al, assigned to the same assignee as the instant application. Figures 2 and ~ and appurtenant description in that application show and describe one embodiment of the prior art for obtaining either banked or interleaved mode of operation, and serve as background for practicing the instant invention.
As previously described supra, a read request is initiated when a CPU service cycle Figure 14, is in the No Hit Mode. Figure 20 illustrates the read request logic. (It should be noted that Figures 14-26 utilize the logic symbology of Figure 27 which provides a greater amount of information than conventional logic block diagrams to a person of ordinary skill in the art. It should further be noted that Tables I and II infra also identify various interface signals in accordance with their mnemonics).
Referring now to Figure 20, 21 and also to Figure 19a, it is seen that a Main Memory Request Flip-Flop 2005 sets as a result of the No Hit Cycle previously referenced and it remains set until all requested data is in cache. In turn, it sets the Cycle Request flip-flop 2008. If the system bus 1900 is not busy, the My Request Flip-Flop 2109 on Figure 21, located in the cache system bus control logic (see Figure 21), sets and if no higher priority requests are pending, the My Data Cycle Now Flip-Flop 2112 sets.
This flip-flop 2112 allows the CPU absolute read address 1907 onto the sys-tem bus 1900 along with the following control signals.
MEMREF+: Memory Reference;
BSDBPL+: Double Pull;
BSWRIT-: Write (See United States Patent No. 4,030,075, issued June 14, 1977 and entitled Data Processing System Having Distributive Priority Network).
If main memory is configured as banked, the Cycle Request flip-flop 2008 is reset, and main memory responds with one of the following sig-

6~3~3 nals: (See Figures 19, 20 and 21).
1. BSACKR ~Positive Acknowledge): In its true state, this signal indicates a positive response from main memory; it resets the My Data Cycle Now Flip-Flop 2112 and the My Request Flip-Flop 2109.
2. BSWAIT (Wait): This signal indicates that main memory is busy and resets My Data Cycle Now Flip-Flop 2112, while My Request Flip-Flop 2109 is allowed to stay set. The system bus cycle repeats ~mtil signal BSACKR or BSNAKR is received.
3. BSNAKR (Negative Acknowledge): This signal signifies that the CPU read address was not in the current range of configured main memory ad-dresses. The My Data Cycle Now Flip-Flop 2112 and the My Request Flip-Flop 2109 resets, and the No Memory Flip-Flop 2007 sets. This in turn sets the Cache Done Flip-Flop 1413 of Figure 14, thus causing the CPU to remove its - request. When the CPU request is removed, the Memory Request Flip-Flop 2005 resets along with the No Memory Flip-Flop 2007. When main memory responds with the Acknowledge Signal (i.e. BSACKR is in its true logic state) and is configured as banked, the read request activity terminates. If, on the other hand, main memory is configured as interleaved, the read request cycle repeats, using the CPU read address plus 1 and main memory responds with one of the following signals:
1. BSACKR (Positive Acknowledge): In its true state, this signal indicates positive response from main memory and terminates the read request ; activity as described supra.
2. BSWAIT (Wait): This signal indicates that main memory is busy servicing some other system bus unit. It resets the My Data Cycle Now Flip-Flop 2112. Since this request is for Processor Memory Request Address plus one PRA+l ~to be further described infra) and not Processor Memory Request Address PRA (i.e. a No Hit Fault) and the memory may be busy for a few more system bus cycle times, it is inefficient to continue and the ~y Data Cycle Now Flip-Flop 2112 and My Request Flip-Flop 2109 reset, terminating the read 3'7~

request operation.
3. sSNAKR (Negative Acknowledge): This signal indicates that the CPU read address plus 1 is not in the configured memory range. Since this is not a CPU out of memory fault condition ~i.e. the cache generated the ad-dress), the read request activity terminates and the My Data Cycle Now and hly Request Flip-Flop resets. The No Memory Flip-Flop 2007 is not set.
When the first memory read request is acknowledged (i.e. positive acknowledge) by signal BSACKR, the Block Flip-Flop 2010 sets and generates the Replacement Address File RAF write strobe signal BAWRIT-OO via AND gate 2204, on Figure 22a which writes the PRA+l address into Replacement Address File ~RAF) 1093 location 01.
The RAF 1903 (Figure 19) is a 4-bit by 18-bit random access memory R~l that has separate write, readJ registers and parts. The write position is addressed by Write Address Counter (WAC) 1909, and is written by a Write Pulse BAWRIT. The WAC is maintained in a reset condition until CPU No Hit service cycle, and is then incremented by signal AORCNT generated at output of NOR gate 2215 of Figure 22b.
Figure 23 shows the timing diagram for the second cycle of the Replacement Address File RAF mode. Referring to Figure 23 and Figure l9a, signal PRA+l is clocked (i.e. strobed) into the Address Out Register (AOR) 1904 by signal BAORCK and the Write Address Counter (WAC) 1909 is incremented to RAF 1903 location 02 by signal AORCNT. The Address Out Register ~AOR) 1904 lS transferred to the AOR adder 1905 where +1 is added to address PRA+l ~i.e. the second memory request absolute address), and then the AOR register 1904 is not clocked any more.
If the main memory configuration is banked, further request activ-ity halts; one main memory request and the absolute address would transfer to main memory and the Replacement Address File RAF has stored the CPU
Memory Request Address ~PRA) and PRA+l at locations 01 and 02.
Figures 24 and 25 are timing diagrams for the third and fourth ~ .
:

cycles for the Replacement Address File RAF 1903 respectively. Referring to these timing diagrams and to Figure 19, when the data associated with the Processor Memory-Reques-t Address Signal ~PRA) from main memory arrives at the cache memory ~mit, 1901 the acknowledge signal on cache side h~ACKR
(see Table II) generates the RAF Write Strobe Signal BAWRIT-00 (see Figure 22a) which writes the data associated with the Processor Request Address PRA+2 into RAF 1903 location 02. The Write Address Counter (WAC) 1909 is incremented to location 03 the contents of Address Out Register ~AOR) 1904 are transferred to the AOR adder 1905 where +2 is added to Processor Request Address PRA+l, forming PRA+3.
If main memory is in thc double-pull configuration, the next data to arrive is associated with Processor Request Address ~PRA) ~if main memory is banked organized or ~PRA+2) if main memory is interleaved). Control sig-nal hNACKR on NAND gate 2213 ~Figure 22b) generates control signal AORCNT+00 via NOR gate 2215 which is applied to NAND gate 2204 ~Figure 22a) via in-verter 2203 generating the RAF Write Strobe signal BAWRIT-00, which writes the contents of PRA+3 address into RAF 1903 location 03. The Write Address Counter ~WAC) 1909 is incremented to location 00 and further activity of the WAC strobe signal ~AORCNT) is inhibited.
When main memory is interleavedj a second memory read request is sent out ~i.e. single pull equals PRA+l; double pull equals PRA+3). The Cycle Request Flip-Flop 2208 remains set if the memory is in the interleaved mode, and sends out a second memory request via the ~REQT flip-flop 2109 along with the absolute address PRA+l. When data arrives from the first memory read request, signal h~ACKR generates the RAF Write Strobe Signal ~BA~RIT-00), as described supra with respect to Figures 22a and 22b; this in turn writes the contents of address PRA+2 into RAF location 02. The Write Address Counter ~WAC) 1909 is incremented to locations 03 and ~he contents of the Address Out Register ~AOR) 1904 is transferred to the AOR adder 1905 where +2 is added to PRA+l, forming PRA+3.

- 6~ -~;~2~73 ~ hen the first memory read reguest data associated with the PRA
address arrives, the contents of (PRA+2) address is written into RAF loca-tion 02. The Write Address Co~mter (WAC) is incremented to location 03 and the contents of the Address Out Register (AOR) is added to *2, forming ad-dress PRA+3. The ne~t data to arrive is the data associated with the (PRA~2) address; signal hNACKR again generates the RAF Write Strobe BAWRIT-00 as previously described with respect to Figures 22a and 22b, and the contents of the (PRA+3) address are written into RAF location 03. The Write Address Counter (WAC) is incremented to location 00 and further activity of the Write Address Counter Strobe Signal AORCNT is inhibited. If the main memory is double-pull, then the data associated with addresses (PRA+l) and (PRA+3) will arrive and be written into the cache directory and data buffer.
When the cache memory is in the No Hit Replacement Mode, the CPU
receives its requested data/instruction words from main memory via the buf-fer bypass logic 1918 of the cache memory unit. The buffer bypass logic 1918 sends the requested main memory data/instruction words to the CPU while the cache memory unit is still processing and storing the information, thereby increasing the data transfer rate. Since the CPU can request another word after the first requested word is received, the cache memory unit is de-signed to remain unavailable (i.e. busy) to the CPU until the read requestactivity is terminated and all the requested data transfers are completed.
A data counter (see Figure 26) is the mechanism that determines when all of the requested data has been received and the memory request cycle is com-pleted by resetting the Memory Request Flip-Flop 2005. The data counter 2600 comprised of flip-flops 2603 and 2607 counts the number of data trans-fers it received by counting when signal BSDBPL on NAND gate 2601 is false.
When the double pull memory is read-requested with double-pull request true, the memory will send two words. When memory sends two words, the first w~rd will have double-pull signal true which indicates more words are to follow.
The second word will have double-pull signal false which indicates no more ~ .

8'73 words to follow. Idcntifies the requestor as being capable of accepting two words in succession with one request. Also it informs that receiver that two words will be received. Regardless of the numher of read requests, whether one or two, and the type of memo-ry, whether single-pull or double-pull, when the count equals 2, the Memory Request Flip-Flop 2005 is reset, completing the memory request cycle. ~len the memory request signal MEMREQ
on reset terminal R on flip-flops 2603 and 2607 is in its reset state, the data counter is reset to 0. On the first memory read request, when the Memory Request Flip-Flop 2005 is set, the data counter is adjusted to 11, depending on whether the main memory configuration is interleaved or banked.
If the main memory configuration is banked, the data counter is preset to one because the data counter always terminates in memory request cycle at a count of two and is incremented by the Data Counter Clock Signal (DATACK-) for single-pull/double-pull memories as follows:
1. Single-Pull Memory: The banked signal from the interleaved/
banked slide switch (not shown) presets the data counter to one. When the data/instruction arrives, the data counter is incremented to two.
2. Double-Pull Memory: The banked signal from the interleaved/
banked slide switch (not shown) presets the data counter to one. The double pull banked memory sends back one or two words, depending on out of memory considerations, and the data counter increments to two on the second of two transfers when the BSDBPL signal is false.
If the main memory configuration is interleaved, the da~a counter is not preset to one, but remains at zero, and is incremented by the Data Counter Clock Signal (DATACK-? for single-pull/double-pull memories as fol-lows:
1. SingLe-Pull Memory: The data counter is incremented to one by a positive acknowledge signal MYACKO when responding to the data/instruction from the first memory request. When the data arrives from the second re-quest, the Data Counter Clock Signal (DATACK-) increments the data counter :~2~373 to two. If the second memory read request is Not Acknowledged (i.e. PRA~l is owt of memory range) or is responded in a Wait Condition (i.e. memory busy), the data counter is preset to one. When the data arrives, the data counter is incremented to two.
2. Double-Pull Memory: The data counter is incremented to one by the positive acknowledge signal MYACKO when responding to the data/instruc-tion from the first memory request. When the data arrives fro~ the second request, the Data Counter Clock Signal (DATACK) increments the data counter to two.
Per reqwest, the double-pull memory sends the following:
1. One Word: If the request was made to read double-pull from its last location (i.e. the last location +l is non-existent), the memory sends the one word with the signal BSDPL false.
2. Two Words: The first word is always with the signal BSDBPL in its true state and the second word with signal BSDBPL in its false state.
Since signal BSDPL is controlled by the double-pull memories, de-pending on the number of words and the priority that main memory uses to send them to the cache memory unit, the Data Counter Clock signal DATACK
increments the data counter for the various possibilities described in Table III infra. When the data counter is equal to a value of 2, it resets the ~lemory Request flip-flop 2005~ allowing the CPU to initiate another ser-vice cycle~ after the last word has completed its replacement cycle.

B'73 TABLE I - MEMORY INTERFACE SIGNALS
_ .
DIRECTION OF
TRANSFER NUMBER
(BUS ~3 MEhlORY) OF LINES DESIGNATION MNFMONIC(S) . --, _ 16 Address BSAD23- through 8 Address BSAD07- through BSADOO-l Acldress Parity BSAPOO-~-~ 18 Data BSDTOO- through BSDT15- BSDTOA-, BSDTOB-2 Data Parity BSDPOO-, BSDP08-1 Memory Reference BSMREF-1 Bus Write BSWRIT-1 Byte Mode BSBYTE-1 Lock BSLOCK-1 Second Half BSSHBC-Bus Cycle 1 Master Clear BSMCLR-1 Power On BSPWON+
1 Bus Request BSREQT-~ 1 Data Cycle Now BSDCNN-< ~ 1 Acknowledge BSACKR-<-3 1 Wait BSWAIT-1 No Acknowledge BSNAKR-2 Error Lines BSYELO-, BSREDD-_~ 9 Tie-breaking Network BSAUOK+ through 1 Tie-breaking Network BShlYOK+
1 Quality Logic BSQLTI-Test In 1 Quality Logic BSQLTO-Test Out 1 Quality Logic BSQLTA+
Test Active _ ~ ~

TABLE I - MEMORY INTERFACE SIGNALS
~ . ~ ........ ~ _ _ , ,, DIRECTION OF
TRANSFER NUhIBER
~BUS hEhlORY) OF LINES DESIGNATION MNEMONIC(S) ...... __ _ 1 Resume Interrupt BSRINT-1 External Control BSEXTC+
~ 1 Timer BSTIMR+
: ~ouble-Word Pull I~/IF

. ~
~.~

TABLE II - SYSTEM BUS INTERFACE LINES
_ . NAME
CACI~ SIDE
CLASS FUNCTION BUS SIDE DRIVER RECEIVER
Timing Bus Request BSREQT- MYREQT+ BSREQT+
Data Cycle Now BSDCNN- MYDCNN+ BSDCNN+
ACK BSACKR- MYACKR+BSACKR+
~ ~ NAK BSNAKR- _ BSNAKR+
Timing ¦ WAIT `BSl~AIT- BSWAIT+
Information Data Bit 0 BSDTOA- ZGND BSDTOA+
1 BSDTOO- LOGIC1+BSDTOO+
2 BSDT01- ZGND BSDT01+
3 BSDTO2- ZGND BSDTO2+
4 BSDT03- ZGND BSDT03+
BSDT04- ZGND BSDTO4+
6 BSDT05- ZGND BSDT05+

7 BSDT06- ZGND BSDT06~

8 BSDT07- ZGND BSDT07+
: 9 BSDTOB- ZGND BSDTOB+
BSDT08 LOGIC1+BSDTO8+
11 BSDT09- CPUIDR+BSDT09+
12 BSDT10- ZGND BSDT10+
13 BSDTll- ZGND BSDT11+
14 BSDT12- ZGND BSDT12+
BSDT13- ZGND BSDT13+
16 BSDT14- ZGND BSDT14+
~ /
Data Bit 17 BSDT15- BLOCKF+BSDT15+
~ Address Bit 0 BSADO0- ZGND
: 1 BSAD01- ZGND

3 BSAD03- ZGND _ . 5 BSADO5- BAOR05+BSAD05-~
6 BSAD06- BAOR06+BSADO6+
7 BSADO7- BAOR07+BSAD07+
8 BSAD08- BAOR08+BSADO8+

9 BSADO9- BAORO9+BSAD09+
BSAD10- BAORlO+BSAD10+
11 BSADll- BAORll+BSADll+
~ 12 BSAD12- BAOR12+BSAD12+
: 13 BSAD13- BAOR13+BSAD13+
14 BSAD14- BAOR14+BSAD14+
BSAD15- BAOR15+BSAD15+
16 BSAD16- BAOR16+BSAD16+
: 17 BSAD17- BAOR17+BSAD17+
: 18 BSAD18- BAOR18+BSAD18+
19 BSADl9- BAOR19+BSADl9+
BSAD20- BAOR20+BSAD20+
21 BSAD21- BAOR21+BSAD21+
~ ~ ~ / 22 BSAD22- BAOR22+BSAD22+
: Information Address Bit 23 BSAD23- ZGND BSAD23+
_ _ TABLE II - SYSTEM BUS INTERFACE LINES ~CONT.) _ _ NAME
CACHE SIDE
CLASS FUNCTION BUS SInE DRIVER RECEIVER
Control Accompanying Memory Reference BSMREF- LOGICl-~ BSMREF-~
Transfer Bus Byte BSBYTE- ZGND BSBYTE+
Bus Write BSWRIT- ZGND BSWRIT+
Second Half Bus BSSHBC- B~l.OCK+ BSSHBC+
Cycle ~ ~ Lock BSLOCK- ZGND
Control Accompanying Double Pull BSDBPL- CYQLTO- BSDBPI+
Transfer . _ .
Integrity Accompanying Red BSREDD- ZGND BSREDD+
Transfer Yellow BSYELO- ZGND
Data Parity Left BSDPOO- LOGICl+ BSDPOO+
~ ~ Data Parity Right BSDP08- BSDP08+ BSDP08+
Integrity Accompanying Address Parity BSAP00- MYAP00+00 Transfer Static Integrity Logic Test Out BSQLTO-Static Integrity Logic Test In BSQLTI- _ ~liscellaneous Control Mas~er Clear BSMCLR- ZGND BSMCLR+
~ Power On BSPWON+ _ Miscellaneous Control Resume Inter- BSRINT- _ rupting _ __ _ Tie-Breaking Network _ BSAUOK+ _ _ BSBUOK+ _ _ BSCUOK+ _ _ _ BSDUOK+ _ _ BSEUOK+ _ _ BSFUOK+ _ _ BSGUOK+ _ _ BSHUOK+ _ _ BSIUOK+ _ Tie-Breaking Network BSMYOK+

TABLE III
RETURNED DATA NORMAL AND INTERMIXED
DATA COUNTER INCREMENT TABLE ~POR TWO REQUESTS, DOUBLE-PULL MEMORY, AND INTERLEAVED MODE) REFER TO NOTE FOR
EXPLANATION OF DATA ADDRESSES
RETURNED REQUESTED ASSOCIATED . _ __ ADDRESS DATA SEQUENCE PRA PRA + 1 PRA + 2 PRA + 3 ~ormal data return sequence ~PRA, PRA + 2) (PRA + 1, PRA ~ 3 . . . + 1 + 2 emory module priority reversal [PRA + 1, PRA) (PRA + 3, PRA + 2 . . .
lemory module priority reversal [PRA, PRA + 1) (PRA + 2, PRA + 3 + 1 + 2 RA + 3 out of range + 2 + 1 PRA, PRA + 2) (PRA + 1) RA + 3 out of ran~e with memory + 1 -~ 2 odule priority reversal [PRA, PRA + 1) (PRA + 2) _ RA + 2, PRA + 3 out of range + 1 + 2 ~PRA, PRA + 1) _ RA + 2, PRA + 3 out of range + 2 + I
ith memory module priority reversal (PRA + 1, PRA) NOTE
The data counter is incremented + 1 or + 2 (i.e., illustrated inside table squares) when signal BSDBPL is false along with the following associated data addresses: PRA, PRA + 1, PRA + 2, and PRA + 3.

$

Claims (7)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. In a data processing system which includes at least one control processing unit (CPU), at least one main memory, and at least one cache store all coupled to a system bus for communicating with each other via said system bus, a portion of said main memory being partitioned in modules, pre-determined ones of said modules being word-organized in banked mode wherein words are stored sequentially at numerical addresses O to n, and predeter-mined others of said modules being word-organized in interleaved mode where-in pairs of modules wherein a first of said pairs of modules has the even numerical addresses and a second of said pairs of modules has the odd num-erical addresses, and said words are stored sequentially at said even and odd addresses alternating between said pairs of modules, a multi-configur-able cache store unit for permitting cache memory to read words from said main memory in any of a plurality of word modes, said multi-configurable cache store comprising:
a. first means responsive to said cache store for reading one word from a selected one of said banked word-organized modules in said main memory; and, b. second means responsive to said cache store for reading two successive adjacent words from a selected pair of interleaved word-organized modules of said main memory, one word being read from said first of said pairs of modules and another word being read from said second of said pairs of modules of said main memory.

2. The apparatus as recited in Claim 1 including third means respon-sive to said cache store for reading two words from two adjacent addresses in a selected one of said banked word-organized modules in said main memory.

3. The apparatus as recited in Claim 2 including fourth means responsive to said cache store for reading four words from two adjacent addresses from a selected pair of interleaved word-organized modules of said main memory> two words being read one each from two successive addres-ses from said first of said pairs of modules and another two words being read from successive addresses of said second of said pairs of modules.

4. The apparatus as recited in Claim 3 including fifth means re-sponsive to said cache store for providing one address request to said banked word-organized main memory, and also including sixth means for re-ceiving in response to said address request one data word from that address of main memory.

5. The apparatus as recited in Claim 4 including seventh means re-sponsive to said cache store for providing one address request to said banked word-organized main memory, and also including eighth means for receiving in response to said one address request two words, one each from that address and from the next adjacent address of said banked word-organized main memory.

6. The apparatus as recited in Claim 5 including ninth means re-sponsive to said cache store for providing two address requests, one each for adjacent addresses of said interleaved mode of said pairs of modules of said main memory, and further including tenth means for receiving in re-sponse to said two address requests two words, one from each of said mod-ules.

7. The apparatus as recited in Claim 6 including eleventh means responsive to said cache store for providing two address requests, one each for adjacent addresses of said interleaved mode of said pairs of modules of said main memory, and further including tenth means for receiving four words in response to said two address requests, two words from each of said mod-ules.