CA1128148A - Fast redundant pulse density analyzer - Google Patents
Fast redundant pulse density analyzerInfo
- Publication number
- CA1128148A CA1128148A CA319,902A CA319902A CA1128148A CA 1128148 A CA1128148 A CA 1128148A CA 319902 A CA319902 A CA 319902A CA 1128148 A CA1128148 A CA 1128148A
- Authority
- CA
- Canada
- Prior art keywords
- output terminal
- threshold
- output
- input
- binary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
- G01R29/033—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values giving an indication of the number of times this occurs, i.e. multi-channel analysers (the characteristic being frequency)
Abstract
D-21,030 A FAST REDUNDANT PULSE DENSITY ANALYZER
by Gerard J. Miille ABSTRACT OF THE DISCLOSURE
A self-checking pulse density analyzer includes substantially similar first and second threshold detection circuits, each of which have one input connected to receive incoming pulse information to be analyzed, and each of which provide the same binary signal state at a separate output terminal, when the pulse density reaches a predetermined level. Each output terminal is connected to a separate input terminal of a threshold equalizing circuit and to respective inputs of first and second gating circuits. The threshold equalizing circuit is activated by the binary signal from the faster acting threshold detection circuit to speed up the operation of the slower threshold detection circuit and, thus, minimize the difference in operating time between the two circuits. These two nearly simultaneous binary indications cause the first gating circuit to operate and, thus, provide a particular binary output signal indicative thereof. When the binary indications are substantially separated in time, or if one does not occur, the second gating circuit is effectuated to indicate a failure of one threshold detection circuit.
by Gerard J. Miille ABSTRACT OF THE DISCLOSURE
A self-checking pulse density analyzer includes substantially similar first and second threshold detection circuits, each of which have one input connected to receive incoming pulse information to be analyzed, and each of which provide the same binary signal state at a separate output terminal, when the pulse density reaches a predetermined level. Each output terminal is connected to a separate input terminal of a threshold equalizing circuit and to respective inputs of first and second gating circuits. The threshold equalizing circuit is activated by the binary signal from the faster acting threshold detection circuit to speed up the operation of the slower threshold detection circuit and, thus, minimize the difference in operating time between the two circuits. These two nearly simultaneous binary indications cause the first gating circuit to operate and, thus, provide a particular binary output signal indicative thereof. When the binary indications are substantially separated in time, or if one does not occur, the second gating circuit is effectuated to indicate a failure of one threshold detection circuit.
Description
~L213~4~
D-21,030C
1 A ~ASr REDUNDANT PUISE DENSI~Y ANALYZER
3 BACKGROUND OF ~HE INVENTION
ield of the Invention 6 ~his invention relates to pulse density an~lyzers which 7 provide an output indication when the pulse density input to the 8 analyzer reaches a certain level and, more particularly, to a self-9 checking analyzer which provides a continuous self-check of the pulse density analysis.
l2 Description of the Prior Ar-t 13 Many prior-art error plllse density analyzers use a l4 combination of a counter and a timer, such as is disclosed in U.S.
Patent No. 4,0~0,589, by Ralph L. Kline, granted March 21, 1978, 16 and entitled "Error Density Detector". 'When such error detectors 17 receive an initial error pulse, a timer is started and error pulses l8 are counted during the timing interval. A disadvantage of this 1~ prior-art technique arises when one tries to make the circuit self-checking. Lasically, one of two methods of self-checkin~ ~ay be 21 used. The first method consists of periodically sending a known-22 density error pulse train through the density calculator and 23 verifying whether or not an alarm signal appears at the output.
24 ~his method does not verify that the circuit is reacting at the correct density threshold because its counter could be overflowing 26 earlier than it should. lhe second method of self-checking 27 involves a redundant error density analyzer circuit. Since the 28 timers use timing ~1 _ ~
D-21,030 1 components with varyin~ manufacturing tolerances, the two
D-21,030C
1 A ~ASr REDUNDANT PUISE DENSI~Y ANALYZER
3 BACKGROUND OF ~HE INVENTION
ield of the Invention 6 ~his invention relates to pulse density an~lyzers which 7 provide an output indication when the pulse density input to the 8 analyzer reaches a certain level and, more particularly, to a self-9 checking analyzer which provides a continuous self-check of the pulse density analysis.
l2 Description of the Prior Ar-t 13 Many prior-art error plllse density analyzers use a l4 combination of a counter and a timer, such as is disclosed in U.S.
Patent No. 4,0~0,589, by Ralph L. Kline, granted March 21, 1978, 16 and entitled "Error Density Detector". 'When such error detectors 17 receive an initial error pulse, a timer is started and error pulses l8 are counted during the timing interval. A disadvantage of this 1~ prior-art technique arises when one tries to make the circuit self-checking. Lasically, one of two methods of self-checkin~ ~ay be 21 used. The first method consists of periodically sending a known-22 density error pulse train through the density calculator and 23 verifying whether or not an alarm signal appears at the output.
24 ~his method does not verify that the circuit is reacting at the correct density threshold because its counter could be overflowing 26 earlier than it should. lhe second method of self-checking 27 involves a redundant error density analyzer circuit. Since the 28 timers use timing ~1 _ ~
D-21,030 1 components with varyin~ manufacturing tolerances, the two
2 timers may have slightly different time-out times. ~his could
3 initiate a self-check alarm since the two circuits have diferent
4 outputs even though there is no circuit failure.
6 SUMMA~Y OF THE INVENTION
8 A self-checking pulse density analyzer includes first 9 and second threshold detection circuits connected so that an input terminal of each accepts the pulses to be analyzed. Each 11 detection circuit separately and simultaneously analyzes the 12 pulse density and provides a predetermined binary output state 13 when a certain predetermined threshold value is obtained. The 14 separate binary outputs from the threshold detector circuits are applied to a threshold equalizing means. The threshold 16 equalizing means changes the threshold reference potential of 17 the threshold detection means for both threshold detection 18 circuits once the predetermined binary output state is obtained 19 from the output terminal of one of the threshold detection circuits. This change in threshold reference potential causes 21 the threshold circuit of the other threshold detection means to ~2 provide a like binary output state when the difference in the 23 response is within that contemplated by the tolerance differences 24 of the elements. Such a result would not occur if one of the ~5 two circuits was not operating within the tolerance limits.
26 The output terminals of each of the threshold detection circuits 27 are connected to inputs of a responsive means which provides 30 ~ inar~ output indication when both threshold detection meens 3~
D-21,030 1 provide the predetermined binary state. Alternatively, the 2 responsi~Je means provides a separate binary output when the 3 binary outputs of the threshold detection means are of unli~e 4 states.
6 B~IEF DESCRIPTION OF THE DRAWING
8 FIG. 1, the only Figure in the drawing, is a schematic 9 of a preferred embodiment of applicant's invention.
11 DE,TAILED DESCRIPTION ~F THE INVENTION
13 Pulses enter the pulse density analyzer via path 2, 14 and these pulses are applied essentially simultaneously to substantially similar threshold detection means 8 and 10. Since 16 the two separate threshold detection means operate in substan-17 tially the same manner, only the arrangement shown in 8 will be 18 described. The incoming pulses on path 4 are applied to the 19 discharge path 12 comprising isolating resistor 14, bias resistor 16, transistor 18, and discharge resistor 20. The 21 incoming pulses bias transistor 18 on, which connects resistor 22 20 to ground, thus discharging capacitor 26. When transistor 23 18 is turned off, i.e., no pulses appearing on path 4, capacitor ~a 26 is charged from supply source +V via resistor 24~ Because -26 the charging and discharging paths are separate, the charging 2~ and discharging rates may be adjusted, by proper selection 27 of resistors 20 and 24, to operate at any desired pulse ~8 density. It is apparent that the discharging rate will ~9 ~0 ~ il3L~
D-21,030 1 generally be greater than the charging rate for error detection 2 purposes. Thus, when pulses occur frequently enough, capacitor 3 2~ will discharge more during the occurrence of the pulses than 4 it char~es during the time between pulses, and the average voltage on capacitor 26 will begin to drop. Since this voltage 6 is applied to the inverting input of comparator 28, when the 7 inverting input voltage drops below the threshold reference 8 voltage established by the potential applied to the noninverting 9 input of the comparator 28, the comparator will switch. This inverts the binary output signal on path 32 which is an alarm 11 or detection state. The threshold reference voltage applied 12 to the noninverting input of comparator 28 is derived from 13 reference source 56 by means of resistors 58 and 60 in a voltage 14 divider arrangement connected between the source voltage ~V
and ground.
16 It is to be noted that threshold detection means 10 17 operates in a similar manner and, if it were to perform its 18 function in the same time period as the threshold detection 19 means 8, there would occur simultaneously on path 54 a binary output signal of the same binary state (detection state) as 21 that obtained on path 32. Paths 32 and 54 are connected to 22 alarm gating means 68 and, as shown in the drawing, each is 23 connected to both AND-gate 7Q and Exclusive-OR gate 72. If 24 a detection state is present at paths 32 and 54 at the same time, AND-gate 70 will so indicate by providing a binary signal 26 on output path 74. Buth if one threshold detection circuit 27 provides a detection state at its output, but the other does 22380 ~ n at or about the same time, the information presented D-21,030 1 to the inputs of Exclusive-OR gate 72 are unlike binary states 2 and gate 72 will provide an output alarm indication. This 3 alarm indication is evidence of the fact that the self-checking 4 circuit shows that the pulse analyzer is not operating properly.
Because of the various manufacturing tolerances that 6 could obtain for the various electrical components included in the two threshold detection means, it is apparent that operation 8 of the arrangement, as described, could indicate that the pulse 9 density analyzer is not operating properly even though, in fact, it is only the tolerances of the components which prevent the 11 two threshold detection means from performing the function 12 within the same time period. To overcome this problem, threshold 13 equalizing means 62 is employed. The function oE equalizing 1~ means 62 is to change the refererlce potential, which is applied to the noninverting inputs of diferential amplifiers 28 and 50, 16 so that the effective threshold clifferential is significantly 17 decreased. This is accomplished by the use of resistors 30 18 and 52, and diodes 64 and 66~as follows. Before the incoming 19 pulses cause threshold detector 8 to reach a threshold state, the output of differential amplifier 28 is a binary 0. In 21 essence, it has a low voltage output signal applied to path 32 ~2 and diode 64 is back biased. Similarly, for the threshold 23 detection circuit 10 and diode 66 When the output signal 2~ of differential amplifier 28 changes states, i.e~, becomes binary 1, the voltage on path 32 swings toward +V, diode 64 26 is forward biased and this new voltage is applied via path 65, 27 junction 59, as the threshold reference potential to the 2390 ~ noninverti inputs of differential arplifiers 28 and 50.
31 _ 5 _ ~Z~
D-21,030 1 This change in threshold reference potential narrows or 2 eliminates the difference in potential between the two inputs 3 of the differential amplifier, i.e., lowers the threshold, and it adds hysteresis. The result is that when one comparator switches, the feedback signal raises the threshold and, if 6 the other comparator is near the switching threshold, it, too, ,~ will now switch since the threshold has been raised. Thus, 8 minor differences in component values will not cause any false 9 self-test alarms. The very narrow differences in time of operation, which could result, can be eliminated with a delay 11 which will not significantly lengthen the response time. Such 12 an arrangement is not shown since it is considered to be known 13 by those having skill in the art.
14 While the invention has been particularly shown and described with reference to a preEerred embodiment thereof, 16 it will be understood by those skilled in the art that change 17 in form and detail may be made therein without departing from 18 the spirit and scope of the invention.
6 SUMMA~Y OF THE INVENTION
8 A self-checking pulse density analyzer includes first 9 and second threshold detection circuits connected so that an input terminal of each accepts the pulses to be analyzed. Each 11 detection circuit separately and simultaneously analyzes the 12 pulse density and provides a predetermined binary output state 13 when a certain predetermined threshold value is obtained. The 14 separate binary outputs from the threshold detector circuits are applied to a threshold equalizing means. The threshold 16 equalizing means changes the threshold reference potential of 17 the threshold detection means for both threshold detection 18 circuits once the predetermined binary output state is obtained 19 from the output terminal of one of the threshold detection circuits. This change in threshold reference potential causes 21 the threshold circuit of the other threshold detection means to ~2 provide a like binary output state when the difference in the 23 response is within that contemplated by the tolerance differences 24 of the elements. Such a result would not occur if one of the ~5 two circuits was not operating within the tolerance limits.
26 The output terminals of each of the threshold detection circuits 27 are connected to inputs of a responsive means which provides 30 ~ inar~ output indication when both threshold detection meens 3~
D-21,030 1 provide the predetermined binary state. Alternatively, the 2 responsi~Je means provides a separate binary output when the 3 binary outputs of the threshold detection means are of unli~e 4 states.
6 B~IEF DESCRIPTION OF THE DRAWING
8 FIG. 1, the only Figure in the drawing, is a schematic 9 of a preferred embodiment of applicant's invention.
11 DE,TAILED DESCRIPTION ~F THE INVENTION
13 Pulses enter the pulse density analyzer via path 2, 14 and these pulses are applied essentially simultaneously to substantially similar threshold detection means 8 and 10. Since 16 the two separate threshold detection means operate in substan-17 tially the same manner, only the arrangement shown in 8 will be 18 described. The incoming pulses on path 4 are applied to the 19 discharge path 12 comprising isolating resistor 14, bias resistor 16, transistor 18, and discharge resistor 20. The 21 incoming pulses bias transistor 18 on, which connects resistor 22 20 to ground, thus discharging capacitor 26. When transistor 23 18 is turned off, i.e., no pulses appearing on path 4, capacitor ~a 26 is charged from supply source +V via resistor 24~ Because -26 the charging and discharging paths are separate, the charging 2~ and discharging rates may be adjusted, by proper selection 27 of resistors 20 and 24, to operate at any desired pulse ~8 density. It is apparent that the discharging rate will ~9 ~0 ~ il3L~
D-21,030 1 generally be greater than the charging rate for error detection 2 purposes. Thus, when pulses occur frequently enough, capacitor 3 2~ will discharge more during the occurrence of the pulses than 4 it char~es during the time between pulses, and the average voltage on capacitor 26 will begin to drop. Since this voltage 6 is applied to the inverting input of comparator 28, when the 7 inverting input voltage drops below the threshold reference 8 voltage established by the potential applied to the noninverting 9 input of the comparator 28, the comparator will switch. This inverts the binary output signal on path 32 which is an alarm 11 or detection state. The threshold reference voltage applied 12 to the noninverting input of comparator 28 is derived from 13 reference source 56 by means of resistors 58 and 60 in a voltage 14 divider arrangement connected between the source voltage ~V
and ground.
16 It is to be noted that threshold detection means 10 17 operates in a similar manner and, if it were to perform its 18 function in the same time period as the threshold detection 19 means 8, there would occur simultaneously on path 54 a binary output signal of the same binary state (detection state) as 21 that obtained on path 32. Paths 32 and 54 are connected to 22 alarm gating means 68 and, as shown in the drawing, each is 23 connected to both AND-gate 7Q and Exclusive-OR gate 72. If 24 a detection state is present at paths 32 and 54 at the same time, AND-gate 70 will so indicate by providing a binary signal 26 on output path 74. Buth if one threshold detection circuit 27 provides a detection state at its output, but the other does 22380 ~ n at or about the same time, the information presented D-21,030 1 to the inputs of Exclusive-OR gate 72 are unlike binary states 2 and gate 72 will provide an output alarm indication. This 3 alarm indication is evidence of the fact that the self-checking 4 circuit shows that the pulse analyzer is not operating properly.
Because of the various manufacturing tolerances that 6 could obtain for the various electrical components included in the two threshold detection means, it is apparent that operation 8 of the arrangement, as described, could indicate that the pulse 9 density analyzer is not operating properly even though, in fact, it is only the tolerances of the components which prevent the 11 two threshold detection means from performing the function 12 within the same time period. To overcome this problem, threshold 13 equalizing means 62 is employed. The function oE equalizing 1~ means 62 is to change the refererlce potential, which is applied to the noninverting inputs of diferential amplifiers 28 and 50, 16 so that the effective threshold clifferential is significantly 17 decreased. This is accomplished by the use of resistors 30 18 and 52, and diodes 64 and 66~as follows. Before the incoming 19 pulses cause threshold detector 8 to reach a threshold state, the output of differential amplifier 28 is a binary 0. In 21 essence, it has a low voltage output signal applied to path 32 ~2 and diode 64 is back biased. Similarly, for the threshold 23 detection circuit 10 and diode 66 When the output signal 2~ of differential amplifier 28 changes states, i.e~, becomes binary 1, the voltage on path 32 swings toward +V, diode 64 26 is forward biased and this new voltage is applied via path 65, 27 junction 59, as the threshold reference potential to the 2390 ~ noninverti inputs of differential arplifiers 28 and 50.
31 _ 5 _ ~Z~
D-21,030 1 This change in threshold reference potential narrows or 2 eliminates the difference in potential between the two inputs 3 of the differential amplifier, i.e., lowers the threshold, and it adds hysteresis. The result is that when one comparator switches, the feedback signal raises the threshold and, if 6 the other comparator is near the switching threshold, it, too, ,~ will now switch since the threshold has been raised. Thus, 8 minor differences in component values will not cause any false 9 self-test alarms. The very narrow differences in time of operation, which could result, can be eliminated with a delay 11 which will not significantly lengthen the response time. Such 12 an arrangement is not shown since it is considered to be known 13 by those having skill in the art.
14 While the invention has been particularly shown and described with reference to a preEerred embodiment thereof, 16 it will be understood by those skilled in the art that change 17 in form and detail may be made therein without departing from 18 the spirit and scope of the invention.
Claims (8)
1. Apparatus for analyzing the pulse density of pulses in a pulse train, including a self-checking circuit, comprising:
a threshold reference potential having an output terminal;
a first threshold detector having a first input terminal arranged to accept said pulse train, having a second input terminal connected to the output terminal of said threshold reference potential, and having an output for providing at its output terminal a binary output signal of one state when the pulse density at said input terminal reaches a predetermined threshold value;
a second threshold detector having a first input terminal arranged to accept said pulse train, having a second input terminal connected to the output terminal of said threshold reference potential, and having an output terminal for providing at its output terminal a binary output signal of said one state when the pulse density at said input terminal reaches said predetermined threshold value;
a threshold equalizer having a first input terminal connected to the output terminal of said first threshold detector, having a second input terminal connected to the output terminal of said second threshold detector, and having output terminal connected to the output terminal of said threshold reference potential, said threshold equalizer being responsive to said one state of the output signal of one of the two threshold detectors, whichever occurs first, for effecting a simultaneous change in the threshold reference potential applied to both threshold detection circuits;
and D-21,030C
means responsive to the output signals from said first and second threshold detectors for providing a first output indication when said binary output signals are of said one state and a second output indication when said binary output signals are of unlike states.
a threshold reference potential having an output terminal;
a first threshold detector having a first input terminal arranged to accept said pulse train, having a second input terminal connected to the output terminal of said threshold reference potential, and having an output for providing at its output terminal a binary output signal of one state when the pulse density at said input terminal reaches a predetermined threshold value;
a second threshold detector having a first input terminal arranged to accept said pulse train, having a second input terminal connected to the output terminal of said threshold reference potential, and having an output terminal for providing at its output terminal a binary output signal of said one state when the pulse density at said input terminal reaches said predetermined threshold value;
a threshold equalizer having a first input terminal connected to the output terminal of said first threshold detector, having a second input terminal connected to the output terminal of said second threshold detector, and having output terminal connected to the output terminal of said threshold reference potential, said threshold equalizer being responsive to said one state of the output signal of one of the two threshold detectors, whichever occurs first, for effecting a simultaneous change in the threshold reference potential applied to both threshold detection circuits;
and D-21,030C
means responsive to the output signals from said first and second threshold detectors for providing a first output indication when said binary output signals are of said one state and a second output indication when said binary output signals are of unlike states.
2. The analyzer of claim 1 wherein said first threshold detector comprises:
a first charge storage means having an input and an output;
first means for continuously supplying charge to said first charge storage means;
a first gating means responsive to the pulses at said first input terminal for discharging said first charge storage means at a rate greater than the charging rate; and a first comparator having a first input terminal connected to said threshold reference potential, a second input terminal connected to the output terminal of said charging means, and having an output terminal connected to the output terminal of said first threshold detector for providing the binary output signal at said output terminal when the charge on said charge storage means reaches a predetermined value.
a first charge storage means having an input and an output;
first means for continuously supplying charge to said first charge storage means;
a first gating means responsive to the pulses at said first input terminal for discharging said first charge storage means at a rate greater than the charging rate; and a first comparator having a first input terminal connected to said threshold reference potential, a second input terminal connected to the output terminal of said charging means, and having an output terminal connected to the output terminal of said first threshold detector for providing the binary output signal at said output terminal when the charge on said charge storage means reaches a predetermined value.
3. The analyzer of claim 2 wherein said second threshold detector comprises:
a second charge storage means having an input and an output;
second means for continuously supplying charging current to said second charge storage means;
D-21,030C
a second gating means responsive to the pulses at said first input terminal for discharging said second charge storage means at a rate greater than the charging rate; and a second comparator having a first input terminal connected to said threshold reference potential, a second input terminal connected to the output terminal of said charging means, and having an output terminal connected to the output terminal of said second threshold detector for providing an output signal at said output terminal when the charge on said second charge storage means reaches a predetermined value.
a second charge storage means having an input and an output;
second means for continuously supplying charging current to said second charge storage means;
D-21,030C
a second gating means responsive to the pulses at said first input terminal for discharging said second charge storage means at a rate greater than the charging rate; and a second comparator having a first input terminal connected to said threshold reference potential, a second input terminal connected to the output terminal of said charging means, and having an output terminal connected to the output terminal of said second threshold detector for providing an output signal at said output terminal when the charge on said second charge storage means reaches a predetermined value.
4. Apparatus in accordance with claim 1 wherein said threshold equalizer further comprises:
first diode means having an input terminal connected to the output terminal of said first threshold detector, and having an output terminal connected to the output terminal of said threshold reference potential; and second diode means having an input terminal connected to the output terminal of said second threshold detector, and having an output terminal connected to the output terminal of said threshold reference potential.
first diode means having an input terminal connected to the output terminal of said first threshold detector, and having an output terminal connected to the output terminal of said threshold reference potential; and second diode means having an input terminal connected to the output terminal of said second threshold detector, and having an output terminal connected to the output terminal of said threshold reference potential.
5. Apparatus in accordance with claim 3 wherein said threshold equalizer further comprises:
first diode means having an input terminal connected to the output terminal of said first threshold detector, and having an output terminal connected to the output terminal of said threshold reference potential; and second diode means having an input terminal D-21,030C
connected to the output terminal of said second threshold detector, and having an output terminal connected to the output terminal of said threshold reference potential.
first diode means having an input terminal connected to the output terminal of said first threshold detector, and having an output terminal connected to the output terminal of said threshold reference potential; and second diode means having an input terminal D-21,030C
connected to the output terminal of said second threshold detector, and having an output terminal connected to the output terminal of said threshold reference potential.
6. Apparatus in accordance with claim 1 wherein said means responsive further comprises:
first gating means having an output terminal, having a first input terminal connected to the output terminal of said first threshold detector, and having a second input terminal connected to the output terminal of said second threshold detector, whereby a binary output signal of a predetermined state appears at said output terminal when the binary input signals on said first and second input terminals are of one like state; and second gating means having an output terminal, having a third input terminal connected to the output terminal of said first threshold detector, and having a fourth input terminal connected to the output terminal of said second threshold detector, whereby a binary output signal of a predetermined state appears at said output terminal when the binary input signals on said first and second input terminals are of unlike states.
first gating means having an output terminal, having a first input terminal connected to the output terminal of said first threshold detector, and having a second input terminal connected to the output terminal of said second threshold detector, whereby a binary output signal of a predetermined state appears at said output terminal when the binary input signals on said first and second input terminals are of one like state; and second gating means having an output terminal, having a third input terminal connected to the output terminal of said first threshold detector, and having a fourth input terminal connected to the output terminal of said second threshold detector, whereby a binary output signal of a predetermined state appears at said output terminal when the binary input signals on said first and second input terminals are of unlike states.
7. Apparatus in accordance with claim 3 wherein said means responsive futher comprises:
first gating means having an output terminal, having a first input terminal connected to the output terminal of said first threshold detector, and having a second input terminal connected to the output terminal of said second threshold D-21,030 detector, whereby a binary output signal of a predetermined state appears at said output terminal when the binary input signals on said first and second input terminals are of one like state; and second gating means having an output terminal, having a third input terminal connected to the output terminal of said first threshold detector, and having a fourth input terminal connected to the output terminal of said second threshold detector, whereby a binary output signal of a pre-determined state appears at said output terminal when the binary input signals on said first and second input terminals are of unlike states.
first gating means having an output terminal, having a first input terminal connected to the output terminal of said first threshold detector, and having a second input terminal connected to the output terminal of said second threshold D-21,030 detector, whereby a binary output signal of a predetermined state appears at said output terminal when the binary input signals on said first and second input terminals are of one like state; and second gating means having an output terminal, having a third input terminal connected to the output terminal of said first threshold detector, and having a fourth input terminal connected to the output terminal of said second threshold detector, whereby a binary output signal of a pre-determined state appears at said output terminal when the binary input signals on said first and second input terminals are of unlike states.
8. Apparatus in accordance with claim 4 wherein said means responsive further comprises:
first gating means having an output terminal, having a first input terminal connected to the output terminal of said first threshold detector, and having a second input terminal connected to the output terminal of said second threshold detector, whereby a binary output signal of a predetermined state appears at said output terminal when the binary input signals on said first and second input terminals are of one like state; and second gating means having an output terminal, having a third input terminal connected to the output terminal of said first threshold detector, and having a fourth input terminal connected to the output terminal of said second threshold detector, whereby a binary output signal of a predetermined state appears at said output terminal when the D-21,030 binary input signals on said first and second input terminals are of unlike states.
first gating means having an output terminal, having a first input terminal connected to the output terminal of said first threshold detector, and having a second input terminal connected to the output terminal of said second threshold detector, whereby a binary output signal of a predetermined state appears at said output terminal when the binary input signals on said first and second input terminals are of one like state; and second gating means having an output terminal, having a third input terminal connected to the output terminal of said first threshold detector, and having a fourth input terminal connected to the output terminal of said second threshold detector, whereby a binary output signal of a predetermined state appears at said output terminal when the D-21,030 binary input signals on said first and second input terminals are of unlike states.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/885,157 US4207534A (en) | 1978-03-10 | 1978-03-10 | Fast redundant pulse density analyzer |
| US885,157 | 1978-03-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1128148A true CA1128148A (en) | 1982-07-20 |
Family
ID=25386284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA319,902A Expired CA1128148A (en) | 1978-03-10 | 1979-01-18 | Fast redundant pulse density analyzer |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4207534A (en) |
| CA (1) | CA1128148A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54156610A (en) * | 1978-05-31 | 1979-12-10 | Tdk Corp | Inspecting method of magnetic recording tapes |
| US4359650A (en) * | 1980-11-13 | 1982-11-16 | The United States Of America As Represented By The Secretary Of The Air Force | High voltage driver amplifier apparatus |
| US4774718A (en) * | 1987-07-24 | 1988-09-27 | Esm International Inc. | Automatic ejector rate normalizer |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3074639A (en) * | 1958-08-12 | 1963-01-22 | Philips Corp | Fast-operating adder circuits |
| US3600606A (en) * | 1968-02-15 | 1971-08-17 | Design Products Corp | Voltage comparator |
| US3851259A (en) * | 1973-03-30 | 1974-11-26 | Bendix Corp | Deadzone circuit |
| US3803425A (en) * | 1973-05-03 | 1974-04-09 | Bendix Corp | Failure detection by period comparison |
| JPS52142955A (en) * | 1976-05-24 | 1977-11-29 | Sumitomo Metal Ind | Method of controlling pulse signal level balance |
| US4065721A (en) * | 1976-11-15 | 1977-12-27 | General Motors Corporation | Solid state threshold detector with hysteresis |
-
1978
- 1978-03-10 US US05/885,157 patent/US4207534A/en not_active Expired - Lifetime
-
1979
- 1979-01-18 CA CA319,902A patent/CA1128148A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4207534A (en) | 1980-06-10 |
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