CA1130008A - Method and apparatus for error control in asynchronous communications - Google Patents

Abstract

ABSTRACT

METHOD & APPARATUS FOR ERROR CONTROL
IN ASYNCHRONOUS COMMUNICATIONS

Error control, in the form of a modulo 2 division re-mainder checksum is added to a packet of reformatted asynchronous characters prior to transmission over a data link connecting two data devices such as a host computer and a teletype terminal. At one end of the link, data in asynchronous form, such as ASCII code, comprising seven data bits, start and stop bits, and a parity bit, is originated by one data device. The start, stop and parity bits of each character are eliminated. The remaining data bits for a selected number of characters are then grouped together to form a data grouping and the checksum and other control in-formation bits added, forming an information packet.
The information packet is then divided into sections or groups of eight bits. Start and stop bits are added to each group, forming ten bit characters. The ten bit characters are then transmitted over the data link in standard asynchronous format. The process is carried out in reverse at the other end of the link, resulting in the other data device receiving the data in the form originated by the first data device.
Sophisticated error control techniques thus may be implemented in asynchronous communications without detrimentally affecting the data capacity on the channel.

Description

3~0C~8 lMETHOD & APPARATUS FOR ERROR CONTROL
_ IN ASYNCHRONOUS COMMUNICATIONS

The present invention primarily concerns the art of asyn-chronous communication, and more particularly relates to a method of providing error control for asynchronous communications.

Historically, asynchronous communication has been low speed, on the order of 5 characters per second (CPS) to 30 cps, assuming ten bit characters. An example of equip-ment using asynchronous communication is the well-known teletype machine. Companion transmission line devices, such as multiplexers and modulator/demodulators (modems), are available which operate at similar speeds.

In asynchronous communication, data is transmitted on a character by character basis, and synchronization is achieved between transmitter and receiver on a character basis by the start and stop bits positioned at the start and end of each data character. Different data code for-mats utilize a different number of data bits per charac-ter. For instance, the ASCII code uses seven data bits, the start and stop bits, and a parity bit to form its 10 bit characters.

Heretofore, there has been no error control utilized in .

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- 2 - 1~3~8 asynchronous communication, except for the parity bit in the ASCII code, which results only in an elementary form of error check. This lack of error control in asyn-chronous communication is in contrast to the rather com-plex error control techniques which have bean developedfor synchronous communication.

In synchronous communication, higher data rates, i.e., 200-1200 cps, are used, and the synchronization between transmitter and receiver is achieved by synchronized clocks at the transmitter and receiver. Sophisticated error control techniques have been developed and used in synchronous communication because of the high error rate present at such high speeds. Only synchronous equipment, which is large and expensive, has had error control cap-ability in the past. In asynchronous communication, theerror rate has historically been relatively low, on the order of one error or less per page of text. Furthermore, errors in asynchronous communication were usually not very serious, as such communication usually involved just text data, to be read by a human being. Errors could thus be relatively easily detected, and corrected by the user.

~owever, errors in asynchronous communication are now be-coming increasingly intolerable, due to several technical developments in the art. Higher transmission speeds, e.g.
120 cps, are now becoming common, but with a corresponding _ 3 _ ~13~8 significant increase in errors. Additionally, graphic type data is being transmitted asychronously, in which even a single bit error can have very serious consequences.
Furthermore, files are being transferred between computers asynchronously, and in such a case, errors cannot be easily discerned and corrected by a human operator.

The parity bit error control technique is not sufficient to achieve the quality of error control necessary with such technical developments, while the more sophisticated error control technigues used in synchronous communica-tion, which add between 8 and 32 bits to a data burst, are not feasible with the current character-by character asynchronous form of data transmission. Adding error con-trol bits to existing character-by-character asynchronous communications would seriously degrade the data capacity of the communication system, which is an unacceptable re-sult.

Thus, there is a significant need for a reliable, sophis-ticated error control technique which can be used in asynchronous communications, but which does not result in a reduction in the data capacity of the communication system. Also, it is desirable that the apparatus for im-plementing such an error control method be useful with existing asynchronous data devices, such as teletypes and modems, while being transparent to the user and host . ~
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, ~3~@8 devices and the transmission line data link, so that no modification of such devices, or the data link, is nec-essary.

Accordingly, it is a general object of the present invention to provide a method of and apparatus for error control for asynchronous communication which overcomes one or more of the disadvantages of the prior art noted above.

The present invention provides for an asynchronous digital data communication system for use with two digital data communication stations, both adapted to operate asynchron-ously with digital characters made up of first control bits and a predetermined number of data bits, comprising: a first terminal and a second terminal operable with the two sta-tions, respectively, and means operatively associated with said first terminal and said second terminal providing a communication cha~nnel therebetween; said first terminal including station input means operable with one station for asynchronously receiving a first character therefrom and combining only the data bits of said first character with string control bits to form a first information bit string, section means operatively associated with said station input means for dividing said first information bit string into sections, each having a number of bits equal to one more than said predetermined number, and channel output means operatively associated with said section means for adding section control bits to each section to form a digital word, and then asynchronously transmitting said digital word via said communication channel; said second terminal including channel input means operatively associated with said commun-ication channel for asynchronously receiving said digital ~ord and then removing sald section control bits thererom ,:

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to form a second information bit string, reformatting means operatively associated with said channel input means for combining only the data bits of said second information bit string with second control bits identical to said first control bits to form a second character identical to said first character, and station output means operatively associated with said reformatting means and operable with the other station for asynchronously presenting said second character to said other station.

The present invention also provides for an asynchronous digital data communication system for use with two digital data communication stations, both adapted to operate asynch-ronously with digital characters made up of first control bits and a predetermined number of data bits, comprising: a first terminal and a second terminal operable with the two stations, respectively, and means operatively associated with said first terminal and said second terminal providing a communication channel therebetween, each terminal includ-ing; (A) FQR TRANSMITTING TO THE OTHER TERMINAL --- station input means operable with one station for asynchronously receiving a first character therefrom and combining only the data bits of said first character with string control bits to form a first information bit string, section means operatively associated with said station input means for dividinq said first information bit string into sections, each having a number of bits equal to one more than said ::.
; predetermined number, and channel output means operatively ~ associated with said section means for adding section -- control bits to each section to form a di~ital word, and ~ then asynchronously transmitting said digital word via said .~'.' `' ' , !l ~
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- 6 - ~ ~8 communication channel; and (B) FOR RECEIVING FROM THE OTHER
TERMINAL --- channel input means operatively associated with said communication channel for asynchronously receiving said digital word and then removing said section control bits therefrom to form a second information bit string, reformat-ting means operatively associated with said channel input means for combining only the data bits of said second information bit string with second control bits identical to said first control bits to form a second character identical to said first character, and station output means operat-ively associated with said reformatting means and operable with the other station for asynchronously presenting said second character to said other station.

Further provided by the present invention is a terminal for presenting digital words to a communication channel and operable with a digital data communication station that is adapted to operate asynchronously with digital characters made up of first control bits and a predetermined number of data bits, the terminal comprising: (A) FOR TRANSMITTING
--- station input means operable with the station for asynchronously receiving a first character therefrom and combining only the data bits of said first character with string control bits to form a first informatio`n bit string;
section means operatively associated with said station input means for dividing said first information bit string into sections each having a number of bits equal to one more than said predetermined number; channel output means operatively associated with said section means for adding section control bits to each section to form a digital word, and then asynchronously presenting said digital word to the communication channel; and (B) FOR RECEIVING --- channel input means operatively associated with the communication , ~, - . .:, : : ., . :
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channel for asynchronously receiving said digital word and then removing said section control bits therefrom to form a second information bit string; reformatting means operativ-ely associated with said channel input means for combining only the data bits of said second information bit string with second control bits identical to said first control bits to form a second character identical to said first character; and station output means operatively associated with said reformatting means and operable with the station for asynchronously presenting said second character to said station.

The present invention further provides for a terminal for presenting digital words to a communication channel and operable with a digital data communication station that is adapted to operate asynchronously with digital characters made up of first control bits and a predetermined number of data bits, the terminal comprising: station input means operable with the station for asynchronously receiving a first character therefrom and combining only the data bits of said first character with string control bits to form a first information bit string; section means operatively associated with said station input means for dividing said first information bit string into sections, each having a number of bits equal to one mor~ than said predetermined number; and cbannel output means operatively associated with said section means for adding section control bits to each section to form a digital word, and then asynchronously presenting said digital word to the communication channel.

Also provided by the present invention is a method for asynchronous digital data transmission for use wi~h a ,' ;~
~: ,.~. , ` -7a-digital data communication station adapted to operate asynchronously with digital characters made up of first control bits and a predetermined number of data bits, the method comprising the steps of: asynchronously receiving a first character from the station; combining only the data bits of said first character with string control bits to form a first information bit string; dividing said first information bit string into sections, each having a number of bits equal to one more than said predetermined number;
adding section control bits to each section to form a digital word; asynchronously transmitting said digital word.

The present invention further provides for a method for receiving digital words for use with a digital data commun-ication station adapted to operate asynchronously with digital characters made up of first control bits and a predetermined number of data bits, said digital words including section control bits and sections, each section having a number of bits equal to one more than said prede-termined number and being a portion of a first information bit string, said first information bit string containing string control bits and only the data bits of a first digital character, the method comprising the steps of:
asynchronously receiving said digital word and then removing said section control bits therefrom to form a second infor-mation bit string; combining only the data bits of said second information bit string with second control bits identical to said first control bits to form a second character identical to said first character; and asynchron-ously presenting said second character to the station.

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~; ;:: ' , ' ' -7b-The present invention will be best understood from the following description of the accompanying drawings, in which:

Figure 1 is a schematic block diagram showing the apparatus which implements the method of the present invention in the environment of an asynchronous data communication link;

Figure 2 is a diagram showing the three diferent tiers, or formats, through which data progresses in the method of the present invention;

Figure 3 is a block diagram of the hardware realization of the apparatus which carries out the method of the present invention;

Figure 4 is a block diagram showing the flow of data inform-ation with the apparatus; and Figure S is a block diagram showing the flow of . .: ~ .- - -, : . ,: , . -- 8 - ~13~0~8 operational control within the apparatus.

The apparatus which is used to carry out the method of the present invention is referred to hereinafter as a terminal service unit (TSU) and is designed to be inte-grated into conventional asynchronous data links, withoutmodification to either the transmission line or any of the other asynchronous communication devices in the link.

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Figure 1 shows in schematic form how the apparatus is integrated into a given asynchronous data link. In Fig-ure 1, an asynchronous terminal device 10, such as astandard teletype machine, communicates with a host com-puter 12 over a transmission line 14 at standard asyn-chronous rates, e.g. 30 cps. The transmission line typically is a conventional telephone line, capable of handling full duplex ~i.e. simultaneous two-way) communi-cation.

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; Between the terminal 10 and the transmission line 14, as well as between the host 12 and transmission line 14 are a pair of modulator/demodulator (modems) 16 and 18, each of which modulate or demodulate the data applied to it, depending on the direction of the data. Additional devices, such as multiplexers and encrypt-decrypt de-; vices, may be on the data link. These devices are, how-ever, specifically designed to handle information at . -. . ~ . - . ~:.

- 9- 1~3~8 asynchronous speeds.

Such asynchronous data devices are usually designed to operate at particular set speeds, e.g. 5, 15 or 30 cps.
This is sometimes referred to as the bandwidth of the system but more accurately refers to the data transmis-sion capacity of the system. If, for instance, the trans-mitting data device and its modem are designed to handle a maximum data rate of 30 cps, information cannot be transmitted through the system faster than that rate, even though data may be available for transmission and the transmission line may be capable of handling higher rates.

The apparatus which implements the method of the present invention is referred to as a TSU, as mentioned above.
The TSU units must be used in pairs on a data link to achieve the advantages of the present invention. Each TSU is associated with a data device and is positioned between that device and the other communication devices, such as the modem, associated with the data de~ice.

In Figure 1, TSU 20 is positioned between terminal device 10 and modem 16 while TSU 22 is positioned between com-puter 12 and modem 18. Each TSU is capable of both trans-mitting and receiving asynchronous communications, and is transparent to the data link. Thus, the appearance .
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- 10 - ~L3~ P8 of the data presented by TSU 20 to modem 16 will be the same as the appearance of the data presented to the TSU
by the terminal device 10.

The information presented to the TSU from the terminal device 10 is in conventional asynchronous coded format, e.g. ASCII code, which comprises a series of 10 bit characters, each character having 7 data bits, a parity bit and start and stop bits. The information at the transmission line side of the TSU, however, while also being 10 bit characters having start and stop bits and thus having the same appearance as the terminal side in-formation, may contain either data or control information and sometimes both. The control information, when pres-ent, relates to a selected group of individual characters, as will be explained hereinafter.

Figure 2 shows in more detail the data reformatting pro-cess carried out by the TSU which permits the addition of control information, such as error control, to an ; asynchronous data transmission without reducing the data capacity of the communication system.
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Referring to Figure 2, tier 1 is representative of the conventional format of asynchronous information trans-mission, and is the coded format used in transmitting information between the TSU and its associated data : .
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113~ 8 device. The diagram shown in tier 1 represants a suc-cession of characters, in standard code format, delivered to the TSU by its associated data device. The characters shown in tier 1 of Figure 2 are in standard ASC~I code so that each character comprises 10 bits, including 7 bits of data, start and stop bits, and one parity bit.

As the characters are presented to the TSU, the start, stop and parity bits of each 10 bit character are stri~
off, and the remaining seven bits of data from each character are bunched together serially to form a data grouping referred to herein as a group of seven tuples, meaning a group of seven-bit blocks of data. This group of data is shown by the numeral 24 in Figure 2. The number of original characters having data in region 24 is determined dynamically by a packetizing algorithm, which will be discussed in more detail hereinafter. In the embodiment shown, the number of characters in the data grouping may vary between zero (only control in-formation is sent in the packet) and 64. Each character has 7 data bits, so if a given data group portion of a packet has 40 data characters, for example, as determined dynamically by the algorithm, the data group portion of the packet would comprise 40 x 7 = 280 bits.

Control information is then added to the end of the 7-tuple group to form what is referred to as an information . ., :; ,, :. ' ' '~

. . ;~' ' ' - 12 - 113~8 packet. The presence of control information in a packet is indicated by the message length not being equal to an integral multiple of seven, the character length in the data grouping, plus four. This feature eliminates the - 5 need for an extra bit to indicate the presence of control information.

The control information is divided into sections. The first section of control information, denoted by the numeral 26 in Figure 2, is a 7 bit control tuple field.
The control tuple is an optional section and comprises a three bit type code followed by a four bit function code.
The control tuples are used for protocol exchange be-tween TSU's, such as connect and disconnect procedures.

The next section is referred to as an extension field and is identified by the numeral 28 in Figure 2. The extension field, like the control tuple field, is not required in every tier 2 frame. The extension field comprises three one bit subfields. The first subfield is an extension NAK position, which, when set, indicates an error in a particular information packet which has been received from the other TSU. The second subfield is for an extension break, which, when set, indicates that a break signal is to be sent following delivery of the 7 tuple data in the packet being transmitted. The break signal holds the transmission line in one state I' ' .

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- 13 - 1~3~

for an extended period of time, e.g. 250 milliseconds.
The last position is an extension escape position which, when set, indicates that a control tuple is present in the packet.

The next section is a pacXet control field 30, which is mandatory in each packet and contains the control bits by which acknowledgement and synchronization of the in-formation packets is accomplished between the TSU's.
The packet control field comprises two three bit fields, referred to as packet number sent (PS) and packet num-ber received (PR). Although these fields will be des-cribed in more detail hereinafter, the packet number sent ~PS) in a particular packet identifies that packet in the sequence of packets being transmitted, while the packet number received (PR) in a packet is the number of the latest packet received and verified from the other TSU.

Following the packet control field 30 is a checksum field 32 which comprises the error control information ~20 in the embodiment shown for the packet. Although var-ious checksum techniques may be utilized in the method of the present invention, the checksum 30 is the re-mainder of modulo 2 division of all the bits in the packet by a generator polynomial. This remainder check-sum is an error control technique which is well known ' .:

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- 14 - 113~8 in synchronous communications. An explanation of this technique for error control may be found in the book titled "Error Correcting Codes," by W. W. Peterson, MIT Press, Cambridge, Massachusetts, 1961.

The particular polynomial used in the present invention is X16 + X12 + X5 +1. The remainder resulting from the division of the bits in the packet by the polynomial, through modulo 2 division, is a sixteen bit number, which forms section 32 of the tier 2 format of Figure 2.

At the other TSU the number of bits in each packet, in~
cluding the checksum, are divided modulo 2 by the same polynomial. If the remainder resulting from this divi-sion is zero, a valid packet has been received. If not, there has been a error, and the negative acknowledge-ment-retransmission error correction system will go in-to effect.

The checksum field in a packet sent by a TSU is also used to differentiate a packet sent by a remote TSU and one sent by itself. A fixed bias or initialization is added to the checksum field for outgoing packets, so that sent packets erroneously returned due to shorts, etc. can be distinguished easily from packets from a remote TSU.

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- 15 - 113~8 The final field in each packet is an eight bit sequence which is either a flag or abort bit sequence. The end of a valid packet is signaled by a sequence of bits re-ferred to as a flag, which in the embodiment shown is defined as the binary sequence 01111110. The bit se-quence defining an abort is a string of seven or more contiguous one bits, which is an instruction to the re-ceiving TSU to ignore and discard information in the partial packet which has preceded it.

The existence of abort and flag sequences, however, raise the possibility of a misinterpretation of other-wise accurate data or control information in the packet.
The presence of six or seven contiguous valid one bits within the body of the packet would otherwise be inter-preted to be a flag or abort sequence. To prevent theinaccurate interpretation of a legitimate string of six or seven one bits as a flag or abort, a bit stuffing technique is utilized.

A conventional bit stuffing algorithm similar to that established by the Advanced Data Communication Control Procedures (ADCCP) standard is followed. The algorithm is as follows: The transmitting TSU will insert a zero bit following a string of five contiguous one bits any-- where within the particular packet, through the check-sum field. The receiving TSU, upon detection of five ~13~ 8 contiguous one bits received from the transmitting TSU, will inspect the following bit. If the following bit is zero, the five one bits are passed as a legitimate data and the zero bit is deleted. If the sixth bit is a one, however, the receiver inspects the seventh bit.
If that bit is a one also, then the receiver knows that a proper abort sequence has been received. If zero, then a flag has been received. The implementation of this algorithm is conventional and may be routinely accomplished by a skilled programmer.

The combination of the 7-tuple data group 24, the con-trol tuple 26 (if any), the extension field 28 (if any), the packet control field 30, the checksum 32, and the flag or abort field 34, along with bit-stuffed zeros (if any), forms one packet in the tier 2 format.
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This tier 2 packet is then broken down into successive sections, each section comprising 8 bits. A start and stop bit is then added to each section, forming ten bit characters, which thus have the exterior appearance of tier one charactexs. If the length of the tier 2 pac-ket is not an even multiple of 8 bits, the partially completed last character may be filled with either the first 1-7 bits in the next packet, if available, or an abort sequence.

- 17 - 1~3~

These ten bit characters, which form the tier 3 format, are then delivered to the line equipment side of the TSU for transmission over the line. Thus, the TSU
appears transparent to the transmitting data device, the other data devices, and the transmission line. The reformatting, from tier 1 to tier 3, results in the in-clusion of sophisticated error control in asynchronous communications, on a packet-by-packet basis, without decreasing the data capacity of the system.

The addition of error control without reducing data capacity results from the elimination of the parity bit from each original character in the packet. For in-stance, in a 40 character packet, 40 parity bits will be eliminated. The control tuple, if present, will add seven bits, the extension field, if present, will add three bits, the packet control field will add six bits, the checksum field will add sixteen bits and the flag/
abort field will add eight bits. The control fields thus will add a total of 40 bits to the packet, which is no more than the bits deleted by the parity bits.
~` Although the number of characters in a given packet ~ .
may vary widely, i.e. from 0 to 64, the average number of characters per packet in a given transmission should be high enough that the data capacity of the system is not decreased by the addition of control information.

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, - 18 - 113!,~8 Thus, by 11) packetizing a series of conventionally coded characters, (2) adding control information, in-cluding error control, to that packet, and then (3) regrouping that packet in ten bit characters, each hav-ing a start and a stop bit, a system for asynchronousdata communication is achieved which has sophisticated error control but does not decrease the original data capacity of the system.

At the receiving end of the link, the incoming charac-ters, in a tier 3 format, are processed on a packet-by-packet basis and initially reformatted into a tier 2 format by stripping off the start/stop bits and bunch-ing all the resulting information, both data and con-trol, together. Acknowledgement and retransmission (if necessary) functions then occur.

Once a packet of data is validated, the control tuple field 2~, the extension field ~, the packet control field 30, the checksum field 32 and the flag/abort field 34 are stripped off, and the remaining data bits are then reformatted into a tier 1 format, i~e., ten hit characters comprising 7 data bits, and parity, start and stop bits for ASCII coded information, and trans-mitted to the receiving data device. The information thus applied to the receiving data device thus is in exactly the same format as it was when it left the .
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- 1 9 - 113~ 8 originating data device.

The TSU accomplishes the above functions through a combination of hardware and firmware which is shown in the block diagrams of Figures 3, 4 and 5. Referring now specifically to Figure 3, the hardware architecture of the TSU is shown. The individual elements disclosed are per se conventional and may be purchased under the nomenclature used in Figure 3, but are organized in a specific combination which makes possible the flow of data and control necessary to carry out the method steps disclosed above.

Input and output to the TSU is achieved through con-ventional RS 232 connectors 44 and 46 which conform to specific standards developed by the electronics indus-tries association (EIA) and are available from severalmanufacturers under the above nomenclature.

The connectors 44 and 46 interface the data device with EIA driver/receivers 48 and 49. The driver/receivers 48, 49 are conventional hardware devices which perform voltage level and impedance translations between the TSU and the modem. The combination of connectors 44 and 46, the driver/receivers 48 and 49 is used in some form by every communication device which forms a part of a data link. Such devices are conventional, and for :

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the most part are now standardized, such as by the EIA
standards.

TSU control and display may be obtained from the front panel of the unit, as shown in Figure 3, by virtue of panel indicator block 50 and panel control block 52.
The panel indicators and panel controls 50 and 52 inter-face with the remaining circuitry of the TSU through conventional hardware internal interfaces 53. Visual indications of various TSU operating conditions are thus provided. Likewise, an operator has the capability of controlling the operating condition and mode of the TSU through the control block 52, which includes the front panel switches on the TSU.

The remaining blocks in Figure 3 are the primary hard-ware blocks comprising the TSU. Central processing ~CPU) unit 54 is an eight bit or sixteen bit micro-processor with a fixed instruction set. The instruc-tion set and the instruction cycle time are such that CPU 54 is capable of processing the firmware present in the TSU.

The random access memory (RAM~ 56 is a memory section ~; which provides up to 15 seconds of temporary storage (buffering) of data received by the TSU at a 120 cps rate. RAM 56 is compatible with the microprocessor ' - 21 - 113~8 comprising CPU 54 and may be any one of various avail-able low cost semiconductor RAM memories.

Read only memory (ROM) 58 is a low cost, high density semiconductor memory, having access time and power re quirements compatible with the CPU microprocessor 54.
ROM 58 contains the firmware which is used by CPU 54 to process, i.e. reformat, the incoming data stream which has been temporarily buffered in RAM 56, in a manner described above and in more detail hereinafter.

ROM 58, RAM 56 and CPU 54 are linked together in con-ventional fashion via data bus 60 and address bus 62 to permit the processing of data. In operation, instruc-tion words in the firmware from ROM 58 are fetched se-quentially by the CPU 54 at the clock rate established in the CPU, and are routed along the data bus 60 to the CPU for execution. The instructions fetched from ROM
58 are selected over an address bus 62 which can direct-ly connect the CPU 54 and the ROM 58 as shown by the dotted line section 64 or indirectly through the combin-ation of memory interface unit 66, address bus 62 anddata bus 60.

Communication between the processing portion of the TSU, i.e. CPU 54, R~M 56, ROM 58, data bus 60 and address bus 62, and the interface circuitry, i.e. connectors 44 , ~ ~
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, .. :, 113~8 and 46 and driver/receivers 48 and 49 is accomplished through a pair of universal asynchronous receiver/trans-mitter (UART) integrated circuit devices 68 and 70.
UART's 68 and 70 perform a serial-to-parallel, and vice versa, bit conversion. Data communications over tele-phone lines is bit serial, i.e. a series data stream of binary ones and zeroes. This results in a transmission of data on a serial character-by-character basis when proper start and stop bits are included. The processing and manipulation of data within a microprocessor, how-ever, is more efficiently done by a byte (8 parallel bits) basis. The UART's 68 and 70 are conventional hardware devices, available from several manufacturers and convert the data from a serial to parallel arrange-ment and vice versa. Thus, the UART's also perform aninterface function between the TSU and the transmission line.
'`' The remaining block in the TSU is the encryption/de-cryption hardware block 72 which is a commercially available device which implements the U.S. Department of Commerce National Bureau of Standards data encryp-tion algorithm. In operation, block 72, using a secret key, performs an encryption function on 8 known charac-ters to produce a series of enciphering characters used by a firmware block operating in what is known as cip-her feedback mode to produce, through an exclusive OR

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- 23 - 113~

gate arrangement, ciphertext characters from plaintext.
Further explanation concerning the enciphering/decipher-ing mode of the apparatus will be provided hereinafter in the section concerning the system firmware.

A specific structural implementation of the more gen-eralized block diagram of Figure 3 can be accomplished with a Fairchild F8 microprocessor. In the F8 micro-processor, a 3850 CPU is driven by a 2.000 megahertz crystal clock. Associated with the 3850 CPU are two 3861 PIO's (peripheral input-output) and a 3853 SMI
(static memory interface). Comparable devices are available from other manufacturers. RAM 56 consists of eight low power IKx4 static RAM chips (2114L's) while ROM 58 comprises four 2Kx8 static EPROM's (2716E's).

15- These devices are linked together by an F8 bus which consists of eight bidirectional data lines, five con-~ ~ trol lines and two clock lines. The parallel to serial ; conversion function is implemented by two SMC COM 2502 UART's. The necessary voltage and impedance transla-tions are accomplished through using MC1489 quad line receivers and MC1488 quad line drivers.

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Although the apparatus has a substantial amount of hard-ware, a considerable portion of the actual operation of the apparatus is carried out in the preferred embodiment -.
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by what is referred to as firmware. Firmware is a term of art which refers generally to a set of instructions for use in processing data which are written permanently into memory, such as a read only memory (ROM). The in-structions are thus virtually hardwired into the appa-ratus. The same logic functions accomplished by the CPU 54 acting on the data stream with the firmware can, of course, be implemented wlth hardware logic circuits, although such an embodiment would be quite bulky and expensive.

The firmware used in the present invention is clarified in Figures 4 and 5, which show, respectively, the move-ment of data between the firmware modules, and the mwe-ment of processing control between firmware modules.
Referring now in particular to Figure 4, interfaces 80 and 82 are the receive and transmit interfaces on the transmission line side of the TSU, referred to as the data communications equipment (DCE) receive and DCE
transmit interfaces, respectively. On the other side of the TSU are interfaces 84 and 86, which are the re-ceive and transmit interfaces on the data device, i.e.
terminal or host computer, side of the TSU, referred to as the data terminal equipment (DTE) receive and DTE
transmit respectively. The function of each interface is explained in the following paragraphs.

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- 25 - 113~

DCE receive interface 80 controls the movement of tier

3 information between the receive buffer in the line equipment UART and the bit unstuff module 96. Informa-tion moves from the buffer in the UART to the interface 80, and then to the bit-unstuff module 96 when process-ing control shifts to that module.

DTE transmit interface 84 controls movement of tier one information between receive buffer 100 and the transmit buffer in the UART on the data device side of the TSU.
When the transmit buffer in the UART has available space, tier one characters move from receive buffer 100 to the UART thr~ugh interface 84. Any control tuples, however, are routed to the control tuple processing module 102.

., DTE receive interface 86 controls movement of tier one information between the receive buffer in the data de-vice side UART and the transmit buffer 90 or the en-cipher~decipher module 88. When a character is avail-able at the receive buffer in the UART, it is delivered either directly to transmit buffer 90, or first to module 88 and then to buffer 90.

DCE transmit interface 82 controls the flow of tier 3 information between the bit stuff module g4, and the transmit buffer of the line equipment side UART. When - 26 - 113~

the transmit buffer is empty, data in eight bit groups, from module 94, is supplied to it.

Thus, in one direction of information flow, data in a tier one format is originated at a user data device such as a terminal or host computer, proceeds through interface 86, then through encipher/decipher module 88 if necessary, then to transmit buffer 90. Transmit buffer 90 forms part of RAM 56, which is hardware, but is shown in Figure 4 for clarity of explanation.

Module 88 implements the encipher/decipher functions of the apparatus. It includes registers which store known characters which are delivered periodically to the encrypting hardware (block 72 in Figure Z) to pro-duce the enciphering/deciphering characters which are ; 15 then used by the encipher/decipher firmware module 88 to produce ciphertext from plaintext and vice versa, by exclusive ORing the plaintext data in the packets with the encipher/decipher characters. The result of the exclusive ORing is also shifted back into the reg-isters to form new known characters. This is a known technique and is referred to as cipher feedback mode.

From transmit buffer 90, the tier one data (enciphered, if desired) is delivered to the transmit data process-ing firmware module 92, which in operational terms is ,: . ~ : :, - 27 - 1~3~8 the CPU 54 operating with the firmware of module 92 stored in ROM 58. Operationally, firmware module 92 concurrently removes characters from transmit buffer 90, initiates reformatting and packetization, and sends the resulting information to bit-stuff module 94. Packet-ization, i.e. determining the cut-off point for the number of characters from the transmit buffer 90 in the packet being formed, occurs when either (1) there are no characters awaiting transmission in the transmit buffer 90 or (2) the maximum packet size of 64 charac-ters has been reached.

After packetization occurs, the control information for the packet is computed by module 92 and this informa-tion is then sent to the bit stuffing module 94. As the characters from transmit buffer 90 and the control information computed by transmit data processing module 92 are acquired by module 94, the bit-stuffing algorithm described above is implemented.

The data emerging from the module 94, which in a given packet will be character or control information, now in tier 3 format, is ready to be transmitted through interface 82 to the transmit buffer of the line equip-ment side UART. From the UART, the data is delivered through various hardware interfaces to the other de-vices, such as modems, prior to the data going out on ... . ~ -.. . ,, ~

- 28 - 113~

the transmission line to a distant TSU. The data char-acters originally present in transmit buffer 90 remain there until an acknowledgement is received from the other TSU When the acknowledgement is received, that space is cleared for more characters from the user data device.

In the other direction, i.e. from the distant TSU over the intermediate transmission line, data is delivered through the line equipment (i.e. modem) and the hard-ware interface to interface 80, which forwards it tobit unstuff module 96, when that module has process control. In bit-unstuff module 96, the stuffed bits are eliminated.

As the stuffed bits are removed from the incoming pac-ket, the data is stored in receive buffer 100, which is another part of RAM 56. This data is then processed by the receiver data processing module 98. The packet control field numbers and checksum fields are examined by the firmware module 98 to determine the validity of the packet. An appropriate signal is then sent to transmit data processing module 92 to cause an acknow-ledgement (NAK), as appropriate, to be sent to the other TSU. The acknowledgement information contained in the received packet is then used to initiate release of storage in transmit buffer 90, for an ACK, or a re-.

113~ 8- 29 -transmission for a NAK.

The 7 tuple data remaining is then released for later delivery by the DTE transmit interface 84.

Concurrently with reception of the next packet from the remote TSU, the DTE transmit interface 84 will access characters in sequence from buffer 100, route them to - module 88 for deciphering, if necessary, append start, stop and parity bits, and then deliver the resulting characters to the transmit buffer of the UART on the data device side of the TSU.

When a control tuple is recognized in buffer 100, it is sent to control tuple processor module 102. Control tuple processing module 102 processes and carries out all of the control tuple requests received from the distant TSU. If a response is necessary, the proper response is routed to the transmit data processing mod-ule 92 for inclusion in the next packet to be transmitted.

~: The flow of process control between the various firm-: ware blocks is shown in schematic form in Figure 5. The flow of control is achieved primarily through a central polling and selection loop 110.

.~ :
~ The loop 110 scans several modules in a priority sequence, . : -.
~ , - ;
;.:` ' .- `., :

- 30 - 11~ 8 including the encrypt/decrypt hardware module 72, DTE
receive interface 86, and the DCE receive interface 80.
A lower priority selection sequencé includes the trans-mit data processing module 92, the DTE transmit inter-face 84, and the DCE transmit interface 82.

Whenever the encrypt/decrypt hardware module 72 is not busy, the data is ready to be deciphered or enciphered by the encipher/decipher module 88, control is trans-ferred to the encrypt/decrypt hardware 72 to develop new enciphering/deciphering characters for use by the module 88. After the module 72 is started, control re-turns to the polling loop 110.

If the encrypt/decrypt hardware 72 is not busy, and there is no data to be enciphered/deciphered, the buffer in the UART associated with the DTE receive module 86 . is then scanned to determine whether data is available ~; there. If so, the DTE receive interface 86 is given control to read a character from the buffer in the ~ associated UART, encipher it if necessary, and then ~ 20 store it in transmit buffer 90 (Figure 4).
: . .

Next, the buffer in the UART associated with the DCE
receive module 80 is scanned to determine whether data is available there. If data is available, control is passed to the DCE receive interface module 80, which .

.

- 31 - ~ 1 3i~ 8 reads the received character from the buffer in the associated UART.

Control is next transferred to bit unstuff module 96 which removes any zeros added by the bit-stuff algo-rithm at the remote TSU, groups the received bits into7-tuples and stores them in the receive buffer 100 (Figure 4). The bit unstuff module also scans for a flag sequence indicating the end of a packet and if one is sensed, transfers control to the receive data proc-essing module 98. If a flag is not sensed, control re-turns to the polling loop 110.

The receive data processing module 98 processes received characters and control information, and if characters or a control tuple is present, sets a request flag to signal the polling loop 110 that the DTE transmit inter-face is to be given control. Processing control is then returned to the polling loop 110.

The processing request flags are now examined by the polling loop llO in a priority order. If a flag is set, that module is given control. For instance, if interface 84 is requested and its associated UART's transmit buffer is empty, the DTE transmit interface module 84 is given control. This routine accesses a character from the receive buffer 100, passes control - 32 - ~i3~

to the decipher portion of module 88 to decipher the character, if necessary, and delivers the character to the transmit buffer in the associated UART. The module then sets its own request flag, causing it to be re-5 entered when the UART transmit buffer is again empty.
If the accessed character is a control tuple, it is not delivered to the UART but control is given to the con-trol tuple processing module 102. If no character is awaiting delivery from module 98, control is returned 10 directly to the polling loop 110.

~o C Again at the polling loop ~, if the request flag for the transmit data processing module 92 is set (which occurs when the TSU is idling), that module is given control. The transmit data processing module 92 checks 15 the transmit buffer 90 (Figure 4) for characters stored by the DTE receive interface module 86, which characters are thus awaiting transmission. If a character is found, it is processed, i.e. reformatted, into a 7-tuple, and control is passed to the bit-stuff module 94, ~ 20 which inserts zeros, as required, by the bit-stuffing - algorithm described earlier. When 8 bits have been prepared for transmission, the bit-stuff module 94 sets a request flag for the DCE transmit interface module 82, and control returns to the polling loop 110.

2~ Again at the polling loop ~, if the DCE transmit - 33 - 113'~

interface module 8~ is requested and the transmit buffer in its associated UART is empty, the DCE transmit mod-ule 82 is given control. This routine accesses the character provided by bit stuff module 94, and delivers it to the transmit buffer in its associated UART. Con-trol is then passed to bit stuff module 94, which then continues the bit-stuffing algorithm on the remaining bits received from the transmit data processing module 92, until 8 bits are again ready for transmission.

The DCE transmit interface 82 is again requested to deliver these bits when the transmit buffer of its associated UART is empty. If, as is likely, the bit-stuff module 94 runs out of bits before 8 bits are ready for transmission, it immediately transfers con-trol to module 92 which in turn acquires the next in-. formation to be transmitted and then returns control to the bit stuff module 94, which can then complete the bit-stuffing process on an 8 bit group of data and re-: quest the DCE transmit interface module 82.

::
This process continues, with control flowing between firmware modules 92, 94 and 82 as characters and con-trol information are accessed from the transmit buffer 90, processed and transmitted. When the transmit data processing module 92 senses that no further data is awaiting transmission, control is returned to polling \

.

- 34 - 1~3~8 loop 110.

The flow of processing control within the TSU and the related flow of data is initiated during the connect procedure, continues through the exchange and process-ing of asynchronous information with a distant TSU andterminates at disconnect. The operational sequence of the TSU is explained in more detail in following para-graphs.

The TSU will initially pass through a connect sequence which is accomplished through an exchange of control tuples, without data. Then normal data exchange oper-ation occurs, with error control, including acknowledge-ment, negative acknowledgement, and retransmission, if necessary. Following the completion of data communi-cations, a disconnect sequence is followed, which againis accomplished through an exchange of control tuples.

:' When a terminal user initially dials into a host, it is not known whether the host has a TSU, and vice versa.
In the connect procedure, the first priority is to de-termine whether a TSU exists at both ends of the link.If not, the one TSU on the link remains in its initial "wire-through" mode, which is essentially a by-pass of the TSU. In the wire-through mode, the data has the same format and content existing as entering. Thus, - ~ . . -: ............. ;.. ..... :
: . : :
- ~,: : :: :
, ~3~

the TSU remains invisible to both the transmission line and its associated equipment.

At the start of the connect sequence, the TSU's are in a wire-through mode. The terminal operator will first dial into the terminal's associated modem. The opera-tor will then type a known start or link-up character.
The local, i.e. terminal side, TSU will see the charac-ter, which is representative of the type of terminal and transmission speed, and will set the characteris-tics of its DTE and DCE interfaces accordingly.

The terminal side TSU will then transmit a correspond-ing start character down the line to the host side TSU.
When the host side TSU receives the character, it sets its DCE and DTE interfaces accordingly and then trans-mits a particular declaration seqùence back down theline to the terminal TSU. The start character received by the host side TSU is saved for later transmission to the host.

The declaration sequence is a unique string of charac-~20 ters, which, when recognized by the terminal side TSU, indicates that a TSU-equipped host port has been reached.
Upon receiving the sequence, the terminal side TSU trans-mits the same sequence back to the host side TSU, thus informing the host side TSU of its presenece. Both : ~

- 36 - 113~

TSU's now know that a dual TSU link has been achieved.

At this point, protocol information may be exchanged between the TSU's as control tuples in an information packet. These packets are treated as data-bearing pac-kets (even though they may carry only control tuple in-formation) and hence the ordinary error control proced-ures are used for the transmission of those packets.

After the exchange of the initial protocol information, the transmission of asynchronous data begins. The ten bit data characters originated at the terminal are then applied to the terminal side TSU. The TSU reformats the data, as explained above. The control information is then added, which comprises a control tuple ~ield, if any, extension field, if any, packet control field, error control field, and flag/abort field.

The packet control field is divided into two sections, a packet number sent and a packet number received. The packet number sent (FS) is based on an end-around memory of eight positions. Hence, the packet number sent will always be 0 through 7. Initially, the packet number sent and received registers will both be zero. The characters acquired by the terminal TSU are stored in buffer memory and identified according to packet. Each packet is assigned a sequential number and this number - , ~ .- .
: . .
:

- 37 - 113'~

is the packet sent (PS) number. The packet received ~PR) number is the number of the last packet which has been received correctly from the remote TSU. The pac-kets identified in memory by the packet sent number are retained in memory until they have been acknowledged by the receiving TSU.

The transmitted packets have no header information, and thus, the 7-tuple data is transmitted to the modem as soon as the reformatting has been accomplished, before the packet is completely formed. By the time the flag field is added to the packet, in fact, the 7-tuple data is already well out on the transmission line and may even bP already received by the remote TSU. This is an advantage in communications systems using human opera-tors, where delays caused by waiting for complete pac-kets prior to transmission can be frustrating.

As the receiving TSU is receiving the packet, it will search through the data until it recognizes the flag sequence indicating the end of the packet. It will then temporarily store the packet, while it is perform-ing the error check on the rest of the packet. It will also check the packet sent number and the packet receive number, as well as the e~tension field, if any, and the control tuple fields, if any, for further protocol in-~ 0~ Y~ ~
C 25 formation. If there is no error ~e~m~ in the received : ~:

~ 38 - 1~3~8 packet, the 7-tuple data is reformatted into ten bit characters with start and stop bits and a parity bit, and then delivered to the host equipment in exactly the same form as originated by the terminal equipment.

At this point, the host TSU may have data to send to the terminal side TSU or it may send just an acknow-ledgement of the correct receipt of the transmission from the terminal TSU. The nost TSU thus becomes a sending TSU and the terminal TSU becomes the receiving TSU. With full duplex communication, of course, which the TSUs are capable of, information can be moving in both directions at once. Data is formatted by the host side TSU for transmission to the terminal side TSU in e~actly the same way as by the terminal TSU.

The packet control numbers will reflect the last cor-rectly received packet, in the PR subfield, and the se-quential position of the packet being sent. If the packet being sent by the host side TSU is the first one to be transmitted, and the host side TSU has just veri-fied the first packet from the terminal side TSU, boththe PS and PR subfields will be one. The host side TSU-originated packet will then be transmitted to the term-inal side TSU, which, upon recognizing the one in the PR subfield, will know that that packet arrived error-free and hence, that the memory space occupied by that ,, : ' .. : ` ~ -t ~ ' '~

~3~0(!~

data in its transmit buffer can be released.

This procedure of transmission and acknowledgement will continue until there is an error discovered by one of the TSU's. At this point, a flag will be placed in the negative acknowledgement (NAK) subfield of the exten-sion field area of the next packet sent back to the originating TSU. Upon transmission of the NAK and recognition by the originator of the packet containing the error, the data from the packet containing the error and all following data will be called out of mem-ory and retransmitted. Upon subsequent acknowledgement, the storage for that data will be released.

This procedure of ACK, NAK and retransmission continues until the communication has been completed. At this point, the link will undergo a disconnect procedure, in which a data-free, but packet control incremented, packet containing control tuple information is trans-mitted and acknowledged in the usual way. The control tuple will be a code indicating a disconnect request.
Upon receipt of this code, the receiving TSU will send a disconnect response. Upon receipt of the disconnect ; response by the sending TSU, the sending TSU will send its own disconnect response signal back to the receiv-ing TSU and the link will then go down, and both TSU's ; 25 will reset.

: ~ -: ;- ' :
~: ' ; `

_ 40 - 113~008 Hence, a method and apparatus has been described which provides a capability for implementing sophisticated error control techniques in asynchronous communications.
The apparatus used is transparent to the terminal/host and line equipment, and requires no modification of existing equipment or transmission lines. Furthermore, it adds an error control capability without in any way reducing the data capacity of the communication system.

Although an exemplary embodiment of the invention has been disclosed herein for purposes of illustration, it will be understood that various changes, modifications and substitutions may be incorporated in such embodi-ment without departing from the spirit of the invention as defined by the claims which follow.

Claims (26)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY OR
PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. An asynchronous digital data communication system for use with two digital data communication stations, both adapted to operate asynchronously with digital characters made up of first control bits and a predetermined number of data bits, comprising: a first terminal and a second terminal operable with the two stations, respectively, and means operatively associated with said first terminal and said second terminal providing a communication channel therebetween; said first terminal including station input means oper-able with one station for asynchronously receiving a first character there-from and combining only the data bits of said first character with string control bits to form a first information bit string, section means operatively associated with said station input means for dividing said first information bit string into sections, each having a number of bits equal to one more than said predetermined number, and channel output means operatively associated with said section means for adding section control bits to each section to form a digital word, and then asynchronously transmitting said digital word via said communication channel; said second terminal including channel input means operatively associated with said communication channel for asynchronously receiving said digital word and then removing said section control bits there-from to form a second information bit string, reformatting means operatively associated with said channel input means for combining only the data bits of said second information bit string with second control bits identical to said first control bits to form a second character identical to said first character, and station output means operatively associated with said refor-matting means and operable with the other station for asynchronously presenting said second character to said other station.

2. An asynchronous digital data communication system for use with two digital data communication stations, both adapted to operate asynchronously with digital characters made up of first control bits and a predetermined number of data bits, comprising: a first terminal and a second terminal operable with the two stations, respectively, and means operatively associ-ated with said first terminal and said second terminal providing a communication channel therebetween, each terminal including; (A) FOR TRANSMITTING TO THE OTHER
TERMINAL --- station input means operable with one station for asynchronously receiving a first character therefrom and combining only the data bits of said first character with string control bits to form a first information bit string, section means operatively associated with said station input means for dividing said first information bit string into sections, each having a number of bits equal to one more than said predetermined number, and channel output means opera-tively associated with said section means for adding section control bits to each section to form a digital word, and then asynchronously transmitting said digital word via said communication channel; and (B) FOR
RECEIVING FROM THE OTHER TERMINAL --- channel input means operatively associated with said communication channel for asynchronously receiving said digital word and then removing said section control bits therefrom to form a second information bit string, reformatting means operatively associated with said channel input means for combining only the data bits of said second information bit string with second control bits identi-cal to said first control bits to form a second char-acter identical to said first character, and station output means operatively associated with said reformat-ting means and operable with the other station for asynchronously presenting said second character to said other station.

3. The system of claim 1 or 2 wherein, said station input means include memory means operatively associated with said section means for storing the data bits and a portion of said string control bits as a storage bit string, said reformatting means include error control means responsive to said string control bits for determining the correctness of said second information bit string, and for transmitting (A) a first acknowledgement signal indicative that said second information bit string is correct, or (B) a second acknowledgement signal indicative that said second information bit string is incorrect, and wherein said channel output means include means operatively associated with said memory means and responsive to said first acknowledgement signal for terminating storage of said storage bit string, and responsive to said second acknowledgement signal for initiating a transfer of said storage bit string from said memory means to said section means, whereupon the data bits may be re-transmitted to said second terminal as such digital words.

4. The system of claim 1 or 2 wherein, said station input means include means for forming said string control bits wherein said string control bits include a required bit sequence and may include an optional bit sequence, said channel input means include means for detecting the presence of said optional bit sequence when the total number of bits in said second information bit string is other than the sum of (A) the number of bits in said required bit sequence and (B) an integral multiple of said predetermined number.

5. The system of claim 1 or 2 wherein, said station input means include means for encoding the data bits forming said first information bit string, and said channel input means include means for decoding the data bits forming said second information bit string.

6. A terminal for presenting digital words to a communication channel and operable with a digital data communication station that is adapted to operate asynchronously with digital characters made up of first control bits and a predetermined number of data bits, the terminal comprising: (A) FOR TRANSMITTING ---station input means operable with the station for asynchronously receiving a first character therefrom and combining only the data bits of said first char-acter with string control bits to form a first infor-mation bit string; section means operatively associated with said station input means for dividing said first information bit string into sections, each having a number of bits equal to one more than said predeter-mined number; channel output means operatively as-sociated with said section means for adding section control bits to each section to form a digital word, and then asynchronously presenting said digital word to the communication channel; and ( B ) FOR RECEIVING ---channel input means operatively associated with the communication channel for asynchronously receiving said digital word and then removing said section control bits therefrom to form a second information bit string;
reformatting means operatively associated with said channel input means for combining only the data bits of said second information bit string with second control bits identical to said first control bits to form a second character identical to said first character; and station output means operatively associated with said reformatting means and operable with the station for asynchronously presenting said second character to said station.

7. The terminal of claim 6 wherein, said sta-tion input means include memory means operatively associated with said section means for storing the data bits and a portion of said string control bits as a storage bit string, said reformatting means include error control means responsive to said string control bits for determining the correctness of said second information bit string, and for transmitting (A) a i first acknowledgement signal indicative that the second information bit string is correct, or (B) a second acknowledgement signal indicative that said second information bit string is incorrect, and wherein said channel output means include means operatively associ-ated with said memory means and responsive to said first acknowledgement signal for terminating storage of said storage bit string, and responsive to said second acknowledgement signal for initiating a transfer of said storage bit string from said memory means to said section means, whereupon the data bits may be re-trans-mitted as such digital words.

8. The terminal of claim 6 wherein, said station input means include means for forming said string con-trol bits wherein said string control bits include a required bit sequence and may include an optional bit sequence, said channel input means include means for detecting the presence of said optional bit sequence when the total number of bits in said second informa-tion bit string is other than the sum of (A) the number of bits in said required bit sequence and (B) an inte-gral multiple of said predetermined number.

9. The terminal of claim 6 wherein, said station input means include means for encoding the data bits forming said first information bit string, and said channel input means include means for decoding the data bits forming said second information bit string.

10. A terminal for presenting digital words to a communication channel and operable with a digital data communication station that is adapted to operate asyn-chronously with digital characters made up of first control bits and a predetermined number of data bits, the terminal comprising: station input means operable with the station for asynchronously receiving a first character therefrom and combining only the data bits of said first character with string control bits to form a first information bit string; section means operatively associated with said station input means for dividing said first information bit string into sections, each having a number of bits equal to one more than said predetermined number; and channel output means opera-tively associated with said section means for adding section control bits to each section to form a digital word, and then asynchronously presenting said digital word to the communication channel.

11. The terminal of claim 10 wherein, said station input means include means for forming said string con-trol bits wherein said string control bits include a required bit sequence and may include an optional bit sequence such that the presence of said optional bit sequence is indicated by making the total number of bits in said first information bit string is other than the sum of (A) the number of bits in said required bit sequence and (B) an integral multiple of said pre-determined number.

12. The terminal of claim 10 wherein, said station input means include means for encoding the data bits forming said first information bit string.

13. A terminal for receiving digital words from a communication channel and operable with a digital data communication station adapted to operate asyn-chronously with digital characters made up of first control bits and a predetermined number of data bits, said digital words including section control bits and sections, each section having a number of bits equal to one more than said predetermined number and being a portion of a first information bit string, said first information bit string containing string control bits and only the data bits of a first digital character, the terminal comprising: channel input means opera-tively associated with said communication channel for asynchronous ly receiving said digital word and then removing said section control bits therefrom to form a second information bit string, reformatting means operatively associated with said channel input means for combining only the data bits of said second infor-mation bit string with second control bits identical to said first control bits to form a second character i identical to said first character, and station output means operatively associated with said reformatting means and operable with the other station for asyn-chronously presenting said second character to the station.

14. A method for asynchronous digital data commun-cation for use with two digital data communication sta-tions both adapted to operate asynchronously with digi-tal characters made up of first control bits and a pre-determined number of data bits, the method comprising the steps of: asynchronously receiving a first charac-ter from one station; combining only the data bits of said first character with string control bits to form a first information bit string; dividing said first information bit string into sections, each having a number of bits equal to one more than said prede-termined number; adding section control bits to each section to form a digital word; asynchronously trans-mitting said digital word; asynchronously receiving said digital word and then removing said section control bits therefrom to form a second information bit string; combining only the data bits of said second information bit string with second control bits iden-tical to said first control bits to form a second character identical to said first character; and asynchronously presenting said second character to the other station.

15. A method for asynchronous digital data communi-cation for use with two digital data communication stations both adapted to operate asynchronously with digital characters made up of first control bits and a predetermined number of data bits, the method at each station comprising the steps of: (A) FOR TRANSMITTING
--- asynchronously receiving a first character from one station; combining only the data bits of said first character with string control bits to form a first information bit string; dividing said first information bit string into sections, each having a number of bits equal to one more than said predetermined number;
adding section control bits to each section to form a digital word; asynchronously transmitting said digital word; (B) FOR RECEIVING --- asynchronously receiving said digital word, and then removing said section control bits therefrom to form a second information bit string; combining only the data bits of said second information bit string with second control bits iden-tical to said first control bits to form a second character identical to said first character; and asynchronously presenting said second character to the othe station.

16. The method of claim 14 or 15, including; stor-ing the data bits and a portion of said string control bits as a storage bit string, determining the correct-ness of said second information bit string based on said string control bits, and transmitting (A) a first acknowledgement signal indicative that said second information bit string is correct, or transmitting (B) a second acknowledgement signal indicative that said second information bit string is incorrect, and respon-ding to said first acknowledgement signal to terminate storage of said storage bit string, or responding to said second acknowledgement signal to initiate dividing said storage bit string into sections, whereupon the data bits may be re-transmitted as such digital words.

17. The method of claim 14 or 15, including form-ing said string control bits wherein said string con-trol bits include a required bit sequence and may in-clude an optional bit sequence, indicating the presence of said optional bit sequence by including a number of bits in said optional bit sequence such that the total number of bits in said second information bit string is other than the sum of (A) the number of bits in said required bit sequence and (B) an integral multiple of said predetermined number.

18. The method of claim 14 or 15, including encod-ing the data bits forming said first information bit string, and decoding the data bits forming said second information bit string.

19. A method for asynchronous digital data communi-cation for use with a digital data communication station adapted to operate asynchronously with digital characters made up of first control bits and a prede-termined number of data bits, the method comprising the steps of: (A) FOR TRANSMITTING --- asynchronously re-ceiving a first character from the station; combining only the data bits of said first character with string control bits to form a first information bit string;
dividing said first information bit string into sec-tions, each having a number of bits equal to one more than said predetermined number; adding section control bits to each section to form a digital word; asyn-chronously transmitting said digital word; (B) FOR
RECEIVING --- asynchronously receiving said digital word, and then removing said section control bits therefrom to form a second infor-mation bit string; combining only the data bits of said second information bit string with second control bits identical to said first control bits to form a second character identical to said first character; and asynchronously presenting said second character to the station.

20. The method of claim 19, including; storing the data bits and a portion of said string control bits as a storage bit string, determining the correctness of said second information bit string based on said string control bits, and transmitting (A) a first acknowledge-ment signal indicative that said second information bit string is correct, or transmitting (B) a second acknow-ledgement signal indicative that said second informa-tion bit string is incorrect, and responding to said first acknowledgement signal to terminate storage of said storage bit string, or responding to said second acknowledgement signal to initiate dividing said stor-age bit string into sections, whereupon the data bits may be re-transmitted as such digital words.

21. The method of claim 19, including; forming said string control bits wherein said string control bits include a required bit sequence and may include an optional bit sequence, indicating the presence of said optional bit sequence by including a number of bits in said optional bit sequence such that the total number of bits in said second information bit string is other than the sum of (A) the number of bits in said required bit sequence and (B) an integral multiple of said pre-determined number.

22. The method of claim 19, including encoding the data bits forming said first information bit string, and decoding the data bits forming said second information bit string.

23. A method for asynchronous digital data trans-mission for use with a digital data communication sta-tion adapted to operate asynchronously with digital characters made up of first control bits and a prede-termined number of data bits, the method comprising the steps of: asynchronously receiving a first character from the station; combining only the data bits of said first character with string control bits to form a first information bit string; dividing said first information bit string into sections, each having a number of bits equal to one more than said predeter-mined number; adding section control bits to each section to form a digital word; asynchronously trans-mitting said digital word.

24. The method of claim 23, including; forming said string control bits wherein said string control bits include a required bit sequence and may include an optional bit sequence, indicating the presence of said optional bit sequence by including a number of bits in said optional bit sequence such that the total number of bits in said first information bit string is other than the sum of (A) the number of bits in said required bit sequence and (B) an integral multiple of said predetermined number.

25. The method of claim 23, including encoding the data bits forming said first information bit string.

26. A method for receiving digital words for use with a digital data communication station adapted to operate asynchronously with digital characters made up of first control bits and a predetermined number of data bits, said digital words including section control bits and sections, each section having a number of bits equal to one more than said predetermined number and being a portion of a first information bit string, said first information bit string containing string control bits and only the data bits of a first digital charac-ter, the method comprising the steps of: asynchronously receiving said digital word, and then removing said section control bits therefrom to form a second infor-mation bit string; combining only the data bits of said second information bit string with second control bits identical to said first control bits to form a second character identical to said first character; and asynchronously presenting said second character to the station.