CA1135869A - Memory preservation and verification system - Google Patents
Memory preservation and verification systemInfo
- Publication number
- CA1135869A CA1135869A CA000348342A CA348342A CA1135869A CA 1135869 A CA1135869 A CA 1135869A CA 000348342 A CA000348342 A CA 000348342A CA 348342 A CA348342 A CA 348342A CA 1135869 A CA1135869 A CA 1135869A
- Authority
- CA
- Canada
- Prior art keywords
- memory
- power supply
- digital
- verification
- preservation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
- G06F11/167—Error detection by comparing the memory output
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0763—Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2015—Redundant power supplies
Abstract
MEMORY PRESERVATION AND VERIFICATION SYSTEM
Abstract A memory preservation and verification system is provided in which memory contents are verified as being valid following an interruption and subsequent reapplication of operating power. A backup power supply is provided to maintain the status of the memory contents during the interruption or loss ofa main power supply. First and second mathematically related numbers are generated and stored in memory locations. These numbers are subsequently retrieved and the mathematical relationship therebetween checked to provide the verification of the status of data in the memory.
Abstract A memory preservation and verification system is provided in which memory contents are verified as being valid following an interruption and subsequent reapplication of operating power. A backup power supply is provided to maintain the status of the memory contents during the interruption or loss ofa main power supply. First and second mathematically related numbers are generated and stored in memory locations. These numbers are subsequently retrieved and the mathematical relationship therebetween checked to provide the verification of the status of data in the memory.
Description
~L~iL3~ 9 MEMORY PRESERVATION A~D VERIFICATION SYSTEM
Background of the Invention Because o~ advances in the state of the art of semiconductor technology in terms of size, cost, and power-consumption reduction, it is advantageous to incorporate digital processing and computational systems into electrical apparatus of all kinds. A problem associated with such systems is that when operating power is interrupted or turned off, data contained in system memories is lost. This problem was solved to some extent by providing back-up battery power to the memory devices to preserve the data stored therein. A further probleml however, is to ensure that the stored data is correct or valid upon re-app~ication of operating power. It has been suggested to store a known data word and verify it as being valid before any data processing is recommencecl.
~owever, such a known data word may always be the same and may always be stored at the same memory location, and through some undetermined physical characteristic associated with the memory device, the storage location of the memory device may take a set of the known data wGrd, analogous to a stored latent image on a display device.
This leads to the danger of the known data word being produced by the memory for verification upon re-application of operating power, even though the contents of the memory may have been destroyed during the loss of operating power.
Summary of the Invention In accordance with an aspect of the invention there is provided a memory preservation and verification system comprising: power supply means coupled to said memory for energization thereof, said power supply means including a main power supply and a backup power supply;
means for generating a first digital number; process and control logic means for generating a second digital number and storing both of said first and second digital numbers ~ . . .
..
""' ': ' ' .` , . , ~3~8~>~
-la-in said memory, said second digital number being mathemat-i.cally related to said first digital number; said process and control logic means also for retrieving said first and second digital numbers and checking the relationship there-between to thereby provide a verification of the validityof the contents of said memory; and utilization means for providing an indication of said verification.
In accordance with the present invention, a memory preservation and verification system is provided in which memory contents are verified as being valid following an interruption and subsequent re-application of operating power.
In an electrical apparatus which incorporates digital processing circuits, a backup power supply is provided to maintain the status of memory contents during the interruption or loss of a main power supply. A pseudo-random digital number Nl is generated and operated on in a particular manner to provide a second digital number N2 which is uniquely related to Nl. The digital numbers Nl and N2 are stored in preselected adjacent first and second memory locations respectively and are maintained in these locations dwring normal ,~
`f: ~
~3~
operation of the apparatus. At any tin-e, the memory status may be checked by retrieving the digital numbers ~1 and N2 and checking the relationship between the two numbers. It is pa. ticularly important to check this relationship following interruption or loss of main power during which time a backup power supply, suchas a battery, is used to preserve data stored in the system memories. A correct relationship between digital numbers Nl and N2 is verification that the status of data in memory has been preserved.
It is therefore one object of the present invention to provide a novel system for memory data preservation and verification.
It is another object to provide a mernory preservation and verification system in which pseudo-randomly generated digital numbers may be stored in preselected memory locations for later verification.
It i5 another object to provide a memory preservation and verification system in which memory contents are verified as being valid following an interruption and subsequent re-application of main operating power by storing a random digital number and a particular code number derived therefrom in adjacent memory locations and later verifying the relationship between ~he digital number and the code number.
Other objects and advantages of the present invention will become apparent upon a readin~ of the following description when taken in conjunction with the drawing.
.
rief Description of the Drawin~
The single FIGURE is a functional block diagram of the preferred embodiment of a memory preservation system in accordance with the present invention.
.
Detailed Descri tion of the Preferred Embodiment P . _ .
The memory preservation and verification system of the present învention may be embodied in any electronic apparatus such as computational or measuremen~ instruments or data transmission equipment in which there are digital processing circuits 10 and a memory device 12. The digital processing .
. . ~ .
~3~
circuits 10 may therefore be any arrangement of lo~ic gates, shift re~isters, flip flops, and so forth, to perform whatever digital signal processing that is required.
Input data is applied to the digital processing circuits 10 over input lines 14 and processed data may be output on da~a lines 16. The input and output lines 14 and 16 respectively may be the same data bus. The digita~ processing circuits 10may also include process and control logic circuits; however, in this embodimentthere is shown a separate process and control logic c;rcuit 18 not only to facilitate the description but because such process and control logic circuit 18could be separate microprocessor or computer hardware. These circuits are conventional and well known in the art; therefore, no detailed description of these circuits is given here.
The memory device 12 in its most simple form may be one or more flip flops; however, it is more likeiy that the memory comprises a random-accessmemory (RAM~ having thousands of addressable memory locations. The memory device 12 is shown connected between a source of electrical power ancl ground for energization thereof. The source of electrical power may be either a main power supply 20 or a backup power supply 22, both of which are connected through a switch 24 to the memory device 12. The main power supply 20 rnay suitably be the power supply of the entire system, while the backup power supply22 may be either a battery located within the apparatus or an external power supply. The switch 24 suitably may be an electronic switch, such as a pair of transistors connected as a comparator with appropriate biasing and sensing circuits to align the switch to the correct power supply. In normal operation, the main power supply 20 is connected through the switch 24 to the mernory 12. If the main power is interrupted or turned off, the backup power supply 22 is switched into the circuit to preserve the data stored in the memory device 12.
Since the switching action of switch 24 cannot be instantaneous, a capacitor 26 is provided to maintain operatin~ power during the switch over and thereby prevent destruction of stored data.
A number generator 30 may be provided to ~enerate digital numbers in a pseudo-random fashion. Such number generator may be, for example, a counter circuit which is cycled continuously. The process and controllo~ic circuit 1~ accepts a digital number Nl from a number ~enerator 3~ and operates on ~his number in a particular manner to provide a second digital number N2 which is uniquely related to Nl. The digital nurnbers Nl and N2 are ~L:13~
1~
stored in the memory device IZ in preselected first and second memory locations respectively, and are maintained in these locations during normal operation of the apparatus during ~vhich time main power supply 20 provldes operating power to the memory. Data being processed by ~he digital processin~ circuits 10 rnay 5 be stored in the memory in the conventional manner. The memory status may be checked at any time by retrieving the digital numbers Nl and N2 and checking the relationship between the two numbers. This may be done by first retrieving the digital number Nl, operating on the number Nl in the same particular manner as originally performed to provide a new digital number r~l2t and then 10 comparing the new digital number N2 with the originally stored digital numberN2. If the numbers match, it is an indication that the data stored in the memory12 has been properly preserved. It is particularly important to check this relationship followin~ a power interruption or loss of main operating power during which time the backup power supply is used to preserve data stored in the15 system memory. A utilization device 34 is coupled to the process and control Iogic circuit 18 to provide an indication of either verification or non-verification of preservation of the memory status. For example, utilization device 34 could be an indicator li~ht, or an alarm, or a reset switch, or some device such as a cathode-ray-tube display or a printer which provides visual indication to an 20 operator.
The preferred embodiment of the memory preservation and the verification system described herein above has universal application. The systemas described is embodied in an oscilloscope having digital computational
Background of the Invention Because o~ advances in the state of the art of semiconductor technology in terms of size, cost, and power-consumption reduction, it is advantageous to incorporate digital processing and computational systems into electrical apparatus of all kinds. A problem associated with such systems is that when operating power is interrupted or turned off, data contained in system memories is lost. This problem was solved to some extent by providing back-up battery power to the memory devices to preserve the data stored therein. A further probleml however, is to ensure that the stored data is correct or valid upon re-app~ication of operating power. It has been suggested to store a known data word and verify it as being valid before any data processing is recommencecl.
~owever, such a known data word may always be the same and may always be stored at the same memory location, and through some undetermined physical characteristic associated with the memory device, the storage location of the memory device may take a set of the known data wGrd, analogous to a stored latent image on a display device.
This leads to the danger of the known data word being produced by the memory for verification upon re-application of operating power, even though the contents of the memory may have been destroyed during the loss of operating power.
Summary of the Invention In accordance with an aspect of the invention there is provided a memory preservation and verification system comprising: power supply means coupled to said memory for energization thereof, said power supply means including a main power supply and a backup power supply;
means for generating a first digital number; process and control logic means for generating a second digital number and storing both of said first and second digital numbers ~ . . .
..
""' ': ' ' .` , . , ~3~8~>~
-la-in said memory, said second digital number being mathemat-i.cally related to said first digital number; said process and control logic means also for retrieving said first and second digital numbers and checking the relationship there-between to thereby provide a verification of the validityof the contents of said memory; and utilization means for providing an indication of said verification.
In accordance with the present invention, a memory preservation and verification system is provided in which memory contents are verified as being valid following an interruption and subsequent re-application of operating power.
In an electrical apparatus which incorporates digital processing circuits, a backup power supply is provided to maintain the status of memory contents during the interruption or loss of a main power supply. A pseudo-random digital number Nl is generated and operated on in a particular manner to provide a second digital number N2 which is uniquely related to Nl. The digital numbers Nl and N2 are stored in preselected adjacent first and second memory locations respectively and are maintained in these locations dwring normal ,~
`f: ~
~3~
operation of the apparatus. At any tin-e, the memory status may be checked by retrieving the digital numbers ~1 and N2 and checking the relationship between the two numbers. It is pa. ticularly important to check this relationship following interruption or loss of main power during which time a backup power supply, suchas a battery, is used to preserve data stored in the system memories. A correct relationship between digital numbers Nl and N2 is verification that the status of data in memory has been preserved.
It is therefore one object of the present invention to provide a novel system for memory data preservation and verification.
It is another object to provide a mernory preservation and verification system in which pseudo-randomly generated digital numbers may be stored in preselected memory locations for later verification.
It i5 another object to provide a memory preservation and verification system in which memory contents are verified as being valid following an interruption and subsequent re-application of main operating power by storing a random digital number and a particular code number derived therefrom in adjacent memory locations and later verifying the relationship between ~he digital number and the code number.
Other objects and advantages of the present invention will become apparent upon a readin~ of the following description when taken in conjunction with the drawing.
.
rief Description of the Drawin~
The single FIGURE is a functional block diagram of the preferred embodiment of a memory preservation system in accordance with the present invention.
.
Detailed Descri tion of the Preferred Embodiment P . _ .
The memory preservation and verification system of the present învention may be embodied in any electronic apparatus such as computational or measuremen~ instruments or data transmission equipment in which there are digital processing circuits 10 and a memory device 12. The digital processing .
. . ~ .
~3~
circuits 10 may therefore be any arrangement of lo~ic gates, shift re~isters, flip flops, and so forth, to perform whatever digital signal processing that is required.
Input data is applied to the digital processing circuits 10 over input lines 14 and processed data may be output on da~a lines 16. The input and output lines 14 and 16 respectively may be the same data bus. The digita~ processing circuits 10may also include process and control logic circuits; however, in this embodimentthere is shown a separate process and control logic c;rcuit 18 not only to facilitate the description but because such process and control logic circuit 18could be separate microprocessor or computer hardware. These circuits are conventional and well known in the art; therefore, no detailed description of these circuits is given here.
The memory device 12 in its most simple form may be one or more flip flops; however, it is more likeiy that the memory comprises a random-accessmemory (RAM~ having thousands of addressable memory locations. The memory device 12 is shown connected between a source of electrical power ancl ground for energization thereof. The source of electrical power may be either a main power supply 20 or a backup power supply 22, both of which are connected through a switch 24 to the memory device 12. The main power supply 20 rnay suitably be the power supply of the entire system, while the backup power supply22 may be either a battery located within the apparatus or an external power supply. The switch 24 suitably may be an electronic switch, such as a pair of transistors connected as a comparator with appropriate biasing and sensing circuits to align the switch to the correct power supply. In normal operation, the main power supply 20 is connected through the switch 24 to the mernory 12. If the main power is interrupted or turned off, the backup power supply 22 is switched into the circuit to preserve the data stored in the memory device 12.
Since the switching action of switch 24 cannot be instantaneous, a capacitor 26 is provided to maintain operatin~ power during the switch over and thereby prevent destruction of stored data.
A number generator 30 may be provided to ~enerate digital numbers in a pseudo-random fashion. Such number generator may be, for example, a counter circuit which is cycled continuously. The process and controllo~ic circuit 1~ accepts a digital number Nl from a number ~enerator 3~ and operates on ~his number in a particular manner to provide a second digital number N2 which is uniquely related to Nl. The digital nurnbers Nl and N2 are ~L:13~
1~
stored in the memory device IZ in preselected first and second memory locations respectively, and are maintained in these locations during normal operation of the apparatus during ~vhich time main power supply 20 provldes operating power to the memory. Data being processed by ~he digital processin~ circuits 10 rnay 5 be stored in the memory in the conventional manner. The memory status may be checked at any time by retrieving the digital numbers Nl and N2 and checking the relationship between the two numbers. This may be done by first retrieving the digital number Nl, operating on the number Nl in the same particular manner as originally performed to provide a new digital number r~l2t and then 10 comparing the new digital number N2 with the originally stored digital numberN2. If the numbers match, it is an indication that the data stored in the memory12 has been properly preserved. It is particularly important to check this relationship followin~ a power interruption or loss of main operating power during which time the backup power supply is used to preserve data stored in the15 system memory. A utilization device 34 is coupled to the process and control Iogic circuit 18 to provide an indication of either verification or non-verification of preservation of the memory status. For example, utilization device 34 could be an indicator li~ht, or an alarm, or a reset switch, or some device such as a cathode-ray-tube display or a printer which provides visual indication to an 20 operator.
The preferred embodiment of the memory preservation and the verification system described herein above has universal application. The systemas described is embodied in an oscilloscope having digital computational
2~ capability. Thus the digital processing circuits 10 and the process and control logic circuits 18 comprise a microprocessor and its associated circuits. The memory 12 is a bank of random-access memories. Main power supply 20 is the power supply for the entire oscilloscope. The number generator 30 is the countercircuits which drive an associated keyboard. The utilization device 34 is the 30 cathode ray tube of the oscilloscope. Since only a portion of the memory is checked in the verification process, the presumption that valid data is stored in the remainder of the memory is based on probability. Severable steps are taken to ensure a high degree of probability that the data is valid. First, the digital numbers 1~1 and N2 are 8-bit digital numbers. The process and control logic 35 circuit 1~ analyzes the number 1~1 and rejects a number which is all zeros or all ones. Therefore, the stored numbers will contain both zeros and ones, eliminating the probability that a memory containing a~l ones or all zeros upon a 1~3~
subsequent power up will be used in the verification prs~cess. The operation which takes place in producing the second digital nurnber N2 is generating the complement of the ~irst digital number Nl. That is, any zeros in the number Nl are converted to ones for the number N2, and the ones of the first nl~mber Nl are 5 converted to zeros for the number N2. The two numbers Nl and N2 are stored in a preselected first and second memory locations, which memory locations are adjacent to each other. It is believed that this situation actually increases the chances of memory destruction during a power interruption, so that, conversely, a positive verification upon a subsequent power up increases the probability that 10 data stored in the rest of the memory is valid. Also, the use of complementary digital numbers Ni and N2 simplifies the verification process in tha~ the digital numbers Nl and N2 may be compared directly without generating a new digital number N2.
In summary, it can he seen that a memory preservation and verification system has been shown and described herein. It will be obvious to those having ordinary skill in the art that many changes may be made in the details of the herein above-described preferred embodiment of the present invention. Therefore, the scope of the present invention should be determined 2~ only by the following claims.
" '.
:,
subsequent power up will be used in the verification prs~cess. The operation which takes place in producing the second digital nurnber N2 is generating the complement of the ~irst digital number Nl. That is, any zeros in the number Nl are converted to ones for the number N2, and the ones of the first nl~mber Nl are 5 converted to zeros for the number N2. The two numbers Nl and N2 are stored in a preselected first and second memory locations, which memory locations are adjacent to each other. It is believed that this situation actually increases the chances of memory destruction during a power interruption, so that, conversely, a positive verification upon a subsequent power up increases the probability that 10 data stored in the rest of the memory is valid. Also, the use of complementary digital numbers Ni and N2 simplifies the verification process in tha~ the digital numbers Nl and N2 may be compared directly without generating a new digital number N2.
In summary, it can he seen that a memory preservation and verification system has been shown and described herein. It will be obvious to those having ordinary skill in the art that many changes may be made in the details of the herein above-described preferred embodiment of the present invention. Therefore, the scope of the present invention should be determined 2~ only by the following claims.
" '.
:,
Claims (2)
1. A memory preservation and verification system comprising:
power supply means coupled to said memory for energization thereof, said power supply means including a main power supply and a backup power supply;
means for generating a first digital number;
process and control logic means for generating a second digital number and storing both of said first and second digital numbers in said memory,said second digital number being mathematically related to said first digital number;
said process and control logic means also for retrieving said first and second digital numbers and checking the relationship therebetween to thereby provide a verification of the validity of the contents of said memory; and utilization means for providing an indication of said verification.
power supply means coupled to said memory for energization thereof, said power supply means including a main power supply and a backup power supply;
means for generating a first digital number;
process and control logic means for generating a second digital number and storing both of said first and second digital numbers in said memory,said second digital number being mathematically related to said first digital number;
said process and control logic means also for retrieving said first and second digital numbers and checking the relationship therebetween to thereby provide a verification of the validity of the contents of said memory; and utilization means for providing an indication of said verification.
2. A memory preservation and verification system in accor-dance with claim I wherein said power supply means further includes switch means for coupling one of said main power supply and backup power supply to said memory and switching to the other of said power supplies under predetermined conditions.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US30,509 | 1979-04-16 | ||
| US06/030,509 US4232377A (en) | 1979-04-16 | 1979-04-16 | Memory preservation and verification system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1135869A true CA1135869A (en) | 1982-11-16 |
Family
ID=21854527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000348342A Expired CA1135869A (en) | 1979-04-16 | 1980-03-25 | Memory preservation and verification system |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4232377A (en) |
| JP (1) | JPS55142499A (en) |
| CA (1) | CA1135869A (en) |
| DE (1) | DE3013523C2 (en) |
| FR (1) | FR2454674A1 (en) |
| GB (1) | GB2047927B (en) |
| NL (1) | NL181154C (en) |
Families Citing this family (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1981002362A1 (en) * | 1980-02-08 | 1981-08-20 | Mostek Corp | Multiplexed operation of write enable terminal of a memory circuit for control and backup power functions |
| US4315162A (en) * | 1980-05-09 | 1982-02-09 | Control Technology, Incorporated | Reserve power supply for computers |
| US5055704A (en) * | 1984-07-23 | 1991-10-08 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit package with battery housing |
| US4998888A (en) * | 1984-07-23 | 1991-03-12 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit package with battery housing |
| US5276354A (en) * | 1981-05-27 | 1994-01-04 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit package with battery housing |
| JPS5840674A (en) * | 1981-09-03 | 1983-03-09 | Fujitsu Ten Ltd | Fault deciding method of microcomputer |
| JPS58171537U (en) * | 1982-05-07 | 1983-11-16 | ブラザー工業株式会社 | Electronics |
| JPS5948899A (en) * | 1982-09-09 | 1984-03-21 | Ishida Scales Mfg Co Ltd | Error checking method of ram |
| JPS59127299A (en) * | 1983-01-08 | 1984-07-23 | Sony Tektronix Corp | Backup confirming method of storage circuit |
| GB2145253A (en) * | 1983-08-17 | 1985-03-20 | Philips Electronic Associated | Method of controlling a domestic appliance |
| JPS60247766A (en) * | 1984-05-22 | 1985-12-07 | Sharp Corp | Program computer |
| GB2166893B (en) * | 1984-10-05 | 1988-03-23 | Sharp Kk | Checking memory at system power-up |
| FR2571870B1 (en) * | 1984-10-15 | 1987-02-20 | Sagem | MICROPROCESSOR MEMORY BACKUP DEVICE. |
| JPS61141056A (en) * | 1984-12-14 | 1986-06-28 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Intermittent error detection for volatile memory |
| US4650957A (en) * | 1985-04-29 | 1987-03-17 | Cyclomatic Industries, Inc. | Voltage control system |
| US4800378A (en) * | 1985-08-23 | 1989-01-24 | Snap-On Tools Corporation | Digital engine analyzer |
| US4779091A (en) * | 1986-01-31 | 1988-10-18 | Nec Corporation | Radio pager receiver capable of informing whether or not memory backup is correct |
| JPH0624335B2 (en) * | 1987-02-27 | 1994-03-30 | 日本電気株式会社 | Selective call receiver with display |
| JPH086799B2 (en) * | 1987-06-20 | 1996-01-29 | 富士通株式会社 | Electronic control device and method for automobile transmission |
| US4874960A (en) * | 1988-03-04 | 1989-10-17 | Square D Company | Programmable controller capacitor and battery backed ram memory board |
| US5028806A (en) * | 1989-04-14 | 1991-07-02 | Dell Corporate Services Corporation | Battery replacement system for battery-powered digital data handling devices |
| US5410713A (en) * | 1992-01-02 | 1995-04-25 | Smith Corona/Acer | Power-management system for a computer |
| ES2107492T3 (en) * | 1992-12-15 | 1997-12-01 | Siemens Ag | PROCEDURE AND ARRANGEMENT FOR THE SUPERVISION OF THE OPERATION OF A DIGITAL CIRCUIT SYSTEM. |
| ATE202224T1 (en) * | 1993-10-04 | 2001-06-15 | Elonex Technologies Inc | METHOD AND DEVICE FOR AN OPTIMIZED POWER SUPPLY FOR A COMPUTER DEVICE |
| JP3474665B2 (en) * | 1995-03-02 | 2003-12-08 | 富士通株式会社 | Power supply control apparatus and method for computer system |
| JP2802744B2 (en) * | 1996-01-26 | 1998-09-24 | 株式会社アイエスエイ | Uninterruptible power supply controller with timer |
| US5857074A (en) * | 1996-08-16 | 1999-01-05 | Compaq Computer Corp. | Server controller responsive to various communication protocols for allowing remote communication to a host computer connected thereto |
| US5796566A (en) * | 1996-08-16 | 1998-08-18 | Compaq Computer Corporation | Printed circuit board having conductors which can be decoupled for isolating inactive integrated circuits connected thereto |
| US5852720A (en) | 1996-08-16 | 1998-12-22 | Compaq Computer Corp. | System for storing display data during first time period prior to failure of computer and during second time period after reset of the computer |
| US6233634B1 (en) | 1996-08-17 | 2001-05-15 | Compaq Computer Corporation | Server controller configured to snoop and receive a duplicative copy of display data presented to a video controller |
| DE102004022792A1 (en) * | 2004-05-08 | 2005-08-11 | Infineon Technologies Ag | Memory circuit for data storage esp. for mobile/cell phone, has control circuit for blocking and enabling read/write functions in first and second state |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3980935A (en) | 1974-12-16 | 1976-09-14 | Worst Bernard I | Volatile memory support system |
| US4122359A (en) * | 1977-04-27 | 1978-10-24 | Honeywell Inc. | Memory protection arrangement |
-
1979
- 1979-04-16 US US06/030,509 patent/US4232377A/en not_active Expired - Lifetime
-
1980
- 1980-03-18 NL NLAANVRAGE8001608,A patent/NL181154C/en not_active IP Right Cessation
- 1980-03-25 CA CA000348342A patent/CA1135869A/en not_active Expired
- 1980-04-08 DE DE3013523A patent/DE3013523C2/en not_active Expired
- 1980-04-15 FR FR8008662A patent/FR2454674A1/en active Granted
- 1980-04-15 JP JP5024780A patent/JPS55142499A/en active Granted
- 1980-04-15 GB GB8012307A patent/GB2047927B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6245572B2 (en) | 1987-09-28 |
| GB2047927A (en) | 1980-12-03 |
| FR2454674A1 (en) | 1980-11-14 |
| DE3013523A1 (en) | 1980-10-23 |
| DE3013523C2 (en) | 1983-09-15 |
| JPS55142499A (en) | 1980-11-07 |
| GB2047927B (en) | 1983-05-25 |
| FR2454674B1 (en) | 1983-06-17 |
| NL8001608A (en) | 1980-10-20 |
| NL181154C (en) | 1987-06-16 |
| US4232377A (en) | 1980-11-04 |
| NL181154B (en) | 1987-01-16 |
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