CA1137619A - Data manipulation apparatus for converting raster-scanned data to a lower resolution - Google Patents

Abstract

ABSTRACT
Data manipulation apparatus is described for converting raster-scanned data received for example from a scanner at a first picture element (pel) resolution to a second lower pel resolution for display for example on a CRT terminal.
The apparatus includes a scale-changing means which func-tions to replace selected sub-groups of pels in the input image by single pels at its output. The significance of each single pel reflects the presence or absence of a pel representing part of an image object in the associated sub-group of pels. The number of pels in the selected sub groups are determined by the degree of compression required to convert to the lower pel resolution. Prior to scale change the apparatus functions to modify the input data in order to minimize merging of adjacent image objects as a result of scale change and thereby improve the legibility of the output image at the lower resolution. The scanned data is first supplied to a data sensitive thinner which detects narrow gaps between adjacent objects and selectively detects image object edge pels in order to widen the gap. The selectively thinned scanned data is then supplied to a further thinner which removes excess image pels from se-lected edges of the image objects. The data from the fur-ther thinner is then supplied to a data sensitive merge inhibit unit which moves selected image object pels from a sub-group in which merging as a result of scale change will occur to an adjacent sub-group where merging will not occur.
Removal of a pel by the selective thinner, or by the fur-ther thinner or movement of a pel by the inhibit unit is inhibited if to do so would result in fragmentation of the associated image object.

Description

~3~g DATA MA~IPULATION APPARATUS FOR CONVERTING RASTER--SCANNED DATA TO A LOWER RESOLUTION

This invention relates to data manipulation apparatus for receiving and manipulating raster-scanned data indicative of an image.

It has previously been proposed that documents could be scanned, digitized and stored electronically in a computer.
The stored data could then be recalled from storage, recon-stituted and either displayed on a display, prin-ted with a printer/plotter, or transmitted over a data link for storage at another location. A document which is to be digitized can be scanned by a scanner whose output is a stream of bits which represent picture elements (pels) in successive lines of the raster scan. The resolution of a scanner is defined in terms of the number of pels per inch. Typical scanner output resolutions are 240, 120 and 9~ pels/inch.

If during operation, a particular scanner produces an output in response to an input pel in the input image which is black over more than 50% say of the pel area but produces no output for pels with more than 50% white, then strokes in the input image which are thinner than 50% of the pel width will not be detected by the scanner resulting in stroke "drop-outO" Furthermore, inter-stroke gaps of less than 50% pel width will also go undetected by the scanner resulting in stroke merging. Clearly therefore, the higher the scanner resolution, the greater the potential legibility of the subsequently displayed image. The visual benefits provided by high resolution sampling, however, are offset by the corresponding rapid increase in the volume of data required ~4~

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l to represent the image. This increase is proportional to the square of the increase in linear resolution. For an A4 size document (approximately 8 by 12 inches) over 3 million pels are required to represent the document at a scanning resolution of 240 pels per inch. The requirements for electronic storage of such scanned documents can become prohibitively expensive.

The conflicting requirements of high resolution scan-ning and economic considerations limiting the amount of data to be stored can be potentially resolved by scanning the input image at high resolution and then compressing the data prior to storage~ Various compression techniques have been proposed. The Complete Specification of our U.K. Letters Patent No. l 396 900 describes a technique in which a predictor predicts whether a pel is 'l' or '0', that is 'on' or 'off'. The predicted pel is compared with the actual pel and an error signal is produced when they differ. These error signals are run-length encoded and the compressed ~ata stored. The Complete Specification of our U.K. Letters Patent No. 1 517 870 describes an alternative technique in which a document is scanned in a raster until an object, for example a character, is located. The contour of the object is followed, recording each pel and moving to the next until the centre of the object is reached. The raster scan is resumed until the next object is encountered. The Complete Specification of our U.K. Letters Patent No. 1 517 870 describes a technique and apparatus for converting a scanned document into vectors. The Complete Specification of our U.K. Letters Patent No. 1 517 869 describes a technique and apparatus for converting scanned character data into a series of segments coded by shape and end-point position.

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1 In some cases, subse~uent display of the compressed image may require the resolution of the display device to be the same as that of the scanner producing the input data.
Under circumstances where high resolution display devices are unavailable, these methods which rely solely on com-pression of the image data are unsatisfac-tory and an alter-native solution must be sought.

A compromise solution is to scan the data at a high resolution and then to perform an appropriate scale change to enable the data to be displayed by the device at a lower resolution. Clearly, the legibility of the displayed image will depend on the nature of the technique used to effect the scale change from raster scanned data at high resolution to the lower resolution required by the display device or printer.

A simple method of manipulation or consolidation of image data from 240 pels per inch to 120 pels per inch would be to perform a straight-forward scale change projection from high to low resolution. This could be achieved by dividing the entire 240 pels per inch matrix from the scan-ner into sub-groups or 'windows' each two pels wide and two pels high and selecting, for example, the top left-hand corner from each window for projection onto the 120 pel per inch matrix required for the output display or printer.
This 'unintelligent' method of consolidation would have a serious disadvantage in that it could cause discontinuities to form and spurious connections to be made in the final output image. For example, if a character in the input image is only one pel thick at some place and if the pel happens not to lie in the top left-hand corner of a 2 x 2 window, then a discontinuity occurs in the output image displayed or printed at the lower resolution. Similarly character gaps which are only one pel wide can be ~K9-78-019 ~ 13'7~

1 eliminated during the scale change operation with the result that adjacent characters or parts of the same character merge together. Such spurious discontinuities and mergings could affec~ the legibility and overall quality of the output image to an unacceptable degree.

The present invention is directed to a means for manipulating or consolidating raster scanned data at a high resolution in order to enable display of an output image at ~`10 a lower resolution which does not suffer so greatly from - the disadvantages of the above simple method.

According to the invention, data manipulation apparatus for receiving raster-scanned data as a first series of bits indicative of individual objects forming an image at a first picture element (pel) resolution and for converting the data into a second saries of bits indicative of the image at a second lower pel resolution, comprising a scale changing means operable on receipt o~ said first series of input bits to convert selected sub-grollps of said input bits each into a single output bit, the significance of each OUtpUI bit being determined by the presence or absence of a ( bi-~ of a predetermined significance anywhere in the associated sub-group of input bits, the size of the sub-groups being determined by the degree of compression required to effect the scale-change from said first to said second pel resolution, and means operable prior to scale change for investigating bits in adjacent sub-groups and selectivel~ to change the significance of one or more of said investigated bits, merging of said objects after scale change to said lower resolution would otherwise occur.

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1 In order that the invention may be fully understood, a preferred embodiment thereof will now be described by way of example with reference to the accompanying drawings.
In the drav;ings:

Figure 1 shows in schematic form data manipulation or consolidation apparatus in accordance with the invention;

Figure 2 shows an array of shift registers forming part Or consolidation apparatus and illustrates conceptuall~ how a 'slice' of image data is processed through the registers;

Figure 3 shows the principle of operation of a scale change projector forming par~ of the consolidation apparatus;

~ igure 4 shows an example of scale change pro~ection where a feature in the input image is preserved in the output image;

Figure ~ shows arl example o~ scale change projectlon where two features in the input image are merged;

- Figure 6 illustrates the operation of a data sensitive ,, ~
thinner, forming part of the consolidation apparatus, 03 sample data;

Figure ~ shows how narrow gaps can be preser~ed in the output image b~r manipulating the input data;

Figure 8 shows a simple logical window for detecting a right-hand edge of a sequence of black pels;

Figure 9 shows a simple logical window for detecting a narrow gap between a right-hand edge and adjacent data;

Figure 10 shows the simple window shown in Figure 9 in relation to t~rpical image data;

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l Figure 11 shows an extended gap detection window;

Figure 12 shows the window shown in Figure 11 in relation to typical image dat.a;

Figure 13 shows the selected window design for the right thinner forming part of the sensitive thinner;

Figure 14 shows various configurations of image data ~` lO to illustrate the need to maintain connectivity;

Figure 15 shows how connectivity may be maintained using a simple window;

Figure 16 shows how T-junctions and corners are detected;

Figure 17 shows how progressive thinning of data can occur with a left thin operation;
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Figure 18 shows the effect on data during a right thin operation;

Figures 19,20,21,22,23,24,25,26,27 and 28 illustrate the effect of various relative window positions and application order with respect to typical image data;

Figures 29 and 30 show the data sensitive thinner i~
schematic form;

Figure 31 shows circuit details of a right thinner forming part of the data sensitive thinner;

Figure 32 shows a timi.ng diagram for operation of the circuits shown in Figure 31;

~376~9 ~ 7 --1 Figure 33 shows a circuit for inhibiting progressiv2 left thinning;

Figure 34 shows a circuit for inhibiting progressive top thinnlng;

~ igures 35 and 36 show the window conditions for a non-selective thinner forming part of the data consolidation apparatus;

Figure 37 shows how ends of thin lines are detected;

Figures 3S and 39 show the non-selective thi~ner in schematic form;

Figure 40 illustrates the operation of the data consolidation apparatus on sample data;

Figure 41 illustrates how merge correction an be used to preserve narrow gaps in the data;

Figure 42 shows some correction stimuli windows for - merge correction;

Figure 43 shows window outline for a horizontal primary merge correction unit;

Figure 44 shows ~vindow conditions for detecting alternative merge states as a result of primary correction;
Figure 4~ shows a further window configuration used for merge correction;

Figure 46 shows window condition for testing connectivity during merge correction;

l Figure 48 shows a further window for applying a connectivity constraint during merge correction;

Figure ~9 shows the stimuli conditions for downward secondary merge correction;

Figure 50 shows the window conditions for detecting alternative merge states as a result of secondary correction;

~~" lO Figures 51 and 52 each show in two parts the merge correction unit in schematic form;

Figure 53 shows in two parts the circuit details of a downward primary merge correction unit;

Figure 54 shows various set patterns for gating registers iorming part of the circuits shown in Figure 53;

Figure 55 shows circuits for performing connectivity tests during merge correction;

Figure 56 shows a circuit detail of the downward merge ,- correction unit.

Figure 57 shows the circuit details of the scale charge projector forming part of the data consolidation apparatus.

Figure 1 shows data consolidation apparatus in which image data on a document 1 is scanned at a high resolution by scanner 2, consolidated in consolidation unit 3, and there-after displayed at a low re.solution on display screen 4. The scanner 2 produces a series of bits at its output representing light and dark areas or pels on the scanned document at the scanner resolution. The consolidation unit 3 includ~s a data ~376~
g l sensitive thinner 5 where bits are selectively removed from the raster scanned input bit pattern in an attempt to preserve the spacial structure of the original image when displayed at the lower resolution; a non-selective thinner 6 which re~oves further bits from the bit pattern to leave a processed or modified bit pættern in which the bits represent predominantly single pel-wide lines; a data sensitive merge inhibit unit 7 which re-positions discrete bits to minimise residual merge states in ~he processed image; and finally a scale change projector 8 which effects the scale change from the high resolution input (say 240 pels/inch) to the low resolution output (say 96 pels/inch).

The data consolidation unit 3 operaLes synchronously from the serial bit raster output which is applied to input termi~al 9 of an array of fourteen serially inter-connected shift registers SRl - SR14, shown in Figure 2. Each shift register has a capacity equal to the total number of bits ~approximately 1600) in a single raster line scan of the image.
At any one time, therefore, the array of shift registers contains up to fourteen rows of image data. The three consolidation fun~.tions prior to scale change projection are ~- continuously performed on a relatively s~all 'slice' o~
image data (less than 50 bits wide) as it moves through the array of fourteen shift r~gisters. The section of shift registers in which the 'slicè' of image data is processed is shown by chain-dotted box 10 in Figure 2.

The upper part of Figure 2 represents conceptually the situation wherein the image 'slice' processed is in its initial position with respect to the shift registers with the first scan row of image data 11 contained in shift register SRl. The lower part of Figure 2 represents the situation wherein the image 'slice' is in its final position with the ~ 13~

l last scan row of the image data 11 contained in shift register SR14. The processed image bit stream emerging from output terminal 12 is ready for the scale change projection required in order to display at the lower resolution.

During the description to follow of the two thinners 5 and 6 and the merge inhibit unit 7, repeated reference is made to the scale change projection subsequently to be performed on the processed image bit stream. Since the nature of the scale change projection imposes limitation on r~
the preceding image data processing functions, it is useful to explain the principle of the projection function at this pcint. The description of the structure of the scale-change projector is given later.

Projection is the function that performs the scale change necessary to convert image data supplied at a relatively high pel resolution to a form suitable for display at a relatively low pel resolution. Thus, in the case where the input image is derived from a scanner having a resolution of 240 pels per inch and the resolution of the display unit to which the image is to be supplied is only 96 pels per inch, the required scale change ratio is 5:2. That is, for every five image bits representing pels in the input image, only two image bits are supplied in the output image.

Clearly, the scale change ratio depends on the change in resolution from input to outpu~ and will vary with different mixes of apparatus. Thus, a simple scale change ratio of 2:1 is required for a scanner with a resolution of 2~0 pels per inch used with a display unit with a display resolution of 120 pels per inch. The non-integral scale change ratio of 5:, presents more difficulties in implementation and has been selected as the preferred embodiment since it represen~s a more general case.

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1 Figure 3 shows an array of 5 x 5 pels in the input image which is converted by the scale change projector to an output image array of 2 ~ 2 pels. In the figure, the input image array is shown divided into four sub-arrays or 'windows' ABCD and the output array similarly divided into four single pel 'windows' abcd. The window boundaries are represented by relatively heavy lines between the individual pel positions. As can be seen, the windows ABCD in the input image are not of e~ual size because the scale change of 5:2 is a non-integral ratio. The function of the projector is to derive a value for each position in the output array on the basis of the values of pels in the corresponding windows in the input array. A simple rule is applied that if there is at least one binary 1 bit in the input window representing a black pel in the original scanned image, then the correspond ing window in the output array is set to a binary 1 bit to provide a black pel in the corresponding position in the out-put image. This rule ensures that connectivity of blac~ data in the input image is preserved duri~g scale-change projection.
Thus In Figure ~, a thin black diagonal line in the input image is not broken or lost during scale change projection and appears in the output image. At the same time, however, as is illustrated in ~igure 5, two vertical quite widely separated lines in the original input image are merged into a single line in the output image as a result of the scale change projection. ~uch merges result in a consequent reduction of legibility of the displayed output image. It is for this reason that the scale-change projection is preceded by the - two thinning and one merge inhibit operations.
Many potential merges which can occur as a result of projection are prevented by data sensitive or selective thinn-ing of the input image prior to the scaIe change projection.
Figure ~ illustrates the operation of the data sensitive thinner 6 on sampie data. Thus an original pel input image is shown in Figure Ga before and after scale change projeclion.
-~3~9 1 The final image illustrates the intercharacter merging which results. Figure 6`o shows the same input image after select-ive thinning again before and after projection The final image in this case shows comparatively good character separation, The object of the thinner is to delete bits from the original image so as to preserve narrow gaps after scale-change projection. Thus, for example, in the upper part of Flgure 7 a typical bit stream is sho~vn representing, by the two binary O's, a two pel wide gap separating two black features. The phasing of the projection windows with respect to the data is such that this two pel wide gap falls in a three pel wide projection window and, by applying the scale-change rules, i5 eliminated in the output image. I~, however, prior to scale-change projection, the gap is extended horizontally one pel to the left as shown in the lower half of Figure 7 then, after projection, a narrow gap is retained in the output image.
These narrow gaps are detected by the sequential investigation of each pel in the input :image in relation to surrounding pels. The investigation is by means of a simple logical window based on a selected pel position. Figure 8 shows a simple case of a window consisting of a group of ~ive pels (pel columns are nominally labelled Xn, Xn~1, Xn+2 ....
pel rows are labelled Yn, Yn+1, Yn~2 ...~ used to detect the presence of a right-hand edge of a se~uence or block of black pels. The window is based on pel position (Xn,Yn) which is the pel under iLvestigation. The values of the bits i~
the remaining pel positions give the various alternative configurations which satisfy the window conditions and lead to the detection of a right-hand edge in the input data between the investigated pel position and its neighbouring pel position (Xn+1, Yn). Thus, in the figure, the cross-hatching gL~376~

l extending upwards from left to right through row Xn-1 represents the requirement that the logical OR of the bits in those pel positions should be 'ONE'. That is, one or more of the pels in the input image correspondin~ to that row must be black. Similarly, the investigated pel (Xn,Yn) must be black and its neighbouring pel (Xn~l,Yn) must be uhite. With these conditions satisfied, a right-hand edge is identified between pel (~Xn,Yn) and pel (Xn+l,Yn~.

The edge detection window is extended as shown in ~ Figure 9 in order to detect a narrow gap between such an edge and adjacent data. The window is extended three pel positions to the right in row Yn. The cross-hatching indicates as before the requirement that the logical OR of the bits in those pel positions should be 'ON~'. That is, one or more pels in the input image corresponding to these three pel positions must be black. It is seen therefore that this logical window will detect gaps of 1,2 or 3 pel widths between a right-hand edge and adj~cent data in the row under consideration. The gap can therefore be extended, i.f desired, by deletion of the pel in position ~Xn,~'n), ~igure 10 shows an image portion which consists of a ( block of ON-pels 13 representing a black feature having a right-hand edge 14 and an àdjæcent narrow horizontæl line 15 of ON or black pels separated from the right-hand ed~e by a single pel position, that is a gap one pel wide. During the row-by-row sequential investigation of the image pels using the gap detection windou showll in Fi~ure 9, the situation eventually arises in which the window is positioned as shown in dotted outline 16, investigating pel posit on (Xn,Yn).
The image data present at that time fulfils the narrow gap window conditions thus enabling pel (Xn,Yn) to be deleted so extending the gap in row Yn one pel position to the left.
Consideration of the corresponding situation in the preceding ~L~371~

1 row Yn-l and succeeding row Yn~l shows that, in the absence of image data in pel positions Yn+2, Yn+3 or Yn+4 or rows ~'n-l and Yn+l, the window requirements are not satisfied and the corresponding pels (Xn,Yn-l) and (Xn,Yn+l) are not dele~ed The gap detection window shown in Figure 11 overcomes this limitation. In this figure, the cross-hatching extending downwards from left to right represents the conditiorl in which the logical AND of the pels in that column is ZERO.
Thus, the window conditions are rnet by image data in which the OR of pels in column ~n-l is ON~, pel (Xn,Yn) is ON~, all p21s in column ~n~l are ZERO, and the OR of pels in columns ~n+l, Xn+2, Xn+3 are all ONE. When these conditions are satisfied, deletion of pel Xn,Yn from the image data may be -initiated. It is seen that the use of this window on row Yn-l and row Yn+l of the image data shown in Figure 10 results in deletion of pels (Xn,Yn-l) and (Xn,Yn+l) respectively. From these examples, it will be realised that, if desired, fur+her ¦20 pels a'long the edge can be deleted simply by extending the window dimensions.

Figure 12 shows a portion of image data in which 'the narrow gap is diagonally inclined between two blocks of data 17 and 18. In this case, the window conditions for deletion of pel (Xn,Yn) are not satisfied because column Yn+l does not contain all ZEROs. The window is shown in dotted outline 19.

¦ Window design is selected so that the stimulus for deletion of a pel under investigation comes from near axial neighbours, diagonal and sub-diagonal neighbours. Thus, in the selected practical implementation, the right thinner includes five different windows which are used in parallel to test the image data. These five windows are shown in Figure 13. The window in Figure 13(a) provides axial stimuli for deletion 37~

l cf the pel under investigation from 2 and 3 pel distance and also from two pels in two anti-clockwise sub-diagonal directions. The stimulus directions are indicated by arrows extending from the pel under investigation. Figure 13(b) extends the stimuli to one further anti-clockwise sub-diago~al pel and to a diagonal pel. Figure 13(c) extends the stimuli to a further diagonal pel and to another sub-diagonal pel rotated further in an anti-clockwise direction. Figure 13(d) and 13(e) show windows providing corresponding stimuli for pel deletion in a clockwise direction. The selection of window conditions for the right thinner shown in Figure 13 does not include a window with clockwise stimuli corresponding to the two additional anti-clockwise stimuli in Figure 13(c) for reasons of economy as will become apparent later. The outline of the complete right thinner including all five sub-windows is shown in Figure 13(f). ~his outline ~ill appear in subsequent figures in which the right thinner is used. It should be pointed out that selection of windo~ conditions is a matter of design choice in t~hich the advantages of extending the pel deletion stimuli are weighed ag&inst the additional cost of implementation.

, The selective thinner requires the integration o~ such "-- thinning windows which perform corresponding thinning operations in all four possible orientations, that is, from the right as described above and shown in Figure 13, from the left, from below, and from above. Thus, thinning from the left is achieved by a left thinner which is essentially the mirror image of the right thinner'described with reference to Figure 13 but extended to be symmetrical about the horizontal axis. Thinning from above is achieved by a top thinner which is essenti'ally the same as the left thinner rotated cloc~wise through 90. Thinning from below is achieved in practice by a number O1 bottom thinners each of which is largely mirror image of the IOp thinner. The - ~hinning ~tindows of the data sensiLive ~hinner have been ~3~61g l designed to de-sensitise the thinners from the efiect of scan~er drop-out. A minimum gap of two vertical pels is required to initiate horizontal thinning, a minimum gap of two horizontal pels is required to initiate vertical thinning.
Details of the actual sizes and shapes of the thinners will be given later after a discussion of the various alternatives available. The actual number of component windows required, their relative positions in these thinners and their operating sequence have been selected in an attempt to minimise merging and -to generate a neutral and symmetrical interpretation as a -thinned result. The various constraints and considerations of alternative arrangements which led to the final selection will now be described.

~ pel will not be removed if its removal would alter the connectivity of the objects in the input data. This first constrainl is illustrated in Figure 14 which shows various 3 x 3 window configurations in which the central pel is being examined. The condition for remov~l is satisfied if 20 the number of separate components in the eight neighbours of the central pel is exactly one. The number of components is ' determined by logically traversing a circular ~ath around the central peI by way of the eight neighbours as shown in Figure 15. The number of white ~o black transitions between consecutive a~ial (non-diagonal) neighbours is counted to obtain a 'crossing number'. A black to white transition does not increment the count. Nor is the count incremented for a move between two consecutive black axial neighbours via an intervening white diagonal neighbour. In other words, the count can only be incremented when moving from a white a~ial neighbour: whether the count will then be incremented depends on whether either of the immediately following diagonal neigh-bour or the following axlal neighbour is black. Thus in the 1~37i~

l example shown in Figure 15,, the count is 2. If the crossing number is 2,3 or 4, the central pel is essential to maintain connectivity and removal is inhibited during the thinning process. Inspection of the various input configurations in Figure 14 shous that the cen~ral pel is deleted in examples (a) to (d) but del,etion is inhibited in examples ~e) (f) and (g). This connectivity constraint is applied only to those pels marked by the thinner for deletion, A pel will not be deleted if it is identified 2S a corner or a T-junGtion pel. The logical operators necessary for determining whether or not the pel is located at the centre of a T-junction are shown in Figures 16a to d and the operators for determining whether or not the pel is located at a corner are shoun in Figures 16e to h.

The selec~ive thinner operates by removing ail pels which will cause merging at the target resolution pro-viding they are not retained by`the connectivity logic, Excessive deletions from open ends are normally prevented by the limited range of the thinning windows. This safeguard is not always able to prevent progressive deletion of a line. Thus, for exampie, as shown in Figure 17a, data (shown cross-hatched~ cansisting of ; two single pel horizontal l,ines separated by a 1-pel gap entering a left thinner (shown in dotled outline) in the direction of the arrow, will result in deletion of the pel in position X of the window. The situation 1-pel time later is shown in Figure 17b in which it is seen that the pel under investigation in position X is again deleted. The process is stopped 1-pel time later as shown in Figure 17c, because the windo~ conditions are no longer satisfied. Clearly, a window 'design in which pel deletion stimulus is obtained from more distant pels will result in further pel stripping. Even so, the initial 1-pel gap has been extended in a relatively uncontrolled manner to a 3-pel gap. In contrast, Figure 18 shows the same data entering a right thinner. The window cor.di~ions are satisfied initially as shown in Figure 18a .... .

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1 and the pel in position X is deleted. The situation 1-pel time later is shown in Figure 18b where, it is seen that the window conditions are not satisfied and no further pel is deleted.

It will be apparent from the foregoing that a similar problem exists ~ith vertical thin lines initially separated by a 1-pel gap. Such lines will be progressively thinned by a top-thinner to produce a 3-pel gap whereas no such problem is experienced with a bottom thinner. This undesirable effect of uncontrolled pel deletion by the left and top thinners which leads to rapid distortion of the pel structure is due to the direction of movement of input image data relative to thinner windows. For this reason, progressive top and left thinni~g is inhibi~ed by continuously monitoring the state of the image data during each scan row. In the case of left thin operations a delete inhibit latch is set as a result of a pel deletion determined by a left thinner and remains set until the entire feature being investigated, that is all the black pels in that particular group of pels, has pas'sed through the thinner.
In the case of top thin operations, the state of the image slice ro~v being considered for top deletion is retained in a 'top deletion' register. This register is set by the top thinning operation and its contents are used to inhibit top edge deletion in corresponding positions in the ne~t image row presented for the top thinning operation. With this technique, multiple pel removals from the tOp edges present in the input image are inhibited.

Although the problem of progressive horizontal pel stripping by a horizontal thinner and progressive vertical pel stripping by a vertical thinner is overcome, a further problem exists in that, under certain circumstances, narrow vertical lines can be completely eliminated by successive ~376~

l operations of left and right thinners.

Figure 19 shows on its right hand side, part of an input image having a 2-pel wide vertical line separated by a 1-pel gap on each side from further image data. As before, the image data is shown cross-hatched. This time however, the thinner windo-s are not shown superimposed on the data.
Instead, the window positions with respect to data and to each other are represented by correspondingly positioned sin~le pels labelled THIN R and THI~T L. These single pels ~_ represent the pels under investigation of the respective right and left thinner windows. The ini~ial input data is shown as lt is supplied line at a time to first a right thinner (THIN R) and the~n to a left thinner (THIN L), both of which are assumed to operate in sequence on the same scan line. The left hand side of the fi~ure shows the resulting progressive vertical deletion of the 2-pel line from the input image. Thus, the top right hand pel of the 2-pel line is deleted by the first right thin operation R1 as the first line of the image slice passes through the right thinner. This is immediately followed by the top left hand pel being deleted by the first left thin operation Ll as the first line passes through the left thinner. Durin~ the next scan line, the next ' ` right hand pel is deleted by the second right thin operation R2 and this is followed by the deletion of the uext Ieft haud pel by the second left thin operation L2. The process is repeated unti] the entire 2-pel wide line has been removed from the input image.

Vertical asyn~etry between left and right thinners will prevent progressive deletion of this nature. ~lore specifically, if the right thinner is used first and one data line delay is introduced between the right thinner and the subsequently applied left thinner, line retention is made possible by the particular pel configuration used for valid :~3 ~

l edge detection, This configuration requires the presence of an adjacent pel on or diagonal to the thinning axis to the one considered for deletion.

Figure 20 shows the same input data as used in Figure 1~ this time applied to vertically off-set left and right thinners. The horizontal off-set has no significance in this figure and should be ignored. This vertical asymmetry between left and right windows is illustrated by the relative ~-10 positions of the respective left and right positions of the ~- pels to be investigated by the two thinners shown at the top of the figure and labelled THIN L and THIN R as before.
T~us, it is seen that the first line of the image is processed by the right thinner T~IN R resulting in deletion , of the top right hand pel by the first right thin operation R1. The second line of the image is also processed by the right thinner resulting in deletion of the next right hand pel by the second right thin operation R2. When the data is applied to the left hand, the previous deletion of the two right hand pels removes the necessary stimulation for the left hand window and no pel is deleted. Consequently the tkin line feature of the input image is retained in the out-( put as shown on the left hand side of Figure 20.
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Thinning patterns are also determined by the interactionof thinning between vertical and hori20ntal axes. For this reason, the position and sequence of the thinning windows can modify the structure of the thinned result. In addition, different mixes of progressive and non-progressive thinning interact differently. ~lany variations are available which give differen~ results. For e~ample, applying a top thinner before a right thinner without vertical offset establishes a thinning progression where each thinning operation takes advantage of the previous one. This example is shown in Figure 21 using the same system for identifying relative - window positions as before. The input data is shown on the ~L~37~

1 left of the figure as an L shaped feature with the results of the thinning operation on the left. It should be mentioned at this point that these examples being discussed are concerned with the effect of relative positions of thinning windows and whether or not the necessar~ stimulants are present for pel deletion has not been considered.
Reversing the order of the thinning windows as shown in ~igure 22 overcomes the problem associated with this example and the alternate widening and deepening of the thinned area , does not occur.
(~;
An alternative arrangement shown in Figure 23 is to provide consecutive top and right thinning with positive t7ertical offset. Progressi-~e thinning of the nature associated with the arrangement in Figure 21 is always absent. The result is only marginally influenced by reversing the order of the window functions as shown in Figure 24 in that an initial application of top thinning reduces the number of iterations required to complete the sequence.

~igure 25 shows consecutive operations of the right thinner and the top thinner with negative ~ertical offset with respect to the image origin whilst Figure 26 shows the thinner order reversed. The results in this case are similar to those where no offset is used, Il will be realised from the foregoing tha~ si~ilar interactions exist between top and bottom thinners. Thus, when bottom thinning is operated on a preceding image row to top thinning, bottom thinning will alwa~s operate first independent of the order of application. If operated on adjacent rows, top thinning of -a single pel gap will occur in the thinning cycle following the one-in which bottom thinning is active.

~::L37~

1 The line by line progression of thinning which occurs in the sequential operation of the selective thinner, linked ~vith the ability of the left and right thinners to delete pels sequentially on both sides of a gap can generate asymmetrical conditions. When using vertical overlays of horizontal thinning windows which have the same dimensions the stimulus for right thin of a gap left edge is generated from the gap right edge. In this instance for a thin right follo~-ed by thin left sequence, as shown in Figure 27, the ~10 last pel on the gap right edge is always retained. This occurs because of the eventual removal of the left thinning s~imulus by the preceding right thinning operation. This condition is cured by extending the left thinner window so that the stimuius inputs to left thinning are accepted from one column more than for right thinning. The thinning sequence of the same input data as that shown in Figure 27 is repeared in Figure ~8 this time using a left thinner with an extended acceptance window. This condition does not arise with vertical thinning provided horizontal overlap of the vertical thinning windows is absent.

~inimising the window sizes is important for cost economy.-In addition, window dimensions are governed by a number of other considerations. An objective of the design is to inhibit merges on all possible axes within the image. The axes on ~vhich the thinners operate are the horizontal, vertical, the diagonals and many sub-diagonals as described previously. To provide multi-dimensional thinning, the selected thinning windows are mostly symmetrical with respect to their main direction of thinning. As has already been mentioned, it is possible to design the selective thinner to thin from proximity data spaced at any distance from the pel under evaluation. If the thinning distance exceeds that necessary ~37~

1 to eliminate merging then unnecessarily low localised spatial frequencies are introduced. Over correction in this way, reduces the opportunities for merge elimination on other adjacent transitions. Progression is provided within the thinning sequence to enable a minimum of 2-pels to be removed from all but top edges assuming that proximity data provides a suitable stimulus and that surplus pels are available for removal. Inadequate thinning is augmented by the subsequent merge correction stages (to ~e described later~, however thinning is preferable to merge correction as it normall~?y results in less distortion of the projected result.

The repeating ~-pel, ~?-pel projection window structure for 2~0 to 96 pel translation re~uires a 4-pel ?r.inimum gap between adjacent data to guarantee gap retention after projection. For some data to projection window phase relationships, a 2-pel or 3-pel gap is adequate. Increasin~
a gap to greater than 4-pels can result in line spacing after projection which unnecessarily exceeds the minimum requi~ements.

The data sensitive thinner 5 ( igure 1) is shown schematically in Figures 29 and 30. The thinning operations performed on the input image data are: two thin from the right operations, one thin from the left operation ? three thin ~rom below oper~tions and one thin from above operation in that order. The relative positions of the individual thinning windows and their dimensions have been chosen to provide adequate thinning on all the selected thinning axes, diagonals and sub-diagonals. ~lerge correction, u~hich results from incomplete thinning wastes space and causes unnecessary distortion of the resulting image. ~or Ihis reason the 3~

l thinner sequence provides a thinning capability which will norm~lly eliminate the need for merge correction given a suitable pel structure as input.

Pel rows of input image data are numbered in ascending numerical order down the page. Thus, if row Y of image data is currently entering the bottom of the image slice, that is shift register SR1 in Figure 2, then the immediately preceding row Y-1 will already be in shift register SR2, the 0 second row of the slice and so on. It is seen from Figure 29 therefore that the selective thinner operates over eight rows of the image slice and that all seven thin operations are performed on rows Y-2 to Y-5 of the slice.

Similarly, pel columns are numbered in ascending numerical order from left to right across the image page, so that if pel X is currently entering the bot~om of the image slice, then the pel immediately preceding it on Ihe page will be pel X-1 and will alread~ be in the slice at the ne~t pel position iIl that ro-v. It is seen from Figure 30 therefore that the selective thinner requires twenty hori~ontal bits or pels of the input slice in order to operate and that all seven thin operations are performed on colum~s X-2 to X-16 of the slice. The criteria for the selection of the thinning windows and their positions as shown in Figure 29 and 30 is as follows:

(1) two right thin operations and one left thin operation will usuall~ ensure that all vertical gaps are expanded to 4-pels.

(2) the right thin operation precedes the left thin operation by one image slice row to prevent deletion of 2-pel vertical lines.

~L~376~

1 (3) ~he right thinners are asymmetric about the horizontal thinning ~xis to limit the vertical dimension of the image slice and save cost.

(4) Ihe left thinner is ~ider than the right thinners to prevent single pel adhesion to the right edges of processed narrow vertical gaps.

(5~ three bottom thin operations and one top thin operation will usually ensure that all horizontal ga~s are ~- expanded to 4-pels~

(6) the configuration of the bottom thin windows B1 and B2 provide a progression from a previous right thin operation so that a 3 pel vertical gap will be generated from a single pel vertical gap incision by a right thinner, and the configuration of the thin u~indows B2 and B3 provide a similar progression from a left tbin operalion which generated a 3-pel vertical gap from a single pel vertical gap incision by a left thinner.

The circuits of the data sensitive thinner for performing the selective thin operation on image data employ conventional `~ logic. Their ~unction is to test the state of selected shift register sta~es containing the image slice to determiDe whether window conditions for pel deletion are met an~ if so, îor deletion oî the pel. Since the image data is continuously clccked through the shift registers, the tests on the data are performed every pel time. Description of Lhe circuitry of the complete data sensitive thinner would be a laborious and pointless task since each of the seven component thinners is essentially the same as all the others.
Accordingly, only the circuitry of the right thinner Rl will be described in detall from which the structure of the other ~3~6~

l thinners will be quite apparent.

The right thinner Rl is shown in ~igure 31. The windows for the thinner occupy the ~irst five adjacent stages of the first six rows of shift registers SRl to SR6 shown in ~igure 2. For convenience, the individual stages of the shift registers are numbered from right to left according to row and column position. Thus, the extreme right-hand stage of shift register SRl is labelled SRl.l, the next to the left (~ SRl.2 and the ne~t SRl.3. The right-hand stage of shift ~ register SR2 is labelled SR2.1, the next to the left SR2.2 and so on. Using this rotation, stage SR3.4 always contains the pel under investigation by the right thinner Rl.

Circuit details of the thinner and its operation will be given with reference to Figure 13 which shows the five separate window conditions for the right thinner. All five windows require that a right hand edge condition be detected.
This condition requires a black pel in at least one of the Ihree adjacent pel positions in the column to the left of the pel under investigation. These pels are contained in shift register stages SR~.5, SR3.5 and SR~.5, the outputs of ( , which are connected as inputs to OR-gate 20. ~n output signal from OR-gate 20 representing that the edge condition has been detected is supplied as one input to AND-gate 21.

The first window shown in Figure 13a requires that both pels contained in stages SR3.3 and SR4.3 are zero representing a two pel vertical gap to the right of the pel being investigated. Accordingly, these stages are connected as inputs to OR-gate 22 which produces no output only when this gap condition is met. The output from OR-gate 22 is supplied as input to inverter 23 which produces a signal at its output when the gap is detected. The output from inverter 23 is ~3~6~

l supplied to one input of AND-~ate 24. A further condition of the window shown in Figure 13a is that a black pel providing the stimulus for deletion exists in at least one of the four adjacent pel positions to the right of the gap contained in shift register stages SR3.1, SR3.2, SR4.1 and SR4.2, Accordingly these stages are connected as inputs to OR-gate 25. An output signal from OR-gate 25 indicates that a deletion stimulus is present and is gated through AND-gate 24 provided the gap condition is detected by OR-gate 22, A signal from AN~-gate 24 is applied via OR-gate 2~ as one input to AND-gate 21 through which it is gated provided the right-edge condition is detected by OR-gate 20, An output from AND-gate 21 indicates that the window conditions shown in Figure 13a have been satisfied a~d, assuming no connectivity or other constraint is detected by constraint logic 27, the pel under investigation is deleted by re-setting shift register stage SR3.4, Simultaneously, the image data is tested against the conditions of the window shown in Figure 13b. This ~indow requires the gap to be extended vertically by one pel and the stimulus for deletion to be accepted from either of t~o further adjacent pel position in shift register stages ~ SRS,1 and SR5.2, Accordingly, the output of gap detect OR-gate 22 is further connected to one input of OR-gate 28, The other input is supplied from the output of shift register stage SR5.3. No output from OR-gate 28 indicates that the extended gap condition is satisfied. As before, the output of the OR-gate 2~ is inverted by inverter 29 and supplied as one input to AND gate 30. Additionally, the output from OR-gate 25 is further applied as one input to OR-gate 31.
Two further inputs to OR-gate 31 are supplied from shift register stages SR5.1 and SR5.2, An output from OR-gate 31 suppliea to a second inpu~ of AND-gate 30 indicates that a ~3~ 9 l stimulus for deletion has been detected. Provided that the extended gap condition is also satisfied, a signal is passed from AND-gate 30 via OR-gate 26 to AND gate 21 as before. The pel in SR3.4 will be deleted provided the edge condition tested by OR-gate 20 is satisfied.

The window shown in Figure 13c extends the gap by one more pel and accepts stimuli for deletion from two further pels in shift register stages SR6.1 and SR6.2. Thus the 1.0 output of OR-gate 28 is supplied as one input to OR-gate 32 which also has an input supplied from shift register stage SR6.3. The output of OR-gate 32 is inverted by inverter 33 and applied as one input to AND-gate 34. Additionally, the output from OR-gate 31 is applied as one input to OR-gate 35 which has two further inputs supplied from shift register stages SR6.1 and SR6.2 The output of OR-gate 35 is connected as a second input to AND-gate 34. The output from AND-gate 34 is passed via OR-gate 26 to AND-gate 21 and indicates that the gap and stimuli conditions of the window shown in ~igure 13c are satisfied. Coinciden1; detection of a right hand edge by OR-gate 20 causes delet:Lon of the pel in shift register stage SR3.4.
~.
The conditions of the windows shown in Figure 13d a~d Figure 13e are simultaneously tested using identical logic.
Thus for the window in Figure 13d, shift register stages SR3.3 and SR2.3 are connected as inputs to OR-gate 36. The output of OR-gate 36 is inverted by Inverter 37 and supplied as one input to AND-gate 38. Shift register stages SR3.1, SR3.2, SR2.1 and SR2.2 are connected to OR-gate 39, the output of which is supplied as a second input to AND-gate 38.
An output from AND-gate 38, indicating that the gap and stimuli conditions of the window shown in Figure 13d are satisfied, ls gated through OR-gate 26 to AND-gate 21.

L376~

l To test the conditions of the window in Figure 13e, the output of OR-gate 36 is further connected as input to OR-gate 40, which receives a second input from shift register stage SR1.3. ~he output O r OR--gate ~0 is inverted by Inverter 41 and supplied as one input to ~D-gate 42.
Additionally, the output from OR-gate 39 is applied as one input to OR-gate 43 which receives two further inputs from shift register stages SR1.1 and SR1.2. The output from OR-gate 43 is supplied as a second input to AND-gate 42 an output from which, indicating that the gap and stimuli conditions of the window shown in Figure 13e are satisfied, is gated through OR-gate 26 to AND-gate 21.

Tests for connectivity, corner and T-junction constraints are performed within a 3 x 3 matrix of pels having the pel being investigated at its centre. In Figure 31 the matri~
is shown enclosed by a dotted outline 43. The constraint tests, which are applied to each of the seven individual thinners in the selective thinner, have been fully discussed with reference to Figures 14, 15 and 16 which disclose the various logical operations required. Further, the same.
connectivity and T-junctions constraints and a similar corner constraint are disclosed in the aforementioned Patent No.
1 517 869. Accordingly, since the logic circuits required will be immediately apparent to one skilled in the art, they are not individually shown on the already detailed circuit diagram of Figure 31 but are represented by a single block 27 with a dotted line connection from the constraint matrix ~3. As explained previously, detèction of an~ one of the various constræints associated with an investigated pel marked for deletion inhlbits deletion of the pel.

In describing the circuils for del-eting a pel under investigation, it is appropriate to refer briefly to the timing control of the selective thinner. Figure 32 shows ~37~

l a simple timing diagram from which it is seen that four timing pulses Tl, T2, T3 and T4 are generated each pel cycle time. Pulse Tl generated at the start of each pel time is used to clock the image data through the bank of shift registers and to reset a latch 44, the output from which is used to delete a pel under investigation. A
delete signal from the constraint detect block 27 requiring such pel deletion is applied to one input of AND-gate 45 and gated through to the set terminal of latch 44 on occurrence of the T2 timing pulsa. The output from the now SET latch 44 is gated through AND-gate 46 on occurrence of the T4 timing pulse to reset the shift register stage SP~3.4 containing the pel under in~estigation. The image data is clocked on one pel position through the shift registers by the Tl pulse at the start of the ne~t pel cycle, the latch 44 reset, and the process is repeated.

The left thinner includes addit:ional circuits to prevent the problem o~ progressive tliinning as described previously with reference to Figure .l7. Shift register stage SR4.3 contains the pel under investigation by the ' left thinner and this and the relevant portions of the ~- left thinner circuits necessary to prevent progressive thinning are shown i~ Figure 33. The same reference numerals are used in this figure as were used to identify corresponding circuits in Figure 31. The object of additional circuits in Figure 33 is to inhibit pel deletion if the pel previously investigated has already been deleted by the left thinner. Thus the state of each pel in shift register SR4.3 is read into two-level latch 47 at T3 time.
The output of this latch represents the state of the pel currently being investigated and remernbers tnis state after the pel has been deleted at T4 time. The output from latch 47 is inverted by Inverter 48 and applied as a third input to AND-gate 45. It is seen therefore that if the previous pel was a black pel which was deleted, the output from ~376~.~

l latch 47 at T2 time will be 'up' and the output from Inverter 48 will be 'down' so that the current pel in shift register stage SR4.3 will not be deleted. The latch 47 remains in this set condition until the current string of black pels has passed through the shift register stage SR4,3, Progressive thinning can also be a problem with the top thinner as previously explained and additional circuits are required in this case also for its prevention. The shift register stage SR4.17 contains the pel under investigation by the top thinner. The relevant portions of the tOp thinner are shown in Figure 34. In this case, ~he problem is complicated by the need to remember, when considering a pel for deletion, whether or not a pel in the corresponding position of the previous row through the shift register stage SR4.17 was deleted in w.hich case the current pel deletion is inhibited. To do this, a closed loop shift register 49,having as many stages.as there are pels in an image row is connected to the output of shift register stage SR4.17. At time T3 the state of the pel currently under investigation is clocked into the first stage of the shift register over-writing the previous stored state. The first -- stage of the register 49 therefore contains the state of the pel under investigation-be~ore its deletion at time T4. The ' image data and the contents of shift register 49 are cloc~ed each pel time by timing pulses Tl and a delete l.ltch 44' is reset. The output îrom the first stage of shift register 49 is inverted by Inverter 48' and su~plied æs a third input to AND-gate 45'. It is seen therefore that at T2 time the first stage of the register 45 is storing the corresponding pel condition for the previous row. Accordingly, if this was a black pel then AND-gate 45' is not enabled and the current pel in stæge SR4.17 is not deleted. In the event that the corresponding pel in the previous row was not a black pel then ~37~

l AND-gate 45' is enabled, and the stage SR4.17 is deleted at T4 time via latch ~4' and AND-gate 46'.

The scale change projec-tion operation utilises the logical OR of pels within the projection ~indows to determine the resultant image. This method has the advantage of preserving connectivity but the disadvantage of increasing the percentage of black pels in the result with respect to the original image.
The data sensitive thinner described above enables pels which contribute to merge states to be given deletion preference. In areas of high spaciaI frequency the proportion of pels removed by this method will normally ensure that the projected result contains a suitable level of percentage black for acceptable viewing. For lower spatial frequencies the selective thinner is inoperative and the projected result can contain unacceptably thick lines. ~o counteract this effect two phases of. non-selective thinning are used to reduce the percentage of black pels prior to projection. The non-selective thinner 6 (Figure 1) performs tWQ additional thin operations on the image data emerging .- from the data sensitive thinner 5. The opera~ions are ~hin ~- ~rom the right and thin ~rom below, applied in that order.
The logical operator for the non-selective right thinner is shown in Figure 35 and consists of a 4-pel window. The pel under investigation is the pel in position (Xn,Yn) and will be deleted if either of the pels in position Xn-1, Ynll or Xn-l,Yn are black and the pel in position Xn+l,Yn i5 white.
The logical operators for the non-selective bottom thinner is showr. in Figure 36 and consists of a 5-pel window.
Again the pel under investigation is the one in po~ition (Xn,Yn) The conditians for deletion are that one of the pels in positions Xn-1, Yn+1; Xn, Yn+1; Xn+1, Yn+l is black and the pel in position Xn, Yn-1 is whi~e.

~L~37~i~9 1 As with the data sensitive thinner, deletion of a pel is prevented if this would cause a discontinuity in the image. Thus, the same connectivity, T-junction and corner constraints are applied to the non-selective thinner as are applied to the data sensitive thinner. An additional constraint is applied if the pel for deletion is ~ound to be at the end of a l-pel thick line. This cond~tion is tested by determining whether the pel has only one neighbour.
Figure 37a to 37h show logical operators, using a similar rotation to Figures 14 and 16, for determining whether a pel is at the end of a l-pel thic~ line. If it is, removal of the pel is inhibited. The same end of line constraint is disclosed in the aforementioned Patent ~'o.
1 5~7 869.

The non-selective thinner is shown schematically in Figures 38 and 39 as extensions of Figures 29 and 30 respectively. Again the location o~ the two thinning windows are shown in relation to tpe two axes of the image slice; Thus the right thinning operation precedes the bottom thinning operation by two row positions but is operative on the same image slice column.
.
The data sensitive and non-selective thinning operations are followed by a data sensitive merge correc~ion opera~ion.
The main objective of merge correction is the discrete re~
positioning of the remaining pels to minimise residual merge states in the image. The operation of merge correction is such that further thinning may occur where previous thinning operations ha~e left surplus pels. Figure 40 illustrates the operation of the data sensitiYe thinner and merge correction unit on sample data. An original pel input image is shown in Figure 40a. ~he same data after th-e thinning operations ~37~

l have been performed before and after scale charge projection is shown in Figure 40(b). The same data after the merge correction operations have been performed again before and after scale change projection is shown in Figure 40c. In this example merge correction stretches the characters both upwards and downwards into the~ free space which exists between lines. In the horizontal direction the strokes and gaps are subject to local repositioning within the available space to avoid merges both within and between characters.
~Ierge correction is performed about the horizontal and vertical axes. For simplicity the following description of merge correction principles are based on horizontal merge correction. Merging can occur when the inter-pel gaps after thinning and prior to scale change projection is two or three pels and the data phasing is unfavourable. ~lerging will always occur with gaps of only one pel, and accordi.ngly merge correction is designed to correct for the two and three peI
gaps, where data phasing may initiate a merge.

The projection window to data relationships for the cases where merge correction is applied are shown in Figure 41, The projection window boundaries are shown as relatively hea~y lines. In general thers ære two opportunities to correct a merge, the left edge of the gap boundary can be moved further to the left or alternatively the right edge can be moved further to the right. Both options are provided by merge correction. For the two pel gap shown in Figure 41a the choice of moves is complicated by the asymmetry of the gap within the window boundaries in that the primary correction option requires only a single position pel move-ment but the secondary oplion re~uires movement of a pel by two positions. Fo-r 3-pel gaps as shown in Figure 4~b this primary/secondary choice does not e~ist becau-se correction can be achieved ~y a single position movement of either pel.

~37~

1 In general the movements made are not simply determined by the choice of primary or secondary corrections but by examination of data in the proximity of the proposed move.
Where correction of a merge would introduce an alternative merge, the pel movement is normally inhibited. The operation of merge correction is a function of the data surrounding the merge and the progress.ion by which merges are detected and corrected. Accept conditions are generated for both primary and secondary correction. Although the injudicious use of secondary correction cannot directly alter pel structure of the projected result, it can limit alternative correction options. Por this reason when primary correction will not subsequently occur as the result of the secondary correction, the secondary move is inhibited.

The correction stimulus conditions for merge correction are similar to those used for selective thinning apart from the addition of projection window boundary gating. This gating introduces row and column selection of the pels which contribute to the correction stimulus. The rows and columns selected are those which ara in the projection windows which are adjacent on the correction axis or diagonals to the one containing the pel under consideration.

Figure 42 illustrates the correction stimuli for the two possible horizontal projection window alignments for the pel (Xn,Yn) under consideration for a primary move across the window boundary between column Xn and Xn-1. The two alternati~e positions of the window boundaries depending on whether the pel XnYn is in a ~-pel or 3-pel wide window are shown as hea~y dotted lines. As with the thinning windows, the stimuli for a primary pel move are taken from pels in horizonlal, diagonal and sub-diagonal positions in lL~3~6~9~
- 36 ~
1 the adjacent horizontal and two diagonal window positions.
The window con-ditions for a primary move require that all pels in locations where the cross-hatching is downward from left to right should be ZE~O, that is, a 2-pel wide gap must always be present between the pel to be moved and its stimulus. Further, the logical OR of the pels in locations where cross-hatching is upward from left to right should be ONE. The minimum 2-pel gap is required when the pel to be moved is contained in a 2-pel or a 3-pel wide window;
lU
Figure 42 shows all eight possible window configurations of acceptable stimuli for horizontal primary movement of a pel. The window configuration d)-is not used with the pel in the position XnYn shown because of the window boundary phasing. Clearly, this configuration is required for a pel in position (~n,Xn-1) but in this case configuration h) is redundant.

Figure 43 shows the window outlines for stimulating horizontal primary moves to the left O:e pels in the five possible pel positions adjacent a vertical boundary. Thus, the window condition a) is the sum of the eight windows shown in Figure 42. In each case, the dotted cross-hatching shows ~ those portions oi the window outlines excluded by the window gating. The gating circuits and their opsration will be described later.

The acceptance conditions generated for merge correction can either prevent alternative merges occurring or, as will be shown later, allow them under controlled conditions. ~he window conditions for detecting alternative merge states resulting from pel movement are shown in ~igure 44. A ONE
in any of the pel positions in the three projection windows (one horizontal and two diagonal) adjacent the window into which it is proposed to move the pel under consideration, is used ~l3~

1 to inhibit the pel movement. The five window conditions a) to e) shown in Figure 4~ are the pel move inhibit conditions associated with the stimuli conditions a) to e) for correspondingly positioned pels in Figure ~3. The alternative position of the 2-pel and 3-pel boundaries are shoun as before as heavy dotted lines. The interleaved cross-hatching shows the e~tent of the inhibit conditions for the two alternative boundary conditions. ~election of the appropriate pels to test these conditions is controlled by boundary gating circuits to be described later.

Each pel under consideration is further tested to determine whether or not merge conditions would be improved by OR-ing it with an existing O~ pel in an adjacent position on the other side of a window boundary. Only three pels are considered as shown in the window configuration of Figure 45.
The window conditions require that a pel in position (XnYn) be moved across the adjacent bo,undary, provided a stimulus for movement is present, if the pel in position (Xn,Yn+1) is ZERO
and either of the two adjacent pels (Xn~l,Yn) or (Xn-1, Yn+1) across the ~oundary are ONE. The existence of an adjacent ON-pel on the thinning axis indicates the acceptability of ,--- furth~r thinning by 'OR'-ing the pels without alternative - merge generation. The existence of the diagonally adjacent pel in the previous row is used to indicate the acceptability of further 'OR'-ing. Examination of these pels, while excluding consideration of the projection structure perpendicular to the correction axis, provides the basis for a practical system. The function tends to preserve the entity structure even when the entities are individually illegible and thus it also localises degradation. It does not guard against alternative merge states but the characteristics of the merge correction connectivity logic when used in combination with this 'OR'-ing condition tends ~o control the type of merges which occur. The result is that merges moslly occur u~ithin ~3~37~l9 1 ~ character or object and the separation of the characters or objects is preserved.

The window shown in Figure 45 effectively provides additional thinning of surplus pels which otherwise would be a direct cause of merging. Insufficient thinning by previous operations may result when the input stro~es to the thinners are not of adequate and even thickness and are spaced by only l-pel. The previous thinner stages do not ~,10 always remove an adequate number of pels to prevent merging after projection, Further, the pel removal criteria used by , the thinners are independent of the relationship between the image data and the projection window structure which overlaps it. It is therefore quite usual to encounter thinned lines which unnecessarily straddle projection boundaries. These lines can contain redundant pels which when projecte~ result in double pel strokes at the target resolution. The move conditions detected by the window shown in Figure 45 override any move inhibit conditions which may''already exist.

,~erge correction is inhibited where it would introduce a change in the connectivity of the image line structure.
"~~ The connection structure is measured J as described previously with respect to selective thinning, by examination of the contents of 3 x 3 windows surrounding the pel under consideration.
Two simple tests are performed on the image data in order to prevent discontinuities being formed by merge correction, The first test involves testin~ the contents of the

3 x 3 windows surrounding both the existing and proposed pel positions. If it is foun,d that the move results in less connections than before, it is inhibited. The test is explained with reference to Figure 46. In Figure 46a) the pel under investigation is the centre pel of the 3 x 3 matrix of pels shown in dotted outline and forms a link ~ ~376~

1 between two horizontal blac~ features. In this case, the proposed move is to the right as indicated by the arrow associated with the pel. Applying the previousl~ described connectivity test to this pel shows that it performs two connec~ion functions with its neighbours. Figure 46b) shows the situation after the move with a clear discontinuity formed. The connectivity test applied to the new pel position now shows that only one connection function is performed and the pel is reset in its original position.

Figure 46c) shows the same image data but with proposed move do~nwards into the position shown in Figure 46d). In this case connectivity is not broken, the connecti~rity test prodllces the same count of connection functions both before and after the move and accordingly the move is permitted.
It will be observed that although each individual test is performed on a 3 x 3 matrix, it must be repeated each time with the pel in its new position. Accordingly, the actual window size required by each merge correct unit ~that is correct to the right, left, down or up) i~ order to accommodate the two overlaid ~indows is a 3 x 4 matrix~

This test can fail under certæin circumstances. For example, inspection of the image data in Figure 47a) shows that there are two connection functions performed by the pel under investigation. The situation after a downward merge correction move is shown in Figure 47b) from which it is seen that the pel still performs two connection functions.
Thus it meets the conditions of the first test which would not preven~ the move and ~?et a clear discontinuity has resulted.

The second test to detect this type of situation is performed b~ inspecting the surrounding pels for a further set of ~indow conditions. These conditions to lnhibit a vertlcal pel movement are shown in Figure 48. Thus, the ~376~

- 4~ -1 central pel will not be moved if any one of the three pels in ro~v Yn+1 is a ONE, and any one of the three pels in row Yn-1 is also a ONE, and the two adjacent pels in row Yn are both ZERO. Under these circumstances the proposed pel movement in ~igure 47 would be inhibited.

This completes the description of the function of a merge correction unit for a primary pel movement. There are, as will have been appreciated, four such units, one lo for each of the four possible directions of merge correction.
C Each unit has identical stimuli windows and inhibit con-s~raints as described with reference to the left move merge correction unit described in detail above. Thus, apart from being rotated with respect to the image slice, to operate in the required direction, they are all identical to each other.

In addition to the four merge correction units for primary pel movement, there are two merge correction units for secondary pel movement. These operate in downward and rightward directions respectively. The stimuli conditions for a downwar~ secondary pel movement a~e show~ in Figure C~ 49. The pels are shown in the five possible positions a) to e) spaced one pel gap from a horizontal boundary. It will be understood that each of the window outlines a) to e) are formed from a number of sub-windows as for the primary windows used to detect stimuli conditions from axial, diagonal and sub-diagonal pels. The dotted cross-hatching shows those portions OI the window outlines made redundant by the phasing of the vertical windows. The acceptance condition for secondary merge correction of a pel is as shown in Figure 50. The accept conditions are those for a pel in the position shown in ~igure 49(a) from which all remaining accept windows will be obvious. It is seen that the requirement for a three pel gap between t~e pel to be moved and the next black feature ensures that a secondary 1~37Çi~L~
., 1 move cannot take place unless the subsequent primary move across the boundary is also permitted. Pels selected for secondary mOVemellt are subjected to the same inhibits and constraints as are pels selected for primary movement.

The data sensitive merge inhibit unit (7) is shown schematically in Figures 51 and 52 as extensions of Figures 29 and 30 respectively, The number and size of the windows of the merge inhibit unit (7) are such that it 10~,- is more convenient to sho~ Figure 51 split into two separate o~erlapping figures, labelled ~igure 51A and ~igure 51B respectively, and Figure 52 into two separate overlapping figures labelled Figure 52A and Figure 52B
respecti~el~. As before, the locations of the ~arious merge correction windows, which together form the complete merge ; inhibit unit (7~, are shown in relation to the two axes of the image slice. The merge correction operations performed by the merge inhibit unit (7) are.: primary correct upwards, secon~ary correct downwards, primary correct dounwards, primary correct leftwards, secondary correct rightwards and primary correct rightwards. These correction moves aimed at preventing data merging o~ projection are applied in the order given above and shown in the two fi~ures.

From this it will be seen that, as the image data passes through the unit ~7), merge correction is effectively applied progressively line by line from the top of the image and ~ilhin each line fro~ left to right. The unit operates incrementally and each pel move is used as an input condition for the next prospective movement. Thus the area of Ihe image:which has been fully thinned ~nd merge corrected lies above or to the left of the current position of the merge correction windows with respect to thinning data~ The first correction operation on each a~is ~3~6~

1 attemp~s to utilise space in the already corrected parts of the image. Thus the first correction operation on the horizontal and vertical axes are left and up respectively.
Merge correction as implemented is asymmetrical in that secondary correction always attempts to resolve merges in areas of the image not yet subjected to correction. The purpose of secondary correction is, it will be recalled, to move a pel having a suitable stimulus into a position from where it can subsequently be moved across a boundary by a primary correction operation.

The sequence of vertical followed by horizontal correction allows the results of vertical correction to be used as input to those horizontal correction moves which can be performed in the-current or a subsequent image slice. As shown in Figure 51 and 52, all primary correction options have been implemented. Secondary correction is applied one row ~head of horizontal primary correction and one column ahead vertical primar~ correction so that iclentified pels are positioned by secondary correction for merge elimination by the primary correction. Although two secondary correctio~
options e~ist on each axis, only one is utilised in each - case, namely, secondary correct downwards and secondary - correct rightwards. The selected secondary correction moves are related to the method of correction and move pels towards the region of the image as yet uncorrected.

A minimum vertical dimension for the scale charge module is desirable in order to reduce cost. Window overlap can result in the incomplete operation of one window generating false conditions for a subsequent function. For example~ an overlap of opposing correction windows could result in two correction operations occurring where, with an adequate operating delay, one operation would suffice.
Complete window separalion is therefore desirable. The ~376~9 _ 43 -l horizontal separation of the up and down page correction windows has a small cost impact. However, vertical separation of the horizontal correction windows is more costly and accordingly some economies have been made in this design in the window dimensions. Progression in the correction sequence is desirable when it allows an edge pel which has been revealed b~ one correction stage to be corrected by a later stage. ~he present vertical correction window alignment preclude~s the upward correction of a pel revealed by a right correction and the leftward correction of a pel revealed by a down~ard correction. Inccmplete -thinning can generate transient gaps which merge correction will atte~pt to resolve. Adequate vertical spacing between - the thinners and merge correction together with reduced correction window dimensions are the practical solution to this problem. Accordingly, all thinning on rows included within the vertical ~erge correction window is compleled prior to-vertical merge correction.

~ertical merge correction introduces a progressive down page correction possibility which is inhibited in the implementation described. Iterative merge correction arises where the correction sequence brings the moved pel ; into 'range' for a second correction from its modified position. Iterative correction is prevented by remembering down page primary correction operations in a correction inhibit register (to be described later), the contents of which inhibits down page secondary correction in column positions where it is set to O~E representing the previous primary correction.

It is seen from Figure 51 that the merge inhibit unit (7) requires fourteen horizontal bits or pels of the input slice in order to operate. All six merge inhibit operations UK9-7~-019 - 1~37~i~Lgl - ~4 -l are per~ormed over twelve row~ of the image slice although the actual pel movements are confined to rows X-7 to X-10 of the slice. Thus the entir~ consolidation unit operates on an image slice fourteen rows deep with each row having forty-six pels or bits.

The circuits of the data sensitive merge inhibit unit employ simple logic. Much of the logic is repetitive and, as with the thinners, description of the complete unit is unnecessary. Accordingly, circuitry of the primary correct C`` downward merge correction unit will be described in sufficient detail for its construction and operation to be understood from which the structure o~ the entire merge - inhibit unit (7) will be quite apparent.

The correct down primary window cireuits are shown in ~igure 53. As before in the description of the selective thinners, the shift register stæges included in the window structures are numbered from right to left according to row a~d column position. Reference to Figures 51 and 52 shows that the pel under investigation for merge correction movement is the pel occupying shift register stage SR10.34 in shift register row Y-9 and column ~-33. During the ,....
following description of the merge inhibit unit, referenee should be made to Figure 43 which shows the various window outlines for stimulating primary pel movement and Figure 44 which shows the conditions which deteet alternative merge states and inhibit pel movement.

Although seale-ehange projection of the image slice does not oecur until after the completion of thinning and merge eorrection, the positions of the seale ehange window boundaries with respeet to image data must-be known in order to seleet the appropriate merge correction windows. The ~37~

- 45 - `
1 projection windows used in this embodiment of the invention are superimposed on the image data with the phasing as shown in Figures 3,4 and 5. That is, the top left-hand pel of the page of image data to be projected to the lower resolution is in the top left-hand corner of a 2 x 2 projection uindow. The relative positions of the scale change boundaries do not change with respect to the image data and may be thought of as accompanying the image data through the shift registers. Thus, a 2-pel vindow boundary may be considered to exist between the second or third pel as it enters the first stage SR1-1 of the shift registers, a 3-pel window boundary between the fifth and sixth pel~
the next 2-pel boundary between the seventh and eighth pel, and so on. The same applies in the vertical direction.
Thus, the first 2-pel boundary lies between the second and third row of pels, the first 3-pel boundary between the fifth and sixth rows, the second 2-pel boundary between the seventh and eighth row of pels, and so on.

The merge correction circuits for a downward pel move-ment are shown for convenience as two parts which together form Figure 53. The logical circuits ~or detecting stimuli conditions for pel movement are shown in Figure 53A and those for detecting inhibit conditions in Figure 53B. For convenience, the row of pels including the pel under investigation is only shown in Figure 53A. The logical windows for detecting stimuli for a downward are as described previously for a left move in Figure 43 but rotated through ninety degrees, The logical windows for detecting inhibit conditions are as described with reference to Figure 44 also rotated through ninety degrees.

Figure ~3 shows the section of shift register stages which are required by the downward merge correction logic.
The ~el under investigation is contained in shift register ~37~

l stage SR10-34 and as mentioned, is shown for convenience in both parts of ~i~ure 53. The output from a shift register stage is positive when a black pel is stored and negative when a white pel is stored.

The basic window configuration for a stimulus requires that a 2 ~ 2 pel gap is present above and to the left or right of the pel under investigation. Thus considering first of all the left half of the circuits, shift register l~ stages SR11-34~ SR11-35, SR12-34 and SR12-35 are connected to negatlve inverting AND (-AI) gate 51 (negative inputs produce a negative output) which has a negative output when the required gap is present. The stimuli conditions further , require at least one black pel to be present in the four pel posi~ions occupying stages SR13-34, SR13-35, SR14 34 and SR14-35. Accordingly these stages are connected to negative OR (-OR) gate 52 (positive inputs produce a nega-tive output~ which has a negative output if the stimuli is preset.
The outputs of (-AI) gate 51 and (-OR~ gate 52 are connected to negative AND (-A) gate 53 (negative inputs produce a positive output) which produces a positive output when the basic stimuli window conditions are satisfied.

( Thls basic window is extended to include pels in the next column to the left and the extended window tested simultaneously. Thus the gap conditions are tested by connecting the outputs from stages SR11-36 and SR12-36 together with the output from (-AI) gate 51 to (-AI) gate 54. A negative output from (-AI) gate 54 indicates that the gap is present. The stimuli conditions are tes~ed by connecting stages SR13-36 ænd SR14-36 to (-OR) gate 55. A
negative output from (-OR) gate 55 ~ndicate~ that the stimulus is present. The outputs from (:AI) gate 54 and (-OR) gate 55 are connected to (-A) gate 56 which provides ~3L3~6~L.'3 1 - ~, ' .

1 a positive output when the first e~tended window conditions are satisfied. Whether or not the windows are extended further to the left to include pels in the third and fourth columr,s depends upon the phase of the proJection windows with respect to the image data as has already been explained.
The selection of these two extended windows is controlled by window gating signals, the derivation of which will be described later. At this time it is sufficient to note that the window is extended to three columns to the left by 10 connecting stages SR11-37 and SR12-37 together with the output from (-AI) gate 54 as inputs to (-AI) gate 57 and stages SR13-37 and SR14-37 as inputs to (-OR) gate 5~. The outputs from (-AI) gate 57 and (-OR) gate 58 are connected as inputs tO positive AND (-A) gate 59. A gating signal for selection of this window is obtained from the last stage of gating register GR1 which is also connected as an input to (-A) gate 59. A positive OUtpllt from (-A) gate 59 indicates that the window conditions for the pels three columns to the left of the investigated pel are satisfied.
Extension of the window to its max:imum dimensions to include pels four columns away is also under control of gating signals. As before stages SR11-38 and SR12-38 together with the output irom (~AI) gate ~7 are connected as inputs to (-AI) gate 60 and stages SR13~38 and SR14--38 are connected as inputs to (-OR) gate 61. The outputs from these latter two gates are connected as inputs to (-~) gate 62 which also receive gating signals from the last stage of gating shift register GR2. A positive output from (+A) gate 62 indicates that the window conditions for the pels four columns to the left of the investigated pel are satisfied. The three left hand window outputs from (-A) ~L~L3~6~

1 gate 53, (-A) gate 56, (-A) gate 59 and ( A) gate 62 are connected to negative inverting OR (-ORI) gate 63 (positive inputs produce a positive output) a positive output from which indicates that a left hand window stimulus condition has been detected. The output from (-ORI) gate 63 is applied as one input to positive AND (~A) gate 64 (positive inputs give a negative output).

Identical circuits detect right hand stimuli conditions and since the function of each block is identified in the figure, a detailed description of the operation of the logic will not be given. As for the left hand windows, gating signals are required to extend the windows to include the las~ tWO columns of pels dependent upon projection window phasing. Thus, a gating signal from gating shift register I GR3 is supplied to (-A) gate 65 to control the selection of ! the window extended to include pels three columns to the right of ~he investigated pel and a gating signal from gating shift register GR4 is supplied to (-A) gate 66 to control the selection of the window extended to its maximum dimension to include pels four columns to the right, A
positive output ~rom (-ORI) ga-ce 67 indicates that a right-hand window stimulus condition has been detected. The out-put from (-ORI) gate 67 is applied as another i~put to (+A) gate 64, Each gating shift register GRl-4 is connected as a closed , loop and contains a predetermined pattern of binary ONE bits.
¦ The pat~erns are clocked one stage around the registers each pel time. A gating signal is derived from the last stage of each register whenever a binary ONE is present in that stage. The gating signals from the gating registers are supplied as negative signals to suit the window logic requirements.

~3~6~9 ~9 1 All four gating registers are set with their respective patterns each time the first pel of a new row of image data enters shift register stage SR3-4, that is, the stage containi~g the first investigated pel of the image slice.
In order to determine the required gating register patterns, the relative position of the pel under consideration, in this case for downward merge correction, in shift register stage SR10-34 with respect to the projection window bound-aries needs to be known. The current investigated pel in stage SR10-34 is horizontally displaced from the first - investigated pel in stage SR3-4 by thirty pels. Accordingly, the phase of the current pel with respect to the projection window boundaries is the same as the phase of the first investigated pel. Since the first pel of the image data is located to the left of a 2~pel projection window, all gating registers are set with a pattern reflecting this condition. The set patterns for all horizontal gating registers and two vertical gating registers to be described later are shown in Figure 54. The"projection window boundaries are shown at the top of the figure.

Gating L egister GP.1 provides gating pulses for the ,- selection of the pel window ex~ended three columns to the left. ~rom ~igure 43 it is seen that this window is always required except when the pel under investigation is in the right hand pel position of a 3-pel projection window. The set pattern for register GR1 is therefore 1 1 0 1 1. The pel uindow extended four columns to the left is only required when the investigated pel is in the right hand pel position of a 2-pel or 3-pel projection window. The set pattern for register GR2 is therefore 0 1 0 0 1. Similarly, the reset pattern for register GR3 selecting the pel window extended three columns to the right is 1 1 1 1 0 and that for register GR4 selecting the window extended four columns to ~L~376~ ~

l the right is 1 0 1 0 0, The inhibit logic shown in ~igure 53B operates in much the same manner as the above described stimuli logic.
Reference to Figure 44 shows that a black pel in any one of the positions occupying shift register stages SR6-32 to SR6-36 inclusive or SR5-32 to SR5-36 inclusive is an inhibit to merge correction of the pel under investigation.
Accordingly, the outputs from these ten stages are connected as inputs to (-OR) gate 68 a negative output from which r~.
indicates the existence of an inhibit condition.

The inhibit windows are symmetrical about the investigated pel and, as with the stimuli logic, only the left-hand window logic vill be described. Selection of extended inhibit windows to include pels three and four columns to the left of the investigated pel is performed by gating signals derived from the gating shift registers GR1-GR4. For convenience, these regi~ters are shown as separate registers in ~igure 53B. Thus, for the first extended window, stages SR5-37 and SR6-37 are connected ta (-OR) gate 69, the output from which is connected as one r~ input ~o (-AI) gate 70. Negative gating signals are supplied to a second input of (-AI) gate 70 from the last stage of gating register GR1. A negative output from (-AI) gate i0 indicates that the extended window conditions are satisfied.

The inhibit window is further extended to include pels four columns to the left of the investigated pel by connect-ing stages SR5-38 and SR6-38 to (~OR) gate 71, the output of which is connected as one input to (-AI) gate 72.
Negative gating signals are supplied to a second input of (-AI) gate 72 from the last stage of gating register GR2.
A negative output from (-AI) gate 72 indicates that the ~37~9 1 extended window inhibit conditions are satisfied. The logic for the corresponding right hand extended window selectio~
is identical and will not be described.

From ~igure 44 and the related description, it will be seen that the inhibit conditions are extended to pels in the row (Y-6) dependent on vertical projection window phasing.
Specifically the row is included when it is located in the top of a 3-pel projection window. Vertical window gating signals are generated by gating shift register GR5. Thus, ~- stages SR7-32 to SR7-36 inclusive are connected as inputs to (-OR) gate 73, the output from which is supplied as one input to (-AI) gate 74. Negative gating signals from gating register GR5 are supplied as a second input to (-~.I) gate 74.
A negative output from this gate indicates that æn inhibit condition exists in the extended row of the basic inhibit window. The window is extended one pel to the left under control of gating signals from gating registers GR1 and GR5 supplied as inputs to (-AI) gate 75 The output from stage SR7-37 is inverted and applied as a third input to this latter gate. A negative output from (-AI) gate 75 indicates that the pel in stage SR7-37 is an inhibit to merge correction. The window is ~urther extended to include the next pel to the left under control of gating signals from gating shift registers GR2 and GR5 supplied as inputs to (-,~I) gate 76. The output from stage SR7-38 is inverted and supplied as a third input ~o this latter gate. A
negative output from (~.4I) gate 76 indicates that the pel in stage SR7-38 is an inhibit to merge correction, The gating signals from gating shift register GR5 are provided by a binary pattern which is continuously clocked ~L~3'~6~5~

1 ~round the register loop once every scan row time, instead of once every pel time as required for horizontal gating.
~rom Figures 29 and 51A, it can be seen that when row (Y-2) contains pels in the top of a 2-pel window, then row (Y-6) is in the bottom of a 2-pel window. Gating of this row of pels is only required when it is the top of a 3-pel window.
Accordingly, the binary pattern set in gating register GR5 - ~hen the first row of the image data eneters row (Y-2) is O 1 0 0 O. This pattern is shown in relation to the projection window boundaries in Figure 54.

The outputs from the various window stages described above are taken to a common connection since any one can be an inhibit to merge correction. Thus the outputs from (-OR) gate 68, (-AI) gates 70,72,74,75,76 and corresponding (-AI) gates from the right-hand window extensions are dot OR-ed and supplied as one input to OR gate 77 (negative inputs give a positive output). Thus a negative input to this gate represents the absence of inhibit conditions.

The window conditions described with reference to r~ Figure 45 which over-ride the merge inhibits are also ~ tested for. Accordingly, shift register stages SR9-34 and SR9-35 are connected as inputs to negative inverting OR
(-ORI) gate 78 (positive inputs give a positive output).
A positive output from this gate indicates the presence of a black pel in, or immediately preceding, the pel position to which the pel under investigation may be moved. The output from (-ORI) gate 78 is supplied as input to (+A) gate 79. The output from shift register stage SR10-35 is inverted and applied as second input to (+A) gate 79. A
negative output from (+A) gate 79 indicates t4at the gap ~3~

1 ~nd stimulus conditions which take precedence over merge inhibit conditions are present. The output from (~A~ gate 79 is therefore supplied as a second input to OR gate 77.
The output from OR gate 77 is applied as a further input to (+A) gate 64.

Connectivity tests as described ~rith reference to Figures 46,47 and 48 are performed on the pel under investiga~ion before a merge correction movement is 10, permitted. One test, described with reference to ~igure 46, involves comparing the connecti~ity counts for the ~el pattern in a 3 x 3 matrix around the investigated pel in its original position with the connectivity count for the new pattern in a 3 x 3 matrix around the proposed pel position.
: .
The circuits for performing the test are shown in Figure 55. The upper portion of the figure shows the window for a pel under consideration in its original position in shift register stage SR10-34. The lower portion of the figure shows the window for the proposed position of the pel in shift register stage SR9-34.

The individual state of each of the ei~ht stages surrounding pel SR10-34 is entered into a corresponding location of a 9-stage cornectivity shift register 80. The state of one stage, in tnis case SR10~33, is additionally entered into the ninth stage of the register 80. The connectivity of the pel under investigation is ascertained by counting the number of white to black transitions which occur around the central pel. This is achieved by shifting the contents of the connectivity register eight times to the right and noting the contents of the two right-most stages. Each 0 1 pattern occurring in these stages indicates a uhi~e to ~lack transition and is counted by counter 81, ,, ~3t76~

- 5~ -lThe individual states of each of the eight stages surrounding pel SR9-34 is similarly entered into shift regis~er 82. Since after merge correction, the contents of scage SR10-34 is always zero this condition is reflected by not makillg a correction from this stage to the corresponding stage in connectivity register 82. Stage SR9-33 is additionally connected to the ninth stage o~ register 82.
The contents of register ~2 are shifted eight times to the right and the occurrence of the pattern 0 1 in the two lOright-most stages detected and counted in counter 83. The contents of the two counters 81 and 83 are compared in comparator 84 which produces a positive output when the accumulated total in counter 81 is equal to or less than the total in counter 83. The second connectivity test is also performed on a 3 x 3 matrix surrounding ~he investigated pel. The logic requirements for merge inhibit are described with reference to Figure 4~. The logic circuits for perfor~ing this simple test is not described but is assumed to produce a positive output.when merge correction does not destroy connectivity. The co~bined output from logic circuits performing this latter test and the output from comparator 84 (Figure 55) are applied as another input !on terminal 85 to (+A) gate 6~.

Primary downward mePge correction is only performed ~hen the pel under investigation is situated immediately above a projection window boundary. Thus (+A) gate 64 is connected to gating register GR6 which provides projection window boundary gating signals at àppropriate ~imes. The binary pattern in this case initially set in register GR6 and clocked around its closed loop once e~ery scan row time is 0 1 0 1 0. This pattern is shown in Figure 54 and 'UK9-78-019 ~3'~6~91 1 can be readily established by considering the relative ertical position of the downw rd merge correction unit with respect to the image slice. A negative output from (+A) gate 64 is ~he merge correction accept signal for the down merge correction unit. The signal is used direct to reset s~age SP.10-34 containing the pel under investigation and after inversion to set the stage SR9-34, or maintain it in, a ONE
state.

All other primary merge correction and secondar~ merge --- correction units forming the complete data sensitive merge inhibit unit (7) are implemented in the same way as described above. All require stimuli conditions for a move, all are tested for merge inhibit and merge inhibit over-ride conditions, and all are tested for connectivi-ty constraints, ~rom the foregoing description of the down merge correction unit, the corresponding logic circuit requirements for the remaining primary correc-tion units and the two secondary correction units will be clearly ap~arent and further description of these units will not be given.

The secondary downward merge correction unit is provided with additional circuitry to inhibit the progressive downward movement of a pel which otherwise could occur due to the correction sequence order of secondary correction before primar~ correction. The circuitry is sho-~n in Figure 56 and ~ill now be described.

Shift register 85 has the same number of stages as the image slice registers already described. Each time a pel under investigation is moved by primary downward merge correclion, the first stage of the register is set to a 1 state. The signal to set the stage is-derived from (+A) gate 86 which produces a negative output in response to positive ~37~

l signals on its three inputs, indicating that an ON pel is in the s~age SR10-34; a stimulus for pel movement exists from (-OR) gate 63, and a boundary timing pulse from GR6 is present. The output from (+A) gate 86 is connected as one input to OR gate 87, a positive output from which is used to set the first stage of the register 85, The stored 1-state is clocked through the register 84 ever~- pel time and therefore reaches the last stage of the register when the associated pel originally in shift C register stage SR10-34 has reached stage SR11-3~3 where it is considered for secondary downward merge correction. A
'1' state in this last stage is used to generate a secondary correction inhibit signal which is supplied to the secondary downward correction unit. Progressive downward merge correction is thereby prevented.

As an additional safeguard, the output of the first stage of register 85 is used to set,a latch 88 to a corresponding state thereby 'remembering' the 1-state during the next pel time. The output from latch 88 is supplied as one input to (~A) gate 89. Boundary timi~g pulses together with a sig~al representing the state of the ~- new pel in stage SR10-34 are supplied as two further inputs to (+A) gate 89, The output of (+4) gate 89 is connected as second input to (OR) gate 89. In the event that this next pel is also ON, the first stage of the shift register 85 is again set to a '1' state even though a stimulus for merge correction may not be present for this pel, Thus ~a stream of 'l's are propagated through shii't register 84 corresponding in number to the pels forming a continuous horizonlal black feature in the input image. Similarly, the last stage of register 85 is connected as input tO the first stage so that the inhibit condition is maintained for 37~
- ~7 -1 corresponding ON pels in the next row of the slice.

The pels emerging from the data sensitive merge inhibit unit (7) are applied froml shift register stage SR15-43 to ~he scale change projector (8) shown in Figure 57. The scale change projector consists of a shift register 90 u~hich is clocked on one stage by window boundary signals derived from gating register GR7. Consideration of the horizontal phasing of the image data in shift register stage 15-43 sh~ws that the binary pattern initially set in register GR7 at the '. start of an image page scan and clocked each pel time is 1 0 1 0 0. Each time a 1 appears at the output of register GR7, shift register 87 is clocked on one stage. Thus the serial by bit pel stream obtained from stage SR15-43 and applied to the input stage of shift register 90 via OR ga~e 91 is OR-ed alternat.ely within the first stage as 2-pel and 3-pel combinations thus providing the desired scale ch~nge in a horizontal .direction.

Similarly, scale change projection in the vertical direction is under control of a further gating register GR8 which controls the alternate 2-row and 3-ro-~ OR combi~atio~s.
-. Of p~ls within the shift register 90. Thus, a 'O' at the - output of gating register GR8, is inverted and applied as input to AND ~ate 92. The output from shift register 90 is applied as second input to AND gate 92 and is transmitted therethrough to a second input of OR gate 91 whenever AND
gate 92 is enabled by the presence-of a '0' at the output o~ register GR8. The recirculated row of pels which have `:
already been scale charge projected in the horizon-tal direction are synchronously combined with the next row of input data as it is correspondingly scal~e charge projected ~376~g ~ 58 -1 through the register. The shift register row is supplied as output via A~D gate 93 whenever a 1 is present at the output of gating register GR8. Consideration of the vertical phasing of the image dala in shift register stage SR15-43 shows that the binary pattern initially set in register GR8 and clocked one position each row line is 0 1 0 0 1. The serial bit output at terminal 94 represents the input image at the new lower resolution of 96 pels per inch.

- The description of the data consolidation apparatus ~ above has assumed throughout that the input image data is free from unwanted Inoise' in the form of single pels usually present on low quality print. The retention of all the inpul data includin~ this 'noise' whilst re-organising its quantised structure increases the undesirable effect of input noise. Further, distortions of valid data often occur to allow space for the noise pels which are in fact unwanted.
The desirability of noise rejection depends largely on the quality of the scanned image. However, with a noisy input image, an improvement in the final consolidated output is produced if initially all single pels are removed from the input image. This can be easily achieved by investigating each pel position as it passes through the centre of a 3 x 3 window and deleting all pels which are completely surrounded by ZERO.

The data consolidation apparatus described allows a real time transformation of black/white li~e images (graphics, characters and handwriting) directly from the threshold output of a scanner. The highly repetitive nature of the logical requirements of the apparatus makes it particularly suitable for implementatio~ in LSI. Although intended for direct operation from scanner data, the ~ ~3~619 l apparatus can also be used to consolidate a processor data stream.

The design of the apparatus is rotatable in adapting the rate of selective thinning and merge correction to the level of partial congestion in the input image. The scale charge projection window structure is effective in merge elimination although a number of residual failure conditions remain where input pel structures cannot be retained even though adequate space exists. Over-correction is mostly absent and therefore the efficiency with which the module utilises the projection space is ~ood. Distortion introduced by scale charge projection is least where the input image stroke widths are leæst. The merge correction facility operates with reference to the projection window structure. This technique tends to formalise the line s2ructure of the image to conform to the line structure of the projectiorl grid particularly in areas of high spatial ~requency. The visual eff~ct of this is normally an enhancement in line regularity.

The design OI the consolidation apparatus described is for conversion of input data scanned at a relatively high resoiution of 240 pels/inch to be displayed at ~he low resolu~ion of 96 pels/inch. ~his relatively complex ratio (~:2) for the transformation has been selected for the preferred description because of its comprehe~sive nature. Clearly the logic requirements for consolidation apparatus for effecti~g a simple ratio (2:1) scale charge transformation would be less complex since the window struclures would be more simple. For example~ seco~dary merge correction could be dropped. The design of apparatus ~:~376~

1 for effecting scale charge transformations of any selected ratio will be apparent from the above description and all apparatus for effecting such transformations are intended to be included in the scope of the invention as defined by the appended claims.

Claims (28)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follow:

1. Data manipulation apparatus for receiving raster-scanned data as a first series of bits indicative of individ-ual objects forming an image at a first picture element (pel) resolution and for converting the data into a second series of bits indicative of the image at a second lower pel resolution, comprising a scale changing means operable on receipt of said first series of input bits to convert selec-ted sub-groups of said input bits each into a single output bit, the significance of each output bit being determined by the presence or absence of a bit of a predetermined significance anywhere in the associated sub-group of input bits, the size of the sub-groups being determined by the degree of compression required to effect the scale-change from said first to said second pel resolution, and means operable prior to scale-change for investigating bits in adjacent sub-groups and selectively to change the signifi-cance of one or more of said investigated bits if merging of said objects after scale-change to said lower resolution would otherwise occur.

2. Data manipulation apparatus as claimed in claim l, in which said means for investigating bits in adjacent sub-groups includes data sensitive thinning means operable to detect narrow gaps separating adjacent objects in the input image by a number of pels equal to or less than the number of pels in the largest sub-group selected by said scale-changing means and, in the absence of constraints, to delete selected edge pels of said objects so that the number of pels in the resultant gap is greater than the number of pels in said largest sub-group.

3. Data manipulation apparatus as claimed in claim 2, in which said data sensitive thinning means includes a plurality of individual selective edge thinners each of which is operable to detect a predetermined edge bit of an object adjacent a narrow gap and, in the absence of said constraints, to delete the detected edge bit, said individual selecting edge thinners being arranged in a predetermined order with respect to image data supplied thereto.

4. Data manipulation apparatus as claimed in claim 3, in which said individual selective edge thinners are capable selectively of detecting right-hand edges, left-hand edges, bottom edges and top edges of objects when said edges are adjacent narrow gaps.

5. Data manipulation apparatus as claimed in claim 4, in which the order of application of the selective edge thinners with respect to the input image data is such that right-hand edges of objects in the input image are considered for deletion before left-hand edge, and bottom edges are con-sidered for deletion before top edges.

6. Data manipulation apparatus as claimed in claim 5, in which the data sensitive thinning means consists of two right-hand selective edge thinners, one left-hand selective edge thinner ! three bottom selective edge thinners, and one top selective edge thinner, the input image data being sequentially supplied from one selective thinner to the next in the above order.

7. Data manipulation apparatus as claimed in claim 2, including further thinning means operable, in the absence of constraints, to investigate remaining bits representing objects in the input image emerging from said data sensitive thinning means and, in response to predetermined stimuli, for deleting further selected bits.

8. Data manipulation apparatus as claimed in claim 7, in which the further thinning means consists of a right-hand edge thinner and a top edge thinner, the image data from said data sensitive thinning means being sequentially supplied first to the right-hand edge thinner and then to the top edge thinner.

9. Data manipulation apparatus as claimed in claim 7 or claim 8, in which the stimuli for deletion of a bit is derived as a result of logical tests performed on adjacent pel positions indicating that deletion of the bit under investigation will not result in fragmentation of the object.

10. Data manipulation apparatus as claimed in claim 8 in which said means for investigating bits in adjacent sub-groups includes data sensitive merge inhibit means operable, in response to predetermined stimuli and in the absence of constraints, to move a bit representing the edge of an object in the input image from one sub-group to another adjacent sub-group to prevent merging of that bit with an edge bit of an adjacent object which would otherwise occur after scale-change to said lower resolution.

11. Data manipulation apparatus as claimed in claim 7, including data sensitive merge inhibit means operable, in response to predetermined stimuli and in the absence of constraints, to investigate remaining bits representing objects in the input image emerging from said further thin-ner to move a bit representing the edge of an object in the input image from one sub-group to an adjacent sub-group to prevent merging of that bit with an edge bit of an adjacent object which would otherwise occur after scale-change to said lower resolution.

12. Data manipulation apparatus as claimed in claim 11, in which said merge inhibit means includes a plurality of individual merge correction units each of which is operable, in the absence of constraints, to move an associated bit in a predetermined direction, said individual merge correction units being arranged to operate in a predetermined order with respect to image data.

13. Data manipulation apparatus as claimed in claim 12, in which said individual merge correction units are capable selectively of moving bits to the left, to the right, up-wards or downwards.

14. Data manipulation apparatus as claimed in claim 13, in which the order of application of the individual merge correction units with respect to input image data is such that bits are tested for possible movement to the left before being tested for movement to the right, and bits are tested for movement upwards before being tested for movement downwards.

15. Data manipulation apparatus as claimed in claim 13 or 14, in which the data sensitive merge inhibit unit consists of a merge correction unit for moving bits upwards, two merge correction units for moving bits downwards, one merge correc-tion unit for moving bits to the left and two merge correc-tion units for moving bits to the right, the input image data being sequentially supplied from one merge correction unit to the next in the above order.

16. Data manipulation apparatus as claimed in claim 10, 11 or 12, in which the stimulus for merge correction of bits is derived as a result of logical tests performed on bits occupying selected near and adjacent pel positions which indicates that re-positioning of the investigated bit will not result in merging with an edge bit of a further adjacent object which otherwise would not occur.

17. Data manipulation apparatus as claimed in claim 14 in which said means for investigating bits in adjacent sub-groups includes constraint means operable to inhibit chang-ing of significance of one or more of said investigated bits if as a result of so doing, fragmentation of the associated object would otherwise occur.

18. Data manipulation apparatus as claimed in claim 2, 3 or 4, in which constraints to deletion of an edge bit are derived as a result of logical tests performed on bits occupying selected near and adjacent pel positions which tests indicate that said bit deletion will not directly result in fragmentation of the associated object.

19. Data manipulation apparatus as claimed in claims 10 r 11 or 12, in which constraints to bit movement are derived as a result of logical tests performed on bits occupying selected near and adjacent pel positions which tests indicate that said bit movement will not directly result in fragmenta-tion of the associated object.

20. Data manipulation apparatus as claimed in claim 17 including a plurality of rows of shift registers connected in series to receive said first series of bits, said bits being supplied to the input of a first of said plurality of shift registers to be progressively shifted pel by pel through the registers to the output of a last of said plurality of shift registers, the arrangement being such that the relative row and column positions of pels within the registers correspond at all times to the original row and column positions of those pels in the raster-scanned input image.

21. Data manipulation apparatus as claimed in claim 20 in which each of said data sensitive thinning means consist of a number of logical circuits connected to test the significance of the bits in a plurality of pre-selected stages of said shift registers in order to detect an edge bit of an object adjacent a narrow gap and means operable in the absence of a constraint condition to delete such an edge bit upon its detection.

22. Data manipulation apparatus as claimed in claim 21, including constraint means operable in response to deletion of a left-hand edge bit in a row of bits to inhibit deletion of an immediately succeeding left-hand edge bit in that row.

23. Data manipulation apparatus as claimed in claim 21 or 22, including further constraint means operable in response to deletion of a top edge in a row of bits to inhibit deletion of a top edge bit in the corresponding position in the next row of bits.

24. Data manipulation apparatus as claimed in claim 21, in which said further thinning means consist of a number of logical circuits connected to test the significance of the bits in a plurality of further pre-selected stages of said shift registers in order to detect edge bits of an object the deletion of which will not cause fragmentation of the object and means responsive to detection of such bits, and in the absence of constraints for deletion of said bits.

25. Data manipulation apparatus as claimed in claim 20, in which each of said data sensitive merge inhibit means units consist of a number of logical circuits connected to test the significance of bits in a plurality of pre-selected stages of said shift registers in order to detect each bit representing a portion of an object in the input image which after scale change would be merged with a bit of an adjacent object and to move each bit detected to an adjacent pel position if after said scale-change no merging occurs with said adjacent or other adjacent object.

26. Data manipulation apparatus as claimed in claim 25 in which the sub-groups of bits are divided into sets, one set containing a different number of pels from another set in order that non-integral valued scale-change may be achieved.

27. Data manipulation apparatus as claimed in claim 26 in which said scale-changing means consists of a shift register connected to receive sequentially in image scanned rows the bits emerging at said first pel resolution from the bit investigating means, stage gating means operable to shift the contents of the register one stage each time a sub-group of bits is received by an input stage of said register, the input stage being set to a state representative of a bit of said predetermined significance if such a bit is present in said received sub-group, register gating means selectively operable to either deliver the contents of the shift regis-ter to an output terminal or to re-circulate the contents through the shift register, the re-circulated image data being applied to the input stage in synchronism with image bits supplied to the input stage from a corresponding sub-group of bits in the current row of scanned image data, the input stage being set to a state representative of said bit of predetermined significances if such a bit is either present in the received sub-group of the current scanned image row or is re-circulated from the corresponding position in the previous scanned image row, said register gating means being operable to deliver the contents of said shift register to said output terminal each time a selected sub-group of image rows has passed through said register, the selection of sub-groups of bits by said stage gating means and sub-groups of rows by said register gating means being such that image data supplied at said output terminal is at said second lower pel resolution.

28. Data manipulation apparatus as claimed in claim 10, in which said scale-changing means consists of a shift register connected to receive remaining bits representing objects in the input image emerging from said data sensitive merge inhibit means, stage gating means operable to shift the con-tents of the register one stage at a time each time a sub-group of pels is received by an input stage of the register, the input stage being set to state representing a bit of said predetermined significance whenever an image bit repre-senting an object is present in the sub-group, register gating means selectively operable to either deliver the con-tents of the shift register to an output terminal or to re-circulate the contents through the shift register, the re-circulated image data being applied to the input stage in synchronism with image pels supplied to the input stage from a corresponding sub-group of pels in the current row of scanned image data, the input stage being set as a result to a state representative of said bit of predetermined sig-nificance if an image bit representing an object is present in the received sub-group of the current scanned image row or is re-circulated from the corresponding position in the previous scanned image row, said register gating means being operable to deliver the contents of the shift register to said output terminal upon passage of a sub-group of rows through the shift register, the selection of the sub-groups of pels by said stage gating means and sub-groups of rows by said register gating means is such that the image data supplied at said output terminal is at said second lower pel resolution.