CA1137630A - Read only memory and integrated circuit and method of programming by laser means - Google Patents
Read only memory and integrated circuit and method of programming by laser meansInfo
- Publication number
- CA1137630A CA1137630A CA000343099A CA343099A CA1137630A CA 1137630 A CA1137630 A CA 1137630A CA 000343099 A CA000343099 A CA 000343099A CA 343099 A CA343099 A CA 343099A CA 1137630 A CA1137630 A CA 1137630A
- Authority
- CA
- Canada
- Prior art keywords
- lines
- layer
- memory
- regions
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
Abstract
IMPROVED READ ONLY MEMORY AND INTEGRATED CIRCUIT AND
METHOD OF PROGRAMMING BY LASER MEANS
Abstract of the Disclosure A programmable read only memory (PROM) includes a first plurality of conductive lines, a second plurality of con-ductive lines and polycrystalline silicon material there-between. At the crossing points of the first and second plurality of lines doped regions are provided in the poly-crystalline silicon in contact with a second line and which extend at least partially through the material. To provide a diode interconnect at any crossing point, the associated region is irradiated by a laser beam to either cause diffusion of dopant atoms to the underlaying conductive line or acti-vate implanted ions, thereby electrically interconnecting the first and second lines through a diode. The PROM is readily fabricated as part of a monolithic integrated circuit or electrical array and can be programmed after completion of the fabrication process.
METHOD OF PROGRAMMING BY LASER MEANS
Abstract of the Disclosure A programmable read only memory (PROM) includes a first plurality of conductive lines, a second plurality of con-ductive lines and polycrystalline silicon material there-between. At the crossing points of the first and second plurality of lines doped regions are provided in the poly-crystalline silicon in contact with a second line and which extend at least partially through the material. To provide a diode interconnect at any crossing point, the associated region is irradiated by a laser beam to either cause diffusion of dopant atoms to the underlaying conductive line or acti-vate implanted ions, thereby electrically interconnecting the first and second lines through a diode. The PROM is readily fabricated as part of a monolithic integrated circuit or electrical array and can be programmed after completion of the fabrication process.
Description
A-! `ll/AJT/
HKW
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IMPROVED READ ONLY MEMORY AND INTEGRATED CIRCUIT AND
M~THOD O~ PROGRAMMING BY LASER MEANS
This invention relates generally to semiconductor devices and integrated circuits, and more particularly the invention relates to programmable read only memories and the method of programming a read only memory.
A read only memory (ROM) comprises a plurality of X lines and a plurality of Y lines which are selectively addressed to read stored bits of information. In one embodiment of a RO~, the X lines and Y lines are selectively interconnected hy diodes to define stored bits of information. By addressing the X
and Y lines the stored information, defined by a current path between the addressed lines (e.g. a "1") or lack thereof (e.g. a "zero"), can be detected. Semiconductor ROM's are known which can be programmed after fabrication by the applica-tion of high voltages to render selected transistor components conductive.
Laser coding has been proposed, also. North and Weick in "Laser Coding of Bipolar Read Only Memories" IEEE Journal of 20 Solid State Circuits, Vol. SC-ll, No. 4, August, 1976, pp.
500-505 propose the coding of high speed bipolar silicon inte-grated circuit memories by the selective vaporization of metal links connecting contact pads of each memory cell to metal bit lines. By vaporizing the conductive link, current paths are interrupted to define the stored code.
Kuhn, et al in "Experimental Study of Laser Formed Connec-tions for LSI Wafer Personali2ation", IEEE Journal of Solid : :
~37631:~
State Physics, Vol. SC-10, No. 4, August 1975, pp. ~19-228 propose the selective forming of contacts by vaporizing and melting material through use of a laser. As described, an aluminum conductor is placed over a contact region of an underlying semiconductor substrate with a thin layer of sili-con oxide therebetween. In forming a connection between the aluminum and the contact region, a laser beam is applied to open the aluminum layer with material being removed hy vaporization. Then the silicon oxide insulating layer is re-moved by controlled microexplosion caused by thermal stressand/or vaporization of material at the silicon oxide-silicon interface. Finally, a conducting path is formed by flow of molten silicon into contact with the aluminum.
These and similar laser processes require considerable laser power and the consequent melting and vaporizing of material can result in damaged devices, thu~, reducing product yield.
In addition, large areas are required. Accordingly, no commercial use of these processes are known.
An ob~ect of the present invention is an improved programmable read only memory.
Another object of the invention is an improved method of pro-gramming a read on]y memory by selective radiation.
Still another object o~ the invention is a programmable readonly memory which is readily fabricated as part of an inte-grated circuit or on top thereof.
Yet another object of the invention is an integrated circuit including read only memory which is readily programmed a~ter fabrication.
Briefly, a programmable read only memory in accordance with the present invention includes a first plurality of spaced parallel conductive lines on a surface of a support means ~37630 and a layer of polycrystalline semiconductor material includes doped regions extending partially through the layer with each region being positioned above a line of the first plurality of conductive lines. A second plurality of conductive lines is provided on the surface of the layer of polycrystalline semiconductor material with the second plurality of conductive lines being skewed with respect to the first plurality of conductive lines. The regions of doped material are provided at cross points of the first plurality of lines and the second plurality of conductive lines, and the first plurality of lines and second plurality of lines are selecti~ely interconnected by applying a radiation beam to selected ones of the doped regions to diffuse dopant atoms to the conductive line thereunder and thus provide diode current paths between the Eirst plurality of lines and second plurality of lines.
Advantageously, no vapori~ing of material results therefrom. Further, the read only memory can be Eabricated on the surface of an integrated circuit and interconnected therewith to become a part thereof. Additional memory layers can be added resu]ting in a compact multilayer structure.
In coding the read only memory, a radiation beam such as a laser or electron beam is directed on a doped region with sufficient energy to cause local diffusion9 with or without melting, of dopants to the underlying line and thereby interconnect the first line to the second line, but without physically damaging the structure.
In an alternative embodiment, the doped regions can be formed by ion implantation with the doped regions extending substantially to the underlying conductive lines. Thereafter, by application of a radiation beam selected implanted regions are activated to form diodes connected between X and Y lines.
Thus, in accordance with one broad aspect of the invention, there :~
31 3L37~i3~
is provided a read only memory comprising support means, a first plurality of spaced parallel conductive lines on a surface of said support means, said first plurality of conductive lines comprising semiconductor material and including dopants of a first conductivity type, a layer of polycrystalline semiconductor material overlying said first plurality of conductor lines, said layer of polycrystalline semiconductor material including regions of doped material extending at least partially through said layer, said doped regions including dopants of opposite conductivity type, each of said regions being positioned above one line of said first plurality of conductive lines, and a second plurality of spaced parallel conductive lines on the surface of said layer of polycrystalline semiconductor material, said second plura-lity of conductive lines being skewed with respect to said first plurality of conductive lines with said regions of cloped material provided at crossing points of said first plurality of lines and said second plurality of lines.
In accordance with another broacl aspect of the invention there is provided a semiconductor integrated circui.t comprising a single crystalline semiconductor substrate, at least one active electrical component defined in said substrate by selective doping, an electrically insulating material provided on a major surface of said substrate, and a read only memory Eormed on said electrically insulative material, said read only memory including a first plurality of spaced parallel conductive lines on said insulative material, said first plurality oE conductive lines comprising semiconductor material and including dopants of a first conductive type, a layer of poly-crystalline silicon material overlying said first plurality of conductive lines, said layer of polycrystalline silicon including doped regions extend-ing at least partially through said layer, said doped regions including dopants of opposite conductivity type, each of said regions being positioned ~3a-~..', 3763~
above one line of said first plurality of conductive lines, and a second plurality of spaced parallel conductive lines on the surface oE said layer of polycrystalline silicon, said second plurality of conductive lines being skewed with respect to said first plurality of conductive lines with said doped regions provided at crossing points of said first plurality of lines and second plurality of lines.
According to another broad aspect of the invention there is pro-vided, in a programmable read only memory having a first plurality of conductive lines and a second plurality of conductive lines overlying said first plurality of conduct-lve lines and a layer of polycrystalline semi-conductive material therebetween, said layer of polycrystalline semiconduct-ive material including doped regions extending at least partially through said layer, each of said regions being positioned between crossing points of said first plurality of lines and said second plurality of lines, the method of selectively interconnecting through diodes said first plurality of lines and said second plurality of lines including irradiating selected ones of said regions the~eby diffusing dopant ions and providing unidirect-ional current paths between said first plurality of lines and said second plurality of lines.
The invention and objects and features thereof will be more readily understood from the following detailed description and appended claims when taken with the drawing.
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Figure 1 is a schematic illustrating a read only memory.
Figure 2 through Figure 5 illustrate in plan view and section view one embodiment of fabrication and programming of a read only memory in accordance with the present invention.
Figure 6 and ~ are section views of alternative embodiments of the invention.
Figure 8 is a section view of a portion of an integrated cir-cuit including a read only memory and a silicon gate field effect transistor in accordance with the present invention.
Figure 9 is a section view of a portion of an integrated cir-cuit including a read only memory and a bipolar junction tran-sistor in accordance with the present invention.
Figure 10 is a perspective view of a microprocessor system including a programmable read only memory in accordance with the present invention.
Referring now to the drawings, Figure 1 illustrates sche-matically a read only memory which includes a plurality of first conductive lines, designated the X lines (Xl-X5), and a second plurality of conductive lines designated the Y lines (Yl-Y4). Typically, the first plurality of lines is skewed with respect to the second plurality of lines with the inter-section of lines either being interconnected through diodes as shown or not connected as illustrated by circles. The mem-ory is read by applying a voltage potential between an Xline and a Y line and detecting the presence or absence of a current. When no connection is made between the lines, the absence of a current may signify a binary "O". Conversely, when a connection is made between the two lines the presence of a current may signify a binary "1". For example, by applying a negative voltage to the X3 line and grounding the Y2 line, a current flowing from the Y2 line through diode 12 ~3~63`~
to the ~3 line is detected. Similarly, by applying the negative voltage to the X3 line and grounding the Y3 line a current flowing from the Y3 line through diode 14 to the X3 line can be detected. However, with the negative voltage on the X3 line and the Y4 line grounded no current flows due to no connection being made between the Y4 and X3 lines, as designated by circle 16. Thus, by addressing the memory array through energization of selected X lines and Y lines, stored data or binary bits can be read out by detecting the presence or absence of a current. It will be appreciated that the array can include thousands of lines and thousands of bits of stored data.
It is advantageous to fabricate a memory array and retain the capability of programming the memory after completion of the array. Moreover, it would be advantageous to in-corporate such a read only memory in a monolithic integrated circuit or other microminiature electrical system. Conven-tional read only memories typically do not include other circuitry and most are preprogrammed during fabrication.
However, a read only memory in accordance with the present invention is readily fabricated at part of an integrated circuit or other electronic array and may be programmed after fabricationO
Referring now to Figure 2(A & B) through Figure 5 (A & B) the fabrication and programming of a read only memory in accordance with the present invention is illustrated in one embodiment. In each of the figures the plan view of a por-tion of a ROM is illustrated in Figure A, and a section viewof the portion of the ROM shown in Figure A is illustrated in Figure B.
In Figures 2A and 2B a semiconductor substrate 20 of silicon, for example, is provided with a silicon oxide layer 22 on a major surface thereof, and a layer of polycrystalline silicon 24 ls formed on the surface of silicon oxide layer ~37~3~3 22. Substrate 20 may comprise a part of an integrated circuit, or the substr-ate may be of other suitable material such as poly~rystalline silicon or glass which has been deposited on a circuit array or the like to accomodate the read only memory. Silicon oxide layer 22 may be typically on the order of 1000 angstroms in thickness to provide electrical insulation and also a suitable surface for the vapor deposition of polycrystalline silicon or like material.
The polycrystalline silicon material 24 may be formed by vapor deposition in a suitable reactor to a thickness on the order of 0.5 micron, and a plurality of spaced parallel conductive lines 26 are formed therein by diffusion or ion implantation techniques. For ~ type conductivity, arsenic may be implanted with a concentration of 5 x 1015 ions per square centimeter at a potential 170 kev, for example. The doped polycrystalline silicon is preferably annealed either in an oven at an elevated temperature (e.g. 1100C for 30 minutes) or by radiation scanning as disclosed by Gat et al in "~ Laser Anneal of Poly~
crystalline Silicon: Crystalline Structure, Electrical Properties", Applied Physics Letters, October 15, 1978. The undoped polycrystalline silicon is non-conducting thereby providing electrical isolation between lines.
Thereafter, as illustrated in Figure 3A and Figure 3B a second lay-er of polycrystalline silicon material 28 is formed on the first layer 2~ by vapor deposition with the thickness of layer 28 being on the order of 0.5 micron. A plurality of rectangularly shaped, P type doped regions 30 are formed in surface regions of layer 28, for example, by implanting boron ions in a density of 5 x 101~ ions per square centimeter at lOO kev. The shallow regions 30 do not extend completely through layer 28 and thus are spaced from the underlying conductive line 26.
As seen in Figure 3A, each of the regions 30 is generally rectangu-lar in shape and is positioned above a conductive line 26 in the underlying polycrystalline layer.
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In Figure 4 a second plurality of conductive lines 32 are formed on the suxface of layer 28 in alignment with the diffused regions 30 and skewed with respect to the underlying plurality of lines 26. Lines 32 may be formed by sputtering or vapor de~sition and selective etching of suitable metal such as aluminum, or alternatively the lines may be formed by doping of the surEace of polycrystalline silicon layer 28.
Importantly, it will be noted that the width of lines 32 are substantially less than the length of the rectangular regions 30. The read only memory is structurally completed at this state, and programming thereof can be accomplished at a later time in accordance with the user's needs.
~eferring to Figure 5 the programming of the read only memory is accomplished by applying a laser beam on a generally cir-cular surface area 34 which overlaps a region 30 but prefer-ably is spaced from the metal lead 32. By melting the region 30 of the polycrystalline layer 28, the P type ions diffuse through layer 28 and into contact with the underlying N type region of layer 24 which defines line 26. Thus, a PN junc-tion, or diode, is formed which int~erconnects metal layer 32 to the underlying line 26. Thus, the first plurality of lines can be selectively interconnected with the second plurality of lines by application of a laser beam and diffu-sion of the P type impurities in the radiated region 30 tothe underlyin~ line.
Advantageously, the radiation beam need not contact the metal lines 32, and no melting of the metal in the lines results.
However, the invention can be practiced by applying the laser beam directly to the line 32 to cause diffusion of impurities in the region 30 immediately underlying the laser beam and the metal line. Particularly if the second plurality of lines are defined by doped polycrystalline material, applica-tion of the laser beam likely would have no deleteriouseffects by being applied directly thereto. Closer spacing of the second plurality of lines can then be effected.
:~37~3~
~8 It will be appreciated, also, that the memory can be pro-grammed prior to application of the second plurality of lines by radiation aided diffusion of impurities in selected regions 30 prior to the definition of the second plurality of lines. Such a procedure may be preferred if later pro-gramming of the ROM is not required.
Rather than use of diffused doped regions for interconnecting the two sets of lines, ion implanted regions can be employed, as illustrated in Figures 6 and 7. In Figure 6, a silicon substrate 120 has a layer 122 of silicon oxide on one surface with a polycrystalline silicon layer 124 formed thereon. The first set of lines 126 are formed in layer 124 and a second polycrystalllne silicon layer 130 is formed thereover. Re-gions 132 are formed by ion implantation with the regionsextending substantially through layer 124. Assuming that the lines 126 are N type conductivity, the regions 132 are P type. A second set of lines are formed over layer 130 such as illustrated by a metal line 134 such as tungsten.
As is well known in the art, implanted ions must be activated by annealing. Selective annealing, where a binary "1" is wished to be written, can be done with a radiation beam either through the metal 134 or on the side of the metal line. sy annealing the implanted region 132, diode interconnections between line 134 and the lines 126 can be created by activat-ing a P type region 132 which then forms a P-N junction with the underlying N type region 126. Advantageously, the anneal-ing of the implanted region can be done selectively by laser irradiation and at a lower temperature than is required for melting. See, for example, Gat, Gerzherg, Gibbons et al "cw Laser Anneal of Polycrystalline Silicon: Crystalline Structure, Electrical Properties", Applied Physics Letters, Octoher 15, 1978.
Figure 7 is a cross-section of a portion of a device similar to that illustrated in Figure 6, but in this embodiment an N
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g type region 131 is implanted in the layer 130 and then the P type region 132 is implanted thereover. Upon activation of the regions 131 and 132 by annealing, the P-M junction of the interconnecting diode is locaLed at the interface of the regions 131, 132.
It will be appreciated that the regions 132 in Figure 6 and regions 131, 132 in Figure 7, as well as the regions 30 in Figure 3, may comprise a continuous, ion-implanted layer.
Prior to annealing the layer is substantially non-conductive.
Only at the locations of irradiation and ion diffusion or annealing does the layer become conductive.
A programmable read only memory in accordance with the present invention is readily fabricated with an integrated circuit array as illustrated in the section views of Figure 8 and Figure 9 of portions of integrated circuits. In Figure 8 a portion of the ROM is illustrated above a silicon gate field effect transistor shown generally at 40 which includes a source 42, drain 44, and a gate electrode 46. The metal interconnects 48 to the source and drain regions are formed over field oxide 49 and are covered with a silicon oxide layer 50, and the read only memory structure is formed on the insulating silicon oxide layer 50. In a structure simi-lar to that illustrated in Figures 2-5, a first plurality of lines are provided in a first polycrystalline silicon layer 52 which is formed directly on silicon oxide layer 50, and the second polycrystalline silicon layer 54 is formed on layer 52 with a second line defined by metal layer 56 on polysilicon 54. Selective interconnection of line 56 to lines in the underlying polycrystalline silicon layer 52 is accomplished by applying a radiation beam to selected re-gions 58 to diffuse dopants therein into engagement with lines in the first polycrystalline silicon layer 52.
A similar cross section view is illustrated in Figure 9 of a portion of an integrated circuit which includes a bipolar ~L~8L37~;3~
junction transistor 60 including emitter 62, base 64, and collector 66. Metal leads 68 are provided to the collector and emitter, respectively, and the leads are covered by an insulating layer of silicon oxide 70. The read only memory is formed directly thereover including a first polycrystalline silicon layer 72, a second polycrystalline silicon layer 74, metal layer 76, and the regions 78 which selectively inter-connect metal layer 76 to lines in layer 72 by means of application of a laser beam.
A read only memory in accordance with the present invention not only can be incorporated as part of an integrated circuit, the array can be fabricated directly on a circuit assembly as shown in Figure 10 which illustrates a perspective view of a microprocessor circuit board. The microprocessor is incorpora-ted in a large scale integrated chip which is mounted on a frame 92 along with suitable processor I/O circuitry 94. The microprocessor LSI chip is coated with a suitable insulating material such as glass or epoxy, and a read only memory array 96 is then formed over the LSI chip. The Y lines of the ROM
are connected to a Y MUX 98, and the X lines of the ROM are connected to an X MUX 99. Again, programming of the ~OM can be effected after completion of the electrical assembly by selectively irradiating the ROM to effect interconnection of selected X and Y lines and thus record binary data.
The invention has been described with reference to several illustrative embodiments, and modifications of the illustrated embodiments have been suggested. For example, the first and second plurality of lines can be fabricated from metal, doped polycrystalline silicon, or other suitable conductive material. While interconnection of the lines is preferably accomplished by applying a radiation beam to a surface area adjacent to the top conductive line and thus avoiding physical alternation of the line, the radiation beam can be applied directly to the line thus allowing higher density assembly of .: .
19L37 Ei31D
the ROM structure. While a laser beam has been described for effecting the diffusion of dopant impurities, other radiation beams such as an electron beam could be utilized.
As indicated, the RO~ can be programmed during fabrication and pxior to formation of the second plurality of lines if so desired. Further, the ROM may comprise multiple layers of address lines in a stacked array thus providing greater storage capacity in the same surface area.
Thus, while the invention has been described with reference to specific embodiments the description is illustrative of the invention and is not to be construed as limiting the invention. These and other modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as definecl by the appended claims.
HKW
~3~3~
IMPROVED READ ONLY MEMORY AND INTEGRATED CIRCUIT AND
M~THOD O~ PROGRAMMING BY LASER MEANS
This invention relates generally to semiconductor devices and integrated circuits, and more particularly the invention relates to programmable read only memories and the method of programming a read only memory.
A read only memory (ROM) comprises a plurality of X lines and a plurality of Y lines which are selectively addressed to read stored bits of information. In one embodiment of a RO~, the X lines and Y lines are selectively interconnected hy diodes to define stored bits of information. By addressing the X
and Y lines the stored information, defined by a current path between the addressed lines (e.g. a "1") or lack thereof (e.g. a "zero"), can be detected. Semiconductor ROM's are known which can be programmed after fabrication by the applica-tion of high voltages to render selected transistor components conductive.
Laser coding has been proposed, also. North and Weick in "Laser Coding of Bipolar Read Only Memories" IEEE Journal of 20 Solid State Circuits, Vol. SC-ll, No. 4, August, 1976, pp.
500-505 propose the coding of high speed bipolar silicon inte-grated circuit memories by the selective vaporization of metal links connecting contact pads of each memory cell to metal bit lines. By vaporizing the conductive link, current paths are interrupted to define the stored code.
Kuhn, et al in "Experimental Study of Laser Formed Connec-tions for LSI Wafer Personali2ation", IEEE Journal of Solid : :
~37631:~
State Physics, Vol. SC-10, No. 4, August 1975, pp. ~19-228 propose the selective forming of contacts by vaporizing and melting material through use of a laser. As described, an aluminum conductor is placed over a contact region of an underlying semiconductor substrate with a thin layer of sili-con oxide therebetween. In forming a connection between the aluminum and the contact region, a laser beam is applied to open the aluminum layer with material being removed hy vaporization. Then the silicon oxide insulating layer is re-moved by controlled microexplosion caused by thermal stressand/or vaporization of material at the silicon oxide-silicon interface. Finally, a conducting path is formed by flow of molten silicon into contact with the aluminum.
These and similar laser processes require considerable laser power and the consequent melting and vaporizing of material can result in damaged devices, thu~, reducing product yield.
In addition, large areas are required. Accordingly, no commercial use of these processes are known.
An ob~ect of the present invention is an improved programmable read only memory.
Another object of the invention is an improved method of pro-gramming a read on]y memory by selective radiation.
Still another object o~ the invention is a programmable readonly memory which is readily fabricated as part of an inte-grated circuit or on top thereof.
Yet another object of the invention is an integrated circuit including read only memory which is readily programmed a~ter fabrication.
Briefly, a programmable read only memory in accordance with the present invention includes a first plurality of spaced parallel conductive lines on a surface of a support means ~37630 and a layer of polycrystalline semiconductor material includes doped regions extending partially through the layer with each region being positioned above a line of the first plurality of conductive lines. A second plurality of conductive lines is provided on the surface of the layer of polycrystalline semiconductor material with the second plurality of conductive lines being skewed with respect to the first plurality of conductive lines. The regions of doped material are provided at cross points of the first plurality of lines and the second plurality of conductive lines, and the first plurality of lines and second plurality of lines are selecti~ely interconnected by applying a radiation beam to selected ones of the doped regions to diffuse dopant atoms to the conductive line thereunder and thus provide diode current paths between the Eirst plurality of lines and second plurality of lines.
Advantageously, no vapori~ing of material results therefrom. Further, the read only memory can be Eabricated on the surface of an integrated circuit and interconnected therewith to become a part thereof. Additional memory layers can be added resu]ting in a compact multilayer structure.
In coding the read only memory, a radiation beam such as a laser or electron beam is directed on a doped region with sufficient energy to cause local diffusion9 with or without melting, of dopants to the underlying line and thereby interconnect the first line to the second line, but without physically damaging the structure.
In an alternative embodiment, the doped regions can be formed by ion implantation with the doped regions extending substantially to the underlying conductive lines. Thereafter, by application of a radiation beam selected implanted regions are activated to form diodes connected between X and Y lines.
Thus, in accordance with one broad aspect of the invention, there :~
31 3L37~i3~
is provided a read only memory comprising support means, a first plurality of spaced parallel conductive lines on a surface of said support means, said first plurality of conductive lines comprising semiconductor material and including dopants of a first conductivity type, a layer of polycrystalline semiconductor material overlying said first plurality of conductor lines, said layer of polycrystalline semiconductor material including regions of doped material extending at least partially through said layer, said doped regions including dopants of opposite conductivity type, each of said regions being positioned above one line of said first plurality of conductive lines, and a second plurality of spaced parallel conductive lines on the surface of said layer of polycrystalline semiconductor material, said second plura-lity of conductive lines being skewed with respect to said first plurality of conductive lines with said regions of cloped material provided at crossing points of said first plurality of lines and said second plurality of lines.
In accordance with another broacl aspect of the invention there is provided a semiconductor integrated circui.t comprising a single crystalline semiconductor substrate, at least one active electrical component defined in said substrate by selective doping, an electrically insulating material provided on a major surface of said substrate, and a read only memory Eormed on said electrically insulative material, said read only memory including a first plurality of spaced parallel conductive lines on said insulative material, said first plurality oE conductive lines comprising semiconductor material and including dopants of a first conductive type, a layer of poly-crystalline silicon material overlying said first plurality of conductive lines, said layer of polycrystalline silicon including doped regions extend-ing at least partially through said layer, said doped regions including dopants of opposite conductivity type, each of said regions being positioned ~3a-~..', 3763~
above one line of said first plurality of conductive lines, and a second plurality of spaced parallel conductive lines on the surface oE said layer of polycrystalline silicon, said second plurality of conductive lines being skewed with respect to said first plurality of conductive lines with said doped regions provided at crossing points of said first plurality of lines and second plurality of lines.
According to another broad aspect of the invention there is pro-vided, in a programmable read only memory having a first plurality of conductive lines and a second plurality of conductive lines overlying said first plurality of conduct-lve lines and a layer of polycrystalline semi-conductive material therebetween, said layer of polycrystalline semiconduct-ive material including doped regions extending at least partially through said layer, each of said regions being positioned between crossing points of said first plurality of lines and said second plurality of lines, the method of selectively interconnecting through diodes said first plurality of lines and said second plurality of lines including irradiating selected ones of said regions the~eby diffusing dopant ions and providing unidirect-ional current paths between said first plurality of lines and said second plurality of lines.
The invention and objects and features thereof will be more readily understood from the following detailed description and appended claims when taken with the drawing.
~3~
Figure 1 is a schematic illustrating a read only memory.
Figure 2 through Figure 5 illustrate in plan view and section view one embodiment of fabrication and programming of a read only memory in accordance with the present invention.
Figure 6 and ~ are section views of alternative embodiments of the invention.
Figure 8 is a section view of a portion of an integrated cir-cuit including a read only memory and a silicon gate field effect transistor in accordance with the present invention.
Figure 9 is a section view of a portion of an integrated cir-cuit including a read only memory and a bipolar junction tran-sistor in accordance with the present invention.
Figure 10 is a perspective view of a microprocessor system including a programmable read only memory in accordance with the present invention.
Referring now to the drawings, Figure 1 illustrates sche-matically a read only memory which includes a plurality of first conductive lines, designated the X lines (Xl-X5), and a second plurality of conductive lines designated the Y lines (Yl-Y4). Typically, the first plurality of lines is skewed with respect to the second plurality of lines with the inter-section of lines either being interconnected through diodes as shown or not connected as illustrated by circles. The mem-ory is read by applying a voltage potential between an Xline and a Y line and detecting the presence or absence of a current. When no connection is made between the lines, the absence of a current may signify a binary "O". Conversely, when a connection is made between the two lines the presence of a current may signify a binary "1". For example, by applying a negative voltage to the X3 line and grounding the Y2 line, a current flowing from the Y2 line through diode 12 ~3~63`~
to the ~3 line is detected. Similarly, by applying the negative voltage to the X3 line and grounding the Y3 line a current flowing from the Y3 line through diode 14 to the X3 line can be detected. However, with the negative voltage on the X3 line and the Y4 line grounded no current flows due to no connection being made between the Y4 and X3 lines, as designated by circle 16. Thus, by addressing the memory array through energization of selected X lines and Y lines, stored data or binary bits can be read out by detecting the presence or absence of a current. It will be appreciated that the array can include thousands of lines and thousands of bits of stored data.
It is advantageous to fabricate a memory array and retain the capability of programming the memory after completion of the array. Moreover, it would be advantageous to in-corporate such a read only memory in a monolithic integrated circuit or other microminiature electrical system. Conven-tional read only memories typically do not include other circuitry and most are preprogrammed during fabrication.
However, a read only memory in accordance with the present invention is readily fabricated at part of an integrated circuit or other electronic array and may be programmed after fabricationO
Referring now to Figure 2(A & B) through Figure 5 (A & B) the fabrication and programming of a read only memory in accordance with the present invention is illustrated in one embodiment. In each of the figures the plan view of a por-tion of a ROM is illustrated in Figure A, and a section viewof the portion of the ROM shown in Figure A is illustrated in Figure B.
In Figures 2A and 2B a semiconductor substrate 20 of silicon, for example, is provided with a silicon oxide layer 22 on a major surface thereof, and a layer of polycrystalline silicon 24 ls formed on the surface of silicon oxide layer ~37~3~3 22. Substrate 20 may comprise a part of an integrated circuit, or the substr-ate may be of other suitable material such as poly~rystalline silicon or glass which has been deposited on a circuit array or the like to accomodate the read only memory. Silicon oxide layer 22 may be typically on the order of 1000 angstroms in thickness to provide electrical insulation and also a suitable surface for the vapor deposition of polycrystalline silicon or like material.
The polycrystalline silicon material 24 may be formed by vapor deposition in a suitable reactor to a thickness on the order of 0.5 micron, and a plurality of spaced parallel conductive lines 26 are formed therein by diffusion or ion implantation techniques. For ~ type conductivity, arsenic may be implanted with a concentration of 5 x 1015 ions per square centimeter at a potential 170 kev, for example. The doped polycrystalline silicon is preferably annealed either in an oven at an elevated temperature (e.g. 1100C for 30 minutes) or by radiation scanning as disclosed by Gat et al in "~ Laser Anneal of Poly~
crystalline Silicon: Crystalline Structure, Electrical Properties", Applied Physics Letters, October 15, 1978. The undoped polycrystalline silicon is non-conducting thereby providing electrical isolation between lines.
Thereafter, as illustrated in Figure 3A and Figure 3B a second lay-er of polycrystalline silicon material 28 is formed on the first layer 2~ by vapor deposition with the thickness of layer 28 being on the order of 0.5 micron. A plurality of rectangularly shaped, P type doped regions 30 are formed in surface regions of layer 28, for example, by implanting boron ions in a density of 5 x 101~ ions per square centimeter at lOO kev. The shallow regions 30 do not extend completely through layer 28 and thus are spaced from the underlying conductive line 26.
As seen in Figure 3A, each of the regions 30 is generally rectangu-lar in shape and is positioned above a conductive line 26 in the underlying polycrystalline layer.
7~
In Figure 4 a second plurality of conductive lines 32 are formed on the suxface of layer 28 in alignment with the diffused regions 30 and skewed with respect to the underlying plurality of lines 26. Lines 32 may be formed by sputtering or vapor de~sition and selective etching of suitable metal such as aluminum, or alternatively the lines may be formed by doping of the surEace of polycrystalline silicon layer 28.
Importantly, it will be noted that the width of lines 32 are substantially less than the length of the rectangular regions 30. The read only memory is structurally completed at this state, and programming thereof can be accomplished at a later time in accordance with the user's needs.
~eferring to Figure 5 the programming of the read only memory is accomplished by applying a laser beam on a generally cir-cular surface area 34 which overlaps a region 30 but prefer-ably is spaced from the metal lead 32. By melting the region 30 of the polycrystalline layer 28, the P type ions diffuse through layer 28 and into contact with the underlying N type region of layer 24 which defines line 26. Thus, a PN junc-tion, or diode, is formed which int~erconnects metal layer 32 to the underlying line 26. Thus, the first plurality of lines can be selectively interconnected with the second plurality of lines by application of a laser beam and diffu-sion of the P type impurities in the radiated region 30 tothe underlyin~ line.
Advantageously, the radiation beam need not contact the metal lines 32, and no melting of the metal in the lines results.
However, the invention can be practiced by applying the laser beam directly to the line 32 to cause diffusion of impurities in the region 30 immediately underlying the laser beam and the metal line. Particularly if the second plurality of lines are defined by doped polycrystalline material, applica-tion of the laser beam likely would have no deleteriouseffects by being applied directly thereto. Closer spacing of the second plurality of lines can then be effected.
:~37~3~
~8 It will be appreciated, also, that the memory can be pro-grammed prior to application of the second plurality of lines by radiation aided diffusion of impurities in selected regions 30 prior to the definition of the second plurality of lines. Such a procedure may be preferred if later pro-gramming of the ROM is not required.
Rather than use of diffused doped regions for interconnecting the two sets of lines, ion implanted regions can be employed, as illustrated in Figures 6 and 7. In Figure 6, a silicon substrate 120 has a layer 122 of silicon oxide on one surface with a polycrystalline silicon layer 124 formed thereon. The first set of lines 126 are formed in layer 124 and a second polycrystalllne silicon layer 130 is formed thereover. Re-gions 132 are formed by ion implantation with the regionsextending substantially through layer 124. Assuming that the lines 126 are N type conductivity, the regions 132 are P type. A second set of lines are formed over layer 130 such as illustrated by a metal line 134 such as tungsten.
As is well known in the art, implanted ions must be activated by annealing. Selective annealing, where a binary "1" is wished to be written, can be done with a radiation beam either through the metal 134 or on the side of the metal line. sy annealing the implanted region 132, diode interconnections between line 134 and the lines 126 can be created by activat-ing a P type region 132 which then forms a P-N junction with the underlying N type region 126. Advantageously, the anneal-ing of the implanted region can be done selectively by laser irradiation and at a lower temperature than is required for melting. See, for example, Gat, Gerzherg, Gibbons et al "cw Laser Anneal of Polycrystalline Silicon: Crystalline Structure, Electrical Properties", Applied Physics Letters, Octoher 15, 1978.
Figure 7 is a cross-section of a portion of a device similar to that illustrated in Figure 6, but in this embodiment an N
:; , :.~ , : :, . .
~37~3~
g type region 131 is implanted in the layer 130 and then the P type region 132 is implanted thereover. Upon activation of the regions 131 and 132 by annealing, the P-M junction of the interconnecting diode is locaLed at the interface of the regions 131, 132.
It will be appreciated that the regions 132 in Figure 6 and regions 131, 132 in Figure 7, as well as the regions 30 in Figure 3, may comprise a continuous, ion-implanted layer.
Prior to annealing the layer is substantially non-conductive.
Only at the locations of irradiation and ion diffusion or annealing does the layer become conductive.
A programmable read only memory in accordance with the present invention is readily fabricated with an integrated circuit array as illustrated in the section views of Figure 8 and Figure 9 of portions of integrated circuits. In Figure 8 a portion of the ROM is illustrated above a silicon gate field effect transistor shown generally at 40 which includes a source 42, drain 44, and a gate electrode 46. The metal interconnects 48 to the source and drain regions are formed over field oxide 49 and are covered with a silicon oxide layer 50, and the read only memory structure is formed on the insulating silicon oxide layer 50. In a structure simi-lar to that illustrated in Figures 2-5, a first plurality of lines are provided in a first polycrystalline silicon layer 52 which is formed directly on silicon oxide layer 50, and the second polycrystalline silicon layer 54 is formed on layer 52 with a second line defined by metal layer 56 on polysilicon 54. Selective interconnection of line 56 to lines in the underlying polycrystalline silicon layer 52 is accomplished by applying a radiation beam to selected re-gions 58 to diffuse dopants therein into engagement with lines in the first polycrystalline silicon layer 52.
A similar cross section view is illustrated in Figure 9 of a portion of an integrated circuit which includes a bipolar ~L~8L37~;3~
junction transistor 60 including emitter 62, base 64, and collector 66. Metal leads 68 are provided to the collector and emitter, respectively, and the leads are covered by an insulating layer of silicon oxide 70. The read only memory is formed directly thereover including a first polycrystalline silicon layer 72, a second polycrystalline silicon layer 74, metal layer 76, and the regions 78 which selectively inter-connect metal layer 76 to lines in layer 72 by means of application of a laser beam.
A read only memory in accordance with the present invention not only can be incorporated as part of an integrated circuit, the array can be fabricated directly on a circuit assembly as shown in Figure 10 which illustrates a perspective view of a microprocessor circuit board. The microprocessor is incorpora-ted in a large scale integrated chip which is mounted on a frame 92 along with suitable processor I/O circuitry 94. The microprocessor LSI chip is coated with a suitable insulating material such as glass or epoxy, and a read only memory array 96 is then formed over the LSI chip. The Y lines of the ROM
are connected to a Y MUX 98, and the X lines of the ROM are connected to an X MUX 99. Again, programming of the ~OM can be effected after completion of the electrical assembly by selectively irradiating the ROM to effect interconnection of selected X and Y lines and thus record binary data.
The invention has been described with reference to several illustrative embodiments, and modifications of the illustrated embodiments have been suggested. For example, the first and second plurality of lines can be fabricated from metal, doped polycrystalline silicon, or other suitable conductive material. While interconnection of the lines is preferably accomplished by applying a radiation beam to a surface area adjacent to the top conductive line and thus avoiding physical alternation of the line, the radiation beam can be applied directly to the line thus allowing higher density assembly of .: .
19L37 Ei31D
the ROM structure. While a laser beam has been described for effecting the diffusion of dopant impurities, other radiation beams such as an electron beam could be utilized.
As indicated, the RO~ can be programmed during fabrication and pxior to formation of the second plurality of lines if so desired. Further, the ROM may comprise multiple layers of address lines in a stacked array thus providing greater storage capacity in the same surface area.
Thus, while the invention has been described with reference to specific embodiments the description is illustrative of the invention and is not to be construed as limiting the invention. These and other modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as definecl by the appended claims.
Claims (8)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A read only memory comprising support means, a first plurality of spaced parallel conductive lines on a surface of said support means, said first plurality of conductive lines comprising semiconductor material and including dopants of a first conductivity type, a layer of polycrystalline semiconductor material overlying said first plurality of conductor lines, said layer of polycrystalline semiconductor material including regions of doped material extending at least partially through said layer, said doped regions including dopants of opposite conductivity type, each of said regions being positioned above one line of said first plurality of conductive lines, and a second plurality of spaced parallel conductive lines on the surface of said layer of polycrystalline semiconductor material, said second plurality of conductive lines being skewed with respect to said first plurality of conductive lines with said regions of doped material provided at crossing points of said first plurality of lines and said second plurality of lines.
2. A read only memory as defined by Claim 1 wherein said regions of doped material extend partially through said layer and wherein said first plurality of lines and said second plurality of lines are selectively inter-connected through diodes by applying a radiation beam to selected ones of said doped regions to diffuse dopants therein to the conductive line thereunder and provide current paths between said first plurality of lines and said second plurality of lines.
3. A read only memory as defined by Claim 1 wherein said polycrystal-line semiconductive material is silicon, said support means includes a mono-crystalline silicon substrate and a layer of silicon oxide on a major surface thereof, said first plurality of conductive lines comprising doped polycyrstal-line silicon.
4. A read only memory as defined by Claim 3 wherein said doped poly-crystalline silicon is formed in a layer of polycrystalline silicon by select-ive doping and annealing.
5. A read only memory as defined by Claim 1 wherein said regions of doped material extend substantially through said layer and are formed by ion implantation and wherein said first plurality of lines and said second plura-lity of lines are selectively interconnected through diodes by selectively annealing said regions.
6. A read only memory as defined by Claim 3 wherein said monocrystal-line silicon substrate includes an integrated circuit.
7. A semiconductor integrated circuit comprising a single crystalline semiconductor substrate, at least one active electrical component defined in said substrate by selective doping, an electrically insulating material pro-vided on a major surface of said substrate, and a read only memory formed on said electrically insulative material, said read only memory including a first plurality of spaced parallel conductive lines on said insulative material, said first plurality of conductive lines comprising semiconductor material and including dopants of a first conductive type, a layer of polycrystalline silicon material overlying said first plurality of conductive lines, said layer of polycrystalline silicon including doped regions extending at least partially through said layer, said doped regions including dopants of opposite conduct-ivity type, each of said regions being positioned above one line of said first plurality of conductive lines, and a second plurality of spaced parallel con-ductive lines on the surface of said layer of polycrystalline silicon, said second plurality of conductive lines being skewed with respect to said first plurality of conductive lines with said doped regions provided at crossing points of said first plurality of lines and second plurality of lines.
8. In a programmable read only memory having a first plurality of conductive lines and a second plurality of conductive lines overlying said first plurality of conductive lines and a layer of polycrystalline semicond-uctive material therebetween, said layer of polycrystalline semiconductive material including doped regions extending at least partially through said layer, each of said regions being positioned between crossing points of said first plurality of lines and said second plurality of lines, the method of selectively interconnecting through diodes said first plurality of lines and said second plurality of lines including irradiating selected ones of said regions thereby diffusing dopant ions and providing unidirectional current paths between said first plurality of lines and said second plurality of lines.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US001,360 | 1979-01-05 | ||
| US06/001,360 US4233671A (en) | 1979-01-05 | 1979-01-05 | Read only memory and integrated circuit and method of programming by laser means |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1137630A true CA1137630A (en) | 1982-12-14 |
Family
ID=21695648
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000343099A Expired CA1137630A (en) | 1979-01-05 | 1980-01-04 | Read only memory and integrated circuit and method of programming by laser means |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4233671A (en) |
| EP (1) | EP0013603B1 (en) |
| JP (1) | JPS5593254A (en) |
| CA (1) | CA1137630A (en) |
| DE (1) | DE3063206D1 (en) |
Families Citing this family (34)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5750467A (en) * | 1980-09-12 | 1982-03-24 | Fujitsu Ltd | Semiconductor memory |
| JPS5750468A (en) * | 1980-09-12 | 1982-03-24 | Fujitsu Ltd | Semiconductor memory |
| US4424579A (en) * | 1981-02-23 | 1984-01-03 | Burroughs Corporation | Mask programmable read-only memory stacked above a semiconductor substrate |
| US4404635A (en) * | 1981-03-27 | 1983-09-13 | International Business Machines Corporation | Programmable integrated circuit and method of testing the circuit before it is programmed |
| FR2520146A1 (en) * | 1982-01-15 | 1983-07-22 | Thomson Csf | MATRIX OF INTEGRATED MEMORY ELEMENTS, WITH SCHOTTKY DIODE ON POLYCRYSTALLINE SILICON, AND MANUFACTURING METHOD |
| JPS58188155A (en) * | 1982-04-27 | 1983-11-02 | Seiko Epson Corp | Double layered rom integrated circuit |
| JPS58209157A (en) * | 1982-05-31 | 1983-12-06 | Seiko Epson Corp | Semiconductor memory cell |
| JPS60245164A (en) * | 1984-05-18 | 1985-12-04 | Fujitsu Ltd | Manufacture of diode array |
| GB2167621B (en) * | 1984-11-27 | 1988-03-02 | Crystalate Electronics | Programmed matrix device |
| US5545904A (en) * | 1986-01-17 | 1996-08-13 | Quick Technologies Ltd. | Personalizable gate array devices |
| IL86162A (en) * | 1988-04-25 | 1991-11-21 | Zvi Orbach | Customizable semiconductor devices |
| US4924287A (en) * | 1985-01-20 | 1990-05-08 | Avner Pdahtzur | Personalizable CMOS gate array device and technique |
| US5679967A (en) * | 1985-01-20 | 1997-10-21 | Chip Express (Israel) Ltd. | Customizable three metal layer gate array devices |
| US5329152A (en) * | 1986-11-26 | 1994-07-12 | Quick Technologies Ltd. | Ablative etch resistant coating for laser personalization of integrated circuits |
| IL82113A (en) * | 1987-04-05 | 1992-08-18 | Zvi Orbach | Fabrication of customized integrated circuits |
| DE3731621A1 (en) * | 1987-09-19 | 1989-03-30 | Texas Instruments Deutschland | METHOD FOR PRODUCING AN ELECTRICALLY PROGRAMMABLE INTEGRATED CIRCUIT |
| US4929995A (en) * | 1988-02-16 | 1990-05-29 | Honeywell Inc. | Selective integrated circuit interconnection |
| JP2778977B2 (en) * | 1989-03-14 | 1998-07-23 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| JPH03225868A (en) * | 1990-01-30 | 1991-10-04 | Hitachi Ltd | Solid-state image pickup element and image pickup device using same |
| JPH0461162A (en) * | 1990-06-22 | 1992-02-27 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPH04115565A (en) * | 1990-09-05 | 1992-04-16 | Mitsubishi Electric Corp | Semiconductor memory device |
| GB9113795D0 (en) * | 1991-06-26 | 1991-08-14 | Philips Electronic Associated | Thin-film rom devices and their manufacture |
| US5811869A (en) * | 1996-01-04 | 1998-09-22 | Micron Technology, Inc. | Laser antifuse using gate capacitor |
| IL116792A (en) * | 1996-01-16 | 2000-01-31 | Chip Express Israel Ltd | Customizable integrated circuit device |
| US5742555A (en) | 1996-08-20 | 1998-04-21 | Micron Technology, Inc. | Method of anti-fuse repair |
| TW306005B (en) * | 1996-11-22 | 1997-05-21 | United Microelectronics Corp | Decoding method of diode-type read only memory array |
| DE19713173C2 (en) * | 1997-03-27 | 2001-02-15 | Siemens Ag | ROM memory |
| US5831893A (en) * | 1997-05-13 | 1998-11-03 | Sipex Corporation | Memory cell |
| KR100263476B1 (en) * | 1998-03-24 | 2000-09-01 | 김영환 | Method for forming variable circuit connector |
| US5885873A (en) * | 1998-04-20 | 1999-03-23 | Texas Instruments--Acer Incorporated | Double coding processes for mask read only memory (ROM) devices |
| US6836000B1 (en) | 2000-03-01 | 2004-12-28 | Micron Technology, Inc. | Antifuse structure and method of use |
| JP4010091B2 (en) * | 2000-03-23 | 2007-11-21 | セイコーエプソン株式会社 | Memory device and manufacturing method thereof |
| US6964906B2 (en) * | 2002-07-02 | 2005-11-15 | International Business Machines Corporation | Programmable element with selectively conductive dopant and method for programming same |
| US7084053B2 (en) * | 2003-09-30 | 2006-08-01 | Intel Corporation | Unidirectionally conductive materials for interconnection |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3763476A (en) * | 1972-03-15 | 1973-10-02 | Gen Electric | Method and apparatus for storing and reading out charge in an insulating layer |
| US3860915A (en) * | 1973-06-29 | 1975-01-14 | Geier Karl Heinz | Matrix arrangement for operating optical elements |
| US4032373A (en) * | 1975-10-01 | 1977-06-28 | Ncr Corporation | Method of manufacturing dielectrically isolated semiconductive device |
| US4130891A (en) * | 1977-08-08 | 1978-12-19 | General Electric Company | Methods of gray scale recording and archival memory target produced thereby |
-
1979
- 1979-01-05 US US06/001,360 patent/US4233671A/en not_active Expired - Lifetime
- 1979-12-28 JP JP17390079A patent/JPS5593254A/en active Pending
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1980
- 1980-01-04 DE DE8080300034T patent/DE3063206D1/en not_active Expired
- 1980-01-04 CA CA000343099A patent/CA1137630A/en not_active Expired
- 1980-01-04 EP EP80300034A patent/EP0013603B1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE3063206D1 (en) | 1983-07-07 |
| EP0013603B1 (en) | 1983-05-18 |
| US4233671A (en) | 1980-11-11 |
| EP0013603A1 (en) | 1980-07-23 |
| JPS5593254A (en) | 1980-07-15 |
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