CA1137645A - Serial storage subsystem for a data processor - Google Patents
Serial storage subsystem for a data processorInfo
- Publication number
- CA1137645A CA1137645A CA000349770A CA349770A CA1137645A CA 1137645 A CA1137645 A CA 1137645A CA 000349770 A CA000349770 A CA 000349770A CA 349770 A CA349770 A CA 349770A CA 1137645 A CA1137645 A CA 1137645A
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- Prior art keywords
- data
- data storage
- processor
- storage
- processor means
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
- G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0638—Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
- G06F5/085—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register in which the data is recirculated
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Information Transfer Systems (AREA)
- Memory System (AREA)
- Communication Control (AREA)
- Image Input (AREA)
- Multi Processors (AREA)
Abstract
Abstract A serial storage subsystem for a data processor is provided. The system includes a first processor and a first data storage device including a plurality of data storage locations for storing data. A
second data storage device includes a plurality of data storage locations for storing data. A control device is provided and is associated with the first processor for selecting one of the plurality of data storage locations of the first data storage device as an access window for accessing the second data storage device, such that the first processor gains access to at least one of the plurality of data storage locations of the second data storage device by addressing a selected one of the plurality of data storage locations of the first data storage device. The system further includes a second processor responsive to the first processor for transferring data between the selected one of the plurality of data storage locations of the first data storage device and at least one of the plurality of data storage locations of the second data storage device.
B11,242
second data storage device includes a plurality of data storage locations for storing data. A control device is provided and is associated with the first processor for selecting one of the plurality of data storage locations of the first data storage device as an access window for accessing the second data storage device, such that the first processor gains access to at least one of the plurality of data storage locations of the second data storage device by addressing a selected one of the plurality of data storage locations of the first data storage device. The system further includes a second processor responsive to the first processor for transferring data between the selected one of the plurality of data storage locations of the first data storage device and at least one of the plurality of data storage locations of the second data storage device.
B11,242
Description
~ ~ ~L376~
SI~ L. ';TOI~AGE sunsYs'l'r`M FOR ~\ DF~TA PROCES~()R
_ _ DE~CRIPTION
Technical Field __ This invention relates to computer systems and data storage subsystems, and more particularly to a multiple dimensioned address space storage system using block storage devices.
E3ackground Art A continuing problem facing computer designers ln and computer programmers is the need to minimize the cost of computer memory without increasing the access time required to locate desired data. Memory devices from which comp~ter programs derive direct data are typically referred to as main or primary memories, and as such must be capable of providing data in various lengths or words. Secondar~ memory storage devices, such as magnetic drums, dis~s or tapes, typically store large quantities of clata which is provided to the primary memory in blocks under control of programmer read and write instructions.
Additionally, ty~ically in the art, address informatiol- for a data element is treated as a data element itself. The largest representation of a ~ data object has become the largest representation of an adc3ress. Therefore, computer architecture has ex~anded to store larger addresses and extended address information at greater expenses. The alternative to such expansion is smaller address space resulting in limited computer usaye.
Prior art memories have been technologically limited to sequential or random access linear lists, which often require that their contents be 1311,~2 13C~-7~-027 ~376~5 continuou~sly reorgani7.ed by programmed instructions.
Typieal mell~ories are organized as sequentially or randomly accessed wordwise-linear, one-climensional lists. ~c3clitionally, stacks and queues are examples of commonly used information structures whieh are not random access.
It has also been proposed to use multi-dimcnsional arrays for memory deviees. Prior art memories include subscripted arrays whieh are lineari%ed throuyh eomplex address translation techniques. Dimensionality refers to the numbeL^
of coordinates of a memory. In a random access, worc3wise one-dimensional linear memory, an n~dimensional array is linearized. Extensive program manipulation is required for sueh linearization.
A need has thus arisen for a multidimensional melnory whiell is invisible or internal to the eomputer arehiteeture for the storage and transfer of blocks of information and whieh does not require progralnmer manipulation. Such a memory system would enable the amount of storage s~aee in a data proeessor to ~e inereased without inereasing the main storage addressing requirements. A
need has further arisen for the use of block storage deviees in combination with direet memory aecess teellniques for implementing state of the art teehnology in memory devices.
Summary Of The Invention In accordance with the present inventionr a serial storage subsystem for a data processor is provided. The system includes a first processor and a first data storage device inelucling a plurality Bl1,2~2 BC9-7~-027 ~37~
of data stora(3e locations for storing data.
second data storage device includes a plurality of data storage locations for storincl data. ~ control device is provided and is associated with the first processor for selecting one of the plurality of data stora~e locations of the first data storage device as an access window for accessing the seconcl data storage device, such that the first processor gains access to at least one of the plurality of data storage locations of the second data storage device by addressing a selected one of the plurality of data storage locations of the first clata storacJe device. The system further includes a second processor responsive to the first processor for transferring clata between the selected one of the plurality of data storage locations of the first data stOraCJe device and at least one of the plurality of data storage locations of the seconcl data storage device.
In accordance with another aspect of the present invention, a storage subsystem for a data processor is provided. The system includes a first processor and a random access data storage device associated with the first processor which inclucles a plurality of data stora~e location~ for storing ~ata. A serial block storage device is provided and includes a plurality of data storage locations of variable widths for storing data. A control device is coupled to the first processor for selecting one of the plurality of data storage locations from the random acces~s data storage device as an access window for acce~ssing at least one of the plurality of data storage locations of the serial block storage device.
A second processor is provided and is responsive to ~311,~
13C9-7~3-027 ~ ~ 3~
the first processor for translerring data hetween the selected one of the plurality of data storaye locations oL the random access data storaye device and at least one of the plurality of data storaye locations of the serial block storage device. A
buffer device is associated with the first processor and a buffer device is associated with the serial block storage device. The buffers temporarily store data prior to data transfer between the storage clevices to thereby increase the s~eed at which data is transferred between the storage devices.
Brief Description of the Drawings For a more detailed description of the present invention and for further objects and advantages thereof, reference is made to the following Description, taken in conjunction with the followiny Drawinys in which:
FIGURE 1 is a schematic block diagram of the major comuonents of a data processiny system incorporating the storage subsystem of the present invention;
FIGURF. 2 is a more detailed schematic block diagram of a data processing system incorporating the present storage subsystem;
FIGURE 3 is a schematic block diagram of a data processing system incorporating the data buffering aspect of the present invention;
FIGURE 4 is a graphical illustration of data storage locations of a block store shown in a riny confiyuration; and FIGUr~E 5 is a schematic block diayram illustratin~ the use of the uresent invention for multiplexing of data from an input/output device.
~11,2~2 e(:~-7~-027 ~3~5 l)escril~tion of ti)e PreEerret3 ~mbodiment ~ eferriny to FIG~RE 1, the major components of a data processing system in which the present serial storage subsystem is utilized is illustrated.
'I`he system includes a data processor generally identified by the numeral 10 and a microprocessor 12.
With certain minor exceptions, the general form of microprocessoL- 12 construction is shown and described in connection with FIGUR~ 17 of United States Patent l~o. 4,038,642 entitled "Input/Output Interface Logic for Concurrellt Operations" granted to Bou~necht et al on July 26, 1977 and assigned to International Business riachines Corporation of Armonk, New York, ~ssociated witll microprocessor 12 is a maill storage device 14 for storing ~rogram instructions and data.
proyram is executed by reading its instructions out of main storage devlce 14 in a sequential manner.
~ssociated ~ith main storage device 14 is a storage address reyister (SAR) 16 which stores the next instruction address for purposes of addressing the next instruction in main storage device 14 via signal lines 18a and 18b.
Main storaye device 14 includes a plurality of storage locations for storing data and instructions.
~or example, ~ata storaye locations ea identified by the numeral 22 and data stora(3e locations eb idelltified by nulneral 2~ are illustrated in FIGURE 1.
Data storage locations 22 and 24, as illustrated, are of variable widths for storing data of different lellyth words, ~]1,242 ~C'~-7~-U27 ~376f~tj G
Thc SC'I ial storage subsystem of the prcsent inventiorl is generally identified by the numeral 30 and comprises a plurality of auxiliary serial block storage devices, illustrated in FI~,UR~ 1, as including serial block storage devices 32 and 34.
Serial bloc~ storage device 32 includes a plurality of data storage locations 36 having a width correspondint3 to the width of data storage location 22 of Main storage deviee 14. Similarly, serial block storage device 34 ineludes a plurality of data storage locations 33 eorrespondinc3 in width to the width o~ data storage location 24 of main storage device 14. ~lthough two serial bloc~ storage deviees 32 anc~ 34 are illustrated as eomprising the serial storaye subsystem 30, it is understood that any number of variable width auxiliary storage deviees ean be appended to a eorresponding number of data storage locations within main storac3e cleviee 1~.
Aeeess to serial storage subsystem 3n is obtained by addressing a seleeted data storac3e loeation within main storage deviee 14 by storage address register 16 whieh locates the first or only word in the seleeted data storac3e location.
Therefore, the selected data storage location within main storac~e deviee 14 serves as an "aecess window"
to serial storage subsystem 30. For example, data storage location 22 of main storage clevice 14 serves as an aecess window to serial bloe~ storac3e deviee 32 and the plurality of data storage locations 36.
Communication between main storage ~eviee 14, microprocessor 12 and serial storage subsystem 30 is via an access meehanism ~2, shown in FIGURE 1 as signal lines 42a and 42b. It therefore ean be seen that additional au~xiliary data storage loeations within serial storage subsystem 30 ean be apr~er)ded to other data storage loeations within r~ 12 ~C~-7~~027 ~3~
!il.lill stora(~c device 14 to furthcr increa,e the stora~3e capilcity o~ data processor 10 without increasing the number of addressable main storage locations within main storage device 14. ~hereEore, an important aspect of the present invention is that a third dilllension is, in effect, added to main stora~e device 14.
As used herein, a "data stora~e location" is cor~l~rised of, for example, at least eiyht bits~
Wider data elements occupy an assigned nnmber oE
conti(3uous storac3e locations. ~hen a data element stored in a data stora~e location is trans~erred, the various bits thereof are transferred in a parallel simultaneous manner. ~s used herein, "data element" includes both address information as t~ell as data information.
Serial hlock storage devices 32 and 34 of serial stbrage subsystem 30 may comprise numerous block stora~e devices in which data is serlally stored.
These devices may inclu~e, for example, a charge coupled storage device manufactured by Texas InstLuments Incorporated, Model Mo. T~IS 306~ JL
wllich is a 65,536-bit CCI) memory device describecl in "~lOS ~5~mory ~ata ~oo~" published by Texas Instruments Incorporated and dated 1373. Such a char~e coupled device is also described in United States Patent No.
3,947,69% issued to Cheek, ~r. et al on ~larcll 30, 1976 and elltitled "Charge Coupled Device ~lultiplexer". Alternatively, serial bloc~ storage devices 32 an(1 34 may comprise magnetic bubble stora~e ~]evices such as a ~50del No. TI~0203 ~agnetic bubble melnory manufactured and sold by Texas Instruments Inc. Such magnetic bubble storage devices are described ir. United States Patent ~o~
~,090,251 issued to Flannigan et al on ~lay 16, 197%
n l 1 , 2~2 " ,~
~7~
ar)t3 cntiLlcd "13ubhle ~qelnory ~edundancy ~torage".
~dditionally~ electron beam addrt-~ssable storage devices and optical beam storage devices may be utilized in thc present invention.
Referring to FIGURE 2, an imp1ementation of the present serial storage subsystem 3~ is illustrated.
Data processor lO may comprise, for example, a host processor and ineludes a central processing unit (CP~) 50 intercollneeted to SAR l~ via signal line 52. Central processing unit 50 performs clata processillg and control functions in response to prograln instructions stored in main storage device l~. CP~ 50 is interconneeted via a data bus 54 to microprocessor 12 within serial storage subsystem 30. i~icroprocessor 12 manages serial block storage device 32.
Serial block storage device 32 inclucles a plurality of data storage locations 36 which can be reached in a one-after-the-other manner, serially, as opposed to a random manner. Serial bloclc storage device 32 is operated as a storage ~staclc of either the last-in-first-out (LIFO) type or th* first-in-first-out (FIFO~ type. The LIFO type is known as a "~ush(lowrl" stack wherein each new data element is aclcle-l to the top of the stack with the e.~isting elem~nts in the stack being pushed or transferred down one data storage location. This operation is referred to as a "push" operation.
Conversely, when transferring data from serial block storage device 32, the data stored within the top data storage loeation is removed from the staek and tlle remaining elemellts within the staek are transferrecl up or are "popped" up a data storage location in the stack. This operation is lcnown as a 1311,2~
13C:t~-7~-027 ~37~
"pop" opcration. For the ~IFO type operation, eacl new elcment is added to the bottom of the stack and old elements move one position closer to the top of the stack when a data element is remove-3 from the top ~;
of the stack. Serial block storage device 32 permits successive data elements to be located arouncl a closed loop path which are accessed in serial order as they move past a fixed read/write c~evice 5 (FIGURE 2)~ ~1icroprocessor 12 is interconnected via a bus 60 to a suitable read/write device 5~ for inputting and receiving data from serial block storage device 32. Serial block storage device 32 is symbolically represented by a rotatable wheel throughout the Figures to indicate the serial order and closecl loop path aspect of the serial block storage devices associated with serial stora~e subsystem 30 of the present invention. The serial : :
storaye subsystem of the present invention is ~:
thereEore particularly well-suited for implementation ~.
o~ LIFO ancl FIFO stack structures.
Each data storage location 3~ within serial b].ock storage device 32 is capable of storing a .-single stack element which includes an index num:ber field and a data element field. The index numbers : 25 are assiyned in numerical or~er to the successive . clata storaye locations 36:stored within serial block - stora(3e device 32. In operation of the pre~,ellt invention in a direct inquiry mode, microprocessor 12 can respond to an index number request to position serial block storage device 32 via serial storage access mechanism represented symbolically by signal line 42a so as to position the particular data -~
storage location 36 havin3 the correspondin~ index number i.n alignment with the read/write device 5~.
Cll/242 ~3C9-7~-027 ~37~f~5 :Ln r~Or l,I~'O alld ~IF~ operations, microproce.ssor 12 is operable to move serial bloek storage device 32 one po.sition ~orward or baekward.
~ata ~)rocessor 10 includes "push" ancl "pop"
instructions for adding and removing data elements from clata stacks or data ~ueues located in main storage deviee 1~. A "push" instruetion adds a n~w data element to a data storage loeation 36 of serial bloek storage deviee 32 and, in tlle LIFO
~eration, data proeessor 10 moves an existinq stack element by one position within a data stora~e location 36 to make room for the new ac]ded data element.
Conversely, a "pop" instruetion from data proeessor 10 removes a data element from serial bloek storage deviee 32 and moves the remaining staek elemellts to a position towards the top of the staek.
~or a read instruetion from data processor 10, the top data element of serial bloek storage deviee 32 is simply read, but the remaining staek elements are not movecl or changed in number. Sim;.larly, for a write instruction from c]ata proeessor 10, new data is written into the top data element of data stora~e loeation 36 of serial block storage device 32, but agaill the stack elements are not moved or ehanc3ed in number. In other worc3s, read and write instruetions do not challge the number of ~3ata elements within the plurality of data storage loeations 36 and do not eause any ehange in the staek indexing mechanism.
The seleeted main storage deviee 1~ f~FIG~E 2) data storage loeation, such as data storage location 22, serves as an access window to serial block storage cleviee 32. The seleeted data storage loeation 22, in effeet, represents the "to~" data nll,2~?
~C'~-7~-f)~7 ~L~3~9L5 11 !
-elcment storecl in data storage locations 36 of serial block storage clevice 32 as far as the program being executed in data proces.sor 10 is concerned. I~hen c]ata processor 10 encounters in its program instruction stream a push instruction, which includes the main storage address of the selected location within main storage device 14, data processor 10 writes the clesired data element into the data storage location within rnain storage device 14 and signals to microprocessor 12 to add a data element to serial block storage device 32. ~licroprocessor 12 records this data element in an empty storage location within the plurality of data storage locations 36 of serial block stora(3e clevice 32 and advances serial block lS storage device 32 to the next empty data storage location 36. Should data processor 10 encounter in its instruction stream a pop instruetion, containinc~
tlle address of a clata storage loeation within rnain stora(3e c]evice 14, data proeessor 10 signals microprocessor 12 that a stack element from serial bloek storac3e deviee 32 is needed. ~lieroprocessor 12 then transfers the appropriate element from data stora~e location 3G to CPU 50 via data bus 54 wllich in turn causes storaye of the selecte(l element into tlle selected data storaye location wittiin main storage clevice 1~ via data bus 56. ~licroprocessor 12 then indieates that the seleeted data storaye location 36 is empty and advances serial block storaqe device 32 one position in the appropriate direction.
Referriny now to FIC~URE 3, wherein like numerals are utilized for like and correspondinc3 eomponents previously iclentified, a further embodiment of the present invention is illustrated. As is shown in EI~.UI~ 1, El~llR~ 3 illustrates serial block storage devices 32 and 34 each having its own separate access 1311,2~2 l3C9-7~3-027 ~3~76~5 ~in(3o~ in main storage dcvice l4 de~si(31late(1 as data storage locations 22 and 24. Microprocessor 12 is illustratc!cl as including a microproce~ssor CPU 70, a microprocessor storat~e deviee 72 and a storage address re~ister (S,~R) 74 by which microprocessor CPU 70 addresst-~s microprocessor storage device 72. S~R 74 applies an address via sitJnal line 76 to microprocessor storage device 72 ancl re~ceivQs addres~
inormation from microproeessor CPU 70 via .signal line 73. ~iieroprocessor storage deviee 72 and microproces~or CPU 70 communicate via bu~s 3n.
~ n irnportant aspect of the present invention, as illustrated in FIGURE 3, is the use of a data buffering arrangement for use with each serial block storage clevice 32 and 34. Data buffers 90 and 92 are provided within data proeessor 10 and eommunieate with CPU 50 via data buses 94 and '~6. Data buffer 90 is used in conjunetion with serial block storage device 32, and data buffer 92 is useci in conjunction 2n with serial block storage deviee 34. A stack element data buffer area lnn and a stack element data buffer area 102 are ~rovided within microprocessor storage device 72 and funetion in eonjunetion ~ith serial block storage deviees 32 and 34. Data buf'cer 90 is designecl to store a single staek element, particularly, a data element and its accompanying index number and can be located in main storage device l~, or as indicatecl in FIG~r~ 3, can form a discrete hard~are register. Data buffer area lO0, ~ithin microprocessor storage deviee 72, stores several clata elements from serial bloek storage device 3~ and stores both an index number and a data element.
~hen c1ata elements are beincl addecl to data storage locations within serial bloe]~ storage deviee 32, eacll data element prot~re.sses from main storage 1311,2~2 ~,C9-7~-027 ~37~4S
.L3 dc)vice 14 through an access winclow such a.s data storage location 22 to data huffer 90 and then to data buffer area 100 within microprocessor storage clevice 72. After a predetermined number of data elements have been accumulated in data buffer area lnn, thc?y are transferred as a group to serial block storaye device 32 wherein each eIement is placecl in a respective data storage location 36 within serial block storage device 32.
In operation, when data elements are being removecl from serial block storage device 32, these elements are transferred to data buffer area 100 within microprocessor storage device 72 and via microprocessor CPU 70 are transferred to main storage device 14 and data storage loeations, such as data storage location 22. The stored data elements within data buffer area 100 of microprocessor storage device 72 are transferred individually to clata buffer 90 for ultimate storage within data storage location 22.
.20 After a supply of data elements frorn data buffer area :~
100 has been e~haustecl, another gro~lp of clata elements and their accompanying index n~lmbers are transferred from serial block storaye device 32 to data buffer area 100. :
The buffering arrangement of the present invention, previously d.escribed, improves thc? speed at which data elements may be transferred to or from serial block storage device 32 to enable continuous processing of data elements at effective rates approaching that of the data handling rate of clata processor 10. In a similar manner, serial bloek storage device 3~ is provided with a data buffer 92 in c3ata processor 10 and a stack element clata.buffer area 10 is provided within microprocessor storage 35 clcvice 72. This buffer arrangement works in the sa~e ~:
ell,242 ~3C~-7~-027 ~1376~
.
1 manner as does the buffer arrangement previously des-cribed relating to serial block storage device 32.
Microprocessor 12 operates asynchronously with respect to data processor 10 in order to maintain data buffers 90 and 92 filled and current.
As shown in FIGURE 4, each data storage location 36 and 38 is capable of storing a single stack element which includes an index number (i) and a data element field (e). The current element within main storage device 14 is denoted by the letter "e" having an index "i". The "next" element present within a data buffer 90 or data buffer 92 (FIGURE 3) is indicated by "e"' having an index "i"'. FIGURE 4 further illustrates serial block storage devices 32 and 34 as a reel or closed ring having a head, 36a and 38a, and tail 36b and 38b. The index "1" is a circular link for the head of the ring and the highest index number (N) in-dicates the tail of the ring. A null or empty storage location 36c and 38c is disposed between the head and tail. A clean bit is utilized in the index number field to avoid unnecessary moves of serial block stor-age devices 32 and 34. The index "0" is a circular link to an index "1" and follows "last in". Index "1" implies "first in"~ If FIFO access has been de-clared, the value of i' of data buffer 90 would be (i+l). If LIFO access had been declared, the value of i' would be (i-l). For direct index access, the value of i' would be i. Data buffer 90 is therefore a look-ahead processing element, or a store through cache in direct inquiry to data elements. Serial block storage devices 32 and 34 in effect can rotate as a "wheel" in a "forward", (i+l), direction or a "reverse", (i-l), direction. A buffer management BC9-78~027 ~l3~6~S
.
system is described in United ~tates ratent Mo.
3,5~ 3~ iss~ec1 to Belady et al on ~une 2~ 71 and entitlec3 "llierarchical Memory Updating ~ystem".
~IGUR~ 5 illustrates yet another aspect of tlle present invention wherein a data multiplexing function is per~ormed using the present serial storac~e subsystem 30. In this aspect of the present invention, there is direct access to serial block storage devices by input/output (I/O) clevices. I/O
devices 110 apply data elements via signal lines 112 to microprocessor 12. Each data element includes a serial block storage device identification field, a position ield and a data field. The identification field indicates which one or more of serial block storage devices, for example, 116, 118 or 120 will receive the data element. ~lso, thè position of the storage location within each serial block storage device 116, 11~ or 1?.0 is designated. ~licroprocessor 12 a~ain performs a controller function and applies data via signal lines 122, 124 and 126 to serial block storage devices 116, 118 ancl 120. Therefore, all or a selected portion of a data element rnay be placed in one or any set of serial block storage c3evices 1l~ r 11~ or 120 and within a similar data storage location. Therefore, data may l~e acquired from I/~ devices and used in different sequences and arrangelllents using the serial storage subsystem of the present invention.
It therefore can be seen that the present invelltion enables the amount of storage space in a data processor to be increased without increasing the main storage addressing requirements by providing a third dilnellsion to data storage utilizincl a serial blocli storage device. ~he serial block storage devices utilized with the present invention can he of l~11,242 BC()-7~-027 1:~L376~
1~) variable WidttlS and various numbers oE serial bloclc storac3e (levices may be uti1ized depending upon the coniyuration and architecture of the data processing sytem.
~hereas the present invention has been described with resE~ect to specific embodiments thereof, it will be understood that various changes and modiEications will be sugyested to one skilled in the art, and it is intended to encompass such changes and modifications that fall within the scope of the appendecl claims.
nll,242 ~3~9-7~-027
SI~ L. ';TOI~AGE sunsYs'l'r`M FOR ~\ DF~TA PROCES~()R
_ _ DE~CRIPTION
Technical Field __ This invention relates to computer systems and data storage subsystems, and more particularly to a multiple dimensioned address space storage system using block storage devices.
E3ackground Art A continuing problem facing computer designers ln and computer programmers is the need to minimize the cost of computer memory without increasing the access time required to locate desired data. Memory devices from which comp~ter programs derive direct data are typically referred to as main or primary memories, and as such must be capable of providing data in various lengths or words. Secondar~ memory storage devices, such as magnetic drums, dis~s or tapes, typically store large quantities of clata which is provided to the primary memory in blocks under control of programmer read and write instructions.
Additionally, ty~ically in the art, address informatiol- for a data element is treated as a data element itself. The largest representation of a ~ data object has become the largest representation of an adc3ress. Therefore, computer architecture has ex~anded to store larger addresses and extended address information at greater expenses. The alternative to such expansion is smaller address space resulting in limited computer usaye.
Prior art memories have been technologically limited to sequential or random access linear lists, which often require that their contents be 1311,~2 13C~-7~-027 ~376~5 continuou~sly reorgani7.ed by programmed instructions.
Typieal mell~ories are organized as sequentially or randomly accessed wordwise-linear, one-climensional lists. ~c3clitionally, stacks and queues are examples of commonly used information structures whieh are not random access.
It has also been proposed to use multi-dimcnsional arrays for memory deviees. Prior art memories include subscripted arrays whieh are lineari%ed throuyh eomplex address translation techniques. Dimensionality refers to the numbeL^
of coordinates of a memory. In a random access, worc3wise one-dimensional linear memory, an n~dimensional array is linearized. Extensive program manipulation is required for sueh linearization.
A need has thus arisen for a multidimensional melnory whiell is invisible or internal to the eomputer arehiteeture for the storage and transfer of blocks of information and whieh does not require progralnmer manipulation. Such a memory system would enable the amount of storage s~aee in a data proeessor to ~e inereased without inereasing the main storage addressing requirements. A
need has further arisen for the use of block storage deviees in combination with direet memory aecess teellniques for implementing state of the art teehnology in memory devices.
Summary Of The Invention In accordance with the present inventionr a serial storage subsystem for a data processor is provided. The system includes a first processor and a first data storage device inelucling a plurality Bl1,2~2 BC9-7~-027 ~37~
of data stora(3e locations for storing data.
second data storage device includes a plurality of data storage locations for storincl data. ~ control device is provided and is associated with the first processor for selecting one of the plurality of data stora~e locations of the first data storage device as an access window for accessing the seconcl data storage device, such that the first processor gains access to at least one of the plurality of data storage locations of the second data storage device by addressing a selected one of the plurality of data storage locations of the first clata storacJe device. The system further includes a second processor responsive to the first processor for transferring clata between the selected one of the plurality of data storage locations of the first data stOraCJe device and at least one of the plurality of data storage locations of the seconcl data storage device.
In accordance with another aspect of the present invention, a storage subsystem for a data processor is provided. The system includes a first processor and a random access data storage device associated with the first processor which inclucles a plurality of data stora~e location~ for storing ~ata. A serial block storage device is provided and includes a plurality of data storage locations of variable widths for storing data. A control device is coupled to the first processor for selecting one of the plurality of data storage locations from the random acces~s data storage device as an access window for acce~ssing at least one of the plurality of data storage locations of the serial block storage device.
A second processor is provided and is responsive to ~311,~
13C9-7~3-027 ~ ~ 3~
the first processor for translerring data hetween the selected one of the plurality of data storaye locations oL the random access data storaye device and at least one of the plurality of data storaye locations of the serial block storage device. A
buffer device is associated with the first processor and a buffer device is associated with the serial block storage device. The buffers temporarily store data prior to data transfer between the storage clevices to thereby increase the s~eed at which data is transferred between the storage devices.
Brief Description of the Drawings For a more detailed description of the present invention and for further objects and advantages thereof, reference is made to the following Description, taken in conjunction with the followiny Drawinys in which:
FIGURE 1 is a schematic block diagram of the major comuonents of a data processiny system incorporating the storage subsystem of the present invention;
FIGURF. 2 is a more detailed schematic block diagram of a data processing system incorporating the present storage subsystem;
FIGURE 3 is a schematic block diagram of a data processing system incorporating the data buffering aspect of the present invention;
FIGURE 4 is a graphical illustration of data storage locations of a block store shown in a riny confiyuration; and FIGUr~E 5 is a schematic block diayram illustratin~ the use of the uresent invention for multiplexing of data from an input/output device.
~11,2~2 e(:~-7~-027 ~3~5 l)escril~tion of ti)e PreEerret3 ~mbodiment ~ eferriny to FIG~RE 1, the major components of a data processing system in which the present serial storage subsystem is utilized is illustrated.
'I`he system includes a data processor generally identified by the numeral 10 and a microprocessor 12.
With certain minor exceptions, the general form of microprocessoL- 12 construction is shown and described in connection with FIGUR~ 17 of United States Patent l~o. 4,038,642 entitled "Input/Output Interface Logic for Concurrellt Operations" granted to Bou~necht et al on July 26, 1977 and assigned to International Business riachines Corporation of Armonk, New York, ~ssociated witll microprocessor 12 is a maill storage device 14 for storing ~rogram instructions and data.
proyram is executed by reading its instructions out of main storage devlce 14 in a sequential manner.
~ssociated ~ith main storage device 14 is a storage address reyister (SAR) 16 which stores the next instruction address for purposes of addressing the next instruction in main storage device 14 via signal lines 18a and 18b.
Main storaye device 14 includes a plurality of storage locations for storing data and instructions.
~or example, ~ata storaye locations ea identified by the numeral 22 and data stora(3e locations eb idelltified by nulneral 2~ are illustrated in FIGURE 1.
Data storage locations 22 and 24, as illustrated, are of variable widths for storing data of different lellyth words, ~]1,242 ~C'~-7~-U27 ~376f~tj G
Thc SC'I ial storage subsystem of the prcsent inventiorl is generally identified by the numeral 30 and comprises a plurality of auxiliary serial block storage devices, illustrated in FI~,UR~ 1, as including serial block storage devices 32 and 34.
Serial bloc~ storage device 32 includes a plurality of data storage locations 36 having a width correspondint3 to the width of data storage location 22 of Main storage deviee 14. Similarly, serial block storage device 34 ineludes a plurality of data storage locations 33 eorrespondinc3 in width to the width o~ data storage location 24 of main storage device 14. ~lthough two serial bloc~ storage deviees 32 anc~ 34 are illustrated as eomprising the serial storaye subsystem 30, it is understood that any number of variable width auxiliary storage deviees ean be appended to a eorresponding number of data storage locations within main storac3e cleviee 1~.
Aeeess to serial storage subsystem 3n is obtained by addressing a seleeted data storac3e loeation within main storage deviee 14 by storage address register 16 whieh locates the first or only word in the seleeted data storac3e location.
Therefore, the selected data storage location within main storac~e deviee 14 serves as an "aecess window"
to serial storage subsystem 30. For example, data storage location 22 of main storage clevice 14 serves as an aecess window to serial bloe~ storac3e deviee 32 and the plurality of data storage locations 36.
Communication between main storage ~eviee 14, microprocessor 12 and serial storage subsystem 30 is via an access meehanism ~2, shown in FIGURE 1 as signal lines 42a and 42b. It therefore ean be seen that additional au~xiliary data storage loeations within serial storage subsystem 30 ean be apr~er)ded to other data storage loeations within r~ 12 ~C~-7~~027 ~3~
!il.lill stora(~c device 14 to furthcr increa,e the stora~3e capilcity o~ data processor 10 without increasing the number of addressable main storage locations within main storage device 14. ~hereEore, an important aspect of the present invention is that a third dilllension is, in effect, added to main stora~e device 14.
As used herein, a "data stora~e location" is cor~l~rised of, for example, at least eiyht bits~
Wider data elements occupy an assigned nnmber oE
conti(3uous storac3e locations. ~hen a data element stored in a data stora~e location is trans~erred, the various bits thereof are transferred in a parallel simultaneous manner. ~s used herein, "data element" includes both address information as t~ell as data information.
Serial hlock storage devices 32 and 34 of serial stbrage subsystem 30 may comprise numerous block stora~e devices in which data is serlally stored.
These devices may inclu~e, for example, a charge coupled storage device manufactured by Texas InstLuments Incorporated, Model Mo. T~IS 306~ JL
wllich is a 65,536-bit CCI) memory device describecl in "~lOS ~5~mory ~ata ~oo~" published by Texas Instruments Incorporated and dated 1373. Such a char~e coupled device is also described in United States Patent No.
3,947,69% issued to Cheek, ~r. et al on ~larcll 30, 1976 and elltitled "Charge Coupled Device ~lultiplexer". Alternatively, serial bloc~ storage devices 32 an(1 34 may comprise magnetic bubble stora~e ~]evices such as a ~50del No. TI~0203 ~agnetic bubble melnory manufactured and sold by Texas Instruments Inc. Such magnetic bubble storage devices are described ir. United States Patent ~o~
~,090,251 issued to Flannigan et al on ~lay 16, 197%
n l 1 , 2~2 " ,~
~7~
ar)t3 cntiLlcd "13ubhle ~qelnory ~edundancy ~torage".
~dditionally~ electron beam addrt-~ssable storage devices and optical beam storage devices may be utilized in thc present invention.
Referring to FIGURE 2, an imp1ementation of the present serial storage subsystem 3~ is illustrated.
Data processor lO may comprise, for example, a host processor and ineludes a central processing unit (CP~) 50 intercollneeted to SAR l~ via signal line 52. Central processing unit 50 performs clata processillg and control functions in response to prograln instructions stored in main storage device l~. CP~ 50 is interconneeted via a data bus 54 to microprocessor 12 within serial storage subsystem 30. i~icroprocessor 12 manages serial block storage device 32.
Serial block storage device 32 inclucles a plurality of data storage locations 36 which can be reached in a one-after-the-other manner, serially, as opposed to a random manner. Serial bloclc storage device 32 is operated as a storage ~staclc of either the last-in-first-out (LIFO) type or th* first-in-first-out (FIFO~ type. The LIFO type is known as a "~ush(lowrl" stack wherein each new data element is aclcle-l to the top of the stack with the e.~isting elem~nts in the stack being pushed or transferred down one data storage location. This operation is referred to as a "push" operation.
Conversely, when transferring data from serial block storage device 32, the data stored within the top data storage loeation is removed from the staek and tlle remaining elemellts within the staek are transferrecl up or are "popped" up a data storage location in the stack. This operation is lcnown as a 1311,2~
13C:t~-7~-027 ~37~
"pop" opcration. For the ~IFO type operation, eacl new elcment is added to the bottom of the stack and old elements move one position closer to the top of the stack when a data element is remove-3 from the top ~;
of the stack. Serial block storage device 32 permits successive data elements to be located arouncl a closed loop path which are accessed in serial order as they move past a fixed read/write c~evice 5 (FIGURE 2)~ ~1icroprocessor 12 is interconnected via a bus 60 to a suitable read/write device 5~ for inputting and receiving data from serial block storage device 32. Serial block storage device 32 is symbolically represented by a rotatable wheel throughout the Figures to indicate the serial order and closecl loop path aspect of the serial block storage devices associated with serial stora~e subsystem 30 of the present invention. The serial : :
storaye subsystem of the present invention is ~:
thereEore particularly well-suited for implementation ~.
o~ LIFO ancl FIFO stack structures.
Each data storage location 3~ within serial b].ock storage device 32 is capable of storing a .-single stack element which includes an index num:ber field and a data element field. The index numbers : 25 are assiyned in numerical or~er to the successive . clata storaye locations 36:stored within serial block - stora(3e device 32. In operation of the pre~,ellt invention in a direct inquiry mode, microprocessor 12 can respond to an index number request to position serial block storage device 32 via serial storage access mechanism represented symbolically by signal line 42a so as to position the particular data -~
storage location 36 havin3 the correspondin~ index number i.n alignment with the read/write device 5~.
Cll/242 ~3C9-7~-027 ~37~f~5 :Ln r~Or l,I~'O alld ~IF~ operations, microproce.ssor 12 is operable to move serial bloek storage device 32 one po.sition ~orward or baekward.
~ata ~)rocessor 10 includes "push" ancl "pop"
instructions for adding and removing data elements from clata stacks or data ~ueues located in main storage deviee 1~. A "push" instruetion adds a n~w data element to a data storage loeation 36 of serial bloek storage deviee 32 and, in tlle LIFO
~eration, data proeessor 10 moves an existinq stack element by one position within a data stora~e location 36 to make room for the new ac]ded data element.
Conversely, a "pop" instruetion from data proeessor 10 removes a data element from serial bloek storage deviee 32 and moves the remaining staek elemellts to a position towards the top of the staek.
~or a read instruetion from data processor 10, the top data element of serial bloek storage deviee 32 is simply read, but the remaining staek elements are not movecl or changed in number. Sim;.larly, for a write instruction from c]ata proeessor 10, new data is written into the top data element of data stora~e loeation 36 of serial block storage device 32, but agaill the stack elements are not moved or ehanc3ed in number. In other worc3s, read and write instruetions do not challge the number of ~3ata elements within the plurality of data storage loeations 36 and do not eause any ehange in the staek indexing mechanism.
The seleeted main storage deviee 1~ f~FIG~E 2) data storage loeation, such as data storage location 22, serves as an access window to serial block storage cleviee 32. The seleeted data storage loeation 22, in effeet, represents the "to~" data nll,2~?
~C'~-7~-f)~7 ~L~3~9L5 11 !
-elcment storecl in data storage locations 36 of serial block storage clevice 32 as far as the program being executed in data proces.sor 10 is concerned. I~hen c]ata processor 10 encounters in its program instruction stream a push instruction, which includes the main storage address of the selected location within main storage device 14, data processor 10 writes the clesired data element into the data storage location within rnain storage device 14 and signals to microprocessor 12 to add a data element to serial block storage device 32. ~licroprocessor 12 records this data element in an empty storage location within the plurality of data storage locations 36 of serial block stora(3e clevice 32 and advances serial block lS storage device 32 to the next empty data storage location 36. Should data processor 10 encounter in its instruction stream a pop instruetion, containinc~
tlle address of a clata storage loeation within rnain stora(3e c]evice 14, data proeessor 10 signals microprocessor 12 that a stack element from serial bloek storac3e deviee 32 is needed. ~lieroprocessor 12 then transfers the appropriate element from data stora~e location 3G to CPU 50 via data bus 54 wllich in turn causes storaye of the selecte(l element into tlle selected data storaye location wittiin main storage clevice 1~ via data bus 56. ~licroprocessor 12 then indieates that the seleeted data storaye location 36 is empty and advances serial block storaqe device 32 one position in the appropriate direction.
Referriny now to FIC~URE 3, wherein like numerals are utilized for like and correspondinc3 eomponents previously iclentified, a further embodiment of the present invention is illustrated. As is shown in EI~.UI~ 1, El~llR~ 3 illustrates serial block storage devices 32 and 34 each having its own separate access 1311,2~2 l3C9-7~3-027 ~3~76~5 ~in(3o~ in main storage dcvice l4 de~si(31late(1 as data storage locations 22 and 24. Microprocessor 12 is illustratc!cl as including a microproce~ssor CPU 70, a microprocessor storat~e deviee 72 and a storage address re~ister (S,~R) 74 by which microprocessor CPU 70 addresst-~s microprocessor storage device 72. S~R 74 applies an address via sitJnal line 76 to microprocessor storage device 72 ancl re~ceivQs addres~
inormation from microproeessor CPU 70 via .signal line 73. ~iieroprocessor storage deviee 72 and microproces~or CPU 70 communicate via bu~s 3n.
~ n irnportant aspect of the present invention, as illustrated in FIGURE 3, is the use of a data buffering arrangement for use with each serial block storage clevice 32 and 34. Data buffers 90 and 92 are provided within data proeessor 10 and eommunieate with CPU 50 via data buses 94 and '~6. Data buffer 90 is used in conjunetion with serial block storage device 32, and data buffer 92 is useci in conjunction 2n with serial block storage deviee 34. A stack element data buffer area lnn and a stack element data buffer area 102 are ~rovided within microprocessor storage device 72 and funetion in eonjunetion ~ith serial block storage deviees 32 and 34. Data buf'cer 90 is designecl to store a single staek element, particularly, a data element and its accompanying index number and can be located in main storage device l~, or as indicatecl in FIG~r~ 3, can form a discrete hard~are register. Data buffer area lO0, ~ithin microprocessor storage deviee 72, stores several clata elements from serial bloek storage device 3~ and stores both an index number and a data element.
~hen c1ata elements are beincl addecl to data storage locations within serial bloe]~ storage deviee 32, eacll data element prot~re.sses from main storage 1311,2~2 ~,C9-7~-027 ~37~4S
.L3 dc)vice 14 through an access winclow such a.s data storage location 22 to data huffer 90 and then to data buffer area 100 within microprocessor storage clevice 72. After a predetermined number of data elements have been accumulated in data buffer area lnn, thc?y are transferred as a group to serial block storaye device 32 wherein each eIement is placecl in a respective data storage location 36 within serial block storage device 32.
In operation, when data elements are being removecl from serial block storage device 32, these elements are transferred to data buffer area 100 within microprocessor storage device 72 and via microprocessor CPU 70 are transferred to main storage device 14 and data storage loeations, such as data storage location 22. The stored data elements within data buffer area 100 of microprocessor storage device 72 are transferred individually to clata buffer 90 for ultimate storage within data storage location 22.
.20 After a supply of data elements frorn data buffer area :~
100 has been e~haustecl, another gro~lp of clata elements and their accompanying index n~lmbers are transferred from serial block storaye device 32 to data buffer area 100. :
The buffering arrangement of the present invention, previously d.escribed, improves thc? speed at which data elements may be transferred to or from serial block storage device 32 to enable continuous processing of data elements at effective rates approaching that of the data handling rate of clata processor 10. In a similar manner, serial bloek storage device 3~ is provided with a data buffer 92 in c3ata processor 10 and a stack element clata.buffer area 10 is provided within microprocessor storage 35 clcvice 72. This buffer arrangement works in the sa~e ~:
ell,242 ~3C~-7~-027 ~1376~
.
1 manner as does the buffer arrangement previously des-cribed relating to serial block storage device 32.
Microprocessor 12 operates asynchronously with respect to data processor 10 in order to maintain data buffers 90 and 92 filled and current.
As shown in FIGURE 4, each data storage location 36 and 38 is capable of storing a single stack element which includes an index number (i) and a data element field (e). The current element within main storage device 14 is denoted by the letter "e" having an index "i". The "next" element present within a data buffer 90 or data buffer 92 (FIGURE 3) is indicated by "e"' having an index "i"'. FIGURE 4 further illustrates serial block storage devices 32 and 34 as a reel or closed ring having a head, 36a and 38a, and tail 36b and 38b. The index "1" is a circular link for the head of the ring and the highest index number (N) in-dicates the tail of the ring. A null or empty storage location 36c and 38c is disposed between the head and tail. A clean bit is utilized in the index number field to avoid unnecessary moves of serial block stor-age devices 32 and 34. The index "0" is a circular link to an index "1" and follows "last in". Index "1" implies "first in"~ If FIFO access has been de-clared, the value of i' of data buffer 90 would be (i+l). If LIFO access had been declared, the value of i' would be (i-l). For direct index access, the value of i' would be i. Data buffer 90 is therefore a look-ahead processing element, or a store through cache in direct inquiry to data elements. Serial block storage devices 32 and 34 in effect can rotate as a "wheel" in a "forward", (i+l), direction or a "reverse", (i-l), direction. A buffer management BC9-78~027 ~l3~6~S
.
system is described in United ~tates ratent Mo.
3,5~ 3~ iss~ec1 to Belady et al on ~une 2~ 71 and entitlec3 "llierarchical Memory Updating ~ystem".
~IGUR~ 5 illustrates yet another aspect of tlle present invention wherein a data multiplexing function is per~ormed using the present serial storac~e subsystem 30. In this aspect of the present invention, there is direct access to serial block storage devices by input/output (I/O) clevices. I/O
devices 110 apply data elements via signal lines 112 to microprocessor 12. Each data element includes a serial block storage device identification field, a position ield and a data field. The identification field indicates which one or more of serial block storage devices, for example, 116, 118 or 120 will receive the data element. ~lso, thè position of the storage location within each serial block storage device 116, 11~ or 1?.0 is designated. ~licroprocessor 12 a~ain performs a controller function and applies data via signal lines 122, 124 and 126 to serial block storage devices 116, 118 ancl 120. Therefore, all or a selected portion of a data element rnay be placed in one or any set of serial block storage c3evices 1l~ r 11~ or 120 and within a similar data storage location. Therefore, data may l~e acquired from I/~ devices and used in different sequences and arrangelllents using the serial storage subsystem of the present invention.
It therefore can be seen that the present invelltion enables the amount of storage space in a data processor to be increased without increasing the main storage addressing requirements by providing a third dilnellsion to data storage utilizincl a serial blocli storage device. ~he serial block storage devices utilized with the present invention can he of l~11,242 BC()-7~-027 1:~L376~
1~) variable WidttlS and various numbers oE serial bloclc storac3e (levices may be uti1ized depending upon the coniyuration and architecture of the data processing sytem.
~hereas the present invention has been described with resE~ect to specific embodiments thereof, it will be understood that various changes and modiEications will be sugyested to one skilled in the art, and it is intended to encompass such changes and modifications that fall within the scope of the appendecl claims.
nll,242 ~3~9-7~-027
Claims (22)
1. A data processing system comprising:
first processor means for generating instructions and push and pop operation codes;
first data storage means coupled to said first pro-cessor means and including a plurality of data storage locations for storing data;
second processor means coupled to said first pro-cessor means;
second data storage means coupled to said second processor means and including a plurality of data stor-age locations for storing data, each of said data stor-age locations of said second data storage means having a larger storage capacity than the storage capacity of each of said data storage locations of said first data storage means;
control means coupled to said first processor means and to said first data storage means to receive said instructions and codes generated by said first processor means for addressing one of said plurality of data stor-age locations of said first data storage means as an access window, such that data stored in said addressed one of said plurality of data storage locations of said first data storage means is provided to said first pro-cessor means for transfer to said second processor means to permit said second processor means to address said second data storage means, such that said first proces-sor means thereby gains access to at least one of said plurality of data storage locations of said second data storage means by instructing said control means to address one of said plurality of data storage locations of said first data storage means; and
1. (continued) said second processor means operable in response to said instructions generated by said first processor means for transferring data received from said addressed one of said plurality of data storage locations of said first data storage means between said first processor means and at least one of said plurality of data stor-age locations of said second data storage means.
2. The data processing system of claim 1 wherein said plurality of data storage locations of said second data storage means are of variable width.
3. The data processing system of claim 1 wherein said control means includes:
means responsive to said push operation code gener-ated by said first processor means for generating an address of one of said plurality of data storage loca-tions of said first storage means, such that said first processor means transfers data from said addressed one of said plurality of data storage locations of said first storage means to said second processor means for storage within one of said plurality of data storage locations of said second storage means.
means responsive to said push operation code gener-ated by said first processor means for generating an address of one of said plurality of data storage loca-tions of said first storage means, such that said first processor means transfers data from said addressed one of said plurality of data storage locations of said first storage means to said second processor means for storage within one of said plurality of data storage locations of said second storage means.
4. The data processing system of claim 1 wherein said control means includes:
means responsive to said pop operation code genera-ted by said first processor means for generating an address of one of said plurality of data storage loca-tions of said first storage means, such that said second processor means transfers data from one of said plurality of data storage locations of said second storage means to said first processor means for storage within said addressed one of said plurality of data storage loca-tions of said first storage means.
means responsive to said pop operation code genera-ted by said first processor means for generating an address of one of said plurality of data storage loca-tions of said first storage means, such that said second processor means transfers data from one of said plurality of data storage locations of said second storage means to said first processor means for storage within said addressed one of said plurality of data storage loca-tions of said first storage means.
5. The data processing system of claim 1 wherein said first processor means comprises host processor means and said second processor means comprises micropro-cessor means.
6. The data processing system of claim 1 wherein said first data storage means comprises random access stor-age means and said second data storage means comprises serial storage means.
7. The data processing system of claim 6 wherein said serial storage means comprises magnetic bubble storage means.
8. The data processing system of claim 6 wherein said serial storage means comprises charge coupled storage devices.
9. The data processing system of claim 6 wherein said serial storage means comprises electron beam address-able storage means.
10. The data processing system of claim 1 wherein said second data storage means comprises serial block storage means.
11. The data processing system of claim 1 and further including:
buffer means coupled to said second processor means for storing data received by said second processor means from said second data storage means prior to trans-fer to said first processor means for storage in said first data storage means to thereby increase the speed at which data is transferred to said first processor means from said second processor means.
buffer means coupled to said second processor means for storing data received by said second processor means from said second data storage means prior to trans-fer to said first processor means for storage in said first data storage means to thereby increase the speed at which data is transferred to said first processor means from said second processor means.
12. The data processing system of claim 11 wherein said buffer means includes a plurality of buffer means wherein each of said plurality of data storage locations of said second data storage means transfers data to said second processor means for storage in one of said plurality of buffer means.
13. The data processing system of claim 1 and further including:
buffer means coupled to said first processor means for storing data received by said first processor means from said first data storage means prior to transfer to said second processor means for storage in said second data storage means to thereby increase the speed at which data is transferred to said second processor means from said first processor means.
buffer means coupled to said first processor means for storing data received by said first processor means from said first data storage means prior to transfer to said second processor means for storage in said second data storage means to thereby increase the speed at which data is transferred to said second processor means from said first processor means.
14. The data processing system of claim 13 wherein said buffer means includes a plurality of buffer means wherein each of said plurality of data storage loca-tions of said first data storage means transfers data to said first processor means for storage in one of said plurality of buffer means.
15. The data processing system of claim 1 and further including:
first buffer means coupled to said first processor means for temporarily storing data; and second buffer means coupled to said second processor means for temporarily storing data, wherein data is transferred between said first and second processor means through said first and second buffer means to thereby increase the speed at which data is transferred between said first and second processor means.
first buffer means coupled to said first processor means for temporarily storing data; and second buffer means coupled to said second processor means for temporarily storing data, wherein data is transferred between said first and second processor means through said first and second buffer means to thereby increase the speed at which data is transferred between said first and second processor means.
16. The data processing system of claim 1 wherein said second data storage means includes a plurality of second data storage means, such that each one of said plurality of second data storage means transfers data to said second processor means for transfer to said first processor means for storage in a corresponding one of said plurality of data storage locations of said first data storage means.
17. A data processing system comprising:
first processor means for generating instructions and push and pop operation codes;
random access data storage means coupled to said first processor means and including a plurality of data storage locations for storing data;
second processor means coupled to said first pro-cessor means;
a plurality of serial block storage means coupled to said second processor means and each including a plurality of data storage locations of variable widths for storing data, each of said data storage locations of said plurality of serial block storage means having a larger storage capacity than the storage capacity of each of said data storage locations of said random access data storage means;
control means coupled to said first processor means and to said random access data storage means to receive said instructions and codes generated by said first pro-cessor means for addressing one of said plurality of data storage locations of said random access data storage means as an access window, such that data stored in said addressed one of said plurality of data storage loca-tions of said random access data storage means is pro-vided to said first processor means for transfer to said second processor means to permit said second processor means to address at least one of said plurality of stor-age locations of a corresponding one of said plurality of serial block storage means;
17. A data processing system comprising:
first processor means for generating instructions and push and pop operation codes;
random access data storage means coupled to said first processor means and including a plurality of data storage locations for storing data;
second processor means coupled to said first pro-cessor means;
a plurality of serial block storage means coupled to said second processor means and each including a plurality of data storage locations of variable widths for storing data, each of said data storage locations of said plurality of serial block storage means having a larger storage capacity than the storage capacity of each of said data storage locations of said random access data storage means;
control means coupled to said first processor means and to said random access data storage means to receive said instructions and codes generated by said first pro-cessor means for addressing one of said plurality of data storage locations of said random access data storage means as an access window, such that data stored in said addressed one of said plurality of data storage loca-tions of said random access data storage means is pro-vided to said first processor means for transfer to said second processor means to permit said second processor means to address at least one of said plurality of stor-age locations of a corresponding one of said plurality of serial block storage means;
17. (continued) said second processor means operable in response to said instructions generated by said first processor means for transferring data received from said addressed one of said plurality of data storage locations of said ran-dom access data storage means between first processor means and at least one of said plurality of data stor-age locations of one of said plurality of serial block storage means;
first buffer means coupled to said first processor means; and second buffer means coupled to said second processor means, wherein said first and second buffer means tempo-rarily store data prior to data transfer between said first and second processor means.
first buffer means coupled to said first processor means; and second buffer means coupled to said second processor means, wherein said first and second buffer means tempo-rarily store data prior to data transfer between said first and second processor means.
18. The data processing system of claim 17 wherein said second processor means operates asynchronously to said first processor means.
19. The data processing system of claim 17 wherein said second processor means comprises microprocessor means.
20. The data processing system of claim 17 wherein said control means includes:
means responsive to said push operation code genera-ted by said first processor means for generating an address of one of said plurality of data storage loca-tions of said random access data storage means, such that said first processor means transfer data from said addressed one of said plurality of data storage locations of said random access data storage means to said second processor means for storage within at least one of said plurality of data storage locations of one of said plurality of serial block storage means; and means responsive to said pop operation code generated by said first processor means for generating an address of one of said plurality of data storage locations of said random access data storage means, such that said second processor means transfers data from one of said plurality of data storage locations of one of said plurality of serial block storage means to said first processor means for storage within said addressed one of said plurality of data storage locations of said random access data storage means.
means responsive to said push operation code genera-ted by said first processor means for generating an address of one of said plurality of data storage loca-tions of said random access data storage means, such that said first processor means transfer data from said addressed one of said plurality of data storage locations of said random access data storage means to said second processor means for storage within at least one of said plurality of data storage locations of one of said plurality of serial block storage means; and means responsive to said pop operation code generated by said first processor means for generating an address of one of said plurality of data storage locations of said random access data storage means, such that said second processor means transfers data from one of said plurality of data storage locations of one of said plurality of serial block storage means to said first processor means for storage within said addressed one of said plurality of data storage locations of said random access data storage means.
21. The data processing system of claim 20 wherein said serial block storage means comprises magnetic bubble storage means.
22. The data processing system of claim 20 wherein said serial block storage means comprises charge coupled de-vices.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/047,005 US4298932A (en) | 1979-06-11 | 1979-06-11 | Serial storage subsystem for a data processor |
| US047,005 | 1979-06-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1137645A true CA1137645A (en) | 1982-12-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000349770A Expired CA1137645A (en) | 1979-06-11 | 1980-04-14 | Serial storage subsystem for a data processor |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US4298932A (en) |
| EP (1) | EP0020983B1 (en) |
| JP (1) | JPS6042501B2 (en) |
| AU (1) | AU535726B2 (en) |
| BR (1) | BR8003595A (en) |
| CA (1) | CA1137645A (en) |
| DE (1) | DE3067517D1 (en) |
| ES (1) | ES492247A0 (en) |
| IT (1) | IT8021908A1 (en) |
Families Citing this family (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE36989E (en) * | 1979-10-18 | 2000-12-12 | Storage Technology Corporation | Virtual storage system and method |
| JPS5717049A (en) * | 1980-07-04 | 1982-01-28 | Hitachi Ltd | Direct memory access controlling circuit and data processing system |
| US4611277A (en) * | 1983-09-15 | 1986-09-09 | Bankamerica Corporation | Microcomputer communications software |
| US5012407A (en) * | 1984-12-11 | 1991-04-30 | Finn Charles A | Computer system which accesses operating system information and command handlers from optical storage via an auxiliary processor and cache memory |
| US5430861A (en) * | 1984-12-11 | 1995-07-04 | Finn; Charles | Computer using optically encoded virtual memory |
| AU595378B2 (en) * | 1986-08-22 | 1990-03-29 | Commonwealth Scientific And Industrial Research Organisation | Content-addressable memory system with active memory circuit |
| US5029125A (en) * | 1989-03-07 | 1991-07-02 | Drexler Technology Corporation | Method of reading and writing files on nonerasable storage media |
| US5513326A (en) * | 1989-06-12 | 1996-04-30 | Quantum Corporation | System for optimizing data transfer |
| JP3315779B2 (en) * | 1993-11-16 | 2002-08-19 | 富士通株式会社 | File transfer device and file transfer method between disk devices |
| WO1998040810A2 (en) | 1997-03-12 | 1998-09-17 | Storage Technology Corporation | Network attached virtual tape data storage subsystem |
| US6658526B2 (en) | 1997-03-12 | 2003-12-02 | Storage Technology Corporation | Network attached virtual data storage subsystem |
| US5931958A (en) * | 1997-04-11 | 1999-08-03 | Dell Usa, L.P. | Processor controlled link resiliency circuit for serial storage architectures |
| US6098146A (en) * | 1997-04-11 | 2000-08-01 | Dell Usa, L. P. | Intelligent backplane for collecting and reporting information in an SSA system |
| US6292844B1 (en) | 1998-02-12 | 2001-09-18 | Sony Corporation | Media storage device with embedded data filter for dynamically processing data during read and write operations |
| US6094605A (en) * | 1998-07-06 | 2000-07-25 | Storage Technology Corporation | Virtual automated cartridge system |
| US6330621B1 (en) | 1999-01-15 | 2001-12-11 | Storage Technology Corporation | Intelligent data storage manager |
| US6247069B1 (en) | 1999-05-12 | 2001-06-12 | Sony Corporation | Automatically configuring storage array including a plurality of media storage devices for storing and providing data within a network of devices |
| US6859846B2 (en) | 1999-05-12 | 2005-02-22 | Sony Corporation | Method of distributed recording whereby the need to transition to a second recording device from a first recording device is broadcast by the first recording device |
| US6721859B1 (en) | 1999-10-21 | 2004-04-13 | Sony Corporation | Multi-protocol media storage device implementing protocols optimized for storing and retrieving both asynchronous and isochronous data |
| US6834324B1 (en) | 2000-04-10 | 2004-12-21 | Storage Technology Corporation | System and method for virtual tape volumes |
| US7720821B1 (en) | 2000-06-30 | 2010-05-18 | Sony Corporation | Method of and apparatus for writing and reading time sensitive data within a storage device |
| US7124292B2 (en) | 2001-05-21 | 2006-10-17 | Sony Corporation | Automatically configuring storage array including a plurality of media storage devices for storing and providing data within a network of devices |
| US20030126132A1 (en) * | 2001-12-27 | 2003-07-03 | Kavuri Ravi K. | Virtual volume management system and method |
| US7290045B2 (en) * | 2002-07-01 | 2007-10-30 | Sun Microsystems, Inc. | Method and apparatus for managing a storage area network including a self-contained storage system |
| US7937557B2 (en) | 2004-03-16 | 2011-05-03 | Vns Portfolio Llc | System and method for intercommunication between computers in an array |
| EP1821198A1 (en) * | 2006-02-16 | 2007-08-22 | Technology Properties Limited | Circular register arrays of a computer |
| US7966481B2 (en) | 2006-02-16 | 2011-06-21 | Vns Portfolio Llc | Computer system and method for executing port communications without interrupting the receiving computer |
| US7617383B2 (en) * | 2006-02-16 | 2009-11-10 | Vns Portfolio Llc | Circular register arrays of a computer |
| US7904615B2 (en) | 2006-02-16 | 2011-03-08 | Vns Portfolio Llc | Asynchronous computer communication |
| US7555637B2 (en) * | 2007-04-27 | 2009-06-30 | Vns Portfolio Llc | Multi-port read/write operations based on register bits set for indicating select ports and transfer directions |
| US20100023730A1 (en) * | 2008-07-24 | 2010-01-28 | Vns Portfolio Llc | Circular Register Arrays of a Computer |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3740723A (en) * | 1970-12-28 | 1973-06-19 | Ibm | Integral hierarchical binary storage element |
| US3761881A (en) * | 1971-06-30 | 1973-09-25 | Ibm | Translation storage scheme for virtual memory system |
| US3918031A (en) * | 1971-10-26 | 1975-11-04 | Texas Instruments Inc | Dual mode bulk memory extension system for a data processing |
| US3725876A (en) * | 1972-02-08 | 1973-04-03 | Burroughs Corp | Data processor having an addressable local memory linked to a memory stack as an extension thereof |
| US3878513A (en) * | 1972-02-08 | 1975-04-15 | Burroughs Corp | Data processing method and apparatus using occupancy indications to reserve storage space for a stack |
| US3810117A (en) * | 1972-10-20 | 1974-05-07 | Ibm | Stack mechanism for a data processor |
| US3889243A (en) * | 1973-10-18 | 1975-06-10 | Ibm | Stack mechanism for a data processor |
| NL7317545A (en) * | 1973-12-21 | 1975-06-24 | Philips Nv | MEMORY SYSTEM WITH MAIN AND BUFFER MEMORY. |
| US3909798A (en) * | 1974-01-25 | 1975-09-30 | Raytheon Co | Virtual addressing method and apparatus |
| US3967247A (en) * | 1974-11-11 | 1976-06-29 | Sperry Rand Corporation | Storage interface unit |
| DE2509835C3 (en) * | 1975-03-06 | 1980-11-06 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | RAM arrangement |
| US4047243A (en) * | 1975-05-27 | 1977-09-06 | Burroughs Corporation | Segment replacement mechanism for varying program window sizes in a data processing system having virtual memory |
| DE2526244C2 (en) * | 1975-06-12 | 1982-09-30 | Siemens AG, 1000 Berlin und 8000 München | Circuit arrangement for clock-controlled circulating memory |
| US4056848A (en) * | 1976-07-27 | 1977-11-01 | Gilley George C | Memory utilization system |
| FR2453467A1 (en) * | 1979-04-06 | 1980-10-31 | Cii Honeywell Bull | METHOD AND SYSTEM FOR OPERATING AN ADDRESSABLE MEMORY FOR ASSOCIATING EXTENSIONS WITH THE DATA CONTAINED IN THE MEMORY |
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1979
- 1979-06-11 US US06/047,005 patent/US4298932A/en not_active Expired - Lifetime
-
1980
- 1980-04-09 JP JP55045810A patent/JPS6042501B2/en not_active Expired
- 1980-04-14 CA CA000349770A patent/CA1137645A/en not_active Expired
- 1980-05-09 DE DE8080102579T patent/DE3067517D1/en not_active Expired
- 1980-05-09 IT IT1980A21908A patent/IT8021908A1/en unknown
- 1980-05-09 EP EP80102579A patent/EP0020983B1/en not_active Expired
- 1980-05-23 AU AU58716/80A patent/AU535726B2/en not_active Ceased
- 1980-06-09 ES ES492247A patent/ES492247A0/en active Granted
- 1980-06-10 BR BR8003595A patent/BR8003595A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| DE3067517D1 (en) | 1984-05-24 |
| AU5871680A (en) | 1980-12-18 |
| EP0020983B1 (en) | 1984-04-18 |
| US4298932A (en) | 1981-11-03 |
| IT8021908A1 (en) | 1981-11-09 |
| IT8021908A0 (en) | 1980-05-09 |
| BR8003595A (en) | 1981-01-05 |
| JPS55164957A (en) | 1980-12-23 |
| EP0020983A1 (en) | 1981-01-07 |
| JPS6042501B2 (en) | 1985-09-24 |
| AU535726B2 (en) | 1984-04-05 |
| ES8105872A1 (en) | 1981-06-01 |
| ES492247A0 (en) | 1981-06-01 |
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