CA1150368A - Multiple pulse-width multiplier - Google Patents
Multiple pulse-width multiplierInfo
- Publication number
- CA1150368A CA1150368A CA000352010A CA352010A CA1150368A CA 1150368 A CA1150368 A CA 1150368A CA 000352010 A CA000352010 A CA 000352010A CA 352010 A CA352010 A CA 352010A CA 1150368 A CA1150368 A CA 1150368A
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- CA
- Canada
- Prior art keywords
- voltage
- input
- stage
- switches
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P21/00—Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation
- H02P21/06—Rotor flux based control involving the use of rotor position or rotor speed sensors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
- G06G7/22—Arrangements for performing computing operations, e.g. operational amplifiers for evaluating trigonometric functions; for conversion of co-ordinates; for computations involving vector quantities
Abstract
ABSTRACT
For forming ? bi. ci, in a pulse width multiplier, two input vol-tages bi are summed at the input of an inverter and are added, after each passes through a separate switch and proportional stage, at the input of a smoothing stage, to the inverter output signal. The switches are actuated by switching pulses which are width-modulated in accordance with the factors ci. The calculated sum is present at the output of the smoothing stage.
Great accuracy in field-oriented control of rotating-field machines is possible when vector analyzers and vector rotators designed in this manner are used.
For forming ? bi. ci, in a pulse width multiplier, two input vol-tages bi are summed at the input of an inverter and are added, after each passes through a separate switch and proportional stage, at the input of a smoothing stage, to the inverter output signal. The switches are actuated by switching pulses which are width-modulated in accordance with the factors ci. The calculated sum is present at the output of the smoothing stage.
Great accuracy in field-oriented control of rotating-field machines is possible when vector analyzers and vector rotators designed in this manner are used.
Description
This invention relates to a pulse-width multiplier in which an input voltage corresponding to the first factor of a product can be switched, with alternating sign, to a smoothing stage, by means of a switch and an inverter. The switch is actuated by width-modulated pulses representing the second factor of the product.
A multiplier of this type, for forming an output ~ = (x/y) z from the input voltages x, y, z is commercially available ~Time-Division-Multiplier Type EL 1/299.02 of Siemens AG, Price List RE 1, May, 1972, pages 6/33 to 36). In this unit, the input voltage z is applied to the input of a smoothing stage via a first double-throw switch, alternating between directly coupled (at switching time tl) and, via an inverter, with reversed sign (at switching time t2). The switch is actuated by means of pulses which are formed from the input voltage x and y, in such a manner that (tl - t2)/(tl + t2) = x/y, so that an output voltage Ua = z-xjy is present ~, at the output of the smoothing stage (by principle of pulse-width multiplica-",~! tion). A sawtooth generator, a limit indicator ~two-level device), and a second double-throw switch are provided for forming the switching pulses.
The second double-throw switch passes the input voltage y either directly or via a further inverter, in alternation, and is switched simultaneously with , . .
the switching pulses for the first double-throw switch. To generate the saw-tooth waveforms employed, the input voltage x and the output signal y' of the second double-throw switch are fed to the inverter input of an I-stage. The output voltage y'=-+y of the double-throw switch is also applied to the limit indicator as a limit, and the output signal of the limit indicator operates the second double-throw switch as soon as the auxiliary voltage furnished by $' ' the I-stage reaches the limit y. After the second double-throw switch is switched into the position y' = +y, the curve of the auxiliary voltage there-' ' ' ., ;~
, ' ' :' - :
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. :
~S~368 fore increases linearly through integration of the input ~ariables (x + y) until it reaches the limit ~y after the time tl. Then the double-throw switch is switched to the position y' = -y and the auxiliary voltage curve decreases linearly during the switching time t~, corresponding to the input variables (x - y~ of the I-stage. For the switching time tl and tz of the two double-throw switches, the condition x/y = ctl - t2j/(tl ~ t2) is thereby achieved.
This known multiplier contains 6 potentiometers for balancing and normalizing.
Such pulse-width multipliers are distinguished by great accuracy.
However, as soon as several such multipliers are required for certain applica-tions, for instance, in controls, the expenditures for switching elements and adjusting labor increase. Furthermore, such pulse-width multipliers are in-tended for multiplying constant input quantities. With variable inputs, dis-tortions in time can occur through the smoothing stage. This happens, for instance, if machines must be controlled as a function of the positions of ; -. rotating machine parts, and if the inputs, variable in time, corresponding to the machine positions, must be multiplied and added together for the analog ` control, where the individual factors of the products to be added are time-",,,~
dependent in common. If such a pulse-width multiplier were used for forming each product, superpositions and beats would occur through the addition of the output signals of the individual smoothing stages; these can be avoided only when the time relationships of the individual smoothing stages are carefully matched to each other. However, since only discrete capacity values with considerable manufacturing tolerances are available for the capacitors required for the smoothing stages, conventional pulse-width multipliers are not suit-"
i able for such purposes. Thus, in German Patent 19 42 312, for instance, characteristic-multipliers are used for control of an asynchronous machine.
It is an object of the present invention to describe an analoe com-, ~5~368 puting circuit for calculating a sum a =i bi.ci of products of the input vol-tages bi and ci, which requires a minimum amount of components and adjusting labor, which is designed for processing quantities which vary in time, and which operates according to the principle of pulse-width multiplication.
SUMMARY OF THE INVENTION
The problem set forth above is solved by a multiplier of the general type described at the outset, in which a common smoothing stage, preceded by a junction point, is provided for all products formed. For all products the input voltages corresponding to the associated first factor of each product are connected to a first common inverter, and the inverter output is connected to the junction point. At the same time, the input voltages corresponding to the first factor of a product are likewise applied to the junction point via ` switches (one switch for each product), which can be operated by switching pulses representing the second factor of the corresponding product and via a proportional stage. The total to be calculated is taken off at the output of , the smoothing stage. If an operational amplifier is used for smoothing, then the proportional stage is formed by appropriate resistors placed in the input ; leads to the amplifier (junction point).
Since, according to the invention, a single smoothing stage is used for smoothing all products, input voltages which are variable in time can be processed without the danger of distortion which could be caused by the super-~, position of signals of several smoothing stages; such stages are difficult to match to each other. It is merely necessary, as is generally the case when pulse-width multipliers are used, for the computing frequency, i.e., the fre-quency of the corresponding switches, to be substantially higher than the fre-quency of the time-varying input voltages. Moreover, the junction point required for adding the individual products can be located at the input of an .~ - 3 -',.
.. . .
, )368 operational amplifier connected as a smoothing stage, obviating a separate summing operational amplifier as well as an output inverter such as is fre-quently required in such summing amplifiers for establishing the correct polarity of the output signal. In addition, the amount of circuitry is also reduced by replacing the switching inverter, required for the formation of each product in the known circuit, by a common inverter.
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In some applications, especially for controlling rotating machines, it is necessary to form two sums, al = ~ bici and a2 = i bici, especially ~; al = b-c + d-e and a2 = b-f + d-g. Application of the teachings of the inven-tion makes possible the formation of these sums simultaneously without appreciable cost, since only a second smoothing stage, a second proportional stage, and a set of further switches, for instance third and fourth switches are required for forming the second sum. Thus, the output voltage of a first inverter, required for forming the first product, is fed, via a second propor-tional stage, to a second junction point at the input of a second smoothing stage. Further, the input voltages corresponding to the original first factor i b and the new first factor d are each fed, by a third and fourth switch, res-~ pectively, actuated in accordance with the further factors f and g. The two E, sums to be computed are present as output voltages at the outputs of the two i~ 20 smoothing stages.
., -Of special importance here is the case f = -e, g = c. ~or, if the :, .
quantities c and e stand for cos~ and sin~ of an angle ~, then the computing , circuit makes it possible to represent a vector a which is given by the coor-dinates b and d with respect to a Cartesian coordinate system, according to the equations al = b cos~ + d sin~
a2 = -b sin~ + d cos~ (1) )368 in a coordinate system restated, relative to the original coordinate system, by the angle. Thereby, a vector, the coordinates of which are determined in a rotating machine, for instance, by corresponding measured values in the stationary coordinate system, can be transformed to a coordinate system rotat-ing with the machine. Also the reverse transformation al = b cos~ - d sin~ ~2) a2 ~ h sin~ ~ d cos~
from a rotating coordinate system to a stationary coordinate system is easily possible.
` 10 For the coordinate transformations, the circuit having two smoothing stages can be used and the switches required for representing cos~ , in the products b cos~ and d cos~ , are actuated by the same switching pulses.
For representing -sin~ in the product -b sin~, the switching pulses already required for forming d sin~ can be used, except that the opening and the closing of the switch must be reversed; this is realized, in the illustrative embodiment, by inserting a NOR stage in the responding switching pulse line.
The circuit of the invention can be used to advantage for determining the position and/or magnitude of a rotating vector, such as the magnetic flux , i~
vector in a rotating-field machine, relative to another, stationary, coordinate system, obtained, for instance, from measurements at the stator of the ~;~ machine, are set in the circuit as inputs. Such an application, as well as the principle of the inventionJ is explained in greater detail in the illus-trative embodiments which follow:
BRIEP DESCRIPTION OF THE DRAWINGS
Figure 1 shows the position of a vector in two coordinate systems which are rotated relative to each other;
Figure 2 is a block diagra~ of an arrangement for transforming the ,.
, , , ~
,~
,, coordinates of the vector from one coordinate system into the other coordinate system;
Figure 3 is a schematic diagram of a circuit realizing the block diagram of Figure 2 with elements in accordance ~ith the prior art; and ;~` Figure 4 is a schematic diagram of a circuit realizing the block diagram of Figure 2, using the teachings of the lnvention.
:-~ DETAILED DESCRIPTION OF THE INVENTION
~ The illustrative embodiment relates to a field-oriented control for O 10 an asynchronous machine. The currents flowing in the stator windings of such a machine can be added up to form a stator vector current i, the coordinates of which, in a stator-related coordinate system, are given by appropriate measurements. Likewise, the coordinates of the magnetic flux vector ~r can be . determined from stator variables (currents and voltages).
According to German Patent 19 41 312, the asynchronous machine can !,,:,,, be controlled or regulated by making the stator current dependent on two elec-;i~ trical variables which are field-axis-related variables. For this purpose, ; the stator current vector is split into a component parallel to the magnetic flux vector and a component perpendicular thereto, i.e., the stator current is represented in a Cartesian system which rotates with the magnetic flux vec-tor. The current component parallel to the field determines the magnitude of the field, and the component perpendicular to the field determines the torque -' of the machine, in Figure 1, the stator-related coordinate system is designated using subscripts sl and s2 and the field-oriented coordinate system with ~1 and ~2. Thus, iSl and iS2 are the stator-related components and i~l and i~2 are the field-related components of the current vector and ~ is the angle between the field vector ~r or the corresponding unit vector ~1 and the vector sl.
The problem is to calculatethe component of a vector parallel and :
.. , ,; .
., , ~ - .
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~15C3 36~3 perpendicular to a reference vector, where the vector and the reference vector are given by their coordinates in an associated Cartesian coordinate system.
Since the reference vector rotates and the vector changes its position, re-lative to the reference vector, the inputs to be fed to the computing circuit are variable in time, but this variation is slow as compared to the operating frequency of the co~puting circuit.
First, the corresponding coordinates of the unit vector must be determined from the stator-related coordinates of the magnetic flux vector, in order to determine the position of the new coordinate system, i.e.J the angle ~. This purpose is served, in the structure of Figure 2, by a vector analyzer such as is described in United States Patent 3,671,731. There, the inputs ~sl and ~s2 are first divided by the amount of the vector~and then the divider outputs are multiplied in multipliers 4 and 5 by the inputs ~sl and ~ 2~ so that the quantity ~25l/~ ~252/~ is present at an additive junction point 6. This variable ~, which can be taken off at junction point 6, is fed to the divisor inputs of dividers 2 and 3.
~,j The quantity ~sl/~ = cos ~5 is therefore present at the output of divider 2 and can be taken off at an output 8. At a corresponding output 7, the quantity ~s2/~ = sin ~s is brought out from the output of multiplier 3.
After this analysis of the reference vector ~, the vector i is now transformed in a vector 10 such as is shown, for instance, in Figure 6 of the mentioned German Patent 19 41 312. This coordinate transformation is accom-plished according to the above k~:~wn formulas ~
i~l= iSl cos ~5 + iS2 sin ~5 i~2 ~isl sin ~s + is2 sin ~ (3) Since pulse-width multiplication can be performed with great accuracy, it would be desirable to realize the circuit of the block diagram of figure 2 using !
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pulse-width multipliers.
In Figure 3, the prior art pulse-width multiplier, mentioned above, is sho~n as 20. ~he input to unit 20, and the output of a first double-throw switch 22 are connected to a first input of an I-stage 21. The I-stage output is connected to a limit indicator 23 which delivers a binary output signal and changes its signal as soon as the voltage fed from the I-state is equal to the voltage y' = +y. The binary output signal is fed back from the output of double-throw switch 22. The output signal of limit indicator 23 actuates double-throw switch 22 which switches the y-input (to unit 30) from the vol-; 10 tage being applied directly to an equal voltage of opposite polarity, derived via an inverter 24. The voltage at the z-input to unit 20 is made available directly, or via an inverter 25, to a second double-throw switch 26, and thence to a smoothing stage 27, driven in synchronism with first switch 22 by limit indicator 23. During the time tt, the voltage z is passed on directly through the switch, and, during the time t2, it is passed on with the opposite sign, so that smoothing stage 27 forms a mean value Ua = ~z-tl - z t2)/~tl + t2). Since, 1 t2, (tl - t2)/(tl + t2) x/y, the voltage z-x/y is present at the output 28 of pulse-width multiplier 20. In the present application, - y = ~ and x = Z = ~sl are fed in, where the same symbols are chosen for the individual defining quantities of the vectors and for the corresponding vol-tages.
Pulse-width multiplier 20 therefore corresponds to the combination of divider 2 and multiplier 4 in Pigure 2 for forming the quantity ~sl2/~. A
pulse-width multiplier 30 of completely identical design is used for forming ~s2/~ The output signals of both pulse-width multipliers are then summed in adding stage 31 followed by an inverter 32 to obtain a DC voltage ~ S12+~ 2 which is applied to the y-inputs of the two pulse-width multipliers and can, )368 in addition, be taken off at an output 33. The quantities cos~S=~5l/~ and sin~S=~s2/~ are formed here, not as DC voltages, but are brought out as pulse trains ~rectangular curve), for instance, of "high" and "low" signals from the vector analyzer.
These pulse trains can now be used for pulse-width multiplication in vector rotator 40. A double-multiplier is used for forming i~l~iSl cos~S
+iS2sin~2. The voltage iSl, which is applied in an analogous manner, with alternating polarity, to smoothing stage 45 by means of an inverter 43 and a double-throw switch 44, is fed to an input 42. Double-throw switch 44 is actuated by the pulse train representing the variable cos ~ via line 34. In smoothing stage 44, the first product is therefore formed by averaging over the voltages ~iSl and -iSl, weighted in accordance with the switching pulse durations tl and t2.
The second product is formed from the input voltage iS2 present at input 46 by means of a further inverter 47, a further double-throw switch 48 ~actuated, via the line 35, by the switching pulses representing the variable sin ~5) and smoothing stage 49. Both products are subsequently added. Since the smoothing stages and the adders are advantageously constructed using oper-ational amplifiers, a subsequent inverter for providing the correct sign is necessary.
A second double-multiplier 41 for forming i~2--i lsin~5lis2cos~s can be constructed in exactly the same manner, the inputs of which for iSl and i 2' and for sin ~s and cos ~5 are likewise connected to lines 42, 46 and 34, 35, respectively. An additional inverter 51 is necessary for representing the negative sign.
Such a design makes it possible to calculate the product sums with great accuracy. Two switching pulse generators are sufficient. Such a switch-., _ g _ ',~
~, :' . ~' . ' - .
:
ing pulse generator contains, as described, a limit indicator 23 with a bin-ary output signal, into which a sawtooth voltage curve and an auxiliary vol-tage (in this case, y'=+~) are set and which always changes its output signal when the sawtooth voltage curve coincides with the auxiliary voltage.
The inputs ~sl and ~s2 as well as iSl and iS2 are time-dependent according to the frequency of the rotating-field machine. These time depen-dences largely cancel out in the formation of the product sums and the result-ing variables ~ or iel and ie2 are time-dependent ~to a much lesser degree.
If, now, the smoothing stages ~for instance, 43 and 47~, required for forming a sum, are not carefully matched to each other, then beats can occur, upon addition at the input of the following summing amplifiers, which simulate a false time dependence. Further superpositions can be produced if two sawtooth generators operating with different frequencies are used.
;, In the circuit of the present invention, the product sums are formed in a computing circuit 60 (Figure 4) which takes the place of components 25, 26, 27, 25', 26', 27', 31 and 32 in the prior art circuit of Figure 3. For forming the sum ~sl cos ~s ~s2 sin ~s' only a single ~smoothing stage is used, advantageously an operational amplifier 61 having a feedback branch which con-sists of a shunt-connected resistor and capacitor. The lnput of operational amplifier 61 is a first junction point 62 which sums the input voltages fed to the operational amplifier. The first factors ~sl and ~s2 to be fed to the computing circuit are fed to junction point 62 via a common inverter 63 and series-connected resistor 64. These factors are also fed, via switches 65 and 66 and associated resistors 67 and 68, respectively, to junction point 62.
Resistors 67 and 68 are each one-half the resistance value of resistor 64 and act as a proportional stage with a gain of 2. When switches 65 and 66 are closed, the voltage ~sl and ~S2 are therefore added with twice the value to ., ' ' ~ , .~ ~ ' ,, ., -.
: ~ .
`` 115~368 ;~ inverter 63, so that during the "on" time (tl) of the switches, the input ~ voltages are present with their orîginal sign and, during the off time, with 5' the opposite sign. Switches 65 and ~6 are actuated similarly to switches 26 and 26' of Figure 3 by switching pulses which effect the pulse-width multi--` plication by the factors cos ~ and sin ~ .
The amount of circuitry necessary for computing circuit 50 is comparatively small. In particular, it is an advantage that the smoothing -; of the pulsed voltages takes place in a common smoothing stage only after they have been summed and that the time behavior of the smoothing stage has the same effect for both summands. No interfering beats are produced.
- In principle, the switching pulses for switches 65 and 66 can be formed in the same way as they were in Figure 3. However, the circuit shown in Figure 4 can also be uséd to advantage, since it requires only a single ` sawtooth generator of constant frequency. A sawtooth generator 70 can be used. This generator consists of a frequency-determining oscillator 71 which applies an input present at input 73 via a double-throw switching device, shown schematically as switch 72, with alternating sign, to an integrator 74.
The output signal of integrator 74 is a triangle wave and is fed via a feed-.
~- back line to a second junction point 75 at the input of switching device 72 ` 20 via a rectifier, for instance, a full-wave rectifier 76, a smoothing stage 77, .;
a proportional stage 78 and a PI-controller 79. With full-wave rectification, the output signal of smoothing stage 77 corresponds to one-half the amplitude of the triangle voltage. When, therefore, this signal is doubled in propor-tional stage 78 and compared at the input of PI-controller 79 with the voltage ' signal present at input 73, the amplitude d the sawtooth voltage is exactly ,';`,' ~, proportional to the input voltage at input terminal 73. In the present case, .
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. - :
)368 the output voltage ~ of computing circuit 60 is fed to input terminal 73.
The sawtooth reference voltage generated in this manner is fed to first and second limit indicators 80 and 81, into which the voltages ~ 1 and ~s2' respectively, are set as limits. Each of the limit indicators generates ~ a binary signal which changes when the reference soltage curve intersects ,~ the respective limit values. These signal sequences (rectangular voltage waves) can serve as switching signals for representing the quantities cos ~ and sin ~ = ~s2/~ It is also possible to represent the vari-ables -cos ~s and -sin ~s by merely reversing the role of the pulses in clos-ing and opening the respective switches. This can be accomplished by connect-ing NOR gates 82 and 83 to the outputs of limit indicator 80 and 81, respectively, to invert the value of the binary limit indicator output signals.
Since switches 65 and 66 of computing circuit 60 apply input voltages with their original sign to smoothing stage 61 only when limit indicators 80 and 81 ~!' respond, i.e., when the reference sawtooth curve is higher than the limits ~sl and ~ 2' and since the smoothing stage furnishes the negative mean value of the pulsed input voltages, the respective switching pulses for switches 65 and 66 are taken off at the outputs of NOR gates 82 and 83.
To calculate the quantities i~l and i~2 according to equation (3), the rectangle waves for cos ~ and sin ~ are multiplied in a vector rotator 90, also shown in Figure 4, by the input voltages iSl and iS2. It is advantageous to build the vector rotator 90 by using the computing circuit taught by the present invention. First, the sum al = b c + d-e is formed, with the variables iSl and iS2 being fed to the inputs for b and d and the variables sin ~ and cos ~s to the inputs for c and c. To this end, the voltages b and d are summed at the input of an inverter 91, in a manner similar to computing circuit i~ 60. The output signal of inverter 91 is fed to a first smoothing stage 93 - 12 _ : .
~5~368 through a resistor 92. In addition, the voltages b and d are fed via first and second switches 94 and 95 and associated series resistors 96, to the input of first smoothing stage 93. As before, resistors 96 have one-half the resistance of resistor 92, and act as a proportional stage for doubling the voltages coming from switches 94 and 95 which are additively linked with the voltage coming from inverter 91 at the input to smoothing stage 93. The quantity al = i~l is taken off at the output of first smoothing stage 93.
To represent the quantity i~2, a sum a2 = b f + d g must be formed at the same time. This is done by connecting the output signal of inverter 91 to a second smoothing stage 98, via resistor 97. The voltages b and d are further added to the inverter output voltage at the input of second smoothing stage 98 by way of third and fourth switches 100 and 101 and resistors 102.
Since resistors 102 again have only one-half the resistance value of resistor 97, they constitute a proportional stage for doubling the applied voltage.
The sum is taken off as an output voltage i~2 at output a2.
To realize equation (3), switches 94 and 95 are also actuated by the output pulses of NOR gates 82 and 83. Since in this case, we must set f = -e and g = c, third switch 100 associated with voltage b is actuated by the complementary signal of the switching signal associated with switch 93, i.e., .,, the necessary reversal of sign is derived, by a logical reversal, from the same output signal of the limit indicator 81. Switches 101 and 94, which are required for representing the factor cos ~ are actuated by the corresponding output signal of limit indicator 80.
Thus, by using common smoothing stages for each sum formation, the occurrence of interfering distortions in time is largely avoided for the vector rotator 90 since all factors of each sum are influenced by the same time behavior of the associated smoothing stage. Time-consuming adjustment work is completely eliminated. It further becomes even more obvious that, :.
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.
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with this vector rotator, the amount of circuitry required is considerably reduced by the invention.
The advantages of the computing circuit of the present invention are readily obtained in a vector analyzer or a vector rotator and, to an increased extent, in a circuit composed of both units, and also in other circuits - calling for formation of the sum of several products from two factors.
Similarly, sums of three or more products can be formed simply in ~his manner.
For the arrangement shown in Figure 4 it does not matter whether the output ~
of the circuit is fed back into the sawtooth generator used to form switching pulses in the vector analyzer for forming cos ~s and sin ~ or whether it is determined in some other manner. Also, vector rotator ~0 can be used for realizing equation (2) for transforming, for instance, a vector given in the field-oriented system. In such a case, where only the signs of the trigonometric functions need to be interchanged, only the corresponding switching pulses need to be negated.
.
., "
A multiplier of this type, for forming an output ~ = (x/y) z from the input voltages x, y, z is commercially available ~Time-Division-Multiplier Type EL 1/299.02 of Siemens AG, Price List RE 1, May, 1972, pages 6/33 to 36). In this unit, the input voltage z is applied to the input of a smoothing stage via a first double-throw switch, alternating between directly coupled (at switching time tl) and, via an inverter, with reversed sign (at switching time t2). The switch is actuated by means of pulses which are formed from the input voltage x and y, in such a manner that (tl - t2)/(tl + t2) = x/y, so that an output voltage Ua = z-xjy is present ~, at the output of the smoothing stage (by principle of pulse-width multiplica-",~! tion). A sawtooth generator, a limit indicator ~two-level device), and a second double-throw switch are provided for forming the switching pulses.
The second double-throw switch passes the input voltage y either directly or via a further inverter, in alternation, and is switched simultaneously with , . .
the switching pulses for the first double-throw switch. To generate the saw-tooth waveforms employed, the input voltage x and the output signal y' of the second double-throw switch are fed to the inverter input of an I-stage. The output voltage y'=-+y of the double-throw switch is also applied to the limit indicator as a limit, and the output signal of the limit indicator operates the second double-throw switch as soon as the auxiliary voltage furnished by $' ' the I-stage reaches the limit y. After the second double-throw switch is switched into the position y' = +y, the curve of the auxiliary voltage there-' ' ' ., ;~
, ' ' :' - :
.:
. :
~S~368 fore increases linearly through integration of the input ~ariables (x + y) until it reaches the limit ~y after the time tl. Then the double-throw switch is switched to the position y' = -y and the auxiliary voltage curve decreases linearly during the switching time t~, corresponding to the input variables (x - y~ of the I-stage. For the switching time tl and tz of the two double-throw switches, the condition x/y = ctl - t2j/(tl ~ t2) is thereby achieved.
This known multiplier contains 6 potentiometers for balancing and normalizing.
Such pulse-width multipliers are distinguished by great accuracy.
However, as soon as several such multipliers are required for certain applica-tions, for instance, in controls, the expenditures for switching elements and adjusting labor increase. Furthermore, such pulse-width multipliers are in-tended for multiplying constant input quantities. With variable inputs, dis-tortions in time can occur through the smoothing stage. This happens, for instance, if machines must be controlled as a function of the positions of ; -. rotating machine parts, and if the inputs, variable in time, corresponding to the machine positions, must be multiplied and added together for the analog ` control, where the individual factors of the products to be added are time-",,,~
dependent in common. If such a pulse-width multiplier were used for forming each product, superpositions and beats would occur through the addition of the output signals of the individual smoothing stages; these can be avoided only when the time relationships of the individual smoothing stages are carefully matched to each other. However, since only discrete capacity values with considerable manufacturing tolerances are available for the capacitors required for the smoothing stages, conventional pulse-width multipliers are not suit-"
i able for such purposes. Thus, in German Patent 19 42 312, for instance, characteristic-multipliers are used for control of an asynchronous machine.
It is an object of the present invention to describe an analoe com-, ~5~368 puting circuit for calculating a sum a =i bi.ci of products of the input vol-tages bi and ci, which requires a minimum amount of components and adjusting labor, which is designed for processing quantities which vary in time, and which operates according to the principle of pulse-width multiplication.
SUMMARY OF THE INVENTION
The problem set forth above is solved by a multiplier of the general type described at the outset, in which a common smoothing stage, preceded by a junction point, is provided for all products formed. For all products the input voltages corresponding to the associated first factor of each product are connected to a first common inverter, and the inverter output is connected to the junction point. At the same time, the input voltages corresponding to the first factor of a product are likewise applied to the junction point via ` switches (one switch for each product), which can be operated by switching pulses representing the second factor of the corresponding product and via a proportional stage. The total to be calculated is taken off at the output of , the smoothing stage. If an operational amplifier is used for smoothing, then the proportional stage is formed by appropriate resistors placed in the input ; leads to the amplifier (junction point).
Since, according to the invention, a single smoothing stage is used for smoothing all products, input voltages which are variable in time can be processed without the danger of distortion which could be caused by the super-~, position of signals of several smoothing stages; such stages are difficult to match to each other. It is merely necessary, as is generally the case when pulse-width multipliers are used, for the computing frequency, i.e., the fre-quency of the corresponding switches, to be substantially higher than the fre-quency of the time-varying input voltages. Moreover, the junction point required for adding the individual products can be located at the input of an .~ - 3 -',.
.. . .
, )368 operational amplifier connected as a smoothing stage, obviating a separate summing operational amplifier as well as an output inverter such as is fre-quently required in such summing amplifiers for establishing the correct polarity of the output signal. In addition, the amount of circuitry is also reduced by replacing the switching inverter, required for the formation of each product in the known circuit, by a common inverter.
~;.
In some applications, especially for controlling rotating machines, it is necessary to form two sums, al = ~ bici and a2 = i bici, especially ~; al = b-c + d-e and a2 = b-f + d-g. Application of the teachings of the inven-tion makes possible the formation of these sums simultaneously without appreciable cost, since only a second smoothing stage, a second proportional stage, and a set of further switches, for instance third and fourth switches are required for forming the second sum. Thus, the output voltage of a first inverter, required for forming the first product, is fed, via a second propor-tional stage, to a second junction point at the input of a second smoothing stage. Further, the input voltages corresponding to the original first factor i b and the new first factor d are each fed, by a third and fourth switch, res-~ pectively, actuated in accordance with the further factors f and g. The two E, sums to be computed are present as output voltages at the outputs of the two i~ 20 smoothing stages.
., -Of special importance here is the case f = -e, g = c. ~or, if the :, .
quantities c and e stand for cos~ and sin~ of an angle ~, then the computing , circuit makes it possible to represent a vector a which is given by the coor-dinates b and d with respect to a Cartesian coordinate system, according to the equations al = b cos~ + d sin~
a2 = -b sin~ + d cos~ (1) )368 in a coordinate system restated, relative to the original coordinate system, by the angle. Thereby, a vector, the coordinates of which are determined in a rotating machine, for instance, by corresponding measured values in the stationary coordinate system, can be transformed to a coordinate system rotat-ing with the machine. Also the reverse transformation al = b cos~ - d sin~ ~2) a2 ~ h sin~ ~ d cos~
from a rotating coordinate system to a stationary coordinate system is easily possible.
` 10 For the coordinate transformations, the circuit having two smoothing stages can be used and the switches required for representing cos~ , in the products b cos~ and d cos~ , are actuated by the same switching pulses.
For representing -sin~ in the product -b sin~, the switching pulses already required for forming d sin~ can be used, except that the opening and the closing of the switch must be reversed; this is realized, in the illustrative embodiment, by inserting a NOR stage in the responding switching pulse line.
The circuit of the invention can be used to advantage for determining the position and/or magnitude of a rotating vector, such as the magnetic flux , i~
vector in a rotating-field machine, relative to another, stationary, coordinate system, obtained, for instance, from measurements at the stator of the ~;~ machine, are set in the circuit as inputs. Such an application, as well as the principle of the inventionJ is explained in greater detail in the illus-trative embodiments which follow:
BRIEP DESCRIPTION OF THE DRAWINGS
Figure 1 shows the position of a vector in two coordinate systems which are rotated relative to each other;
Figure 2 is a block diagra~ of an arrangement for transforming the ,.
, , , ~
,~
,, coordinates of the vector from one coordinate system into the other coordinate system;
Figure 3 is a schematic diagram of a circuit realizing the block diagram of Figure 2 with elements in accordance ~ith the prior art; and ;~` Figure 4 is a schematic diagram of a circuit realizing the block diagram of Figure 2, using the teachings of the lnvention.
:-~ DETAILED DESCRIPTION OF THE INVENTION
~ The illustrative embodiment relates to a field-oriented control for O 10 an asynchronous machine. The currents flowing in the stator windings of such a machine can be added up to form a stator vector current i, the coordinates of which, in a stator-related coordinate system, are given by appropriate measurements. Likewise, the coordinates of the magnetic flux vector ~r can be . determined from stator variables (currents and voltages).
According to German Patent 19 41 312, the asynchronous machine can !,,:,,, be controlled or regulated by making the stator current dependent on two elec-;i~ trical variables which are field-axis-related variables. For this purpose, ; the stator current vector is split into a component parallel to the magnetic flux vector and a component perpendicular thereto, i.e., the stator current is represented in a Cartesian system which rotates with the magnetic flux vec-tor. The current component parallel to the field determines the magnitude of the field, and the component perpendicular to the field determines the torque -' of the machine, in Figure 1, the stator-related coordinate system is designated using subscripts sl and s2 and the field-oriented coordinate system with ~1 and ~2. Thus, iSl and iS2 are the stator-related components and i~l and i~2 are the field-related components of the current vector and ~ is the angle between the field vector ~r or the corresponding unit vector ~1 and the vector sl.
The problem is to calculatethe component of a vector parallel and :
.. , ,; .
., , ~ - .
;
~15C3 36~3 perpendicular to a reference vector, where the vector and the reference vector are given by their coordinates in an associated Cartesian coordinate system.
Since the reference vector rotates and the vector changes its position, re-lative to the reference vector, the inputs to be fed to the computing circuit are variable in time, but this variation is slow as compared to the operating frequency of the co~puting circuit.
First, the corresponding coordinates of the unit vector must be determined from the stator-related coordinates of the magnetic flux vector, in order to determine the position of the new coordinate system, i.e.J the angle ~. This purpose is served, in the structure of Figure 2, by a vector analyzer such as is described in United States Patent 3,671,731. There, the inputs ~sl and ~s2 are first divided by the amount of the vector~and then the divider outputs are multiplied in multipliers 4 and 5 by the inputs ~sl and ~ 2~ so that the quantity ~25l/~ ~252/~ is present at an additive junction point 6. This variable ~, which can be taken off at junction point 6, is fed to the divisor inputs of dividers 2 and 3.
~,j The quantity ~sl/~ = cos ~5 is therefore present at the output of divider 2 and can be taken off at an output 8. At a corresponding output 7, the quantity ~s2/~ = sin ~s is brought out from the output of multiplier 3.
After this analysis of the reference vector ~, the vector i is now transformed in a vector 10 such as is shown, for instance, in Figure 6 of the mentioned German Patent 19 41 312. This coordinate transformation is accom-plished according to the above k~:~wn formulas ~
i~l= iSl cos ~5 + iS2 sin ~5 i~2 ~isl sin ~s + is2 sin ~ (3) Since pulse-width multiplication can be performed with great accuracy, it would be desirable to realize the circuit of the block diagram of figure 2 using !
, ~.. . ~ '.
-' ',. r ' ~
'.; ' .
pulse-width multipliers.
In Figure 3, the prior art pulse-width multiplier, mentioned above, is sho~n as 20. ~he input to unit 20, and the output of a first double-throw switch 22 are connected to a first input of an I-stage 21. The I-stage output is connected to a limit indicator 23 which delivers a binary output signal and changes its signal as soon as the voltage fed from the I-state is equal to the voltage y' = +y. The binary output signal is fed back from the output of double-throw switch 22. The output signal of limit indicator 23 actuates double-throw switch 22 which switches the y-input (to unit 30) from the vol-; 10 tage being applied directly to an equal voltage of opposite polarity, derived via an inverter 24. The voltage at the z-input to unit 20 is made available directly, or via an inverter 25, to a second double-throw switch 26, and thence to a smoothing stage 27, driven in synchronism with first switch 22 by limit indicator 23. During the time tt, the voltage z is passed on directly through the switch, and, during the time t2, it is passed on with the opposite sign, so that smoothing stage 27 forms a mean value Ua = ~z-tl - z t2)/~tl + t2). Since, 1 t2, (tl - t2)/(tl + t2) x/y, the voltage z-x/y is present at the output 28 of pulse-width multiplier 20. In the present application, - y = ~ and x = Z = ~sl are fed in, where the same symbols are chosen for the individual defining quantities of the vectors and for the corresponding vol-tages.
Pulse-width multiplier 20 therefore corresponds to the combination of divider 2 and multiplier 4 in Pigure 2 for forming the quantity ~sl2/~. A
pulse-width multiplier 30 of completely identical design is used for forming ~s2/~ The output signals of both pulse-width multipliers are then summed in adding stage 31 followed by an inverter 32 to obtain a DC voltage ~ S12+~ 2 which is applied to the y-inputs of the two pulse-width multipliers and can, )368 in addition, be taken off at an output 33. The quantities cos~S=~5l/~ and sin~S=~s2/~ are formed here, not as DC voltages, but are brought out as pulse trains ~rectangular curve), for instance, of "high" and "low" signals from the vector analyzer.
These pulse trains can now be used for pulse-width multiplication in vector rotator 40. A double-multiplier is used for forming i~l~iSl cos~S
+iS2sin~2. The voltage iSl, which is applied in an analogous manner, with alternating polarity, to smoothing stage 45 by means of an inverter 43 and a double-throw switch 44, is fed to an input 42. Double-throw switch 44 is actuated by the pulse train representing the variable cos ~ via line 34. In smoothing stage 44, the first product is therefore formed by averaging over the voltages ~iSl and -iSl, weighted in accordance with the switching pulse durations tl and t2.
The second product is formed from the input voltage iS2 present at input 46 by means of a further inverter 47, a further double-throw switch 48 ~actuated, via the line 35, by the switching pulses representing the variable sin ~5) and smoothing stage 49. Both products are subsequently added. Since the smoothing stages and the adders are advantageously constructed using oper-ational amplifiers, a subsequent inverter for providing the correct sign is necessary.
A second double-multiplier 41 for forming i~2--i lsin~5lis2cos~s can be constructed in exactly the same manner, the inputs of which for iSl and i 2' and for sin ~s and cos ~5 are likewise connected to lines 42, 46 and 34, 35, respectively. An additional inverter 51 is necessary for representing the negative sign.
Such a design makes it possible to calculate the product sums with great accuracy. Two switching pulse generators are sufficient. Such a switch-., _ g _ ',~
~, :' . ~' . ' - .
:
ing pulse generator contains, as described, a limit indicator 23 with a bin-ary output signal, into which a sawtooth voltage curve and an auxiliary vol-tage (in this case, y'=+~) are set and which always changes its output signal when the sawtooth voltage curve coincides with the auxiliary voltage.
The inputs ~sl and ~s2 as well as iSl and iS2 are time-dependent according to the frequency of the rotating-field machine. These time depen-dences largely cancel out in the formation of the product sums and the result-ing variables ~ or iel and ie2 are time-dependent ~to a much lesser degree.
If, now, the smoothing stages ~for instance, 43 and 47~, required for forming a sum, are not carefully matched to each other, then beats can occur, upon addition at the input of the following summing amplifiers, which simulate a false time dependence. Further superpositions can be produced if two sawtooth generators operating with different frequencies are used.
;, In the circuit of the present invention, the product sums are formed in a computing circuit 60 (Figure 4) which takes the place of components 25, 26, 27, 25', 26', 27', 31 and 32 in the prior art circuit of Figure 3. For forming the sum ~sl cos ~s ~s2 sin ~s' only a single ~smoothing stage is used, advantageously an operational amplifier 61 having a feedback branch which con-sists of a shunt-connected resistor and capacitor. The lnput of operational amplifier 61 is a first junction point 62 which sums the input voltages fed to the operational amplifier. The first factors ~sl and ~s2 to be fed to the computing circuit are fed to junction point 62 via a common inverter 63 and series-connected resistor 64. These factors are also fed, via switches 65 and 66 and associated resistors 67 and 68, respectively, to junction point 62.
Resistors 67 and 68 are each one-half the resistance value of resistor 64 and act as a proportional stage with a gain of 2. When switches 65 and 66 are closed, the voltage ~sl and ~S2 are therefore added with twice the value to ., ' ' ~ , .~ ~ ' ,, ., -.
: ~ .
`` 115~368 ;~ inverter 63, so that during the "on" time (tl) of the switches, the input ~ voltages are present with their orîginal sign and, during the off time, with 5' the opposite sign. Switches 65 and ~6 are actuated similarly to switches 26 and 26' of Figure 3 by switching pulses which effect the pulse-width multi--` plication by the factors cos ~ and sin ~ .
The amount of circuitry necessary for computing circuit 50 is comparatively small. In particular, it is an advantage that the smoothing -; of the pulsed voltages takes place in a common smoothing stage only after they have been summed and that the time behavior of the smoothing stage has the same effect for both summands. No interfering beats are produced.
- In principle, the switching pulses for switches 65 and 66 can be formed in the same way as they were in Figure 3. However, the circuit shown in Figure 4 can also be uséd to advantage, since it requires only a single ` sawtooth generator of constant frequency. A sawtooth generator 70 can be used. This generator consists of a frequency-determining oscillator 71 which applies an input present at input 73 via a double-throw switching device, shown schematically as switch 72, with alternating sign, to an integrator 74.
The output signal of integrator 74 is a triangle wave and is fed via a feed-.
~- back line to a second junction point 75 at the input of switching device 72 ` 20 via a rectifier, for instance, a full-wave rectifier 76, a smoothing stage 77, .;
a proportional stage 78 and a PI-controller 79. With full-wave rectification, the output signal of smoothing stage 77 corresponds to one-half the amplitude of the triangle voltage. When, therefore, this signal is doubled in propor-tional stage 78 and compared at the input of PI-controller 79 with the voltage ' signal present at input 73, the amplitude d the sawtooth voltage is exactly ,';`,' ~, proportional to the input voltage at input terminal 73. In the present case, .
B
~ . .
.- :
. - :
)368 the output voltage ~ of computing circuit 60 is fed to input terminal 73.
The sawtooth reference voltage generated in this manner is fed to first and second limit indicators 80 and 81, into which the voltages ~ 1 and ~s2' respectively, are set as limits. Each of the limit indicators generates ~ a binary signal which changes when the reference soltage curve intersects ,~ the respective limit values. These signal sequences (rectangular voltage waves) can serve as switching signals for representing the quantities cos ~ and sin ~ = ~s2/~ It is also possible to represent the vari-ables -cos ~s and -sin ~s by merely reversing the role of the pulses in clos-ing and opening the respective switches. This can be accomplished by connect-ing NOR gates 82 and 83 to the outputs of limit indicator 80 and 81, respectively, to invert the value of the binary limit indicator output signals.
Since switches 65 and 66 of computing circuit 60 apply input voltages with their original sign to smoothing stage 61 only when limit indicators 80 and 81 ~!' respond, i.e., when the reference sawtooth curve is higher than the limits ~sl and ~ 2' and since the smoothing stage furnishes the negative mean value of the pulsed input voltages, the respective switching pulses for switches 65 and 66 are taken off at the outputs of NOR gates 82 and 83.
To calculate the quantities i~l and i~2 according to equation (3), the rectangle waves for cos ~ and sin ~ are multiplied in a vector rotator 90, also shown in Figure 4, by the input voltages iSl and iS2. It is advantageous to build the vector rotator 90 by using the computing circuit taught by the present invention. First, the sum al = b c + d-e is formed, with the variables iSl and iS2 being fed to the inputs for b and d and the variables sin ~ and cos ~s to the inputs for c and c. To this end, the voltages b and d are summed at the input of an inverter 91, in a manner similar to computing circuit i~ 60. The output signal of inverter 91 is fed to a first smoothing stage 93 - 12 _ : .
~5~368 through a resistor 92. In addition, the voltages b and d are fed via first and second switches 94 and 95 and associated series resistors 96, to the input of first smoothing stage 93. As before, resistors 96 have one-half the resistance of resistor 92, and act as a proportional stage for doubling the voltages coming from switches 94 and 95 which are additively linked with the voltage coming from inverter 91 at the input to smoothing stage 93. The quantity al = i~l is taken off at the output of first smoothing stage 93.
To represent the quantity i~2, a sum a2 = b f + d g must be formed at the same time. This is done by connecting the output signal of inverter 91 to a second smoothing stage 98, via resistor 97. The voltages b and d are further added to the inverter output voltage at the input of second smoothing stage 98 by way of third and fourth switches 100 and 101 and resistors 102.
Since resistors 102 again have only one-half the resistance value of resistor 97, they constitute a proportional stage for doubling the applied voltage.
The sum is taken off as an output voltage i~2 at output a2.
To realize equation (3), switches 94 and 95 are also actuated by the output pulses of NOR gates 82 and 83. Since in this case, we must set f = -e and g = c, third switch 100 associated with voltage b is actuated by the complementary signal of the switching signal associated with switch 93, i.e., .,, the necessary reversal of sign is derived, by a logical reversal, from the same output signal of the limit indicator 81. Switches 101 and 94, which are required for representing the factor cos ~ are actuated by the corresponding output signal of limit indicator 80.
Thus, by using common smoothing stages for each sum formation, the occurrence of interfering distortions in time is largely avoided for the vector rotator 90 since all factors of each sum are influenced by the same time behavior of the associated smoothing stage. Time-consuming adjustment work is completely eliminated. It further becomes even more obvious that, :.
Ç , r ~ , . ' ~ '.
.
:
with this vector rotator, the amount of circuitry required is considerably reduced by the invention.
The advantages of the computing circuit of the present invention are readily obtained in a vector analyzer or a vector rotator and, to an increased extent, in a circuit composed of both units, and also in other circuits - calling for formation of the sum of several products from two factors.
Similarly, sums of three or more products can be formed simply in ~his manner.
For the arrangement shown in Figure 4 it does not matter whether the output ~
of the circuit is fed back into the sawtooth generator used to form switching pulses in the vector analyzer for forming cos ~s and sin ~ or whether it is determined in some other manner. Also, vector rotator ~0 can be used for realizing equation (2) for transforming, for instance, a vector given in the field-oriented system. In such a case, where only the signs of the trigonometric functions need to be interchanged, only the corresponding switching pulses need to be negated.
.
., "
Claims (5)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. In a pulse-width multiplier having a smoothing stage to which an input voltage corresponding to the first factor of a product is fed, with alternating polarity, by means of a switch and of an inverter, the switch being actuated by width-modulated pulses representing the second factor of the product, the improvement comprising: means for calculating a sum from the products of two factors comprising a first junction point feeding a first smoothing stage for forming all the products within the sum; a first inverter having an input to which the input voltages corresponding to the first factor of each product are connected and having an output voltage which is fed to the first junction point; a plurality of switches, each switch corresponding to one of the products and having an input to which an input voltage corresponding to the first factor of the corresponding product is fed and having outputs connected via a proportional stage, to the first junction point; and means for actuating the switches in response to switching pulses representing the second factors; and the first smoothing stage having an output at which a voltage representing the sum to be calculated is made available.
2. In a multiplier in accordance with Claim 1, the further improvement comprising: means for generating the switching pulses for operating the switches comprising one limit detector for each switch each having a sawtooth voltage as one input and each having a voltage representing the second factor of the product corresponding to said switch as another input, the out-put of each limit detector being the switching pulses representing the second factor of the corresponding product and each limit indicator changing its output state at times when the sawtooth voltage and the voltage representing the second factor intersect.
3. In a multiplier in accordance with Claim 2, the further improve-ment comprising: means for forming and supplying a sawtooth voltage of constant amplitude and frequency to the limit detectors; and means for sup-plying the voltages corresponding to the second factors to the limit detectors as fractions of the sawtooth voltage amplitude which are proportional to the voltages representing the second factors of the products.
4. In a multiplier, useful as a vector rotator, in accordance with any one of Claims 1 to 3, the further improvement comprising: a second junction point feeding a second smoothing stage for forming, simultaneously with the first sum, an additional sum from other products, the output of the inverter being coupled to the second junction point; each voltage corres-ponding to the first factors of one product also being fed to the second junction point via a corresponding further switch and a second proportional stage, means for actuating the further switches in response to switching pulses representing the second factors of the other products; and the second calculated sum being a voltage taken off at the output of the second smoothing stage.
5. In a multiplier, useful as a vector rotator, in accordance with any one of Claims 1 to 3, the further improvement comprising: a second junction point feeding a second smoothing stage for forming, simultaneously with the first sum, an additional sum from other products, the output of the inverter being coupled to the second junction point; each voltage corres-ponding to the first factors of one product also being fed to the second junction point via a corresponding further switch and a second proportional stage, means for actuating the further switches in response to switching pulses representing the second factors of the other products; the second calculated sum being a voltage taken off at the output of the second smoothing stage, and the plurality of switches consisting of two switches, the further improvement comprising: two inverter stages, each having an input to which one of the switching pulses representing the second factors of the first sum is fed and each having an output driving one of the further switches.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19792919786 DE2919786A1 (en) | 1979-05-16 | 1979-05-16 | PULSE WIDTH MULTIPLE MULTIPLIER |
| DEP2919786.2 | 1979-05-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1150368A true CA1150368A (en) | 1983-07-19 |
Family
ID=6070886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000352010A Expired CA1150368A (en) | 1979-05-16 | 1980-05-15 | Multiple pulse-width multiplier |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US4335444A (en) |
| EP (1) | EP0019139B1 (en) |
| JP (1) | JPS55153071A (en) |
| AT (1) | ATE3340T1 (en) |
| CA (1) | CA1150368A (en) |
| DE (2) | DE2919786A1 (en) |
| DK (1) | DK210080A (en) |
| FI (1) | FI70334C (en) |
| IN (1) | IN152817B (en) |
| NO (1) | NO151724C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3139136A1 (en) * | 1981-10-01 | 1983-04-14 | Siemens AG, 1000 Berlin und 8000 München | Device for determining the frequency of alternating electrical quantities, particularly of a rotating-field machine |
| JPS6423607A (en) * | 1987-07-17 | 1989-01-26 | Otis Elevator Japan | Multiphase multiplier circuit |
| JPH0374064U (en) * | 1989-11-20 | 1991-07-25 | ||
| US6237017B1 (en) * | 1996-04-25 | 2001-05-22 | Texas Instruments India Limited | Lossy technique for image and speech processing |
| CA2675303A1 (en) * | 2007-01-25 | 2008-07-31 | Rgb Systems, Inc. | Method and apparatus for producing triangular waveform with low audio band noise content |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2880935A (en) * | 1954-09-27 | 1959-04-07 | Gilfillan Bros Inc | Means for electronic multiplication |
| US2927734A (en) * | 1954-12-30 | 1960-03-08 | Rca Corp | Computing system for electronic resolver |
| DE1170685B (en) * | 1960-05-21 | 1964-05-21 | Telefunken Patent | Electronic arrangement for analog division |
| US3473011A (en) * | 1965-07-12 | 1969-10-14 | Gen Electric | Electronic analog resolver |
| DE1239507B (en) * | 1965-10-14 | 1967-04-27 | Siemens Ag | Method and device for forming a signal, the mean value of which is proportional to the quotient of a first and a second analog signal multiplied by a third analog signal |
| US3466460A (en) * | 1967-01-20 | 1969-09-09 | Weston Instruments Inc | Time division multiplier |
| US3536904A (en) * | 1968-09-23 | 1970-10-27 | Gen Electric | Four-quadrant pulse width multiplier |
| CA930867A (en) * | 1968-10-09 | 1973-07-24 | Canadian Marconi Company | Pythagoreas adder or solid state resolver |
| US3569688A (en) * | 1968-12-24 | 1971-03-09 | Audn Corp | A multiplier in which a capacitor is charged at a rate proportional to the product of two analogue inputs |
| CH539980A (en) * | 1971-09-09 | 1973-07-31 | Siemens Ag | Device for generating two amplitude-stabilized, sinusoidal and frequency-variable alternating voltages, electrically offset from one another by 90 ° |
| FR2271616A1 (en) * | 1974-05-14 | 1975-12-12 | Decca Ltd | Orthogonal resolver with pulse generator - has conditioning, summing and forming circuits and feedback to generator |
| DE2816614C2 (en) * | 1978-04-17 | 1980-02-21 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Coordinate converter for converting polar vector quantities into Cartesian vector quantities |
-
1979
- 1979-05-16 DE DE19792919786 patent/DE2919786A1/en not_active Withdrawn
-
1980
- 1980-03-13 IN IN287/CAL/80A patent/IN152817B/en unknown
- 1980-04-18 FI FI801247A patent/FI70334C/en not_active IP Right Cessation
- 1980-04-28 AT AT80102302T patent/ATE3340T1/en not_active IP Right Cessation
- 1980-04-28 DE DE8080102302T patent/DE3063056D1/en not_active Expired
- 1980-04-28 EP EP80102302A patent/EP0019139B1/en not_active Expired
- 1980-05-09 US US06/148,141 patent/US4335444A/en not_active Expired - Lifetime
- 1980-05-14 DK DK210080A patent/DK210080A/en not_active Application Discontinuation
- 1980-05-14 NO NO801454A patent/NO151724C/en unknown
- 1980-05-15 JP JP6466880A patent/JPS55153071A/en active Pending
- 1980-05-15 CA CA000352010A patent/CA1150368A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4335444A (en) | 1982-06-15 |
| IN152817B (en) | 1984-04-14 |
| DK210080A (en) | 1980-11-17 |
| ATE3340T1 (en) | 1983-05-15 |
| NO801454L (en) | 1980-11-17 |
| EP0019139B1 (en) | 1983-05-11 |
| NO151724B (en) | 1985-02-11 |
| FI801247A (en) | 1980-11-17 |
| FI70334B (en) | 1986-02-28 |
| NO151724C (en) | 1985-05-22 |
| FI70334C (en) | 1986-09-15 |
| EP0019139A1 (en) | 1980-11-26 |
| DE2919786A1 (en) | 1980-11-27 |
| DE3063056D1 (en) | 1983-06-16 |
| JPS55153071A (en) | 1980-11-28 |
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