CA1152212A - Main storage configuration control system - Google Patents
Main storage configuration control systemInfo
- Publication number
- CA1152212A CA1152212A CA000341797A CA341797A CA1152212A CA 1152212 A CA1152212 A CA 1152212A CA 000341797 A CA000341797 A CA 000341797A CA 341797 A CA341797 A CA 341797A CA 1152212 A CA1152212 A CA 1152212A
- Authority
- CA
- Canada
- Prior art keywords
- configuration
- main storage
- unit
- data
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
- G06F12/0653—Configuration or reconfiguration with centralised address assignment
Abstract
ABSTRACT OF THE DISCLOSURE
In a data processing system which is provided with a main storage unit comprising a main storage composed of a plurality of configuration units and a main storage controller for select-ing one of the configuration units of the main storage and con-trolling read and write of information with respect to the select configuration unit, and a central processor unit, configuration data from a configuration data generation unit is written in a configuration data storage means and one of the configuration units of the main storage is selected by the configuration data read from the configuration data storage means in accordance with an address from the central processor unit so that the selected configuration is accessed.
In a data processing system which is provided with a main storage unit comprising a main storage composed of a plurality of configuration units and a main storage controller for select-ing one of the configuration units of the main storage and con-trolling read and write of information with respect to the select configuration unit, and a central processor unit, configuration data from a configuration data generation unit is written in a configuration data storage means and one of the configuration units of the main storage is selected by the configuration data read from the configuration data storage means in accordance with an address from the central processor unit so that the selected configuration is accessed.
Description
.. . .. . ... . ... .. . .. . .. ..
BACKGROUND OF THE INVEN~ION
Field of the Invention This invention relates to a main storage configuration control system, and more particularly to a main storage con-figuration control system for a data processing system in which a main storage unit, combined with a central processor unit, comprises a main storage and a main storage controller, and the main storage is composed of a plurality of configuration units from and in which storage information are simultaneously read and written.
Description of the Prior Art In the system in which the main storage is composed of a plurality of configuration units, such an arrangement is reguired that permits free selection of each configuration unit.
To this end, it is customary in the prior art to provide in the main storage controller an address translation circuit, formed by a switching circuit or jumper circuit, for the translation of an address bit and a circuit for decoding the address after this translation to determine which one of the configuration units is activated, or to employ an arrangement which holds an address to be accessed for each configuration unit and compares it with an address from the central processor unit and activates the configuration unit whose address coincides with that from the central processor unit~ Such a conventional method, however, involves the use of the address translation circuit, the configu-ration selec~or circuit or the address comparator for each con-figuration unit, and hence greatly affects the performance and ~k ~15Z2~2 reliability of the data processing system.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a main storage configuration control system in which a reloadable random access storage ele-ment, which receives, as an address from the central processor unit and outputs a configuration data signal, is provided in the main storage controller of the main storage and configuration data is outputted using the storage element, thereby to overcome the abovesaid defects of the prior art.
Briefly stated, according to the present invention, in a main storage configuration control system for a data processing system in which a main storage unit, combined with a central processor unit, is composed of a main storage and a main storage controller and the main storage is composed of a plurality of configuration units which perform simultaneous storage infor-mation read-write operation, there are provided a reloadable configuration RAM
for generating configuration data in accordance with an address from the control processor unit and a configuration RAM controller for controlling write of con-figuration data from a configuration data generation unit provided outside the main storage unit in the configuration RAM and read therefrom of the configura-tion data in accordance with an address from the central processor unit; and by the-control of the configuration controller, the configuration data is written in the configuration RAM and read therefrom to access the main storage.
Thus, in accordance with a broad aspect of the invention, there is provided a main storage configuration control system for a data processing system which is provided with a main storage unit comprising a main storage composed of a plurality of configuration units and a main storage controller for selecting one of the configuration units of the main storage and controlling read and write of information with respect to the selected configuration unit, . ., ~15229 2 and a central processor unit, the main storage configuration control system comprising: a reloadable configuration unit select information storage means for outputting configuration data in accordance with an address from the cent-ral processor unit; and a configuration unit selection controller for writing in the configuration unit select information storage means configuration data from a configuration data generation unit provided outside the main storage unit and controlling read-out from the configuration unit select information storage means in accordance with the address from the central processor unit;
wherein the configuration data is written by the configuration unit selection controller in the configuration unit select information storage means and read therefrom in accordance with the address from the central processor unit to ~: select one of the configuration units of the main storage for an access thereto.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram illustrating an embodiment of this invention;
-3a-~52Z12 Figs. 2 and 3 are explanatory of the stored content of a configuration RAM; and Fig. 4 is a block diagram s'nowing a configuration RAM
address controller, a configuration RAM and a configuration RAM
access control circuit for use in this invention.
DESCRIPTION OF THE P~FERRED EMBODIMENTS
In Fig. 1 there is ill~strated in block form an embodiment of this invention. Reference numeral 1 indicates a main storage unit; 2 designates a central processor unit; 3 identifies a configuration data generation unit; 4 denotes a main storage;
5 represents a main storage controller; 6 to 13 show first to eighth configuration units; 14 refers to an access control and timing generate circuit; 15 indicates an address control circuit;
16 designates a read data circuit; 17 identifies a write data circuit; 18 denotes a configuration RAM address control circuit;
1~ represents a configuration RAM; 20 shows a configuration RAM
access control circuit; 21 refers to an access controller and expander driver; 100 indicates a main storage access request bus;
101 designates a main storage address bus; 102 identifies a main storage read data bus; 103 denotes a main storage write data bus;
104 represents a configuration data bus; 105 shows a configuration R~l access control bus; 10~ refers to a configuration RAM write address bus; 107 indicates a main storage address bus; 108 to 110 designate first to third main storage configuration unit select addresses; 111 to 113 identify first to third configura-tion RAM write addresses; 114 to lZl denote first to eighth configuration data for the configuration RAM; 122 represents a ~S~212 storage timing bus; 123 shows a configuration unit address bus;
124 to 126 refer to firs~ to third configuration RAM addresses;
127 to 134 indicate first to eightn configuration unit select signals; 135 designates a configuration RAM access control signal; 136 identifies a confi~3uration unit read data bus; 137 denotes a configuration unit ~rite data bus; and 138 represents a configuration RAM address control signal.
The main storage 4 of the main storage unit 1 has the first to eighth configuration units 6 to 13, and the configuration RAM
19 has an 8 word~8 bit configuration.
Between the main storage unit 1 and the central processor unit 2 there are provided the main storage access request bus 100 for requesting write or read, the main storage address bus 101 for transferring an address of an access ~equest, the main storage read data bus 102 for transferring data read from the storage unit 1 and the main storage write data bus 103 for transferring data to be written in the main storage unit 1.
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`~ In the main storage controller 5 of the ~ain storage unit 1, ," ~ ~
upon reception of the access request on the main storage access ~ request bus 100, the access control and timing generate circuit ': 14 generates on the storage timing bus 122 a timing necessary for the main storage 4 and supplies it to the access controller ~., and exp~nder driver 21. The address control circuit 15 takes therein via the main storage address bus 107 that part of an address in the main storage address bus 101 ~hich is required in the configuration unit to be selected, and supplies that address part to the access controller and expander driver 21.
~lS~Z5LZ
Meanwhile, either the first to third main storage configura-tion unit select addresses 108 to 110 in the main storage address bus 101 or the first to third configuration RAM write addresses 111 to 113 from the configuration data generation unit 3 are selected by the configuration RAM address control circuit 18 and used as first to third configuration RAM addresses. This selection is performed by the configuration ~AM address control signal 138 which is produced by the configuration RPM access control circuit 20 in accordance with a signal on the configuration RAM access control bus 105.
The configuration RAM 19 has an 8 word-8 bit configuration, and the first to eighth configuration data 114 to 121 for the configuration RAM are produced by the configuration data genera-tion unit 3 and supplied via the RAM configuration data bus 104.
The first to eighth configuration unit select signals 127 to 134 derived from the configuration RAM 19 are each sent to the access ; ~ controller and expander driver 21, as a signal for selecting one ~ ~h,t~
of the eight configuration ~n~t of the main storage 4, to activate the configuration unit.
The write data to the main storage 4 is sent from the , ~
central processor unit 2 via the write data bus 103 to the write data circuit 17 and thence to the selected configuration unit via the configuration unit write data bus 137 and the access controller and expander driver 21. Data read from the selected configuration unit is sent via the configuration unit read bus 136 to the read data circuit 16 and thence to the central processor
BACKGROUND OF THE INVEN~ION
Field of the Invention This invention relates to a main storage configuration control system, and more particularly to a main storage con-figuration control system for a data processing system in which a main storage unit, combined with a central processor unit, comprises a main storage and a main storage controller, and the main storage is composed of a plurality of configuration units from and in which storage information are simultaneously read and written.
Description of the Prior Art In the system in which the main storage is composed of a plurality of configuration units, such an arrangement is reguired that permits free selection of each configuration unit.
To this end, it is customary in the prior art to provide in the main storage controller an address translation circuit, formed by a switching circuit or jumper circuit, for the translation of an address bit and a circuit for decoding the address after this translation to determine which one of the configuration units is activated, or to employ an arrangement which holds an address to be accessed for each configuration unit and compares it with an address from the central processor unit and activates the configuration unit whose address coincides with that from the central processor unit~ Such a conventional method, however, involves the use of the address translation circuit, the configu-ration selec~or circuit or the address comparator for each con-figuration unit, and hence greatly affects the performance and ~k ~15Z2~2 reliability of the data processing system.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a main storage configuration control system in which a reloadable random access storage ele-ment, which receives, as an address from the central processor unit and outputs a configuration data signal, is provided in the main storage controller of the main storage and configuration data is outputted using the storage element, thereby to overcome the abovesaid defects of the prior art.
Briefly stated, according to the present invention, in a main storage configuration control system for a data processing system in which a main storage unit, combined with a central processor unit, is composed of a main storage and a main storage controller and the main storage is composed of a plurality of configuration units which perform simultaneous storage infor-mation read-write operation, there are provided a reloadable configuration RAM
for generating configuration data in accordance with an address from the control processor unit and a configuration RAM controller for controlling write of con-figuration data from a configuration data generation unit provided outside the main storage unit in the configuration RAM and read therefrom of the configura-tion data in accordance with an address from the central processor unit; and by the-control of the configuration controller, the configuration data is written in the configuration RAM and read therefrom to access the main storage.
Thus, in accordance with a broad aspect of the invention, there is provided a main storage configuration control system for a data processing system which is provided with a main storage unit comprising a main storage composed of a plurality of configuration units and a main storage controller for selecting one of the configuration units of the main storage and controlling read and write of information with respect to the selected configuration unit, . ., ~15229 2 and a central processor unit, the main storage configuration control system comprising: a reloadable configuration unit select information storage means for outputting configuration data in accordance with an address from the cent-ral processor unit; and a configuration unit selection controller for writing in the configuration unit select information storage means configuration data from a configuration data generation unit provided outside the main storage unit and controlling read-out from the configuration unit select information storage means in accordance with the address from the central processor unit;
wherein the configuration data is written by the configuration unit selection controller in the configuration unit select information storage means and read therefrom in accordance with the address from the central processor unit to ~: select one of the configuration units of the main storage for an access thereto.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram illustrating an embodiment of this invention;
-3a-~52Z12 Figs. 2 and 3 are explanatory of the stored content of a configuration RAM; and Fig. 4 is a block diagram s'nowing a configuration RAM
address controller, a configuration RAM and a configuration RAM
access control circuit for use in this invention.
DESCRIPTION OF THE P~FERRED EMBODIMENTS
In Fig. 1 there is ill~strated in block form an embodiment of this invention. Reference numeral 1 indicates a main storage unit; 2 designates a central processor unit; 3 identifies a configuration data generation unit; 4 denotes a main storage;
5 represents a main storage controller; 6 to 13 show first to eighth configuration units; 14 refers to an access control and timing generate circuit; 15 indicates an address control circuit;
16 designates a read data circuit; 17 identifies a write data circuit; 18 denotes a configuration RAM address control circuit;
1~ represents a configuration RAM; 20 shows a configuration RAM
access control circuit; 21 refers to an access controller and expander driver; 100 indicates a main storage access request bus;
101 designates a main storage address bus; 102 identifies a main storage read data bus; 103 denotes a main storage write data bus;
104 represents a configuration data bus; 105 shows a configuration R~l access control bus; 10~ refers to a configuration RAM write address bus; 107 indicates a main storage address bus; 108 to 110 designate first to third main storage configuration unit select addresses; 111 to 113 identify first to third configura-tion RAM write addresses; 114 to lZl denote first to eighth configuration data for the configuration RAM; 122 represents a ~S~212 storage timing bus; 123 shows a configuration unit address bus;
124 to 126 refer to firs~ to third configuration RAM addresses;
127 to 134 indicate first to eightn configuration unit select signals; 135 designates a configuration RAM access control signal; 136 identifies a confi~3uration unit read data bus; 137 denotes a configuration unit ~rite data bus; and 138 represents a configuration RAM address control signal.
The main storage 4 of the main storage unit 1 has the first to eighth configuration units 6 to 13, and the configuration RAM
19 has an 8 word~8 bit configuration.
Between the main storage unit 1 and the central processor unit 2 there are provided the main storage access request bus 100 for requesting write or read, the main storage address bus 101 for transferring an address of an access ~equest, the main storage read data bus 102 for transferring data read from the storage unit 1 and the main storage write data bus 103 for transferring data to be written in the main storage unit 1.
1`' ~ ' '~ ' ' . : .
`~ In the main storage controller 5 of the ~ain storage unit 1, ," ~ ~
upon reception of the access request on the main storage access ~ request bus 100, the access control and timing generate circuit ': 14 generates on the storage timing bus 122 a timing necessary for the main storage 4 and supplies it to the access controller ~., and exp~nder driver 21. The address control circuit 15 takes therein via the main storage address bus 107 that part of an address in the main storage address bus 101 ~hich is required in the configuration unit to be selected, and supplies that address part to the access controller and expander driver 21.
~lS~Z5LZ
Meanwhile, either the first to third main storage configura-tion unit select addresses 108 to 110 in the main storage address bus 101 or the first to third configuration RAM write addresses 111 to 113 from the configuration data generation unit 3 are selected by the configuration RAM address control circuit 18 and used as first to third configuration RAM addresses. This selection is performed by the configuration ~AM address control signal 138 which is produced by the configuration RPM access control circuit 20 in accordance with a signal on the configuration RAM access control bus 105.
The configuration RAM 19 has an 8 word-8 bit configuration, and the first to eighth configuration data 114 to 121 for the configuration RAM are produced by the configuration data genera-tion unit 3 and supplied via the RAM configuration data bus 104.
The first to eighth configuration unit select signals 127 to 134 derived from the configuration RAM 19 are each sent to the access ; ~ controller and expander driver 21, as a signal for selecting one ~ ~h,t~
of the eight configuration ~n~t of the main storage 4, to activate the configuration unit.
The write data to the main storage 4 is sent from the , ~
central processor unit 2 via the write data bus 103 to the write data circuit 17 and thence to the selected configuration unit via the configuration unit write data bus 137 and the access controller and expander driver 21. Data read from the selected configuration unit is sent via the configuration unit read bus 136 to the read data circuit 16 and thence to the central processor
2 via the main storage read data bus 102.
~15~2~2 Figs. 2 and 3 show examples of storea contents of the configuration RAM 19. In Figs. 2 and 3, reference numerals 200 to 202 indicate address ~its, which'correspond to bits on the signal buses 108 to 110 and 111 to 113 in Fig. 1, and 203 to 210 designate data bits, which'correspond to bits on the signal ' buses 114 to 121 and 127 to 134. 'In the`access to the main . ~ . . . .
storage, when the address isr for example, "000", the data bit 203 is 1" in the example of Fig. 2, so that the first configuration unit 6 in the main storage 4 is selected; in the example of Fig. 3, the data bit 210 is "1", so that the eighth configuration unit 13 in the maln storage 4 is selected. The contents of the configuration RAM 19 can be reloaded arbitrarily by the control of the configuration data generation unit 3, as mentioned previously.
Fig. 4 shows in block form the configuration RAM address control circuit 18, the configuration RAM 19 and the configura-tion RAM access circuit 20. In Fig. 4, reference numeral 600 indicates a decoder; 601 to 607 designates NAND gates; 608 :
identifies a 8-bit register; 609 denotes a set-reset flip-flop;
610 represents a 8-bit register; 611 to 616 show NAND gates forming a multiplexer 633; 617 to 624 refer to edge-trigger flip-, ., flops; 625 to 632 indicate RAM's, each having a storage capacity ~ of~256 words x 1 bit, which constitute the principal part of the '; configuration RAM; and 700 to 780 designate various signals.
.. ~ . . .
The data 714 to 721 from the'configuration data generationunit 3 respectively correspond to thè first to third configura-tion RAM write addresses 111 to 113 and the first to eighth ; . _ ~15223~
configuration data 114 to 121 in Fi~. 1 and are indicated by separate signal buses in Fig. 1 for convenience of description, but in practice, these data are transferred on a time-shared basis via the signal bus shown in Fig. 4.
A description will be given first of the address setting.
; From the configuration data generation unit 3, the data 714 to 721 are transferred as configuration RAM write addresses to the register 610 and "1101" is transferred as the addresses 700 to 703 to the decoder 600 and a strobe pulse 704 is added to the NAND gate 607. The decoder 600 operates in accordance with the fact that the address 703 is "1" and the output signal 708 from the decoder 600 becomes "1", with the result that an output signal 780 from the NAND gate 604 is applied to the register ~t 608 to set therein the data 714 to 721.
" ~ -Next, the addresses 700 to 703 becomes "0001" and the de,c~de~
output signaI 705 of the\600 becomes ~ln. Further, the strobe ~` pulse 704 is provided, by which the output signal 722 of the ~, . , NAND gate 601 is applied as a set signal to the flip-flop 609 which serves as an address control register. By setting of the flip-flop 609, the signals 744 and 745 become "1" and "0"
respectively. Consequently, the multiplexer 633 outputs the output signals 736 to 743 of the register 608 as the address 754 to 761 of the RAM's 625 to 632.
Then, data to be written in the RAM's 625 to 632 are transferred as the data 714 to 721 and "0101' is transferred as the data 700 to 703, making the output signal 707 of the decoder 600 "1". By the application of the strobe pulse 704, ~15~2~l2 the output signal 724 of the NAND ~ate 603 is provided as a set signal to the register 610 to set therein the data 714 to 721.
Thereafter, the addresses 7~0 to 703 become "1111" and the output signal 712 from the decoder 600 become "1". By the application of the strobe pulse 704, the output signal 726 of the NAND gate 606 is applied as a clock to each of the flip-flops 617 to 624. As a consequence, the data 714 to 721 set in the register 610 are set as the data 764 to 753 in the flip-flops 617 to 624, whose set outputs ~4 to 771 are provided to the RAM's 625 to 632.
Next, the addresses 700 to 703 are rendered into "0111"
and the output signal 711 of the decoder 600 becomes "1", and by the application of the strobe pulse 704, the output signal 725 of the NAND gate 605 becomes "0" and is applied as a writ:e -enable signal to each of the RAM's 625 to 632. As a result of this, write data which are the set outputs 764 to 771 of the flip-flops 617 to 624 are written in the RAM's 625 to 632 in accordance with the addresses 754 to 761 provided from the multiplexer 633.
By repeating the above operations, desired data are written in the RAM!s 625 to 632. Upon completion of this write, the addresses 700 to 703 become "1001" and the output signal 706 of the decoder 600 becomes "1". Then, when the strobe pulse 704 is applied, the output signal 723 of the NAND gate 602 becomes "0" to reset the flip-flop 609, whose output signals 744 and 745 become "0" and "1", respectively. As a consequence, the multi-plexer 633 outputs access addresses 728 to 735 as the addresses 754 to 761.
_ g _ ~lS~Z~Z
~ hen the RAM's 625 to 632 are supplied with the addresses 754 to 761 as a result of the application of the access addresses 728 to 735, data previously written in the RAM15 625 to 632 are read therefrom as read data 772 to 779, which correspond to the first to eighth configuration unit select signals in Fig. 1 and become a signal for selecting one of the configuration units 6 to 13 of the main storage 4.
In the case of the main storage 4 having the eight configu-ration units 6 to 13, the co4figuration RAM is sufficient to have a 3-bit configuration, but the~above embodiment is arranged so that a configuration unit select signal of 8 bits from the RAM' s 625 to 632 may be outputted so as to cope with expansion of the configuration unit.
As has been described in the foregoing, according to this invention, in a data processing system employing a central data processor unit and a main storage unit in combination, a configuration RAM is used in a main storage controller, and a eonfiguration data generation unit is provided outside the main storage unit for producing configuration RAM write information, and an address from the central processor unit is used as an address input to the eonfiguration RAM and an output data therefrom is used as a main storage eonfiguration unit select signal; therefore, the main storage configuration and the main storage configuration unit selection can be achieved at the same time and with a small quantity of hardware used.
While the present invention has been described with respect to a specific embodiment thereof, it is to be understood that the ~15;22~Z
present invention is not limited thereto in any way but covers .~ny and all changes and modificati~ns which will become possible within the scope of the appended claims.
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~15~2~2 Figs. 2 and 3 show examples of storea contents of the configuration RAM 19. In Figs. 2 and 3, reference numerals 200 to 202 indicate address ~its, which'correspond to bits on the signal buses 108 to 110 and 111 to 113 in Fig. 1, and 203 to 210 designate data bits, which'correspond to bits on the signal ' buses 114 to 121 and 127 to 134. 'In the`access to the main . ~ . . . .
storage, when the address isr for example, "000", the data bit 203 is 1" in the example of Fig. 2, so that the first configuration unit 6 in the main storage 4 is selected; in the example of Fig. 3, the data bit 210 is "1", so that the eighth configuration unit 13 in the maln storage 4 is selected. The contents of the configuration RAM 19 can be reloaded arbitrarily by the control of the configuration data generation unit 3, as mentioned previously.
Fig. 4 shows in block form the configuration RAM address control circuit 18, the configuration RAM 19 and the configura-tion RAM access circuit 20. In Fig. 4, reference numeral 600 indicates a decoder; 601 to 607 designates NAND gates; 608 :
identifies a 8-bit register; 609 denotes a set-reset flip-flop;
610 represents a 8-bit register; 611 to 616 show NAND gates forming a multiplexer 633; 617 to 624 refer to edge-trigger flip-, ., flops; 625 to 632 indicate RAM's, each having a storage capacity ~ of~256 words x 1 bit, which constitute the principal part of the '; configuration RAM; and 700 to 780 designate various signals.
.. ~ . . .
The data 714 to 721 from the'configuration data generationunit 3 respectively correspond to thè first to third configura-tion RAM write addresses 111 to 113 and the first to eighth ; . _ ~15223~
configuration data 114 to 121 in Fi~. 1 and are indicated by separate signal buses in Fig. 1 for convenience of description, but in practice, these data are transferred on a time-shared basis via the signal bus shown in Fig. 4.
A description will be given first of the address setting.
; From the configuration data generation unit 3, the data 714 to 721 are transferred as configuration RAM write addresses to the register 610 and "1101" is transferred as the addresses 700 to 703 to the decoder 600 and a strobe pulse 704 is added to the NAND gate 607. The decoder 600 operates in accordance with the fact that the address 703 is "1" and the output signal 708 from the decoder 600 becomes "1", with the result that an output signal 780 from the NAND gate 604 is applied to the register ~t 608 to set therein the data 714 to 721.
" ~ -Next, the addresses 700 to 703 becomes "0001" and the de,c~de~
output signaI 705 of the\600 becomes ~ln. Further, the strobe ~` pulse 704 is provided, by which the output signal 722 of the ~, . , NAND gate 601 is applied as a set signal to the flip-flop 609 which serves as an address control register. By setting of the flip-flop 609, the signals 744 and 745 become "1" and "0"
respectively. Consequently, the multiplexer 633 outputs the output signals 736 to 743 of the register 608 as the address 754 to 761 of the RAM's 625 to 632.
Then, data to be written in the RAM's 625 to 632 are transferred as the data 714 to 721 and "0101' is transferred as the data 700 to 703, making the output signal 707 of the decoder 600 "1". By the application of the strobe pulse 704, ~15~2~l2 the output signal 724 of the NAND ~ate 603 is provided as a set signal to the register 610 to set therein the data 714 to 721.
Thereafter, the addresses 7~0 to 703 become "1111" and the output signal 712 from the decoder 600 become "1". By the application of the strobe pulse 704, the output signal 726 of the NAND gate 606 is applied as a clock to each of the flip-flops 617 to 624. As a consequence, the data 714 to 721 set in the register 610 are set as the data 764 to 753 in the flip-flops 617 to 624, whose set outputs ~4 to 771 are provided to the RAM's 625 to 632.
Next, the addresses 700 to 703 are rendered into "0111"
and the output signal 711 of the decoder 600 becomes "1", and by the application of the strobe pulse 704, the output signal 725 of the NAND gate 605 becomes "0" and is applied as a writ:e -enable signal to each of the RAM's 625 to 632. As a result of this, write data which are the set outputs 764 to 771 of the flip-flops 617 to 624 are written in the RAM's 625 to 632 in accordance with the addresses 754 to 761 provided from the multiplexer 633.
By repeating the above operations, desired data are written in the RAM!s 625 to 632. Upon completion of this write, the addresses 700 to 703 become "1001" and the output signal 706 of the decoder 600 becomes "1". Then, when the strobe pulse 704 is applied, the output signal 723 of the NAND gate 602 becomes "0" to reset the flip-flop 609, whose output signals 744 and 745 become "0" and "1", respectively. As a consequence, the multi-plexer 633 outputs access addresses 728 to 735 as the addresses 754 to 761.
_ g _ ~lS~Z~Z
~ hen the RAM's 625 to 632 are supplied with the addresses 754 to 761 as a result of the application of the access addresses 728 to 735, data previously written in the RAM15 625 to 632 are read therefrom as read data 772 to 779, which correspond to the first to eighth configuration unit select signals in Fig. 1 and become a signal for selecting one of the configuration units 6 to 13 of the main storage 4.
In the case of the main storage 4 having the eight configu-ration units 6 to 13, the co4figuration RAM is sufficient to have a 3-bit configuration, but the~above embodiment is arranged so that a configuration unit select signal of 8 bits from the RAM' s 625 to 632 may be outputted so as to cope with expansion of the configuration unit.
As has been described in the foregoing, according to this invention, in a data processing system employing a central data processor unit and a main storage unit in combination, a configuration RAM is used in a main storage controller, and a eonfiguration data generation unit is provided outside the main storage unit for producing configuration RAM write information, and an address from the central processor unit is used as an address input to the eonfiguration RAM and an output data therefrom is used as a main storage eonfiguration unit select signal; therefore, the main storage configuration and the main storage configuration unit selection can be achieved at the same time and with a small quantity of hardware used.
While the present invention has been described with respect to a specific embodiment thereof, it is to be understood that the ~15;22~Z
present invention is not limited thereto in any way but covers .~ny and all changes and modificati~ns which will become possible within the scope of the appended claims.
~ . "~ ~
:: :
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Claims (3)
- WHAT IS CLAIMED IS:
l. A main storage configuration control system for a data processing system which is provided with a main storage unit comprising a main storage composed of a plurality of configuration units and a main storage controller for selecting one of the configuration units of the main storage and controlling read and write of information with respect to the selected configuration unit, and a central processor unit, the main storage configuration control system comprising:
a reloadable configuration unit select information storage means for outputting configuration data in accordance with an address from the central processor unit; and a configuration unit selection controller for writing in the configuration unit select information storage means con-figuration data from a configuration data generation unit provided outside the main storage unit and controlling read-out from the con-figuration unit select information storage means in accordance with the address from the central processor unit;
wherein the configuration data is written by the configura-tion unit selection controller in the configuration unit select information storage means and read therefrom in accordance with the address from the central processor unit to select one of the configuration units of the main storage for an access thereto. - 2. A main storage configuration control system according to claim 1, wherein the configuration unit select information storage means is formed by a random access memory.
- 3. A main storage configuration control system according to claim 1, wherein the configuration unit selection controller has a multiplexer for selecting addresses from the configuration data generation unit and the central processor unit to the con-figuration unit select information storage means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15482778A JPS5580164A (en) | 1978-12-13 | 1978-12-13 | Main memory constitution control system |
| JP154827/1978 | 1978-12-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1152212A true CA1152212A (en) | 1983-08-16 |
Family
ID=15592738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000341797A Expired CA1152212A (en) | 1978-12-13 | 1979-12-13 | Main storage configuration control system |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4562532A (en) |
| JP (1) | JPS5580164A (en) |
| AU (1) | AU532288B2 (en) |
| CA (1) | CA1152212A (en) |
| DE (1) | DE2949768C2 (en) |
| ES (1) | ES486724A1 (en) |
Families Citing this family (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5740790A (en) * | 1980-08-25 | 1982-03-06 | Fujitsu Ltd | Storage control system |
| IT1153611B (en) * | 1982-11-04 | 1987-01-14 | Honeywell Inf Systems | MEMORY MAPPING PROCEDURE IN DATA PROCESSING SYSTEM |
| US4630230A (en) * | 1983-04-25 | 1986-12-16 | Cray Research, Inc. | Solid state storage device |
| US4829467A (en) * | 1984-12-21 | 1989-05-09 | Canon Kabushiki Kaisha | Memory controller including a priority order determination circuit |
| US4658359A (en) * | 1984-12-31 | 1987-04-14 | The United States Of America As Represented By The Secretary Of The Navy | Method for managing redundant resources in a complex avionics communication system |
| US4744025A (en) * | 1985-05-02 | 1988-05-10 | Digital Equipment Corporation | Arrangement for expanding memory capacity |
| CA1234224A (en) * | 1985-05-28 | 1988-03-15 | Boleslav Sykora | Computer memory management system |
| JPS6219904A (en) * | 1985-07-18 | 1987-01-28 | Diesel Kiki Co Ltd | Controller using microprocessor |
| JPS62124689A (en) * | 1985-11-25 | 1987-06-05 | Nec Corp | Programmable chip select signal generating circuit |
| US4740916A (en) * | 1985-12-19 | 1988-04-26 | International Business Machines Corporation | Reconfigurable contiguous address space memory system including serially connected variable capacity memory modules and a split address bus |
| US4980850A (en) * | 1987-05-14 | 1990-12-25 | Digital Equipment Corporation | Automatic sizing memory system with multiplexed configuration signals at memory modules |
| US5115511A (en) * | 1987-09-08 | 1992-05-19 | Siemens Ak. | Arrangement for loading the parameters into active modules in a computer system |
| US5268319A (en) * | 1988-06-08 | 1993-12-07 | Eliyahou Harari | Highly compact EPROM and flash EEPROM devices |
| US5142638A (en) * | 1989-02-07 | 1992-08-25 | Cray Research, Inc. | Apparatus for sharing memory in a multiprocessor system |
| EP0617363B1 (en) | 1989-04-13 | 2000-01-26 | SanDisk Corporation | Defective cell substitution in EEprom array |
| US5168555A (en) * | 1989-09-06 | 1992-12-01 | Unisys Corporation | Initial program load control |
| CA2028551A1 (en) * | 1989-11-03 | 1991-05-04 | John S. Thayer | Data destination facility |
| US5179686A (en) * | 1990-08-16 | 1993-01-12 | Ncr Corporation | Method for automatically detecting the size of a memory by performing a memory warp operation |
| US5206952A (en) * | 1990-09-12 | 1993-04-27 | Cray Research, Inc. | Fault tolerant networking architecture |
| US6230233B1 (en) * | 1991-09-13 | 2001-05-08 | Sandisk Corporation | Wear leveling techniques for flash EEPROM systems |
| AU4221993A (en) * | 1992-05-04 | 1993-11-29 | Compaq Computer Corporation | Single map data destination facility |
| US5537646A (en) * | 1992-11-19 | 1996-07-16 | The United States Of America As Represented By The Secretary Of The Navy | Apparatus initialized for selected device based upon timing, interrupt, and DMA control commands within configuration data passed from processor to transfer data to selected device |
| US5446860A (en) * | 1993-01-11 | 1995-08-29 | Hewlett-Packard Company | Apparatus for determining a computer memory configuration of memory modules using presence detect bits shifted serially into a configuration register |
| US5341494A (en) * | 1993-02-12 | 1994-08-23 | Compaq Computer Corporation | Memory accessing system with an interface and memory selection unit utilizing write protect and strobe signals |
| US5586300A (en) * | 1994-07-20 | 1996-12-17 | Emc Corporation | Flexible addressing memory controller wherein multiple memory modules may be accessed according to comparison of configuration addresses |
| US6047361A (en) * | 1996-08-21 | 2000-04-04 | International Business Machines Corporation | Memory control device, with a common synchronous interface coupled thereto, for accessing asynchronous memory devices and different synchronous devices |
| US6314489B1 (en) * | 1998-07-10 | 2001-11-06 | Nortel Networks Limited | Methods and systems for storing cell data using a bank of cell buffers |
| US6694385B1 (en) * | 1999-09-10 | 2004-02-17 | Texas Instruments Incorporated | Configuration bus reconfigurable/reprogrammable interface for expanded direct memory access processor |
| CN100483552C (en) * | 2002-10-28 | 2009-04-29 | 桑迪士克股份有限公司 | Automated wear leveling in non-volatile storage systems |
| US6928511B2 (en) * | 2003-03-03 | 2005-08-09 | High Tech Computer, Corp. | Method and system for managing virtual memory |
| CN106547719A (en) * | 2016-09-26 | 2017-03-29 | 中国电子科技集团公司第二十九研究所 | A kind of system communication and control process synchronous method |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3902164A (en) * | 1972-07-21 | 1975-08-26 | Ibm | Method and means for reducing the amount of address translation in a virtual memory data processing system |
| JPS532296B2 (en) * | 1973-03-19 | 1978-01-26 | ||
| FR130806A (en) * | 1973-11-21 | |||
| DE2364408C3 (en) * | 1973-12-22 | 1979-06-07 | Olympia Werke Ag, 2940 Wilhelmshaven | Circuit arrangement for addressing the memory locations of a memory consisting of several chips |
| CA1053352A (en) * | 1974-11-12 | 1979-04-24 | Scott A. Inrig | Method for providing a substitute memory module in a data processing system |
| US3967104A (en) * | 1974-11-26 | 1976-06-29 | Texas Instruments Incorporated | Direct and indirect addressing in an electronic digital calculator |
| DE2524802A1 (en) * | 1975-06-04 | 1976-12-16 | Siemens Ag | Working memory arrangement for several different processes - employed in data processing installation of time sharing operational type |
| US4028684A (en) * | 1975-10-16 | 1977-06-07 | Bell Telephone Laboratories, Incorporated | Memory patching circuit with repatching capability |
| US4149244A (en) * | 1976-06-07 | 1979-04-10 | Amdahl Corporation | Data processing system including a program-executing secondary system controlling a program-executing primary system |
| US4244032A (en) * | 1977-12-16 | 1981-01-06 | Oliver Douglas E | Apparatus for programming a PROM by propagating data words from an address bus to the PROM data terminals |
| US4223381A (en) * | 1978-06-30 | 1980-09-16 | Harris Corporation | Lookahead memory address control system |
| US4320453A (en) * | 1978-11-02 | 1982-03-16 | Digital House, Ltd. | Dual sequencer microprocessor |
| US4281379A (en) * | 1978-12-18 | 1981-07-28 | Mcdonnell Douglas Corporation | Computer driven control system for a numerically controlled machine tool |
| US4394734A (en) * | 1980-12-29 | 1983-07-19 | International Business Machines Corp. | Programmable peripheral processing controller |
-
1978
- 1978-12-13 JP JP15482778A patent/JPS5580164A/en active Pending
-
1979
- 1979-12-06 AU AU53530/79A patent/AU532288B2/en not_active Ceased
- 1979-12-10 ES ES486724A patent/ES486724A1/en not_active Expired
- 1979-12-11 DE DE2949768A patent/DE2949768C2/en not_active Expired
- 1979-12-13 CA CA000341797A patent/CA1152212A/en not_active Expired
-
1982
- 1982-05-24 US US06/381,554 patent/US4562532A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE2949768C2 (en) | 1986-09-11 |
| AU5353079A (en) | 1980-06-19 |
| ES486724A1 (en) | 1980-09-16 |
| JPS5580164A (en) | 1980-06-17 |
| DE2949768A1 (en) | 1980-06-19 |
| US4562532A (en) | 1985-12-31 |
| AU532288B2 (en) | 1983-09-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |