CA1158738A - Video and data distribution module with subscriber terminal - Google Patents

Abstract

VIDEO AND DATA DISTRIBUTION MODULE WITH SUBSCRIBER TERMINAL
ABSTRACT OF THE DISCLOSURE

A subscriber data distribution system comprising first means for translating data received from a transmission line and transmitting the data to a subscriber terminal via a subscriber drop, second means for translating data received from a subscriber terminal and transmitting the data to the transmission line, the first and second means including means for isolating the transmission line from the subscriber terminal, and for regenerating the data transmitted both to and from the subscriber terminal.

Description

~1 This invention relates to transmission systems and 02 particularly to two-way interactive distribution and subscriber 03 terminals.
04 Systems have been proposed for -the distribution o~
05 data to individually addressed su~scriber terminals, data and 06 video acquisition and interaction from and between subscriber 07 terminals, acquisi-tion of data from energy rneters, burglar and 08 fire alarms, etc., located on a subscriber's premises, etc.
09 These systems are most efeiciently implemented using a "tree"
type distribution system along CATV distribution system model.
11 In this system a main trunk, fed from a head end terminal, eeds 12 a plurality of branch lines, with individual subscribers 13 connected -to the branch lines. This system is of course one 14 way, cable TV programs beiny distributed to various subscribers.
Such system have been in the past limited in the 16 acquisition of data from the subscribers toward the head end by 17 the problem of noise gathering. This problem results in noise 18 from subscriber terminals adding and being amplified by return 19 amplifiers, seriously degrading the signal quality. Accordingly return signals have been limited to high amplit~de, very low 21 fre~uency signals, such as what could be produced by burglar 22 alarms, fire alarms, and energy meters.
23 The two-way transmission oE data at high speed, 24 in which useful amounts of data from a large number o-E
subscribers must be forwarded to a head end terminal however, 26 has been a problem. Of necessity, to accommodate a large number 27 of subscribers on a typical tree type system, the signal speed 28 must be significantly higher than the relatively simple systems 29 noted above.
In the present invention, the noise gathering aspect 31 of the return direction transmission is substantially reduced by 32 introducing a video and data distribution module which 33 regenerates data passing in both directions. BecausP the data 34 is regenerated, noise received from the subscriber terminals is substantially reduced. The present invention is directed to the 36 first data regeneration module and its associated group of 37 subscriber terminals.
38 In the present system, it is preferred that ~{`? ~ ~ ~

~L~LS~37~8 01 transmission should take place according to a packetized ~S-1 ~2 format. In a typical ~S-l format, the data signal is forwarded 03 in frames, 8000 frames per second being transmitted. Each frame 04 is comprised of ~93 bits, divided into 24 time slots, and one 05 frame bit, each time slot being comprised of 8 bits. Each of 06 the 24 time slots thus provides one channel.
07 The 193rd bit in each frame is called a frame bit.
08 Twelve frames form a superframe; the frame bits on each 12 09 frames forming a predetermined repeating ~ttern. The frame bit pattern is used for synchronization.
11 The 8th bit of each time slot on the 6th frame and 12 each 12th frame thereaf-ter forms a low speed so-called "A"
13 signa].ling channel. The 8th bit of each time slot on the 12th 14 frame and each 12th frame thereafter ~orms a second low speed so-called 'IB" signalling channel. Each of the A and B
16 signalling channels provides 24, 666 bit per second data 17 channels. Each of the 24 time slots within a frame provides a 18 64 kilobits per second data channel.
19 The problem of synchronization between terminals of the system is solved using an invention described in Canadian 21 patent application serial 350,913, filed April 30, 1980 and 22 assigned to the same assignee.
23 In general, the inven-tion is a subscriber data 24 distribution system comprising first means for translating data received from a transmission line and transmitting the data to a 26 subscriber terminal via a subscriber drop, second means for 27 translating data received from a subscriber terminal and 28 transmitting the data to the transmission line, the first and 29 second means including means for isolating the transmission line from the subscrib~r terminal, and for regenerating the data 31 transmitted both to and from the subscriber terminal.
32 More particularly, an embodiment of the invention is a 33 subscriber communications terminal comprising a modem for 34 receiving data signals modulated on an incoming carrier having a irst frequency, or deriving a bit clock signal from the 36 incoming carrier and for transmitting data signals on an 37 outgoing carrier having a second frequency, means for applying 38 the received data signals to a bus system, means for connecting ~.~

37~38 01 a pLurality of ports to the bus system, the ports being adapted 02 to connect clata generating ~pparatus to the bus system, when 03 enabled, means for applying outgoing data slgnals to the modem 04 for modulation on the outgoing carrier, control means connected OS to the bus system and to the means for connectiny a plurality o-f 06 ports for controlling the operation of the ports, and for 07 generating said outgoiny data siynals in response to -the 08 application of control siynals :Erom the data generation 09 apparatus to the bus system, in synchronization with said bit clock.
ll According to another embodiment, the invention is an 12 interactive buffer and controller module for distributed 13 subscriber terminals comprising means for receiving incoming 14 data signals from a transmission line, the data signals being divided into a plurality of frames, each frame being divided 16 into a plurali-ty of channels, each channel having a 17 predetermined number of bits, each Erame terminating with a 18 frame bit, the data signals designated as address, data and l9 control signals, means for stripping off the control signals and integrating new control signals wi-th the data signals, means for 21 carrying the data and new control signals to an output switching 22 circuit, a plurality of subscriber drops, means for switching 23 the data and new control signals to predetermined ones of the 24 subscriber drops, and controller means for controlling the switching means whereby said data ana new control signals are 26 applied to designated ones of said subscriber drops.
27 Features and the preferred embodiment of the invention 28 will be better understood upon reading the detailed description 29 below, in conjunction with the following drawings, in which:
Figure l is a general block diagram of a system using 31 the invention;
32 Figure lA is a frequency diagram showing the 33 frequencies of transmissions in both directions, 34 Figure 2A is a general block diagram of a subscriber terminal, 36 Figure 2B is a general block diagram of the video-data 37 distribution module, 38 Figure 3 is a diagram of the preferred form of a modem 39 ~ ~ 3 01 used in the video-data distribution moclule, 02 Figure 4 is a diagram of the elements o~ the video 03 dist~ibution module translating data Erom the transmission line 04 to the su~scriber terminal, 05 Figure ~A is a block schema-tic oE a circuit for 06 generating timing signals, appearing on the same sheet as Figure 07 6, 08 Figures 5 and SA form a diagram of the portion of the 09 data distribution module which translates da-ta from the subscriber terminal to the outward-yoing transmission line, 11 Figure 6 is a diagram of a modem and interface circuit 12 between the vi~eo-data distribution module and the subscriber 13 terminal, 14 Figures 7 and 8, when placed together, forms the diagram showing the preferred embodiment of a subscriber 16 terminal, 17 Figure 9 is a logic schema-tic of a synchronization 18 detector and Figure 10 is a diagram of a pre~erred form of a 19 television converter.
Turning first to Figure 1, a general system of the type 21 which uses the invention is shown. A head end 1 is coupled to a 22 wide band, two-way transmission medium 2 such as a coaxial 23 cable, fiber optic link, or the like. The head end includes a 24 cable TV distribution frame 3, of well known form, which provides television channels such as channels 2-6, A-W and 7-13 26 as well as F.M. broadcasts. 'rhese signals are applied through 27 coupler 4 to transmission medium 2. It may be seen in Figure lA
28 that these signals generally are transmitted from 50 megahertz 29 up to about 300 megahertz, although higher frequency signals can be transmitted as such distribution systems improve in 31 capability.
32 An interactive data system is also coupled to the 33 transmission medium. This generally is comprised of a data 34 storage and control frame 5, which includes a computer, a distribution control terminal DCT 6, which is connected via 36 modem 7 to coupler 4, and which couples the signal to -the 37 transmission medium. The system including data storage and 3~3 control, distribution control terminal 6, and modem 7 is an 39~ 4 ., . !

37;~3 01 interactive terminal and both receive~ and transmits data. This 02 terminal poLls individual remote stations, accesslng data stored 03 thereat, and forwards instructions and data to the remote 04 terminals. ~ata which is gathered are, for example, pay T.V.
05 channel accessing data, T.V. converter channel change data, 06 opinion polling, energy meter usage data, requests for specific 07 data to be accessed, as well as burglar and fire alarm 08 triggering data, etc.
09 While the head end does not form part of the present invention, it should be noted tha~ is preferred tha-t the data 11 signals should be in -the form of -t~he well known DS-l type of 12 transmission. In this form of transmission, the data is 13 transmitted in frames of 193 bits, the 193rd bit ~orming a 14 so-called frame bit. Tha remaining 192 ~rames are divided into 24 time slots of 8 bits each. Preferably t~e da-ta is 16 transmitted in packets of information, which includes 17 destination address, instruction, da-ta, parity bits, and 18 termination bits. Signals transmitted from -the head end koward 19 the remote stations are preferably modulated on a 12.35 megahertz carrier, and signals received at the head end are 21 preferably modulated on a 6.17 megahertz signal. The frequency 22 allocations are shown in Figure lA, although others can be used 23 if more appropriate in some electromagnetic environments.
24 ~onnected to the -transmission medium are remote video data distribution modules RVDM 8. The RVDMs are located in 26 subscriber neighbourhoods, each RVDM serving typically 12 27 households. Each RVDM is coupled via two-way subscriber drops 9 28 to a subscriber terminal unit STU 10, located typically in the 29 basement of a subscriber's home 11. Connected to -the STU is an asynchronous bus 12, to which such typical pieces o~ apparatus 31 as keypads 13, keyboards, burglar alarms, or other addressable 32 modules are connected. Also connected to the STU, in the 33 alternative to being connected to the asynchronous bus, are 34 interface circui-ts connected to burglar or fire alarm switches 14, energy meters 15, or the liXe. A T.V. set 16 is also 36 connected to the STU for receiving T.V. channels. The T.V. set 37 is normally connected to the subscriber drop 9, which carries 38 the T.V. channel along with the data. However, as will be ~.~LS~73~
01 described later, a T.V. set or other video monitor can be 02 connected to a high speed unit which is an optional portion of 03 the STU for displaying alpha-numeric or graphical data. Clearly 0~ with the ~acility of the connection of keypads, and data 05 addressed from the STU to the head end and return, an 06 interactive data system is afforded. However this depends on 07 the substantial reduc-tion of noise genera-ted by -the myriad of 08 data generation modules at each of up to several hundred or 09 thousand subscribers connected eventually to each head end. The combination of the RVDM and STU blocks -the noise gathering, and 11 facilitates the provision of an interactive two-way data system.
12 Figure 2A is a general block diagram of the prefsrred 13 form of the STU. m e two-way transmission line, such as coaxial 14 cable, constituting subscriber drop 9 is connected to a modem 18. A common T.V. set 16 is connected to modem 18 for receivin~
16 CATV television channels carried on subscriber drop 9. Modem 18 17 demodulates the data signals and applies them to a bus system 18 19, from where they are received by a control systern 20. The 19 con-trol system also addresses a plurality of ports 21, which are shown as two-way ports, and which are connected to the bus 21 system 19. Control 20, upon receiving signals addressed by the 22 data storage and control 5 and the DCT 6 to specific ports, 23 activates the ports and applies data thereto or receives data 24 therefrom according to its internal timing.
An UART is also connected to data bus system 19, and 26 as is well known translates data addressed -thereto from parallel 27 to serial, with an asynchronous Eormat, having a start bit, 28 address sequence, data sequence, parity bit, and termination 29 bit. The UART is connected via asynchronous bus 23 to one or more addressable UARTs 22. Various types of keypads, keyboa~ds, 31 displays, etc., are connected to the addressable UARTs, as will 32 be described in more detail later. Also energy meters, burglar 33 alarms, etc., can be connected to the addressable VART.
34 Alternatively as will be appreciated in the description below, signals from these devices can be connected directly into the 36 STU via one of its data ports.
37 Also connected to the bus system 19 is a bit 38 synchronization circuit 24, which is also connected to a frame counter Z5. The con~rol circuit 20 ls aLso connected to the bit synchronization circuit and f-rame counter.
The output oE the frame counter is a timing signaL
bus 26, which is connected to a time slot assi&nor 27 and tim-ing generator 28. The time slot assigno-r and timing generator are also both connected to the bus system 19.
The outputs oE the time slot assignor 27 and timing generator 28 are connected to a synchronizer 29A, which has its outputs connected to the control inputs of a plurality of switches 29-32, which can be tri-state gates controlled by the synchronizer. Under control of the timing generator and time slot assignor,the synchronizer closes one of each of the gates 29-32 at the proper time. This will be discussed in more de-tail later.
Bus system 19 also is connected through decoders (not shown) to switches 29 and 31, whereby data signals can be appl-ied to a common output lead 33. Common output lead 33 is con-nected to the input of a delay build-out circuit 34, the output of which is applied to modem 18 for remodulation and outputting on subscriber drop 9 to the video and data distribution module 8.
The present invention also provides means for operat-ing a digital telephony system. A telephony module 35, which includes filters, a two/four wire network, a coder-decoder (CODEC), etc., is connected to a local analog telephone set 36.
The codec 37 interfaces the telephony module 35 with the data output of modem 18. Timing information is derived from the time slot assignor 27. A port 38 is connected between bus system 19 and telephony module 35, for commanding and reading supervisory signals and ringing. The output of codec 37 is connected to the input of switch 30 for application of outgoing ~' 7;~8 data signals to the subscriber drop. Another high speed port (not shown) can be utilized for receiving and transmitting high speed data to a remote clata terminal, and its outgoing signals are applied to the input of switch 32 (shown not connected). In this manner, signals are applied to the de-lay build-out circuit 34 for application to modem 18 and transmission by a subscriber drop 9 to the RVDM 8.
Delay build-out 34 has a variable delay, the con-trol inputs of which are connected to the bus system 19.
Under control of control system 20, the delay of delay build-out 34 is established, just sufflcient to transmit data signals to the RVD~I whereby it arrives in exact synchronism with the signals transmitted from the RVDM to the STU. The mechanism by which this operates will be described in more detail later.
Turning now to Figure 2B, a basic block diagram of the RVDM is shown. Transmission medium 2 is connected via a normal CATV splitter to the RVDM the input line of which is shown at 627. A low pass filter and splitter 625 passes signals includin~ 18 megahertz, and blocks those above. Two signals preferably, with control channels in inverse rela-tionship to each other, constituting two DS-l channels are applied in parallel to modems 626. While two modems are pre-ferred to handle both signals, (with control signals invert-ed from each other for redundancy and error correction), the signal operation and translation below, described in de-tail, will relate only to one signal since both signals are handled similarly.
The bidirectional signal is carried on bidirec-tional paths 727 to the control and logic 728 of the RVDM.

,:

Here the signals are processed in both directions, isolat-ing the STU from the transmission medium 2. The signals in both di-rections are passed thro~lgh modem 729, decoder 73Q
and through transceivers 731 to individual subscriber drops 9, leading to STUl, STU2..... STU8.
In operation the control and logic controls a switch in decoder 730, which sends and receives data signals to each of the STUs via corresponding STU drops in indi-vidual time slots allocated in sequence. In the preferred embodiment of the invention there are 12 STUs possible for each RVDM, and 24 time slots. Again in the preEerred embodi-ment of the invention, only one time slot, time slot 1 (TSl), is allocated or all the STUs, and data is transmitted and received from the STUs in that time slot.
The control and logic 728 is itself controlled by a microprocessor 732.
Also connected to transmission medium 2 is a high pass filter 733 which blocks frequencies below about 15 megahertz and passes CATV television signals which are, of course, of higher frequency. A plurality o television channel converters 833, one for each STU, is connected to the output of high pass ilter 733. The output of each con-verter is connected to a corresponding subscriber drop for transmission of a television channel along the subscriber drop, for reception by a television set, such as television set 16 (Figure 2A). Contro] inputs of converters 833 are connected to microprocessor 732.
Upon reception of converter control signals from a corresponding STU within an allocated time slot, wnich signals are received through transceiver 731, modem 729, control and logic 728 to processor 732, the corresponding 373~3 converter changes channels, and transmits the selected signal on channel 2 or 3 (or another unused channel) to the STU.
At the same time, the channel chang~ control information is retained by processor 732, and upon polling from a head end connected to transmission medium 2, the channel change in-formation is transmitted thereto for recording. In this manner pay T.V. selection or control signals can be record-ed at the head end, as well as the selection of special service or extended service television channels.
Further, interrogatiOn or control signals for various units connected to the ports or addressable UARTs at the STU are received from transmission medium 2, demodu-lated in modem 626, processed in control logic 72~, modulat-ed in modem 729 and are applied to the appropriate STU de-signated by the time slot of the received data or, if the data is received in packets, by the address of the port at the STU. The STU demodulated the received signal in modem 18, the control signal is received in control 20 ~Figure 2A), and the appropriate port is enabled and addressed.
.'0 Return signals from the port or data generation apparatus at the STU is passed via bus 19 and switch 31 to delay build-out 34. Switch 31 is controlled by synchronizer 29 which itself is controlled by time slot assignor and tim-ing generator 28, further under control of the timing signals ar.d controller 20. The signals are delayed in build-out 34 until the proper time for transmission within the prede-signated time slot, and is passed into modem ]8 for remodu-lation and transmission via subscriber drop 9 to the RVDM.
Here it is received in transceiver 731, passed through modem 729, control logic 728 to processor 732. Under control of ,~ . ~

~S~3~3 processor 732, the data is reEormattect, delayed for proper synchronization at the RVVM, and is t-ransmitted via modem 626 to transmission medium 2 to the head end, where it is received in exact synchronization, one frame delayed, with the outgoing signal at head end 1.
It should be noted that data from the RVDM is transmitted to the transmission line in two data streams, one the inverse of the other, one modulated on a 6.17 mega-hertz carrier and one modulated on a 9.26 megahertz carrier.
~ata is received from the transmission line as two data streams, one with control bits the inverse of the other, one modulated on a 12.35 megahertz carrier and one modulated on an 18.53 megahertz carrier. The data is thus considered as being contained within a 4.35-30 megahertz band width.
In addition, the transmission line carriers power for the RVD~I, typically 40-60 volts at 60 hertz, and video signals, typically 50-300 megahertz, including f.m. radio, 88-108 megahertz.
The circuit to be described below assumes that all - ~ signals except the nominally 6, 9, 12 and 18 megahertz signals have been stripped off the transmission line, and deals with those signals only. Since in this invention the bit clock is derived from the nominally 12 megahertz carr-ier signal, the incoming signals will be considered first.
The frequencies referred to below will be nominal, but will actually be multiples of 1.544 megahertz as noted above.
Turning to Figure 3, the 12 and 18 megahertz signals are received from the transmission line 300, and are applied to a 9 megahertz notch filter 301 via directional coupler 302. Directional coupler 302 is a conventional CATV

-lOA-~S8738 type coupler or the like and need merely have a 30 megahertz band width.
The signal is passecl through notch fiLter 301, low noise preamp:L.ifier 303, another 9 megahertz notch filter 304, IO megahertz high pass .Eilter 305, to the input of video amplifier 306. The action of the aforenoted 9 megahertz notch filters and -lOB-'7~

01 10 megahertz high pass ~ilter is to reduce the 9 megahe.rtz 02 outgoing signal (which signal is the closest signal to the 12 03 megahertz signal to be received), to a very low level, and to 04 otherwise pass signals above 10 megahertz, which include the 12 05 and 18 megahertz DS-l modulated signals to video ~mplifier 306.
06 Video amplifier 306 separates the 12 and 18 megahertz ~7 signals, which are respectively applied via gain control 08 potentiometers 307 and 308 to the input of low level a.m.
09 de-tectors 309 and 310. These de-tectors are preferably synchronous detectors, such as injection locked oscillators 11 (such as those typically used in commercial television sets f~r 12 horizontal and vertical oscillators).
13 The outputs of detectors 309 and 310 are respectively 14 connected through low pass filters 311 and 312 and hard limitors 313 and 314 to leads 100 and 101. These leads carry the 16 demodulated DS-l bit streams. It is preferred that low pass 17 filters 311 and 312 should be resonant at the bit rate, and 18 should be heavily damped. It is also preferred that limitors 19 313 and 314 should have above 5% hysteresis, in order to reduce multiple zero crossings for a given amount of detected noise.
21 The output from low pass filter 311 is also used to 22 control the gain of both the 12 and 18 megahertz channels. This 23 output is applied to a detector and filter 315 (which can be 24 merely a series co~nected diode ~ollowed by a parallel capacitor), i.e., a peak and hold filter. The output of 26 detector and filter 315 is applied through buffer 316 and 27 integrator 317 to a gain control input 318 of video amplifier 28 306.
29 It was noted earlier that in the present invention the 12 megaher-tz carrier is used to provide a bit rate clock. The 31 AFT output of detector 310, which carries the 12 megahertz 32 signal is applied to fast limiter 319, and the output thereof, 33 on a 12 megahertz signal is applied through buffer 320 to lead 34 321. This signal is used for conversion to the bit clock after division by 8 to 1.544 megahertz, which will be shifted to the 36 center of the demodulated data bits.
37 The output of limiter 319 is applied through a 38 divide-by-2 circuit 322 to be converted to six megahertz, ~i ~.c` ..

~l~5~7~3~3 01 through buffer 323 to the input of 6 megahertz low pass ~ilter 02 324.
03 ~he AFT signal ~rom video cletector 309, 18 megahertz, 04 is applied through fast limiter 325 and di~ide-by-2 circuit 326 05 and b~ffer 327 -to -the input of 9 megahertz low pass filter 328.
06 Low pass filters 324 and 328 are matched filters, which convert n7 square waves to sine waves.
08 The outgoing DS-l signals are applied via leads 157 09 and 157a, buffers 329 and 330 to the inputs of respective low pass filters 331 and 332. These filters are preferably raised 11 cosine filters, and are heavily damped low pass tuned filters 12 which peak at 1/2 the bit rate.
13 The output of filter 324, which carries the 6 14 megahertz sine wave carrier, and filter 331, which carries one channel of DS-l data, are applied to t~e inputs o~ balanced 16 modulator 333. Similarly, the 9 megahertz carrier signal at the 17 output of low pass filter 328 and the second channel data 18 signals at the output of low pass filter 332 are applied to 19 inputs of balanced modulator 334.
The outputs from modulators 333 and 334 are 21 respectively applied through buffers 335 and 336 to the inputs 22 of combiner (summer) 337. The output of combiner 337 is 23 connected to the outgoing input of directional coupler 302, for 24 application to bidirectional transmission line 300.
We have thus seen how signals are removed from the 26 bidirectional transmission line and are provided as data 27 signals, and how outgoing data signals are modulated on carrier 28 signals at 1/2 the incoming frequency, and are applied to the 29 transmission line. At the same time, the 12 megahertz incoming carrier signal is utilized to form the bit rate clock, at 1.544 31 megahertz.
32 Turning now to Figure 4, the two DS~l bit streams on 33 leads 100 and 101 which are received from the main transmission 34 line modem are applied to latch 102. Since the bit streams are received from the main transmission line, they are typically 36 poorly shaped, and the latch is used to sample them and place 37 them into good pulse form with proper pulse width, etc. Lead 38 BCl connected to latch 102 clocks the latch at the assumed ~`

37~

01 centre of the data. The pulse on lead BCl is derived from a 02 timing con-trol circuit as will be described later.
03 The corcected pulse -two DS-l bit streams appear on 04 leads Dl and D2, and are applied to ~rame bi-t logic circuit 103 05 and a logical switching circuit 10~ ~or selecting one of the two 06 DS-1 streams on leads Dl or D2.
07 Frame bit strobe signals are applied from the timing 08 control to the T21 and T16 leads, which strobe the ~rame bit 0g logic circui-t in time with the assumed frame bits, that is, once every 193 bits. The output appears on sync lead 105, for 11 application to the microprocessor. The microprocessor samples 12 the pulses on the sync lead, and compares them with a stored 13 pattern.
14 The frame bit strobe on leads T21 and T16 should appear each 193 bits to provide a synchronization bit pat-tern on 16 the sync lead 105. However if the sync bit pa-ttern does not 17 match the stored sync bit pat-tern in the microprocessor, the 18 frame bit strobe signals are shifted one bit earlier. The 19 microprocessor continues -to monitor the sync bit pat-tern on sync lead 105 continuously, as the frame bit strobe signal shifts 21 toward the beginning of the frame.
22 At one point, the ~rame bit pat-tern matches the stored 23 pattern in the microprocessor. At that point the ~rame bit 24 strobe signal on leads T21 and T16 do no* shift any ~urther, and the frame -timing is assumed to have been found.
26 The microprocessor then monitors the frame bit on each 27 of sync lead 105 and 105a, which respec-tively carry the 28 synchronization bits for each of the DS-l lines. Assuming that 29 the two are ident~cal, synchronization is assumed to have occurred. However if one differs ~rom the other, it is assumed 31 that a glitch has occurred, or that one of the streams has gone 32 out of synchronization, or that equipment has malfunctioned.
33 One or the other stream can then be monitored or the timing can 34 be synchronized as described above.
Assulning that the ~rame timing has been ~ound, the A
36 channel signalLing bits are monitored. Assuming that the DS 1 37 stream on lead Dl is monitored, switching circuit 104 is 38 switched to apply the signal to the latch and shif-t register 39 ~ 13 ~i8~

106. This circ~lit is strobed on lead T17 in time with the A signalling bit, that is, the least significant bit, in frame 6 and every 12 Erames thereafter. The A signalling bit is received from switching circuit 104 and are first latched and then stored in the associated shift register serially, storing them eight bits at a time. Eight parallel bits at a time are then strobed onto the system data bus 107, for application through bidirectional interface 108 to the microprocessor. Since there are 24 A signalling bits to a Erame, this will occur three times for each A signall-ing bit frame.
The ~S-l stream is also applied from switching circuit 104 to switching circuit 109. It should be noted that the data carried includes the entire bit stream includ-ing the A signalling bits. However since it is intended that time slot 1 signals should be applied to the STU for control, switching circuit 109 switches between the lead carrying the full DS-l stream and a lead carrying substitute time slot 1 control signals, in switching circuit 109.
The new control signals are received from the microprocessor on data bus 107, pass through bidirectional interface 108 and inverter 111, and are applied to latch 112, from which, at the appropriate time designated by a signal from the microprocessor carried by lead 113, the signal is applied to bus 114. Bus 114 carries the new control signal to the input of shift register 115. Shift register 115 re-ceives the new control signals 8 bits at a time, and shifts them out serially to switching circuit 109.
Under control of timing signals on the T16 and T20 leads, switching circuit 109 switches between the DS-l data r ,i.~,) ~ 3 ~

bit stream and the new source of control signals in time slot 1 from shift register 115 which is substituted.
This signal is applied to latch 102 for synchron-ization with the incomLng bit stream, and is applied on lead 116 to the STU output modem.
At the same time this signal is applied to AND
gate 117 with the 193rd (frame) bit received from the tim-ing control, providing framing bits to the STU on lead 118, for synchronization.

7~

01 We have thus seen how demodulated input signals from 02 the main transmission line are received, how the system locates 03 the proper ~rame timing, extracts the A signalling bit stream 04 and applies it to the data bus for applica~tion to the 05 microprocessor. We have fur-ther seen how the DS-l bit stream is 06 applied to the STU with new or substitute control signals 07 applied in frame 1, in place oE those originally received from 08 the main transmission line.
09 Turning now to the timing control, Figure 4~, a clock signal is applied to BCl, to a divide-by-193 counter. This 11 circuit is well known and need not be described further.
12 However suf~ice to say that every 193 pulses of the bit clock, a 13 single output pulse is provided. This can be obtained merely by 14 subtracting 193 from the achieved count, and when a coincidence is found, an output pulse i5 generated. This pulse coincide 16 with the frame bit -timing.
17 ~owever in order to shift the timing of the frame bit 18 as is required for applica-tion to the frame bit logic circuit, 19 as described earlier, the counter is converted to a divide-by-192 counter. In this case, the frame bit shifts one 21 bit position, continuously shifting every 193 bits. When the 22 frame bit pattern has been found by the microprocessor as 23 described earlier the counter is converted back to a 24 divide-by-193 bit counter.
The bit clock pulses are also applied to bit decoder 26 125, time slot decoder 126, and frame decoder 127, which have 27 respective signals output therefrom divided respectively by the 28 bi-t timing, time slot timing, and frame timing, depending on the 29 required count. Since the bit clock signal applied thereto is shifted by counter 119, the outputs therefrom are also shifted 31 by one bit time slot. Their outputs are carried on bus 128 32 through gates 129 to timing bus 130. Timing bus 130 is 33 comprised of the aforenoted leads T16, T20, T21, etc.
34 Bit clock BCl of course carries the 1.55 megahertz clock signal, at the data rate, with its rising edge in the 36 middle o~ a data bit.
37 In the reverse direc-tion, signals are received from 38 the STU bo-th as control signals in time slot 1 (TS-l) and in ~.' : ~5~73~
01 designated time slots as polled by the RVDM in designated time 02 slots.
03 Normally a signal is sent to synchronize a STU by the 04 RVDM using the circuit already described in TSl by sending a 05 resync code to the STU. The STU responds by sending an 06 acknowledgement signal on what it considers -to be TSl. This 07 signal is used for detec-tion of synchronization, as will be 08 described below. Selected STUs are thus able to become 09 synchronized. Once synchroni7.ation has occurred, STUs are requested to trànsmit data in designated time slots, as 11 indicated by control messages in TSl.
12 Input from an STU received from a modem, as will be 13 described below, is received on lead 135, is inverted in 14 inverter 136, and is applied to synchronization (eye finder) detector 137, shown in detail in Figure 9. The purpose of the 16 synchronization detector 137 is to sample the received data at 17 its centre, or maximum reliability.
18 In synchronization detector 137, three flip flops 60, 19 61 and 62 have their data inputs connected together to a source of the input serial data bit stream, i.e., to the received DS-l 22 data stream. Clock source BCl is connected to the clock input 23 of flip flop 60 and samples the received data at its presumed 24 centre. Clock source BC2 is connected to the clock input of 26 flip flop 61 and the opposi-te phase of the clock source BC2, is 27 connected to the clock input of flip flop 62. It may thereEore 28 be seen that as clock BC2 advances, the input data appears 29 alternately at output Q of flip flops 61 and 62.
3l _ The rising edge of BC2 occurs 1/4 bit before that of 32 BCl. Therefore flip flop 61 samples the data 1/4 bit before the 34 assumed centre. The rising edge of BC2 occurs 1/4 bit after 36 that of BCl. Therefore flip flop 62 samples the data 1/4 bit 37 after -the assumed centre.

38 The Q outputs of flip flops 61 and 62 are respectively 39 connected to corresponding inputs of EXCLUSIVE O~ ga-tes 63 and 64. The output inputs of EXCLUSIVE OR gates 63 and 64 are 41 connected together to a flip flop 60.

, 373i~

The input data applied to flip flops 60, 61 and 62 is taken from the data received from the remote unit.
~t is only the phase of the pulses which are of concern, and not the actual data.
The outputs of EXCLUSIVE OR gates 63 and 64 are connected respectively to one input of corresponding OR
gates 65 and 66. ~he outputs thereoE are respectively con-nected to the data inputs of corresponding flip flops 67 and 68. The Q outputs of flip flops 67 and 68 are respec-tively connected to the second lnputs of the corresponding inverting OR gates 65 and 66. A clock source is connected to the clock inputs of flip flops 67 and 68, and the Q out-puts thereof form the outputs of the circuit QCCl and QCC 2, representing the difference in the sampled, from the received data.
If the signal is retarded from the STU, it must be advanced and lead QCCl has a high level signal on it.
Similarly if the signal from the STU is advanced, it must be retarded, and a signal appears on lead QCC2 which is high.
These leads are connected to the microprocessor circuit.
The microprocessor sends a control signal to the STU to ad-vance or retard its timing by 1/4 bit lntervals if either QCCl or QCC2 carry a high level signal. Accordingly the STU timing is shifted into synchronization in l/4 bit inter-vals.
The signal from the STU is also applied to latch and shift register 138 (Figure 5). The serial STU data is serially received, stored in the shift register, and applied to data bus 107, similar to latch and shift register 106.
Timing is determined by the signal on timing lead T9, from : `

7~

the timing control. It should be noted that all time slot 1 data passes into ]atch and shift register 13~, including all messages such as me~er reading data, video channel change data, etc.
Data from the STU is also applied to switching circuit 139 and to switching circuit 140. As will be noted later, this allows telephony and high speed data to be out-put to the central control.
The TSl data and messages received from the STU
having been received by the microprocessor via data bus 107 is reformatted into packets for transmission to the remote central ~S873~

01 control. The data i9 applied via bidirectional in-ter~ace 108, 02 inverter 111, latch 112 to bus 11~ and thence to shift register 03 141. This shift register operates identically to shift register 04 115, receivin~ data 8 bits at time and shifting -them out 05 serially to switching circuit 139, and via inverter 142 to 06 switching circuit 140.
07 The microprocessor also applies a HEX10 signal to 0~ switching circuits 139 and 140 for transmis3ion on TSl, for 09 synchronization detection.
The output leads 143 and 1~3' of switching clrcuit 139 11 and 140 carry the two DS-l channel signals for transmission to 12 the central control, after delay compensation.
13 Operation of switching circui-ts 139 and l40 thus 14 aEfords selec-tion of the leads carrying telephony and high speed data, etc., data from one or more of the STUs or local RVDM
16 destined ~or the cen-tral control, or A signalling channel data.
17 The determination of what signals should be applied to 18 output leads 143 and 143' via switching circuits 139 and 140 are 19 controlled by the microprocessor as determined in a connection memory which has been loaded via data received on leads 100 and 21 101 (described earlier) Erom the central control. Control 22 signals for ~witching circuits 139 and 140 are applied at 23 appropriate times to cause output leads 143 and 143' to be 24 switched to the appropriate input at the proper time.
The control signals for switching circuits 139 and 140 26 are received on bus 144 from the connection memory, and carries 27 logic signals to designate what time slot is assigned, whether 28 low speed data in on the time slot, whether output lead 143 or 29 143' is utilized, etc., and in general controls the logic timing of these switching circuits.
31 The output signals on leads 143 and 143' are applied 32 to latch 150, which is strobed by the bit clock BCl. As noted 33 earlier these bits are at the bit ratel of 1.544 megahertz.
34 The data stored in latch 150 is written into memory 151. The address of the storage is designated by the output of 36 a 64 stage counter 152 which is incremented by the bit clock 37 BCl. The output is applied through adder 153 to the address 3~ input of memory 151. If there is no further input to adder 153, ~d~

~5873l3 01 -the addre3s i9 desiynated by -the output of counter 152.
02 Assuming ~hat delay compensa-tion is to be provided, a 03 delay signal is received from data bus 107 by latch 154, which 04 ~ignal i9 a delay diEference numeral to be added to the output 05 of counter 152 by adder 153. Accordingly, when -the output of 06 latch 154 is enabled, the stored number is added to -the address 07 of counter 152 to designa-te a read address to memory 151.
08 Memory 151 is preferred to be of the type which writes 09 with its write/read (W/R) lead high, and reads with its W/R
input low. The signal on the W/R lead i~ applied from the BCl, 11 in synchronism with the output enable of latch 154. Accordingly 12 memory 151 writes data with scl high at an address indicated by 13 the output of counter 152, then reads the data out at an address 14 offset therefrom by the value of -the signal stored in latch 154.
The data read from memory 151 is applied to latch 155, 16 which is synchronized to the falling edge of signal BCl therein, 17 and is then applied via latch 156 and output bus 157 to the 18 output modem connected to the transmission line leading the 19 central control.
Latch 156 provides 1/4 bit synchronization by 21 selective connection of its strobe input S to one of four phases 23 of clock source BC1 which are 90 out-of phase, BC1, BC2, BC1 BC2. This selection is achieved in switching circuit 158 under 26 control from the microprocessor on bus 159. The lat-ter bus is 27 connected to the data bus via latch 160 which has its input 28 connected to the output of inverter 111.
29 The selection of which of the four bit clock phases are 90 (1/4 bit) out~of-phase is determined by the 31 microprocessor as a result of the presence or not of signals on 32 the QCCl and QCC2 leads which were described earlier. The 33 microprocessor sends phase corrections upstream as commands to 34 the upstream microprocessor. It should be noted -that should more than 360 correction be required, after shifting the phase 36 of the signal applied to the S lead of latch 156 by 360, the 37 signal stored in latch 154 is incremented by one bit position.
38 If synchronization is still not achieved, the 1/4 bit phase 39 shift cycles again, etc., until synchronization has occurred.

7~3 01 We have thus seen how the signal from an STU is 02 received, checked Eor 1/4 bit synchronization, and how data is 03 received by the microprocessor. Upon being re~ormatted, the 04 signal from the STU is applied through a switching circuit, is 05 written into a memory, and is read out of memory with a delay 06 determined under control oE the microprocessor, depending on -the 07 required delay compensation to ~orce signals to be in 08 synchroniza-tion at the next stage in the system such as the 09 central control. The output signal from -the memory is then resynchronized, corrected for phase in 1/4 bit intervals, and is 11 applied to a bus for reception by an output modem and 12 application to the transmission system to the central control.
13 The ~elephony or high speed data can be output 14 directly without being reformatted, under control of the data stored in the connection memory. Data directly ~rom the 16 microprocessor is inserted on on the ~ channel.
17 As described earlier, data is applied to data bus 107 18 through the latch and shift register 138, as received from the 19 incoming DS-l bit stream. This data is applied -to a central processing unit CPU200 (Figure 5A) through a bidirectional 21 interface 201. Preferably the CPU is type 6802, although other 22 CPUs could be used. The CPU is also connected to address bus 23 202, along with random access memory R~M203, read-only memory 24 PROM204 (which memories are also connected to data bus 107), chip select decoders 205, 205a and 205b, and mul-tiplexers 206a 26 and 206b. It has been found that RAM203 should be 8 bits wide 27 by 128 bits long, and PROM204 should be 4,096 bits by 8 bits.
28 Chip select decoder 205 should decode 1 of 8, 205a should decode 29 1 of 4, and 205b should 1 of 8.
Data applied to data bus 107 designates the STU
31 number, and as well the control information in TSl. Data 32 applied by the CPU to address bus 202 is comprised o~ the time 33 slot number, ~hich designates a memory address for the 34 connection memory. Data is stored in the connection memory, to be noted later, at addresses designating the time slot.
36 Therefore for particular STUs, which are to be accessed at 37 particular time slots, such time slots are designated by the 38 connection memory address which holds data to be output in the t l~

73~3 01 designated tilne slot.
02 Accordingly the CPU accesses STUs by looking up the 03 correspondiny address in PROM204 memory for the da-ta. It should 04 be noted that the STU can be accessed during more than one -time 05 slot. In the present system we have defined 24 time slots which 06 are randomly accessed, and shared among 12 STUs. An STU can 07 therefore be accessed on more than one time slot.
08 With the provision o the connection memory address on 09 the address bus 202, it is applied via switching circui-t 207 to the address input of connection memory 208. Data to be stored 11 therein is applied from bus 107 via switch 209 and bus 210 to 12 the data input terminals of connection memory 208. This 13 connection memory can be a 128 by 8 ~its random access memory 14 RAM.
Switching circuit 207 con-tains two positions, a write 16 and a read position. In the wri-te position, the address inputs 17 of RAM208 are connectecl to address bus 202, whereby data from 18 data bus 207 can be written. The switching clrcuit is placed in 19 the wri-te switch position under control o~ a chip select output 211 of chip select decoder 205, via buffer 212. This output 21 also provides chip select and R/W inputs for RAM208 via OR gates 22 213 and 213a. R~M208 is also operated via OR gate 213 under 23 control of a timing signal on lead T20 from timing bus 130~ The 24 R/W lead connected to OR gate 213a is an output of CPU 200.
Under normal condi-tion~, however, R~M208 will be 26 continuously read. A counter address bus 214 which is derived 27 from the counter 119 continuously increments under control of 28 the bit clock, providing a continuously incrementing read 29 address for RAM208. For reading, the chip select 205a decodes a signal from the CPU which switches switching circuit 20~ to the 31 read R position, whereby the counter address bus is connected to 32 the address inputs of RAM208.
33 RAM208 reads the memory location contents to bus 210, 34 which data is latched in la-tch 215. This data, which is 8 bits wide, utilizes four bits which designate the type of 36 in~ormation, such as telephone, high speed data, VRAM, etc., and 37 the other four bits designate the STU number. Data on ~he 38 aforenoted first four bits, the type of information, is applied ,, .~,, ;~

73~

01 to bus 114, which controls switching circui-ts 139 and 140, and 02 designates what type of information is applied to the outgoing 03 data streams. The latter four bits designating the STU number 04 is decoded and used to enable the transceivers to individual 05 STUs.
06 Multiplexers 20~a and 206b are used to apply data to 07 address bus 202. Connec.ed to the input of multiplexer 206a is 08 a DIP switch array 216, also connected to ground. Closure of 09 various switches designates the particular RVDM address.
Multiplexer 206a has its enable lead connected to an output of 11 decoder 205b.
12 Multiplexer 206b has its inputs connected to various 13 other leads mentioned earlier with respect to the RVDM, for 14 instance the ~CCl, QCC2, sync, B193, etc., leads, which provide polled hardware in~ut flags to the microprocessor. The enable 16 lead of multiplexer 206b is connected to another ou-tput of 17 decoder 205b.
18 A1SG connected to data bus 107 and address bus 202 is 19 a peripheral input device, which has an address bus 217 and a data bus ~18 connected -to a VRAM, shared amongst all STUs, and 21 video converters, each of which is individual to an STU.
22 Operation of the CP~J, memories, chip select decoders 23 and multiplexers are well known to persons skilled in the art 24 and will not b~ described further. A description of the operation of central processing units with their associated 26 memories, etc., may be obtained from Motorola, Inc., In~el 27 Corp., both of the United States, or from -the book Microcomputer 28 Primer, by Mitchell Waite and Michael Pardee published by Howard 29 W. Sams & Co. Inc. Similarly, it is assumed that a person skilled in the art would be able to derive various alternative 31 software for operation of the central processing unit and 32 associated memories, to provide the functions described in this 33 speciEication, and will not be given herein since the soEtware 3~ does not constitute the invention.
Figure 10 shows a block diagram of the preferred form 36 of the converter used in the RVDM. The VHF bus 165 is connected 37 via broadband amplifier 166 to the input of a low pass filter 38 167, which passes through all signals below 300 megahert~. The ~,~

01 output signal is applied via hybrid 168 to a directional coupler 02 69. If desired, one of the terminations on hybrid 168 can be 03 connected ~o a second rank o~ 12 subscribers, Gtherwise it is 04 terminated with, for example, 75 ohms.
05 Directional coupler 69 is connected to the emitter 06 input of g~ounded base transistor 70 via resistor 71. The 07 collector output applies the video signals to a mixer 72. A
08 local oscillator 73 has its output also connected to mixer 72.
09 Preferably local oscillator 73 is a digitally controlled phase locked loop, which has its digital selection inpu~ connected via ll a data bus 74 (reference 218 in Fig. 5A) to a microprocessor.
12 The microprocessor referred to is element 32 of Figure 2, and 13 the data bus 74 is control bus 40 of Figure 2B.
14 ~ccordingly upon receiving a channel selection request by means of a data word applied to digitally controlled phase 16 lock loop formin~ local oscillator 73, a local osci~lator signal 17 is mixed with the incoming video signals, producing an 18 intermediate ~requency signal.
19 The intermediate frequency signal i9 applied through Eilter 75, which can be a two-pole L-C filter, through amplifier 21 76, to a very sharp bandpass Eilter 77 centered on the IF signal 22 frequency. Preferably the bandpass filter 77 is a SAW filter.
23 In one prototype, the local oscillator provide a 24 digitally synthesized local oscillator signal frequency of between 430 and 680 megahertz, providing an intermediate 26 frequency of 380 megahertæ when mixed with the incoming signal.
27 The output signal of filter 77 is applied to one input 28 of mixer 78.
29 A further local oscillator tnot shown) generates a signal which is applied to all of the converters used in a 31 particular distribution terminal. This signal is applied to the 32 emitter input of a grounded base transistor 79 through resistor 33 80. This signal is applied to a tank circuit 81, to peak up its 34 amplitude, and a portion thereof is tapped of~ and applied to an input of hybrid 82. This signal which is at the output of 36 hybrid 82 is c~nnected to the second input of mixer 78, and as a 37 result, the down-converted intermediate frequency is applied to 38 a band split filter 83. The down-converted signal from mixer 78 7~3 01 passes through the low pass portion of Eilter 83 to i-ts output.
02 ~n ~.m. signal is applied to the emitter of grounded 03 base transistor 84 via resistor 85. Build out resistors from 04 resistor 85 can carry the .m. signal to the next converter if 05 desired.
06 The collector output of transi~tor 84 is connected to 07 the high pass portion of band stop Eilter 83, and is carried to 08 the output of the filter.
09 Where the local oscillator signal applied to transistor 79 is, for example, 436 megahertz, mixed with the 380 11 megahertz intermediate frequency signal, the resultant output 12 signal from mixer 78 is at television channel 2. This signal, 13 with the f.m. 88-108 megahertz is applied to band split filter 14 86 to the subscriber drop 87. A data line 88 which carries the DS-l data signal from, and to modems 21 and 22 (Figure 2) is 16 also connected to band split filter 86. Accordingly fil-ter 86 17 forms diplexer l9 shown in Figure 2.
18 If a second channel is required, a second converter is 19 utilized, and outputs on a differen-t channel than the first.
The transmission line or subscriber drop to the STU
21 carries both video, in either channel 2 or channel 3, and data, 22 in designated time slots modulated on a 12 megahertz carrier 23 signal. The video signal carries either signals from a VRAM at 24 the RVDM, or from a selected television channel, reduced to channel 2 or channel 3, typically. The transmission line 26 carrying this signal to the subscriber drop is not shown.
27 However the description below, with Figure 6, relates to the 28 data signal.
29 It will be recalled that data transmission to and from an STU is carried out within a des~gnated time slot, -there being 31 24 time slots available for 12 STUs (or whatever other number is 32 desired depending on traffic limitation). The firs-t time slot 33 (TSl) is used for control messages, providing 23 time slots for 34 transmission of data. Each of the frames is scanned by -the RVDM
under control of its CPU. It is therefore required to enable 36 transmission to individual STUs within the designated time 37 slots, whereby data transmitted from the RVDM within tha-t time 38 slot is transmitted to a particular subscriber drop.

. .~ J~

~5~73~

01 As described earlier, the output o~ latch 215 is 8 02 bit~, 4 of which designate the STU. These bits are carried via 03 bus 400 to the input terminals of 1/16 decoder 401 (only 12 04 decode outputs of which are used where 12 STUs are to be 05 connected).
06 The output of decoder 401 which designates STU #l is 07 applied through inverter 402 to one input o~ AND gate 403. This 08 is the enable lead, and is on, high, or active for the entire 09 time slot period required to transmit to STU #1.
At the same time data to be transmitted to that STU is 11 present on le~d 116, which is output from latch 102 described 12 earlier as carrying data or the STU. This data is passed 13 through inverter 404, and is applied to the second input of AND
14 gate 403. The output of AND gate 403 is connected to the control input of bit modulator 405.
16 The 12 mega~ert~ carrier which is output from fast 17 limiter 319 is applied via lead 4Q6, buf~er 407 and isolation 18 resistor 408 through 15 megahertz low pass filter 409 to 19 isolation resistor 410 which is connected through resistor 411 to ground. Bit modulator 405 is connected from ground through 21 resist.or 412 to the junction of resistors 410 and 411.
22 Accordingly -the junction of resistors 410 and 411 carries 12 23 megahertz carrier, modulated at the bit rate output from AND
24 gate 403, during the time slot designated b~ the output of decoder 401. When there i9 no output of decoder ~01, AND gate 26 403 is inhibited and there is no modulation of the 12 megahertz 27 carrier at the junction of resistors 410 and 411.
28 The modulated carrier a-t the junction of resistors 410 29 and 411 is applied to the transmit input oE directional coupler 413, which applies the signal to a stripline 414. The output of 31 stripline 414 is combined with the channel 2 or 3 video signal 32 and connected to a subscriber drop specifically leading to STU
33 #1.
34 The bidirectional signal received from stripline 414 is applied via directional coupler 413 through buffer 415 and 36 switch 416 to the input of buffer 417. The output of inverter 37 402 enables switch 416 closed during the entire period that STU
38 #1 is being transmitted-to, i~e. during the bidirectional time 39 ~ ~ 25 37~
01 slot desi~3nated for STU #1.
02 The above-described circuit including inverter 402, 03 AND gate 403, switch 405, resistors 410, 411, and 412, 04 directiona~ coupler 413, buffer 415, and switch 416 and their 05 ancillary circuits constitutes a transceiver 418a. Other 06 transceivers 418b, 418c.. ~418m are identical in construction, 07 and have their corresponding resistors 410 connected to the 08 output oE low pass 40~ for reception of the 12 megahertz 09 carrier. Similarly the outputs of their corresponding switches 416 are connected to the input of buffer 417. The input of 11 their corresponding inverters 402 are connected to individual 12 outputs of decoder 401, whereupon each is enabled within a time 13 910t designated by the input code at the input of decoder 401 on 14 lead 400 from latch 215, which code is obtained from the output of connection memory RAM218. The particular STIJ enabled is thus 16 controlled by the CPU, under guidance of the signal received on 17 data bus 107, which is received as described earlier with 18 respect to the RVDM from the transmission line, which signals 19 are originated at a central control.
Output signals from the STU received via buffer 417 21 are applied through 6 megahertz low pass fil-ter 419 and 1 22 megahertz high pass filter 420 to the input of video amplifier 23 421 and then -to the input of a.m. detector 422. The output is 24 connacted to the input of limiter 423. The output of limi-ter 423 is applied via switch circui-t 424 to lead 135, for 26 application to the outgoing or upstream portion of the RVDM, as 27 described earlier.
28 Switch 424 need only be used where it is described to 29 provide an additional feature of self-checking of signals applied to the STU. In this case a spare output of decoder 401 31 is used at the enable input of switch circuit 424 to switch lead 32 135 away from the output of limiter 423, and to the output of an 33 inverting buffer 425 which has its input connected to lead 116 34 which carries the data which is to be output to the STU. Since this data, during the time slot designated by the spare output 36 of decoder 401 does not go to an STU, it is in this time slot 37 looped back to the RVDM for checking of the circuitry, and of 38 course the data received back should be iden-tical to the data ~ ~S~'7~3~
01 -transmitted.
02 Filters 4l9 and 420 form an effective 1-6 video 03 bandpass filter for receiving -the 6 megahertz signal transmitted 04 by the STU toward the RVDM. The signal is carried through video 05 amplifier 421, is detected in a.m. detector 422, is limi-ted in 06 limiter 423 and is passed back to the RVDM. The output of a.m.
07 video detec-tor 422 is applied through detec-tor and filter 426, 08 integrator 427, to the gain control input of video amplifier 09 421. The last-noted loop ~hus forms an AGC control. Video amplifier 421 is similar -to a~plifier 306, detec-tor 422 is 11 similar to detector 309, and fil-ter and integrators 426 and 427 12 are similar to ilter and integrators 3]5 and 317. As this 13 circuit is a well known AGC circuit, it need not be described 14 further.
As noted earlier, transmission to STU by the RVDM is 16 by data modulated on a 12 megahertz carrier, while transmission 17 back from the STU to the RVDM is by da-ta modulated on a 6 18 megahertz carrier. The transmission line also carries video and 19 f.m. from converters at the RVDM under control o the subscriber's key pad at the STU, and monitored by a central 21 control connected to the main transmission line, if this service 22 is extended. The STU is a microprocessor controlled -terminal 23 located at the subscribers home for automatically monitoring and 24 controlliny various functions, such as burglar and Eire alarms, energy and water meters, or shedding loads off the power line 26 under control of the power company interfacing with the remote 27 cen-tral control, for providing digital telephony service, for 28 selecting cable T.V. video channe}s, for accessing remote data 29 banks, for displaying data on a video screen, for forwarding and receiving data e.g. from a computer, etc. As described earlier, 31 the control signals transmitted between the RVDM and STU occur 32 in time slot 1, -the remaining 23 time slots being reserved for 33 data transmissions.
34 The structure and operation of the STU will be conveniently described with reference to the passage of a signal 36 through it, by which all of the various componen-ts are 37 exQrcised. Please refer to Figures 7 and 8.
38 The signal received from the RVDM along the STU drop . 7 .~
, i ~ ~, `,`, :~lS~7~

SU~ referrecl to in ligure 6 is applied to rnoclem 5~ lere T.V. (typically channel 2 or 3) ancl f.m. signals are remov-ed by hlgh pass filtering and applied via cable 502 to a tele-vision set 503.
In addition, a data output signal is applied via output cable 500 to the ~TU drop leading to the RVD~.
In a manner analogous to the modem described with reference to Figure 3, the 12 megahertz carrier is removed as a pilot tone, and appears on lead 505. This signal is also divided by 8 using conventional means, resulting in a bit clock signal at 1.544 megahertz carried by leacl 506.
The data, at a rate of 1.544 megahertz~ is carried on lead 507. In addition, lead 508 carries the synchronization pulse carry output. It is assumed that the data rate is in synchronism with the bit clock; if it is found that it is not, ~he bit clock data carried on lead 506 should be shift-ed in phase so that both the bit clock and data are in phase.
The data is applied to a center bit sampler with the bit clock signal from lead 506. The center bit sampler is a flip flop, the data being applied to its D input and - the bit clock signal being applied to its clock input. The center bit sampler 509 performs the function of bit edge ad-justment relative to the bit clock pulses.
The Q output of the center bit sampler flip flop i09 carries the sampled data, and is applied to the input of a shift register 510. This shift register has its out-put connected to data bus 511, and its enable E input con-nected to read strobe bus 512. Under control of the local micrOprocessor, to be described below, shift register 510 is strobed after time slot 1, whereby control information from the RV~M is passed into the shift register. The data ~5~7~3~

in this shiEt register will be reacl by the microprocessor.
Shift register 510 also is connected to AND gate 513 which has one input comlected to the 1.544 megahertz clock source lead 506, and the other to a lead which deEines time slot 1, to be describecl i.n more detail later. Accordingly shift re-gister 510 receives the control data in time slot 1, and once 8 bits have been received, the control data is strobed onto the data bus for reception by the microprocessor. In this 3 ~5~3~731~

01 manner control signals from the RVDM are received by the STU.
02 Let us a~swme for this example that the control 03 is connected to data bus 511 and address bus 523. 4096 bytes oE
04 ROM524 is similarly connected to the data and address buses, 05 memory select circuits 525 al~o being connected between address 06 bus 523 and the ROM. The central processing unit is also 07 connected to a control bus 526, which is connected -to read 08 s-trobe decoder 527 and write strobe decoder 528. The read and 09 write strobe decoders have their address inputs connected to address bus 523, and their decoded outputs connected 11 respectively to the read strobe bus 512 and the write strobe bus 12 514. A watch dog timer 529 is connected from the write strobe 13 output to the central processing unit, in a well known manner.
1~ It was noted earlier that transmission oE control data between the RVDM and STU occurs in the first time slot of frame 16 6. However there is time delay of transmission in both 17 directions, due to transmission path delays, and component 18 operation delays in the STU. It is therefore desired -to 19 formulate the data signals being transmitted toward the RVDM in the fif-th frame, and then to introduce a delay just prior to 21 trans~ission which will cause the return signal to arrive at the 22 RVDM in synchronism with time slot 1 of the 6th frame. The 23 generation of the timing will be described below.
24 The receive bit clock at 1.544 megahertz is applied from lead 506 to a divide-by-193 channel counter 535, which 26 establishes the number of frames per second (8,000). The 27 output of counter 535 is connected to a divide-by-12 frame 28 counter 536. The outputs of channel counter 535 and frame 29 ~ounter 536 include tilning signals designating various time 3~ slots, frames, including frame 6.
31 Initially, it is necessary to synchronize the bits and 32 frames with the receive bits and frame times. Therefore the 33 receive cloc~ signal on lead 506 is applied to channel counter 34 535. Each 193 bits, oE course, is expected that a frame bit will be present, and as no-ted earlier, the frame bits form a 36 pattern. The assumed frame bits, bit 193, are thus applied 37 through a latch 599 to data bus 511. Latch 599 includes an 8 38 bit shift register, and when strobed by a lead from the strobe .~.

73~

01 bus ~14, applies the assumed correct Erame bit pat-tern to data 02 bus SLl. The microprocessor compares this with code pattern 03 with the correct pattern stored in its ROM. If it is not the 04 correct pattern, an additional bi-t is added -to counter 535, 05 causing it in one count to count 194. This effectiYely shifts 06 the phase oE subsequent counts by 1 bit, and the next bit in -the 07 frame sequence of each successive frame is moni-tored for 08 conformity with the correct frame bit sequence. Once -the 09 correct frame bit sequence has been found, there is no further inser-tion of an additional bi-t for counting ~y the channel 11 counter, and it continues to sequence with 193 ~its.
12 Once the correct bit phase has been found, counter 13 reset circuit 538 is strobed on the write strobe bus 514, 14 resetting the frame counter 536 following the end oE the frame bit seq~ence. In this manner both the frame and time slot 16 phases are synchronized with the corresponding incoming time 17 slots and fra~es.
18 The outputs of channel and frames counters 535 and 536 19 are various timing signals designating data bit positions, and various frame positions. The timing signals for time slo-t 1 are 21 applied to the time slot 1 generator 539, which in response 22 applies an output pulse on lead 540 for the duration of time 23 slot 1. Similarly the A channel transmission bit timing signal 24 is applied to timing strobe generator 540, which applies an output pulse on lead 541 for the duration of the A bit.
26 Aaditional time slot assignors 542 and 543 are 27 similarly connected for other time slots, which apply output 28 pulses on leads 544 and 545 respectively during the time periods 29 of high speed channels and telephony, to be discussed in more detail later.
31 The timing signals on leads 540, 541, 544 and 545 are 32 applied to a flip flop 546, for resynchronizing with the data 33 bits. Resynchronization is done to the input bit cloc~, lead 34 506 being connected to the clock input of flip flop 546.
The four outputs of flip flops 546, which correspond 36 with the outputs from the time slot assignors, time slot 1 37 generator and timing strobe generator are applied to the control 38 inputs of corresponding switches (such as CMOS switches 547, ~51~73~
01 ;~8, 549 and 550). Accordingly, for example, when a s.ignal 02 appears on lead 545, it is applied, after synchronization with 03 the receive bit clock, to the control input of switch 547.
04 The input of swi-tch 5~7 is connected to the output of 0S shift register 530, which, it wi.Ll be recalled, c~rried the data 06 output s:ignal from the STU to the RVDM. This pa~ses, during 07 time 910t 1, through switch 547, and on -to transmit data bus 08 551. Similarly the output of each of switches 548, 549, and 550 09 is connected to transmit data bus 551, one of each of the switches bei~g closed during appropriate time periods designated 11 by the outputs from time slot assignors 542 and 543 and time 12 slot generator 539 and timing strobe generator 540. Only one is 13 of course closed at a time.
14 As was noted earlier, it is preferred that -time slot 1 generator 539 should be enabled during the first time slot of 16 frame 5, .rather than frame 6. It is thereEore necessary to 17 introduce a delay if the data is to pass out toward the ~VDM in 18 frame 6. It has been found desirable to introduce both a fixed 19 delay and a variable delay, which variable delay i8 controlled depending on transmission path and component delays. This can 21 of course vary with temperature, aging of components, etc.
22 Data bus 551 is connected to a shift register 552, 23 which introduces a fixed delay which has usefully ound to be 24 adequate with 128 bits delay. The output of shift register 552 is connected to the input of a variable 64 bit delay shift 26 register 553. The combined maximum delay, is of course, one 27 complete frame of 192 bits, discounting the frame bits. The 28 output of shift register 553 is connected via output cable 504 29 to modem 501, where it is applied to the STU drop 500 for transmission to the RVDM, and further processing as was 31 described earlier. Modem 501 modulates the output data signal . 32 from shift register 553 on a 6 megahertz carrier, which is 33 divided by 2 from the 12 megahertz received carrier.
34 The 12 megahertz received carrier, as was noted earlier, appears from modem 501 on ~he pilot tone lead 505, and 36 is applied to a divide-by-8 counter 554. The output signal is 37 at the transmit clock frequency of 1.544 megahertz, which 38 signals are applied to the clock C inputs of shift registers 552 3b~S1~373~3 01 and 553.
02 From time to ~ime, and at initialization, -the RVDM
03 checks -the synchronization of received and transmi-tted signals 04 in time slot 1 of channel 6. As was described earlier, it 05 transmits a code to the S~'U and determines whe-ther the correct 06 code has been received. The introduction of delay was described 07 earlier with respec-t to transmission of data Erom the RVDM up 08 the transmission line to a central control, the delay being 09 introduced as a memory o~fset address signal.
The present circuit operates similarly, the RVDM
11 sending a delay code to the STU microprocessor for application 12 to latch 555. The latched code is applied to shift register 13 553, for varying the delay from 0 up to 6as bits.
14 The transmit clock 554 is also adjusted similarly. A
two bit code is introduced from the microprocessor which adds 2, 16 4 or 6 bits to the clock count, thereby advancing shift 17 registers 552 and 553 by 1/4 bit intervals.
18 Latches 555 and 556 are enabled from the right strobe 19 bus 514.
It has thus been seen how a message, e.g. a command to 21 a load shedding relay is sent by the RVDM over subscriber drop 22 500, and how a return signal is generated and is applied in time 23 slot 1 back to the RV~M, modulated on a 6 megahertz carrier.
24 As ~as noted earlier, meters and alarms can also be read~ A meter port, comprising encoder 559, has a plurality o~
26 inputs 560 connected to a source of pulses corresponding to 27 meter rotation. Sources of pulses of this type are well known, 28 and may consist, for example, oE a magnetically generated pulse 29 each time a rotor, driven by an energy consuming load rotates.
Pulse generator 561 has its output connected through buffer 562 31 to meter input 560 o~ encoder 559. Encoder 559 is strobed by a 32 lead from read strobe bus 512. The CPU, in routinely enabling 33 encoder 560, allows pulses generated in pulse generators such as 34 561 connected to its input ports to be applied to various leads of data bus 511. The microprocessor thus counts pulse 36 transitions, thus retaining a reading count for later routine or 37 designated polling ~rom the central control.
38 Similarly, an alarm port comprising a group of ~.~.., Ql switches 563 interconnects aiarm inputs 564 to data bus 511 when 02 strobed ~rom a lead in read s-trobe 512. Alarm inputs s~ch as 03 564 are each connec-ted through make or break swi-tches 565 to 04 ground. Upon read s-trobing Erom strobe bus 512, each of the 05 switches within alarm port 563 are connected to individual bus 06 leads, and the closure or opening of switehes such as 565 07 provide an alarm input to the microprocessor. Upon this 08 occurring, the microprocessor generates an in-terrupt and sends 09 an alarm message to the RVDM for transmission to the central control. The alarm switches 565 are Eor connection as fire or 11 burglar alarm indications.
12 As noted earlier, the STU can request data to be 13 transmitted to the subscribers television set 503 by the use o~
14 a local key pad. A UART 570, with its local crystal, is connected with its parallel data input to data bu~ 511. The 16 output of UART S70 is an asynchronous serial signal. This 17 signal is applied to an asynchronous bus system runnin~
18 -throughout the subscriber's house. Preferably the UART is a 19 CMOS type 1854, available from Radio Corporation of America.
The UART receives parallel data and formulates it asynchronous 21 format, containing a low level start bit, 8 data bits, an even 22 parity bit, and then one or more high level stop bits. In the 23 present case, the UART is to address one or more addressable 24 UARTs, such as Motorola type MC14469, in a format containing two 11 bit words of the type described above, the Eirst word 26 containing the address and the second containing the command or 27 data word. Addressable UART 572 is connected to asychronous bus 28 571. A key pad 573 is connected in a conventional manner to 29 UART 572. Key pad 573 contains light emitting diodes and a plurality of keys, e.g., 20, as well as 2-7 segment displays.
31 UART 570 is read in a similar manner as the meter and 32 alarm ports described above. The U~RT 570 addresses UART 572, 33 commanding it -to ~orward any data which is input thereto.
34 Assuming the subscriber depresses a button in key pad 573, UART
572 sends it along asynchronous bus 571 to UART 570, which 36 applies it in parallel form to data bus 511. The microprocessor 37 sends a message back to key pad 573 via UART 570, bus 571 and 38 UART 572 to illuminate a light emitting diode, and indicate the ~; :r '7;~B
Q1 depressed digit in the 7 segment, dual digit display. At the 02 same time it Eormulates a si~nal which i5 transmitted to the 03 RVDM indicating request for a television chann~1. m e signal is 04 dealt with as described with respect to the RV~M, and is, if 05 necessary forwarded to the main transmission line for 06 transmission to the central control.
07 Upon reception oE a signal Erom the srru the RVDM
08 microproces~or applies a channel selection signal to the 09 converter connected to the STU drop related to the present STU
which has requested the service. The selected channel is -thus 11 received by television set 503.
12 In -this manner, the key pad may be used to select 13 various television channels, including pay t.v. channels, or 14 other data or video signals from the central control, and display it on -the local television se-t 503. It should be noted 16 that since each command signal ~rom key pad 573 i8 transmitted 17 towards the central control, the central control can obtain 18 billing inEormation Eor pay t.v., can amass channel viewing 19 information, etc., for the use of advertisers or the like.
Further key pad 573 can be used for interactive video by which 21 audiance response can be offerred to a broadcaster.
22 The present invention also provides means for 23 accessing and displaying high data rate signals, such as 24 computer signals, high resolution videotex such as TELIDO~
signals, telephony voice signals, etc.
26 For high speed data according to one embodiment, a 27 latch 575 is connected to data bus 511, and is enabled by write 28 strobe 514. The output of latch 575 is colnprised of control 29 bits for con-trolling alphanumerics and colour on a video screen 576. The video screen may be a t.v. monitor, television set, or 31 television set modified to display high resolution alphanumerics 32 and graphics. The control signals Erom latch 575 are applied 33 via bus 577 to a high speed data module 578 such as a TELIDON
34 terminal, Eor controlling the application of signals to video monitor 576.
36 Also connected to high speed module 578 is the output 37 oE addressable UART 579, which is addressed from asynchronous 38 bus 571 in a similar manner as addressable UART 572. A -Eur-ther ~`;' .

01 addressable UART 580 is connected -to asynchronous bus 571, and 02 i5 furthec connected to a keyboard 581.
03 Keyboard 581 operates ln a similar manner as key pad 04 573, by which services is reques-ted and keys are depressed. A
05 video display generator (VDG) in the RVDM receives the signals 06 and cau~es d:isplay of the keyed information as alphanumeric 07 data, preferably on a line at the bottom of the display in video 0~ monitor 576. The video signals themselves are received from the 09 output of the centre bit sampler 509 as high speed data (up to 56 kilobits) and are applied by the high speed data module 578 11 directly to video monitor 576.
12 The high speed data service supplies a RS-232 protocol 13 interface to the subscriber, having two transmission functions, 14 the first being the transmission of actual data to be transmi-tted and received, and the second to transmit and receive 16 RS-232 protocol control bits.
17 According to another embodiment, a high speed service 18 module interEaces the high speed data service unit 578 located 19 near the keyboard and high speed terminal with the codec and switch 549, and itself is located in the equipment cabinet. The 21 latch 575 is deleted. The high speed data service unit 578 22 converts l12 volt signals received from the high speed terminal 23 to TTL levels and feeds these signals to the high speed service 24 module. The high speed service module converts the asynchronous data to a format suitable for transmission in a time slot.
26 The RS-232 control bits are applied to addressable 27 UART 579. This U~RT is read from and written to by UART 570 in 28 the subscriber unit in a similar manner to the ke~board.
29 When the line of alphanumerics in the video display is correct for the user, a control key is depressed on keyboard 31 581, which causes the VDG to forward that entire line to the 32 central control. The central control accesses the data 33 requested from a file and forwards it in a high speed data 34 channel to -the VDG~
In the alternative the data can be sent in video 36 format from central control on a spare television channel, which 37 is selected by the converter associated with the present STU, 38 converted to channel 2 or 3, and viewed on television set 503, 39 ~ ~ ~ 35 B

01 rather than tel.evision set 576.
02 It ~hould be noted tha-t if a local data terminal is to 03 be used, it can be connectecl bet.ween latch 575 and a high speed 04 data port 582, which is si~ilar to ports Sl9, 559 and 563. Port 05 582 operates similarly as the others, and reads the control bits 06 associated with high speed module 578, which, it will be noted, 07 can be either a data terminal or means Eor controlling video 08 monitor 576.
09 The presen-t system may also be lsed to control load shedding devices, i.e. drive relays to turn on and off loads in 11 the home. This is done by the microprocessor recei~ing commands 12 from the RVDM and transEerring them over data bus Sll to load 13 shedding port 515.
14 As it is often important to receive positive feedback that the load shedding command has been implementecl, the present 16 system provides a load shedding sense port 520. It is expected 17 that the inputs to the port will he connected to sense contacts 18 of load shedding relays to determine whether they have actually 19 changed s-tate. The microprocessor polls these inputs similarly to the alarm ports over bus 511 and reports any changes o state 21 to the RVDM.
22 The present system can also be used -to provide digital 23 telephone service. Upon recep-tion of a request for service from 24 a local telephone set 585, an off-hook detector 586 provides a signal to a telephone read port 587, which is similar to -the 26 above-identified ports 519, 559, etc. Upon s-trobing by a read 27 strobe on read strobe bus 512, the microprocessor determines 28 that there is an off-hook condition, and sends a ~essage to the 29 central control of a requsst for service, and that a high speed telephony digital channel should be opened. The analog signal 31 from telephone 585 is applied to 2/4 wire network 588, which is 32 connected via filters 589 in a conventional manner to codec 33 590. The output signal is applied from codec 590 to the input 34 of switching circuit 550, for application to data bus 551 within the frame or frames assigned under control of the CPU by time 36 slot assignor 542. The time slot assignation from the 37 microprocessor is applied to assignor 542 by latch 591, which 38 has its input connected to data bus 511 and which is strobed ~ ~ S~73B
01 from right strobe bus 5l4.
02 Similarly, the high speed data module 578 or high 03 speed ser~ice module output is conne~ted to switch 549 for 04 ou-tward transmission of high speed data under control of -the 05 microprocessor having assigned time slots for transmission of 06 the high speed data. As no-ted earlier, this can be at a 56 07 kiLobit per second rate. m e time slot is assigned by the 08 microprocessor, the time slot number being la-tched in latch 592, 09 and is applied to time slot assignor 543 for controlling the timing of the closure of switch 549, as described earlier.
11 In a similar manner, switch 548 is controlled, latch 12 593 controlling its closure during the application of a bit 13 control signal.
14 A person skilled in the art understanding this description may now conceive of other embodiments or 16 varia-tions. All are considered to be within the sphere and 17 scope of this invention as defined in claims appended hereto.

1~3 37

Claims

CLAIMS:
(1) A digital data transmission system compris-ing a central station including means for transmitting and receiving digital data signals in a format having a series of frames each having a plurality of time slots and each time slot having a plurality of bits, a plurality of re-mote subscriber terminal units each including means for transmitting and receiving digital data signals in said for-mat, a plurality of remote receiving stations, each receiv-ing station having connected thereto a plurality of said subscriber terminal units, and tree-type transmission means interconnecting said central station with each of said re-ceiving stations, each receiving station including means for receiving digital data signals in said format from said central station and from said subscriber terminal units connected thereto and for regenerating from said received data signals new data signals in said format and means for transmitting said new data signals to said subscriber ter-minal units and to said central station respectively.
(2) A system as defined in Claim 1 wherein said transmitting means includes means for scanning each of the subscriber terminal units in sequential time slots and means for transmitting said data signals to respective subscriber terminal units in time slots allocated thereto.
(3) A system as defined in Claim 1 wherein the format includes data signals designated as address, data and control signals, wherein the transmission means of each receiving station includes means for stripping of the con-trol signals and integrating new control signals with re-generated data signals, and means for transmitting the new control signals and regenerated data signals to designated ones of said subscriber terminal units.

(4) A system as defined in Claim 3, including means for modulating the data signal and new control bits on an outgoing carrier for transmission to the subscriber drops, the outgoing carrier being derived from the incoming carrier.
(5) A system defined in Claim 1, wherein each said receiving station includes means for receiving data signals from the individual subscriber terminal units modu-lated on a second carrier each during the predetermined time slots, means for demodulating the second carrier to derive demodulated data bits, means for applying the demodulated data bits to a controller, the controller being adapted to reformat the demodulated data bits and to write them at first predetermined times designated by the controller into a memory, means for reading the memory at times delayed from the first predetermined times, and means for applying the data from the memory to a modem for modulation on an out-going carrier and application to the transmission means, the delay being predetermined to place the outgoing data in bit synchronization and in a predetermined frame with the incoming data at a remote location connected to the transmission lines.
(6) A system as defined in Claim 5 further in-cluding a plurality of television channel converters having inputs connected to the transmission means for reception of CATV signals, individual outputs thereof connected to corresponding subscriber terminal units, control inputs of the converters being connected to the receiving stations for controlling individual channels applied to the sub-scriber terminal units upon reception of a converter selec-tion control signal from a corresponding subscriber terminal unit.

(7) A system as defined in Claim 1 in which each subscriber terminal unit is comprised of:
(a) a modem for receiving data signals modulated on the incoming carrier having a first frequency, for de-riving a bit clock signal from the incoming carrier and for transmitting data signals on an outgoing carrier having a second frequency, (b) means for applying the received data signals to a bus system, (c) means for connecting a plurality of ports to the bus system, the ports being adapted to connect data generating apparatus to the bus system, when enabled, (d) control means connected to the bus system and to the means for connecting a plurality of ports for con trolling the operation of the ports, and for generating said outgoing data signals in response to the application of control signals from the ports generated by said data generating apparatus to the bus system, in synchronization with said bit clock, and (e) means for applying outgoing data signals to the modem for modulation on the outgoing carrier.
(8) A system as defined in Claim 7, in which the means for connecting a plurality of ports to the bus system is comprised of a plurality of switches enabled from the bus system under control of the control means.
(9) A system as defined in Claim 8, further in-cluding a codec connected in a circuit to the modem for re-ceived data signals therefrom, a subscriber line interface circuit connected to the codec and having a tip and ring lead for connection to a telephone set, means for detecting supervisory signals generated by a telephone set connected between the tip and ring lead and a read port connected to the bus system, and a write port connected between the bus system and the subscriber line interface system fro genera-ting ringing signals for application to the tip and ring lead (10) A system as defined in Claim 8, in which said ports are adapted to receive data from at least one of a load activity indicator, an energy meter, a keypad, a keyboard, a telephone supervisory state sensor, a fire alarm, a smoke alarm, and a plurality of burglar alarm switches, and to apply control signals to at least one of a load controller, an alphanumeric and/or illuminated dis-play, telephone control apparatus, and a data terminal.
(11) A system as defined in Claim 7, in which the means for connecting a plurality of ports to the bus system is comprised of a master UART, having an asynchron-ous bus connected to a plurality of remote addressable UARTs, further including means for connecting said data generating apparatus to the addressable UARTs.
(12) A system as defined in Claim 10, in which the means for connecting a plurality of ports further in-cludes at least one write port and at least one read port, the read port being comprised of a plurality of switches enabled from the bus system under control of the control means, the write port being under control of the control means for receiving data addressed to the write port and applying said data to a terminal including are means for display of and control by said data addressed to the write port.
(13) A system as defined in Claim 7, in which the transmitting means of each receiving station is arrang-ed to transmit data in a predetermined time slot unique to the respective terminal in one frame of said format, and in which the transmitting of said respective terminal unit is arranged to transmit data in the same time slot and the same frame number of a later following sequence of frames.
(14) A system as defined in Claim 12, wherein each terminal unit includes means for storing the data for transmission for a controllable period of time, means for applying said data to the storing means via a switch, means under control of the controlling means for generating time slot controlling signals, and for applying the time slot controlling signals to the switch for controlling the appli-cation of the data to the storing means within predetermin-ed time slot periods, and means for setting the storage time sufficient to delay the data to a period whereby it arrives at the receiving station in the same time slot and frame number.
(15) A system as defined in Claim 14, in which the data signals are divided into frames of data words, and including a sequence of frame bits, the frame bits having a predetermined bit pattern, the data signals including control signals in a predetermined frame, means for apply-ing the control signals to the bus system when strobed by the bit clock and by signals designating the predetermined frame, means for deriving bits from the bit clock at a frame bit rate, means for comparing the derived bit pattern with a predetermined pattern stored in the control means, means for shifting the dervied frame bit rate by one bit in the event the derived bit pattern does not match the prede-termined pattern, means for counting frame bits to derive a frame count, and means for generating said time slot con-trolling signals from the means for deriving bits from the bit clock and the means for counting frame bits.
(16) A system as defined in Claim 7 in which each subscriber terminal is comprised of:
(a) a modem for receiving data signals from an incoming carrier having a first frequency, for deriving a bit clock signal from the incoming carrier, for generating an outgoing carrier from the incoming carrier and for trans-mitting outgoing data signals on the outgoing carrier, (b) the incoming data signals being in the form of frames of data bits, each frame divided into channels of a predetermined number of bits and ending with an extra frame bit, the frame bits forming a predetermined pattern, control signals being contained in a predetermined channel, (c) a first shift register connected in a circuit with the modem for receiving the data signals, (d) means for enabling the shift register during the time of the predetermined channel whereby the control signals are read into and stored in the shift register dur-ing the time of the predetermined channel, (e) a bus system for receiving the control signals from the shift register, (f) means for receiving the bit clock signal and for generating frame and channel count timing signals there-from, (g) a second shift register connected to the bus system for receiving outgoing data signals, (h) a circuit including a switch for carrying the outgoing data signals to the modem for modulation on the outgoing carrier, (i) a time slot generator adapted to receive the timing signals for generating control signals for said switch and for the second shift register, for controlling the time of application of said outgoing data signals in a predetermined outgoing channel, (j) a port means connected to the bus system for connection to at least one of data generating and receiving apparatus, and (k) a microprocessor connected to the bus system for receiving the incoming data signals, generating control signals, reading signals from the port means and writing signals to the port means, and generating said outgoing data signals.
(17) A system as defined in Claim 16 in which said circuit including said switch includes a controllable delay means adapted under control of the microprocessor to delay outgoing data signals at time sufficient to syn-schronize data signals transmitted and received by said receiving station.
(18) A system as defined in Claim 17 in which the incoming and outgoing carrier signals are at different frequencies carried by a coaxial cable subscriber drop, the subscriber drop also carrying CATV television signals, and further including means for connecting a television set to the subscriber drop with the modem.
(19) A system as defined in Claim 18 further in-cluding means for connection to one of said ports for gen-erating television channel selection control signals, for transmission via the outgoing carrier to a remote tele-vision channel converter, for control of a CATV channel transmitted along the subscriber drop for reception by the television set.
(20) A system as defined in Claim 19 in which at least one of said ports is a master UART, having an asynchronous bus output for connection to a remote UART, said remote UART comprising means for connection to said television channel selection control signal generator.