CA1161168A - Digital code word detection - Google Patents
Digital code word detectionInfo
- Publication number
- CA1161168A CA1161168A CA000357379A CA357379A CA1161168A CA 1161168 A CA1161168 A CA 1161168A CA 000357379 A CA000357379 A CA 000357379A CA 357379 A CA357379 A CA 357379A CA 1161168 A CA1161168 A CA 1161168A
- Authority
- CA
- Canada
- Prior art keywords
- code word
- bit
- bits
- digital
- word
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
- H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/12—Arrangements providing for calling or supervisory signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/08—Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q1/00—Details of selecting apparatus or arrangements
- H04Q1/18—Electrical details
- H04Q1/30—Signalling arrangements; Manipulation of signalling currents
- H04Q1/39—Signalling arrangements; Manipulation of signalling currents using coded pulse groups
Abstract
PHN. 9548 22 ABSTRACT:
A method by which code words in a received digi-tal bit stream can be detected in a reliable manner, without word synchronization, in an environment where the bit error rate is high. The bit stream is divided into data blocks having a number of bits equal to the number of bits of the code word. The number of times that the same bit state is detected in a plurality of blocks in the same relative position in the data block is accumulated. For each bit position the accumulated value is compared with a threshold value and when the threshold value for each bit position is exceeded, the code word is detected from the digital state of the accumulated value. The cyclic permutation of the bits of the code word and the code word itself represent one an the same message. In a device using this method, bit counter feeds a word counter with the bit stream applied at an output, a shift register receiving each data block as effectively formed by the word counter. Counters count the "1" and "0" occurrences in each shift register section in successive data blocks. Threshold devices pro-vide outputs when their thresholds as given by generators are exceeded. The outputs are gated by combinational o logic gates to record a detected code word in a register which addresses a store to find the associated message.
A method by which code words in a received digi-tal bit stream can be detected in a reliable manner, without word synchronization, in an environment where the bit error rate is high. The bit stream is divided into data blocks having a number of bits equal to the number of bits of the code word. The number of times that the same bit state is detected in a plurality of blocks in the same relative position in the data block is accumulated. For each bit position the accumulated value is compared with a threshold value and when the threshold value for each bit position is exceeded, the code word is detected from the digital state of the accumulated value. The cyclic permutation of the bits of the code word and the code word itself represent one an the same message. In a device using this method, bit counter feeds a word counter with the bit stream applied at an output, a shift register receiving each data block as effectively formed by the word counter. Counters count the "1" and "0" occurrences in each shift register section in successive data blocks. Threshold devices pro-vide outputs when their thresholds as given by generators are exceeded. The outputs are gated by combinational o logic gates to record a detected code word in a register which addresses a store to find the associated message.
Description
PHN 9548 18.07.80 "Digital Code Word Detection"
The invention relates to a method of a type suitable for detecting a message in the form of a digital code word, the code word cotaining a sequence of a prede-ter-mind number of bits and being included in a few times consecutively and sequen-tially in a bit stream. The in-vention also rela-tes to means for performing the method.
A method of the above type is known from French Patent Specification 2309101. This meth~d is used to detect digital code word which are transmitted for signaling purposes in a PCM telephone system. The code words consist of two groups of bits: ,a first group (the bits 1 to ~)which is the same for all code words, the so-called prefix, and a second group (the bits 5 to 10) which is different for all code words. By means of the prefix it is determined where the distinguishing portion of the corde word starts.
In telephone systems in which signaling is in accordance with the compelled release procedure a forward signal is not ended until after the reception of a backward signal, which is ended after -the appearance of the forward signal has been detected. This considerably increases~he chance that a code word which is repeatedly received is exactly the same as the desired code word.
Delta-modulation is used as the speech codi~gmethod in some digital telephone systems, the reason being that,at a relatively low bit rate (16 to 32 ~bits/s) a better perf,ormance is obtained than with the PC~I and that the speech encoded in accordance with this method has a greater resistance against the effect of a high bit error ' rate. A furthèr reason is that a single channel does not require word synchroniza-tion. The compelled signaling in these systems is also effected in the ~orm of ,code words.
Typical requirements imposed OIl the d0tection of the code word in such a high bit error rat'e system are:
for signaling in -the set-ting~up phase:
Q~
PHN 9548 - 2 - 18.07.80 - if a bit stream is presented with 0% bit error rate (BER),then a code word mus-t be detected af-ter the reception o~ not more than lO (iden-tical) code words.
- if a bit stream is presented with 10% BER, -then the code wo~ ~ust be detected with a probability of 99. 99%
-that it is the correct code word, after the recep-tion of not more than 64 code wordsO
Eor signaling in the traffic phase the requirements are more stringent, as the signaling informa-tion is transmitted amongst speech or data information. The problem then occurs that tha-t information could immitate a code word.It is a requirement that a random bit pattern at the input of s detector must not cause spurious detector response more than once in 7.7 x 10 bits. Addi-tional requirements in the traffic phase are that the code lS word must have been detected with a`probability of 99. 99%
that it is the correct code wordt after not more than 40 code words for 0% BER and after not more than 256 code words for 10% BER.
It is an objec-t of the invention to provide 20 a method with which code words occurring in a bit stream with a high bit error rate are reliably detected in a simple manner, without word synchronization. To -that end, according to the invention, a method of the type referred to is characterized in that 25 - the bit stream is randomly divided into data blocks, each block having a number of bits which is equal to the the number of bits of the code word;
- the digital bit state is determined and recorded for each bit position in the data block;
30 - -the recorded data o~ each bit position are a cumulated for a plurality of consecu-tive da-ta blocks;
- the accumulated value of each b:it posi-t:ion -in the cla-t block is compared with a threshold value; and - the code word is detected from -the digi-tal state of the accumula-ted values when the thresholcl value for each bi-t PHN ~548 _ 3 _ 18.07.80 position in the data block has at leas-t been reached.
In principle 2 messages can be coded with N-bit code l~ords. Groups of code words which are detectable without word synchronization are ob-tained by allotting the same message to a code wo~l ~ld to all the code words derived ~rom this code word by cyclic permutation of the bits. With N = 8, that is to say with 36 messages ~rom 256 words, the majority of which may occur in 8 configu-rations, it is possible to satis ~y amply the need for signaling and switching characters for the majori-ty of telephone systems A further advantage of the method according to the invention is that it can be realized in a simple mannerin universal sequentially programmable logic circui-ts, such as commercially available microprocessors,with associated stores~nd peripheral equipment.
If is a ~urther object of the invention to protvide a code de-tector ~or carrying out the method in accordance with the invention, which code detector comprises, a shift register having a number o~ sections equal to the 20 number of bits (N) of the code word, each sec-tion of the shift register having an output, means for randoml-~ dividing the bit stream into data blocks o~ N bits, these data blocl~ being applied to an input of the shift register, the output of each section being coupled to assicated couting 25 means for determining the number of times that in -the same digital state o~ the bit has occurred in each section in a plurality of data blocks and, the current detector further comprising threshold devices each having a firs-t input for re~eiving a threshold value and a second input 30 connected to -the associated coun-ting means, arJd an outpu-t, the outputs of,the threshold devices providing signal values, which are a representation of` the cocl~ word when -the threshold value of each th~esho:Ld device is exceeded.
Embodiments of the invention and i-ts advan-tageswill be fur-ther explained with re:~erence to -the accompa-~6~68 PHN 9548 _ 4 ~ 18.7.8Onying drawings, in which the same reference numerals are used in different Figures for corresponding elemen-ts. In the drawin~s:
Figure 1 is an illustration of a series of sequential, consecutive identical code words in a bit 5 stream;
Figure 2 shows a code word and the cyclic permuta-tions of that code wordt for use in accordance with the invention;
Figure 3 shows a block schematic diagram of a first embodiment of a code detector for detecting code words of the type shown in Figure 2, for carrying -the method according to the invention into effect;
- Figure 4 is a flow chart of a first embodi-mentof the method according to the invention;
Figure 5 shows a block schematic diagram of a second embodiment of a code detector for de-tecting code words of the type shown in Figure 2 for carrying the method according to the invention into effect; and Figure 6 is a flow chart of a second embodi-ment of the method according to the in~ention.
In communicat ion sy stems,not only the informa-tion i-tself but also special characters or messages must be transmitted.These messages may occur prior to, subsequent to,or amongstithe information. In telephone systems, for example, the exchange of information is preceded by the transmission of dial num'bers, busy characters, check characters and other characters characterizing the trans-mission path and the swii~ching ,sta-te thereof.Register call-back signals are, for example, transmitted amongst the information. A digital bit stream such as may be found in a digital communica-tion sys-tem is shown in Figure 1.The information to be transmitted is designa-ted by SP and the special characters or messsages in the form Or digi-tally 35 coded words - the ~ode words - are designated by CW.The .
PHN 954~ ~ 5 ~ 18.7.80 . code words CW are repea-tedly transmit-ted in order to determine acorrect code word on the basis of a majority decision in the case where a code word is mutilated as the result of a fault. In telephone systems operating in accordance with ~he compelled release procedure, a code wordt is transmitted un-til -the receiver acknowledges the ' detection of the code word. The next code word or informa-tion is no-t transmitted until a consequential ac~nowledge-ment signal has been received. Generally, recognition .of a code word will take longer according as the bit error rate is greater. This also appears from the requirements which are imposed on the maximum number of code word repetitions that is required to determine a correct code word with a certain probability.
T A B L E
~laximum number o* code words . 0~0~~
setting-up ~ 10 64 . _ __ ....... _.. _ . ~.. _ I
. . - . traffic 10 256 Table I shows an example of requirements which may be imposed in practice on a telephone system. In the setting-up phase, a code word must have been dete~cted with certainty after a maximum of 10 repetitions of the code word ~or a bit error rate of 0% and with a probability of 99. 99%
after a maximum.of 64 code word repetitions fo~ a bit error rate of 10%. In the traffic phase, during the trans-mission of information, these numbers are 40 and 256 c-ode words, respectively.~ fu~ther requirernent is tha-t spurious code word bit patterns generated by means of a randomly distributed noise cause ~ response of not more than once in 7.7 x 101 bits.
In some digital telephone systems delta modulation is used as the speech coding method.In such systems the si~g~le channe:L does not require (word) synchro-nizationas regards-the speech -transmission. The s-i-tuation is PHN 9548 - 6 - 18.7.80 different for a code word, Since a good code ~ord is repeatedly transmitted, an incorrect code word will be received when there is not synchronization between the receiver and the transmitter. In order to avoid the necessity of word synchronization for the code words, code words which can be derived~rom one anotherby cyclic permutation are given the same m~ssage as regards -their meaning. In principle,
The invention relates to a method of a type suitable for detecting a message in the form of a digital code word, the code word cotaining a sequence of a prede-ter-mind number of bits and being included in a few times consecutively and sequen-tially in a bit stream. The in-vention also rela-tes to means for performing the method.
A method of the above type is known from French Patent Specification 2309101. This meth~d is used to detect digital code word which are transmitted for signaling purposes in a PCM telephone system. The code words consist of two groups of bits: ,a first group (the bits 1 to ~)which is the same for all code words, the so-called prefix, and a second group (the bits 5 to 10) which is different for all code words. By means of the prefix it is determined where the distinguishing portion of the corde word starts.
In telephone systems in which signaling is in accordance with the compelled release procedure a forward signal is not ended until after the reception of a backward signal, which is ended after -the appearance of the forward signal has been detected. This considerably increases~he chance that a code word which is repeatedly received is exactly the same as the desired code word.
Delta-modulation is used as the speech codi~gmethod in some digital telephone systems, the reason being that,at a relatively low bit rate (16 to 32 ~bits/s) a better perf,ormance is obtained than with the PC~I and that the speech encoded in accordance with this method has a greater resistance against the effect of a high bit error ' rate. A furthèr reason is that a single channel does not require word synchroniza-tion. The compelled signaling in these systems is also effected in the ~orm of ,code words.
Typical requirements imposed OIl the d0tection of the code word in such a high bit error rat'e system are:
for signaling in -the set-ting~up phase:
Q~
PHN 9548 - 2 - 18.07.80 - if a bit stream is presented with 0% bit error rate (BER),then a code word mus-t be detected af-ter the reception o~ not more than lO (iden-tical) code words.
- if a bit stream is presented with 10% BER, -then the code wo~ ~ust be detected with a probability of 99. 99%
-that it is the correct code word, after the recep-tion of not more than 64 code wordsO
Eor signaling in the traffic phase the requirements are more stringent, as the signaling informa-tion is transmitted amongst speech or data information. The problem then occurs that tha-t information could immitate a code word.It is a requirement that a random bit pattern at the input of s detector must not cause spurious detector response more than once in 7.7 x 10 bits. Addi-tional requirements in the traffic phase are that the code lS word must have been detected with a`probability of 99. 99%
that it is the correct code wordt after not more than 40 code words for 0% BER and after not more than 256 code words for 10% BER.
It is an objec-t of the invention to provide 20 a method with which code words occurring in a bit stream with a high bit error rate are reliably detected in a simple manner, without word synchronization. To -that end, according to the invention, a method of the type referred to is characterized in that 25 - the bit stream is randomly divided into data blocks, each block having a number of bits which is equal to the the number of bits of the code word;
- the digital bit state is determined and recorded for each bit position in the data block;
30 - -the recorded data o~ each bit position are a cumulated for a plurality of consecu-tive da-ta blocks;
- the accumulated value of each b:it posi-t:ion -in the cla-t block is compared with a threshold value; and - the code word is detected from -the digi-tal state of the accumula-ted values when the thresholcl value for each bi-t PHN ~548 _ 3 _ 18.07.80 position in the data block has at leas-t been reached.
In principle 2 messages can be coded with N-bit code l~ords. Groups of code words which are detectable without word synchronization are ob-tained by allotting the same message to a code wo~l ~ld to all the code words derived ~rom this code word by cyclic permutation of the bits. With N = 8, that is to say with 36 messages ~rom 256 words, the majority of which may occur in 8 configu-rations, it is possible to satis ~y amply the need for signaling and switching characters for the majori-ty of telephone systems A further advantage of the method according to the invention is that it can be realized in a simple mannerin universal sequentially programmable logic circui-ts, such as commercially available microprocessors,with associated stores~nd peripheral equipment.
If is a ~urther object of the invention to protvide a code de-tector ~or carrying out the method in accordance with the invention, which code detector comprises, a shift register having a number o~ sections equal to the 20 number of bits (N) of the code word, each sec-tion of the shift register having an output, means for randoml-~ dividing the bit stream into data blocks o~ N bits, these data blocl~ being applied to an input of the shift register, the output of each section being coupled to assicated couting 25 means for determining the number of times that in -the same digital state o~ the bit has occurred in each section in a plurality of data blocks and, the current detector further comprising threshold devices each having a firs-t input for re~eiving a threshold value and a second input 30 connected to -the associated coun-ting means, arJd an outpu-t, the outputs of,the threshold devices providing signal values, which are a representation of` the cocl~ word when -the threshold value of each th~esho:Ld device is exceeded.
Embodiments of the invention and i-ts advan-tageswill be fur-ther explained with re:~erence to -the accompa-~6~68 PHN 9548 _ 4 ~ 18.7.8Onying drawings, in which the same reference numerals are used in different Figures for corresponding elemen-ts. In the drawin~s:
Figure 1 is an illustration of a series of sequential, consecutive identical code words in a bit 5 stream;
Figure 2 shows a code word and the cyclic permuta-tions of that code wordt for use in accordance with the invention;
Figure 3 shows a block schematic diagram of a first embodiment of a code detector for detecting code words of the type shown in Figure 2, for carrying -the method according to the invention into effect;
- Figure 4 is a flow chart of a first embodi-mentof the method according to the invention;
Figure 5 shows a block schematic diagram of a second embodiment of a code detector for de-tecting code words of the type shown in Figure 2 for carrying the method according to the invention into effect; and Figure 6 is a flow chart of a second embodi-ment of the method according to the in~ention.
In communicat ion sy stems,not only the informa-tion i-tself but also special characters or messages must be transmitted.These messages may occur prior to, subsequent to,or amongstithe information. In telephone systems, for example, the exchange of information is preceded by the transmission of dial num'bers, busy characters, check characters and other characters characterizing the trans-mission path and the swii~ching ,sta-te thereof.Register call-back signals are, for example, transmitted amongst the information. A digital bit stream such as may be found in a digital communica-tion sys-tem is shown in Figure 1.The information to be transmitted is designa-ted by SP and the special characters or messsages in the form Or digi-tally 35 coded words - the ~ode words - are designated by CW.The .
PHN 954~ ~ 5 ~ 18.7.80 . code words CW are repea-tedly transmit-ted in order to determine acorrect code word on the basis of a majority decision in the case where a code word is mutilated as the result of a fault. In telephone systems operating in accordance with ~he compelled release procedure, a code wordt is transmitted un-til -the receiver acknowledges the ' detection of the code word. The next code word or informa-tion is no-t transmitted until a consequential ac~nowledge-ment signal has been received. Generally, recognition .of a code word will take longer according as the bit error rate is greater. This also appears from the requirements which are imposed on the maximum number of code word repetitions that is required to determine a correct code word with a certain probability.
T A B L E
~laximum number o* code words . 0~0~~
setting-up ~ 10 64 . _ __ ....... _.. _ . ~.. _ I
. . - . traffic 10 256 Table I shows an example of requirements which may be imposed in practice on a telephone system. In the setting-up phase, a code word must have been dete~cted with certainty after a maximum of 10 repetitions of the code word ~or a bit error rate of 0% and with a probability of 99. 99%
after a maximum.of 64 code word repetitions fo~ a bit error rate of 10%. In the traffic phase, during the trans-mission of information, these numbers are 40 and 256 c-ode words, respectively.~ fu~ther requirernent is tha-t spurious code word bit patterns generated by means of a randomly distributed noise cause ~ response of not more than once in 7.7 x 101 bits.
In some digital telephone systems delta modulation is used as the speech coding method.In such systems the si~g~le channe:L does not require (word) synchro-nizationas regards-the speech -transmission. The s-i-tuation is PHN 9548 - 6 - 18.7.80 different for a code word, Since a good code ~ord is repeatedly transmitted, an incorrect code word will be received when there is not synchronization between the receiver and the transmitter. In order to avoid the necessity of word synchronization for the code words, code words which can be derived~rom one anotherby cyclic permutation are given the same m~ssage as regards -their meaning. In principle,
2 messages can be coded with code words of N bits. The same message is given to code words which can be derived from other code words by cyclic permu-tation. Consequently, 10 word synchronization for the code words is superfluous.
1~ith N = 8, that is to say with 2 = 256 code words, 36 different code words are obtained, which cannot be made identical to one another by cyclic permutation. The code word 111111 11 is not so suitable,as a short-circuit in the 15 transmission path may s-timula-te this word. The code word 00000000 may be generated by an open circuit in the transmission pa-th. Further, the code words 10000000 and 01111111 (and any of their 7 cyclic permutations) are not utilized. this leaves 32 unique code words, a number of 20 which is amply sufficient.;o cover the need for signaling characters in telephone systems. ~wenty-eight of these 32 code words occur in eight configur tions, such as, for example, the corde word shown in Figure 2a. Three code words (11101110, 11001100 and 10001000)occur in four 25 configurations and one corde word (10101010) comprises only 2 cyclic permutations. When -the cod~ word shown in Figure 2a is transmi-tted, the same ~ode word as shown in Figure 2a will be received when there is word synchroniza-tion. However, if there is no synchronization, the code 30 word as shown in Figure 2b will be recieved when the re-ceiver is 7 bit positions "slow" with respect to the transmitter, the code word shown :in F:Lg~re 2c wheIl -the receiver is 6 bit positions "s:Low", and so on f`or the remaining Figures 2d-2h. ~s all -these code words ha~ been given the same message, synchron:i~ation :is superfluous.
:
PHN 95L~8 _ 7 _ 18.7.80 ' The method of de-tec-ting the code words will now be described with reference to the Figures 3 -to 6.
Figure 3 shows a first embodiment of a code detector. A shift register 2 comprises N sections 2-1, 2-2, ... 2-N, each section having a "1" output and a "0"
ou-tput. A binary digital 'bit stream is applied to -the input of the shift register 2. The bit stream is divided into random data blo~k of N bits. The number of bits of each data block is counted by a bit counter 3, ~or example a modulo-~ counter, which is connected to an input 1. The number of data blocks is counted by a resettable word counter 4, connected to the output of the modulo-N
counter 3.After an N-bit word has been entered into the shift register 2, it is determined in known ~anner for bit position i (i = 1,2 ... N) whether the bit position lS contains a logic valuelof a first type, for example a "1", or a logic va'lue of a second -type, for example, a "0".
A code detector comprises two groups of counters 5-1, 5-2 ... -to 5-N and 6-1, 6-2 to 6-N. Each one of the counters 5-1 to 5-N and 6-1 to 6-N is connected to the associated ssction 2-1 ~o 2 N of t~e shift register 2. The'~ounters 5-1 to 5-N are increased by one when a "1" is detected ' ' in the associated section(~ shift register 2, whereas the counters 6-1 to 6-N are increased by one when a "O"has been de-tected in the associated sec-tion. Thereafter, a next N-'bit word is entered into the shift register 2, the word counter 4 is consequen-tly increased by 1 and it is again deterrnined which logic value has been stored in each sec-tion, and counters 5-1 -to 5-N or counters 6-1to 6N
are increased again in dependence thereon. An output of each of the counters 5-1 to 5-N is connected to an associated threshold device 7-1 to 7-N. Similarly, an output of each of the counters 6-1 to 6-N is connected to an assoclated threshold device 8-'l -to 8-N. Fur-ther inpu-ts of each of -the threshold devices 7 and 8, respec-tive:Ly, are connec-ted to P~N 9548 - 8 - 18.7.80 a respective threshold value genera-tor 9 or 10, and (in common) to an output o~ a threshold device 37. The threshold value which is applied by the respective threshold value generator 9 or 10 to the respective threshold devices 7-1 to 7-N and 8-1 to 8-N is set by means of a control signal applied to control the inputs 11 and 12, respectively, of the threshold value genera-tors 9 and 10. I:f -the counting values of one of the counters 5-1 -to 5-N and 6-1 to 6-N
exceeds the threshold value and -the threshold device 37 supplies a logical "1"(enable signal), a signal ~s supplied, for example in the form of a logic "1", at the output of the asso~iated threshold;' devices 7-1 to 7-N and 8-1to 8-N. The outputs of these -threshold devices are connec-ted, in pairs,to exclusive OR-circuits 32-1 to 32~, the outputs of threshold devices 7-1 and 8-1 being connected to inputs of exclusive OR-gate 32-1,the ou-tputs of threshold devices 7-2 and 8-2 to inputs of exclusive OR-gate circui-t 32-2 and so on. Each one of the outputs of the exclusive OR-gate circuits 32-1 to 32-N is connected to an associated N input of an AND-gate circuit 13, the output of exclusive OR-gate circuit 32-1 being connected to in~ut 13-1 the ou-tpu-t of exclusive OR-gate circuit 32-2-~o input 'i3-2, and so on-. If N or 2N counters 5-'l to 5-N and 6-1to ~-N exceed -the th eshold value, namely one of each pair 5-1/6-1, 5-2/6-2 ....5-N/6-N, the output of the AND-gate 13 changes state.
The outputs o~ the threshold devices 7-1 to 7-N and 8-'l to 8-N are further c7-nnected in pairs to AND-gates 14-1 -to 14-N. Each of the AND-ga-tes 14-1 to 14-N has an inverting and a non-inverting input.The threshold devices 7-1 to 7-N
are connected to the non-inverting inputs and -the -threshold devices 8-'l to 8-N are cunnec-ted -to -the inver-ting inputs.
Outputs of -the AND-ga-tes14-'l to 14-N are connected to an associated section o:f a register 15. If the threshold value of threshold device 7-1 is exceeded and, consequentLy, -the threshold value of threshold dev:ice 8-1 :is no-t exceeded, 6~.
P~N 9548 _ 9 _ 18.7.80 the output of the AND-ga-te 14-1,which is connected to the output of these threshold devices, will change s~ate.If, on the contrary, the threshold value of threshold device 8-1 is exceeded ~and consequently, the theshold value of threshold device 7-1 is not exceeded) the output o~ this AND-gate:14-1 does not change state. The ou-tput signals of the AND-gates 14-1 to 14-N are stored in the register 15 at an instant, determined by the instant at which ~D-gate 13 changes state.To this end t~he output of AND-gate 13 is conne~:ted to a control input 16 of the register l5. The register 15 now contains the bit value of the code word.
Outputs of register 15 are connected to a store 33 for addressing a storage location corresponding to -the code word and containing one of -the messages. In the example given hereinbefore, namely N _ 8, the store 33 contains a total of 256 addresses, at each different 8 of which the same message can be ~ound30 that one output of 32 messages can be found altogether. After deteotion of a code word the assiciated message is available at an output 34 of store 33. The word counter 4 is reset after detection of the code word.To this end the outpu-t of AND-gate' 13 is also connected to a resetting input of the word coun-ter 4. The output of AND-gate 13 is also connected to rese~ting inputs of the coun-ters 5-1 to 5-N and 6-1 to 6-N for resetting these ~ounters on detection of the code word. In addition, the output of the word counter 4 is connected to a threshold element 35 to apply, when a threshold value ~hich was applied to input 36is exceeded, a resettlng pulse to the rese-tting inputs of t'he counters 5-1 to 5-N and 6-1 to 6-N, which resetting inputs are connec-ted to the ou-tput of the -threshold element 35. The output of word cown-ter 4 :is connected to a threshold device '37 for supplying a Iogica:L
"1",enable signal to the thresho:Ld devices 7-1 to 7N when a theshold value applied to input 8 is e~ceeded ancl ~-'l to 8-N.
:
.~
PHN 9548 _ 10 - 18.7.80 ; The code detector shown in Figure 3 opera-tes as follows in, for example, a telephone sys-tem. In the setting-up/signaling phase, the threshold value genera-ted ` by the thresholcl~ values genera-tors 9 and 10 is adjusted to 5,when the requirements shown in Table I are used. The threshold value of the threshold element 35 is adjusted to 32.The bit stream applied -to the input 1 is applied -to the register 2 in groups of N bits.Le-t is be assumed that N = 8 and that the code word is the code word shown in Figure 2a. After the occurrence of -the five consecutive words in the register 2,and -the numbers of "1" and "O"
have been recorded in the associated counters, the counters 5-1, 6-2, 6-3, 6-4, 5-5, 6-6, 6-7 and 5-8, for example, will have att~ined a counter position which is equal to the threshold value 5, provided no bit errors ` 15 have occurred. All 8 inputs of AND-gate 13 will then change \
` state and the code word is determined in register 15 by ~` means of the AND-gates 14. The input,connected to threshold device 7-1, o:f AND-gate 14-1will be high and the inverting input,connected to -the threshold device 8-1, of AND-gate ` 14-1will be low. A logic value 1,which will be entered in the register sec-tion 15-1, will consequently be available at the output of AND-gate 14-1, Similarly, AND-gate 14-2 will have a zero available at its output, which will be entered into the register~ection 15-2. Other logic values ! are entered simiarly in the remaini~g regis-ter sections 15-3 to 15-N. The code word has now been decoded and the word counter 4 and the counters 5-1 to 5-N and 6-1 to 6-N
are reset.
The threshold value has been chosen so that i-t is half the maximwm permissib:Le number of` 10, to ensure tha-t the code words wlll be de-tected within 10 code words.
If, namely,the first 8-bit word entered into shift register2 consists par~ly of -the preceding codc word and partly of`
-PHN 9548 - 11 - 18.7.80 the new code word still to be detected, -then, if the threshold value is 10,it would not be possi~l~ to detect the code word within the required number o-f 10 code word repe-titions, but only after 20 code word repe-titions. If, on the contrary, -the threshold value is 5 and the code word has not been detected after five repetitions of -the code word,for example for the above reasons, -then the code word will be recognized wi-th certainty in the next cycle~of 5 codè words and has then been de-tected after 9 code words.
When the bit error rate in the incoming bit stream is unequal to zero, the code word will be muti~
latedowing to bit errors,so that more code words will be required to determine which code word was transmitted. In view of the requirement~aid down in Table I, 32 consecutive code words are examined to determine which code word occurs five times. If the code word is detected,the word counter 4 and the counters5-1 to 5-n and 6-l -to 6-N are reset by means of a signal supplied by AND-gate 13. If, on the contrary, the code word has not been detected after 32 words, the word counter 4 exceeds the threshold value of threshold element 35 and the coun-ters 5-1 to 5-N and 6-1 to 6-N are reset.
In the traffic phase, :in accordance with the specification of Table I, the threshold values generated by threshold value generators 9 and 10 are adjusted to 2 and the threshold elemen-t 35 is adjusted to 128.In the traffic phase the code detector operates in exactly the same manner as in the setting up/signaling phase.
The flow chart shown in Figure 4 illustrates a first embodiment of the method ~ detecting code words.
The following explana-tory texts belong to the legends in -the geome-tric ~igures wh:ich explain the func-tions and the states of the method of -time-sequen-tial detec-tion of code words. It should be noted tha-t such ~ -time sequence of functions and associa-ted sta-tes of the me-thod of cletecting P~IN 9548 _ 12 - 18.7.80 code words can be realized in universal sequentially programmable logic circuits such as commercially available microprocessors with associated stores and peripheral equipment(f`or example type CDP 1804 of` RCA).
5 legend descri~tion -1- STRT S-tart -2- T1=T2=~.. T2N=K =0 Registers T1, T2f --TN are given a value zero. The bi-ts into which the bit stream is divided is counted in a register K which is given the value zero
1~ith N = 8, that is to say with 2 = 256 code words, 36 different code words are obtained, which cannot be made identical to one another by cyclic permutation. The code word 111111 11 is not so suitable,as a short-circuit in the 15 transmission path may s-timula-te this word. The code word 00000000 may be generated by an open circuit in the transmission pa-th. Further, the code words 10000000 and 01111111 (and any of their 7 cyclic permutations) are not utilized. this leaves 32 unique code words, a number of 20 which is amply sufficient.;o cover the need for signaling characters in telephone systems. ~wenty-eight of these 32 code words occur in eight configur tions, such as, for example, the corde word shown in Figure 2a. Three code words (11101110, 11001100 and 10001000)occur in four 25 configurations and one corde word (10101010) comprises only 2 cyclic permutations. When -the cod~ word shown in Figure 2a is transmi-tted, the same ~ode word as shown in Figure 2a will be received when there is word synchroniza-tion. However, if there is no synchronization, the code 30 word as shown in Figure 2b will be recieved when the re-ceiver is 7 bit positions "slow" with respect to the transmitter, the code word shown :in F:Lg~re 2c wheIl -the receiver is 6 bit positions "s:Low", and so on f`or the remaining Figures 2d-2h. ~s all -these code words ha~ been given the same message, synchron:i~ation :is superfluous.
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PHN 95L~8 _ 7 _ 18.7.80 ' The method of de-tec-ting the code words will now be described with reference to the Figures 3 -to 6.
Figure 3 shows a first embodiment of a code detector. A shift register 2 comprises N sections 2-1, 2-2, ... 2-N, each section having a "1" output and a "0"
ou-tput. A binary digital 'bit stream is applied to -the input of the shift register 2. The bit stream is divided into random data blo~k of N bits. The number of bits of each data block is counted by a bit counter 3, ~or example a modulo-~ counter, which is connected to an input 1. The number of data blocks is counted by a resettable word counter 4, connected to the output of the modulo-N
counter 3.After an N-bit word has been entered into the shift register 2, it is determined in known ~anner for bit position i (i = 1,2 ... N) whether the bit position lS contains a logic valuelof a first type, for example a "1", or a logic va'lue of a second -type, for example, a "0".
A code detector comprises two groups of counters 5-1, 5-2 ... -to 5-N and 6-1, 6-2 to 6-N. Each one of the counters 5-1 to 5-N and 6-1 to 6-N is connected to the associated ssction 2-1 ~o 2 N of t~e shift register 2. The'~ounters 5-1 to 5-N are increased by one when a "1" is detected ' ' in the associated section(~ shift register 2, whereas the counters 6-1 to 6-N are increased by one when a "O"has been de-tected in the associated sec-tion. Thereafter, a next N-'bit word is entered into the shift register 2, the word counter 4 is consequen-tly increased by 1 and it is again deterrnined which logic value has been stored in each sec-tion, and counters 5-1 -to 5-N or counters 6-1to 6N
are increased again in dependence thereon. An output of each of the counters 5-1 to 5-N is connected to an associated threshold device 7-1 to 7-N. Similarly, an output of each of the counters 6-1 to 6-N is connected to an assoclated threshold device 8-'l -to 8-N. Fur-ther inpu-ts of each of -the threshold devices 7 and 8, respec-tive:Ly, are connec-ted to P~N 9548 - 8 - 18.7.80 a respective threshold value genera-tor 9 or 10, and (in common) to an output o~ a threshold device 37. The threshold value which is applied by the respective threshold value generator 9 or 10 to the respective threshold devices 7-1 to 7-N and 8-1 to 8-N is set by means of a control signal applied to control the inputs 11 and 12, respectively, of the threshold value genera-tors 9 and 10. I:f -the counting values of one of the counters 5-1 -to 5-N and 6-1 to 6-N
exceeds the threshold value and -the threshold device 37 supplies a logical "1"(enable signal), a signal ~s supplied, for example in the form of a logic "1", at the output of the asso~iated threshold;' devices 7-1 to 7-N and 8-1to 8-N. The outputs of these -threshold devices are connec-ted, in pairs,to exclusive OR-circuits 32-1 to 32~, the outputs of threshold devices 7-1 and 8-1 being connected to inputs of exclusive OR-gate 32-1,the ou-tputs of threshold devices 7-2 and 8-2 to inputs of exclusive OR-gate circui-t 32-2 and so on. Each one of the outputs of the exclusive OR-gate circuits 32-1 to 32-N is connected to an associated N input of an AND-gate circuit 13, the output of exclusive OR-gate circuit 32-1 being connected to in~ut 13-1 the ou-tpu-t of exclusive OR-gate circuit 32-2-~o input 'i3-2, and so on-. If N or 2N counters 5-'l to 5-N and 6-1to ~-N exceed -the th eshold value, namely one of each pair 5-1/6-1, 5-2/6-2 ....5-N/6-N, the output of the AND-gate 13 changes state.
The outputs o~ the threshold devices 7-1 to 7-N and 8-'l to 8-N are further c7-nnected in pairs to AND-gates 14-1 -to 14-N. Each of the AND-ga-tes 14-1 to 14-N has an inverting and a non-inverting input.The threshold devices 7-1 to 7-N
are connected to the non-inverting inputs and -the -threshold devices 8-'l to 8-N are cunnec-ted -to -the inver-ting inputs.
Outputs of -the AND-ga-tes14-'l to 14-N are connected to an associated section o:f a register 15. If the threshold value of threshold device 7-1 is exceeded and, consequentLy, -the threshold value of threshold dev:ice 8-1 :is no-t exceeded, 6~.
P~N 9548 _ 9 _ 18.7.80 the output of the AND-ga-te 14-1,which is connected to the output of these threshold devices, will change s~ate.If, on the contrary, the threshold value of threshold device 8-1 is exceeded ~and consequently, the theshold value of threshold device 7-1 is not exceeded) the output o~ this AND-gate:14-1 does not change state. The ou-tput signals of the AND-gates 14-1 to 14-N are stored in the register 15 at an instant, determined by the instant at which ~D-gate 13 changes state.To this end t~he output of AND-gate 13 is conne~:ted to a control input 16 of the register l5. The register 15 now contains the bit value of the code word.
Outputs of register 15 are connected to a store 33 for addressing a storage location corresponding to -the code word and containing one of -the messages. In the example given hereinbefore, namely N _ 8, the store 33 contains a total of 256 addresses, at each different 8 of which the same message can be ~ound30 that one output of 32 messages can be found altogether. After deteotion of a code word the assiciated message is available at an output 34 of store 33. The word counter 4 is reset after detection of the code word.To this end the outpu-t of AND-gate' 13 is also connected to a resetting input of the word coun-ter 4. The output of AND-gate 13 is also connected to rese~ting inputs of the coun-ters 5-1 to 5-N and 6-1 to 6-N for resetting these ~ounters on detection of the code word. In addition, the output of the word counter 4 is connected to a threshold element 35 to apply, when a threshold value ~hich was applied to input 36is exceeded, a resettlng pulse to the rese-tting inputs of t'he counters 5-1 to 5-N and 6-1 to 6-N, which resetting inputs are connec-ted to the ou-tput of the -threshold element 35. The output of word cown-ter 4 :is connected to a threshold device '37 for supplying a Iogica:L
"1",enable signal to the thresho:Ld devices 7-1 to 7N when a theshold value applied to input 8 is e~ceeded ancl ~-'l to 8-N.
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PHN 9548 _ 10 - 18.7.80 ; The code detector shown in Figure 3 opera-tes as follows in, for example, a telephone sys-tem. In the setting-up/signaling phase, the threshold value genera-ted ` by the thresholcl~ values genera-tors 9 and 10 is adjusted to 5,when the requirements shown in Table I are used. The threshold value of the threshold element 35 is adjusted to 32.The bit stream applied -to the input 1 is applied -to the register 2 in groups of N bits.Le-t is be assumed that N = 8 and that the code word is the code word shown in Figure 2a. After the occurrence of -the five consecutive words in the register 2,and -the numbers of "1" and "O"
have been recorded in the associated counters, the counters 5-1, 6-2, 6-3, 6-4, 5-5, 6-6, 6-7 and 5-8, for example, will have att~ined a counter position which is equal to the threshold value 5, provided no bit errors ` 15 have occurred. All 8 inputs of AND-gate 13 will then change \
` state and the code word is determined in register 15 by ~` means of the AND-gates 14. The input,connected to threshold device 7-1, o:f AND-gate 14-1will be high and the inverting input,connected to -the threshold device 8-1, of AND-gate ` 14-1will be low. A logic value 1,which will be entered in the register sec-tion 15-1, will consequently be available at the output of AND-gate 14-1, Similarly, AND-gate 14-2 will have a zero available at its output, which will be entered into the register~ection 15-2. Other logic values ! are entered simiarly in the remaini~g regis-ter sections 15-3 to 15-N. The code word has now been decoded and the word counter 4 and the counters 5-1 to 5-N and 6-1 to 6-N
are reset.
The threshold value has been chosen so that i-t is half the maximwm permissib:Le number of` 10, to ensure tha-t the code words wlll be de-tected within 10 code words.
If, namely,the first 8-bit word entered into shift register2 consists par~ly of -the preceding codc word and partly of`
-PHN 9548 - 11 - 18.7.80 the new code word still to be detected, -then, if the threshold value is 10,it would not be possi~l~ to detect the code word within the required number o-f 10 code word repe-titions, but only after 20 code word repe-titions. If, on the contrary, -the threshold value is 5 and the code word has not been detected after five repetitions of -the code word,for example for the above reasons, -then the code word will be recognized wi-th certainty in the next cycle~of 5 codè words and has then been de-tected after 9 code words.
When the bit error rate in the incoming bit stream is unequal to zero, the code word will be muti~
latedowing to bit errors,so that more code words will be required to determine which code word was transmitted. In view of the requirement~aid down in Table I, 32 consecutive code words are examined to determine which code word occurs five times. If the code word is detected,the word counter 4 and the counters5-1 to 5-n and 6-l -to 6-N are reset by means of a signal supplied by AND-gate 13. If, on the contrary, the code word has not been detected after 32 words, the word counter 4 exceeds the threshold value of threshold element 35 and the coun-ters 5-1 to 5-N and 6-1 to 6-N are reset.
In the traffic phase, :in accordance with the specification of Table I, the threshold values generated by threshold value generators 9 and 10 are adjusted to 2 and the threshold elemen-t 35 is adjusted to 128.In the traffic phase the code detector operates in exactly the same manner as in the setting up/signaling phase.
The flow chart shown in Figure 4 illustrates a first embodiment of the method ~ detecting code words.
The following explana-tory texts belong to the legends in -the geome-tric ~igures wh:ich explain the func-tions and the states of the method of -time-sequen-tial detec-tion of code words. It should be noted tha-t such ~ -time sequence of functions and associa-ted sta-tes of the me-thod of cletecting P~IN 9548 _ 12 - 18.7.80 code words can be realized in universal sequentially programmable logic circuits such as commercially available microprocessors with associated stores and peripheral equipment(f`or example type CDP 1804 of` RCA).
5 legend descri~tion -1- STRT S-tart -2- T1=T2=~.. T2N=K =0 Registers T1, T2f --TN are given a value zero. The bi-ts into which the bit stream is divided is counted in a register K which is given the value zero
-3- CW A N-bit word is written in.
~ - K:=K+I Register K is increased one unit l5 -5~Ti:=Ti+l(bi=1) The content bi of CW is examined Ti~N:Ti+N+1(bi ) f`or each bit posi-tion i(i-1,...N) If` bi has a value 1, register Ti is increased one unit; if`, on the contrary, bi has a value 0, register Ti+N is increased one unit.
7 i/ i+N ~J ? The registers T1~ t2'-- T2n are compared wi-th a value n. If` of`
each pair Ti/Ti+N(i=1,2,..N)one register reaches or exceeds the value n, then step -8- is per-f`ormed. If` the value n is not reached or no-t exceeded, step -2- is performed.
30 -6- K - m? The number of` words K is compared with a~de-termined value m.If` K
is eclual to m, operation is cont:inued wi-th s-tep -7-.If K is no-t equal to m, s-tep -3- is per~ormed.
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PHN 9548 - 13 - 18.7.80 legend description -~- CWN The code word is formed from -the N registers ln which the value n was exceeded, registers - 5 Ti representing a value 1 and registers Ti~N representlng a value 0.
-9- STP stop.
Figure 5 shows a bloc~ schematic diagram of a second embodiment of the code detector for the detection of code words. Input terminal 1,which receive~s a binary digital bi-t stream is connected to~the input of a shift register 2 having N sections. The bits are counted by a ~` counter 3,for example a modulo-N counter,connected to the input terminal 1. A resettable word counter 4 for recording the number of times a group of N bits has been entered into shift register 2 is connected to an output of the counter 3. A second shift register 19 is conected to an output of shift register 2.Shift register 19,and also shift register 2,comprise-s N sections. Those sections of the shift registers 2 and 19 of the same numerical order, that is to say æctions 2-1 and 19-1, 2-2 and 19-2 ... to 2-N
and 19-N, are connected to exclusive OR-circui-ts 20-1, 20-2 to 20-N. Qhen the bit values i corresponding positions in -the shift registers 2 and 19 are identical, -the ou-tputs of -the exclusive OR-circui-ts change state. The outputs are connected -to the same number of inputs of a NAND-circuit 21.
The OUtp~lt of NAND-circuit 21 is connected to an input of a resettable counter 22 and,by way of an inverting gate circuit 23, to a reset input of the counter 22. Each -time the exclusive OR-circuits de-tec-t bit agreement, coun-ter 22 is increased one unit. If -there is no bit agreement, -the counter 22 is reset by way of the invcrting gate c:Lrcuit 23.
The output of counter 22 ls connected to a firs-t input o:f a threshold elemen-t 24.A second inpu-t receives a thresho:Lcl va:Lue.
PHN 9548 ~ 14 _ 18.7.80 A further outpu-t of each secttion of shift register2 is connected to a corresponding coun-ter 25-1 to 25-N. The counters 25-1 to 25-N are up/down counters. I~hen a "1~occurs in the bi-t section to which the counter is connected the counting value is increased one unit and when "0~ occurs -the counting value is decreased one unit.
Connected to the output of each of the counters 25-1 to 25-N is an associated -threshold device 26-1 -to 26-N whose output changes state when a threshoid value, generated by a threshold value generator 27 and applied to a further output of these -threshold devices, is exceeded. The output of each threshold device 26~1 -to 26-N is connected to one of N inputs of an AND-circuit 29. The threshold devices 26-1 to 26-Nhave been designed sothat only the absolu-te value of the content of each of -the counters 25-1 to 25-N is compared with the threshold value.
The outputs of -the counters 25-1 to 25-N are further connected to a sign determination device 30. The ou-tput of AND-circuit 29 is connected to a control input 310f sign determination device 30. ~hen the output of AN~-circuit 29 changes state, the sign determination device 30determines the sign of the counting value of each of the counters 25-1 to 25-N. The code word is then availabla at the output of -the device 30. For the same purpose the output of threshold element 24 is also connected to input 31 of sign determination davice 30.The outputs of AND-ga-te circuit 29 and threshold element 24 are further connec-ted to a rese-tting input of counter 22, to a resetting input of word counter 4 and to resetting inputs of counters 25-1 to 25-N for resetting counter 22, word counter ~ and the up/down counters 25-1 ro 25-N, after -the code word has been de-tected. An output of l~ord counter 4 :is connec-ted to threshold element 35 for applying reset s:ignals to the resetting inpu-ts of the counters 25-1 to 25-N when a value which is applied to a further input 36 of threshold elemen-t P~IN 9548 - 15 - 18.7.80 35 is exceeded.
The code detector shown in Figure 5 in, for example, a telephone systenn having the speci~ication indi-cated in Table I, operates as follows. A threshold value 9 tsetting-up phase) or a threshold value 39(traffice phase) is applied to threshold element 2L~; a threshold element 32 is applied in the setting-up phase to threshold element 35:
a threshold value 128 is applied in the traffic phase t~ threshold elemen-t 25.Threshold value generat`or 27 generates a threshold value in the setting-up phase and a threshold value 64 in the traffice phase. The 'bit stream applied~ input'terminal 1 is divided into groups of 8 bits.
The number of groups is counted in counter ~.A group of eight `bits is entered into the shift register 2.It is determined for each section whether a "1" or a "0" is present. If a "1" is present, the associated bit counter 25-1 to 25-Nis increased by one unit, if a "0" is present, the associat'ed bit counter is reduced by one bit. Thereafter, a next group of 8 'bits is entered into shift register 2, 20 and so on. ~hen the'absolute ~alue of all counters 25-1 to 25-N exceeds the threshold value(6 in the setting-up phase and 6~ in the traffic phase)the AND-gat'e cuit 29 connected to the threshold devices 26 activates -the sign de-termination device 30 by means of a signal applied to 25 input 31. Device 30 converts the sign of the counting , values of the relevant counter into a logic value. The logic values on the parallel output 18 form the code word to be detected. If the code worde has not been detected after32 (setting-up phase) or 128 (-traffic phase)groups of 30 8 bits, the counters 25-1 -to 25-N are reset and a new cycle is started. In order -to de-tect~ for a 'bit error ra-te of 0%j the code word within -the maximum numbe~r of code words, the second shift register 19 is connected -to the ou-tput of shift register 2.Af-ter a group of 8 bits has 'been 35 examined in regis-ter 2, this group is entered :i-n -thc second ~6~
PHN 9548 - 16 - 18.7.80 shift register l9 and a new group of 8 bits is entered into the shift register 2. It is cheeked whe-ther there is bit agreement in each corresponding section.If this is the case for each position7 the outputs of the exclu~ed OR-gate circuit 20 change state, c~using NAND-gate circuit 21 to change the state and to supply a pulse -to counter 22.
The counting value of counter 22 will reach the threshold value after 9 code words in the case of a 0% BER, which is an indic~tion tha-t the code word has been detected. The code word is , for example, read by activating sign determination device 30 or by using an output 32 of shift register 19. After the threshold value o~ threshold element 24 has been reached, coun-ters 25-1 to 25-N and the counters 22 and 4 are reset.
A second embodiment of` the method o~ detecting code wordsis illustrated by the flow chart of Figure 6. The following explanatory -texts are associated with the legens in the geometric Figures which explain the functionsand the eonditions of the method of` detecting code words in time sequence.
legend description -1- STRT Start -2- I:=O Register I is given a value zero. Register I is used to record how many times two consecutive code words are identical.
-3- T1= TN=K:0 Registers T1,T2,... TN are given a value zero. The words into which the bit s-tream is divided are counted :in a regis-ter K, which is given a value zero as -the in:i-tial value;
PHN 9548 ~- 17 - 18.7.80 legend descriptlon
~ - K:=K+I Register K is increased one unit l5 -5~Ti:=Ti+l(bi=1) The content bi of CW is examined Ti~N:Ti+N+1(bi ) f`or each bit posi-tion i(i-1,...N) If` bi has a value 1, register Ti is increased one unit; if`, on the contrary, bi has a value 0, register Ti+N is increased one unit.
7 i/ i+N ~J ? The registers T1~ t2'-- T2n are compared wi-th a value n. If` of`
each pair Ti/Ti+N(i=1,2,..N)one register reaches or exceeds the value n, then step -8- is per-f`ormed. If` the value n is not reached or no-t exceeded, step -2- is performed.
30 -6- K - m? The number of` words K is compared with a~de-termined value m.If` K
is eclual to m, operation is cont:inued wi-th s-tep -7-.If K is no-t equal to m, s-tep -3- is per~ormed.
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PHN 9548 - 13 - 18.7.80 legend description -~- CWN The code word is formed from -the N registers ln which the value n was exceeded, registers - 5 Ti representing a value 1 and registers Ti~N representlng a value 0.
-9- STP stop.
Figure 5 shows a bloc~ schematic diagram of a second embodiment of the code detector for the detection of code words. Input terminal 1,which receive~s a binary digital bi-t stream is connected to~the input of a shift register 2 having N sections. The bits are counted by a ~` counter 3,for example a modulo-N counter,connected to the input terminal 1. A resettable word counter 4 for recording the number of times a group of N bits has been entered into shift register 2 is connected to an output of the counter 3. A second shift register 19 is conected to an output of shift register 2.Shift register 19,and also shift register 2,comprise-s N sections. Those sections of the shift registers 2 and 19 of the same numerical order, that is to say æctions 2-1 and 19-1, 2-2 and 19-2 ... to 2-N
and 19-N, are connected to exclusive OR-circui-ts 20-1, 20-2 to 20-N. Qhen the bit values i corresponding positions in -the shift registers 2 and 19 are identical, -the ou-tputs of -the exclusive OR-circui-ts change state. The outputs are connected -to the same number of inputs of a NAND-circuit 21.
The OUtp~lt of NAND-circuit 21 is connected to an input of a resettable counter 22 and,by way of an inverting gate circuit 23, to a reset input of the counter 22. Each -time the exclusive OR-circuits de-tec-t bit agreement, coun-ter 22 is increased one unit. If -there is no bit agreement, -the counter 22 is reset by way of the invcrting gate c:Lrcuit 23.
The output of counter 22 ls connected to a firs-t input o:f a threshold elemen-t 24.A second inpu-t receives a thresho:Lcl va:Lue.
PHN 9548 ~ 14 _ 18.7.80 A further outpu-t of each secttion of shift register2 is connected to a corresponding coun-ter 25-1 to 25-N. The counters 25-1 to 25-N are up/down counters. I~hen a "1~occurs in the bi-t section to which the counter is connected the counting value is increased one unit and when "0~ occurs -the counting value is decreased one unit.
Connected to the output of each of the counters 25-1 to 25-N is an associated -threshold device 26-1 -to 26-N whose output changes state when a threshoid value, generated by a threshold value generator 27 and applied to a further output of these -threshold devices, is exceeded. The output of each threshold device 26~1 -to 26-N is connected to one of N inputs of an AND-circuit 29. The threshold devices 26-1 to 26-Nhave been designed sothat only the absolu-te value of the content of each of -the counters 25-1 to 25-N is compared with the threshold value.
The outputs of -the counters 25-1 to 25-N are further connected to a sign determination device 30. The ou-tput of AND-circuit 29 is connected to a control input 310f sign determination device 30. ~hen the output of AN~-circuit 29 changes state, the sign determination device 30determines the sign of the counting value of each of the counters 25-1 to 25-N. The code word is then availabla at the output of -the device 30. For the same purpose the output of threshold element 24 is also connected to input 31 of sign determination davice 30.The outputs of AND-ga-te circuit 29 and threshold element 24 are further connec-ted to a rese-tting input of counter 22, to a resetting input of word counter 4 and to resetting inputs of counters 25-1 to 25-N for resetting counter 22, word counter ~ and the up/down counters 25-1 ro 25-N, after -the code word has been de-tected. An output of l~ord counter 4 :is connec-ted to threshold element 35 for applying reset s:ignals to the resetting inpu-ts of the counters 25-1 to 25-N when a value which is applied to a further input 36 of threshold elemen-t P~IN 9548 - 15 - 18.7.80 35 is exceeded.
The code detector shown in Figure 5 in, for example, a telephone systenn having the speci~ication indi-cated in Table I, operates as follows. A threshold value 9 tsetting-up phase) or a threshold value 39(traffice phase) is applied to threshold element 2L~; a threshold element 32 is applied in the setting-up phase to threshold element 35:
a threshold value 128 is applied in the traffic phase t~ threshold elemen-t 25.Threshold value generat`or 27 generates a threshold value in the setting-up phase and a threshold value 64 in the traffice phase. The 'bit stream applied~ input'terminal 1 is divided into groups of 8 bits.
The number of groups is counted in counter ~.A group of eight `bits is entered into the shift register 2.It is determined for each section whether a "1" or a "0" is present. If a "1" is present, the associated bit counter 25-1 to 25-Nis increased by one unit, if a "0" is present, the associat'ed bit counter is reduced by one bit. Thereafter, a next group of 8 'bits is entered into shift register 2, 20 and so on. ~hen the'absolute ~alue of all counters 25-1 to 25-N exceeds the threshold value(6 in the setting-up phase and 6~ in the traffic phase)the AND-gat'e cuit 29 connected to the threshold devices 26 activates -the sign de-termination device 30 by means of a signal applied to 25 input 31. Device 30 converts the sign of the counting , values of the relevant counter into a logic value. The logic values on the parallel output 18 form the code word to be detected. If the code worde has not been detected after32 (setting-up phase) or 128 (-traffic phase)groups of 30 8 bits, the counters 25-1 -to 25-N are reset and a new cycle is started. In order -to de-tect~ for a 'bit error ra-te of 0%j the code word within -the maximum numbe~r of code words, the second shift register 19 is connected -to the ou-tput of shift register 2.Af-ter a group of 8 bits has 'been 35 examined in regis-ter 2, this group is entered :i-n -thc second ~6~
PHN 9548 - 16 - 18.7.80 shift register l9 and a new group of 8 bits is entered into the shift register 2. It is cheeked whe-ther there is bit agreement in each corresponding section.If this is the case for each position7 the outputs of the exclu~ed OR-gate circuit 20 change state, c~using NAND-gate circuit 21 to change the state and to supply a pulse -to counter 22.
The counting value of counter 22 will reach the threshold value after 9 code words in the case of a 0% BER, which is an indic~tion tha-t the code word has been detected. The code word is , for example, read by activating sign determination device 30 or by using an output 32 of shift register 19. After the threshold value o~ threshold element 24 has been reached, coun-ters 25-1 to 25-N and the counters 22 and 4 are reset.
A second embodiment of` the method o~ detecting code wordsis illustrated by the flow chart of Figure 6. The following explanatory -texts are associated with the legens in the geometric Figures which explain the functionsand the eonditions of the method of` detecting code words in time sequence.
legend description -1- STRT Start -2- I:=O Register I is given a value zero. Register I is used to record how many times two consecutive code words are identical.
-3- T1= TN=K:0 Registers T1,T2,... TN are given a value zero. The words into which the bit s-tream is divided are counted :in a regis-ter K, which is given a value zero as -the in:i-tial value;
PHN 9548 ~- 17 - 18.7.80 legend descriptlon
-4- CW An N-bit word is written in.
1 Register K is increased by one unit.
1 Register K is increased by one unit.
5 -6_ CW= CW0 ? The word CW is compared bit-by-bit wi-th the preceding code word CWO.I f there is bit agreement, the nex-t step is performed.If there is no bit agreement step -9- is performed as the next step.
-7- l~ 1 Register I is increased by one uni-t;
-8- I=THR ? The conten-t of register I is compared with a threshold value THR. I-t is has not reached this value step -10- is performed as the next s-tep. If I has reached this value then step -13- is performed as the next step.
20 ~9- I: =0 Register I is given the value zero;
_10- T1 :=T1~ b1 The regis-ter values T1, T2,.T
N N- N are increased by one unit or reduced by one unit, depending on whether the associated bit posi-tion b1, b2 ... bN has a first or a second binary value;
-12- T1'T2'--TN ~n ? The con-tent of the registers T1 .. TN is compared with a threshold value n.When all the reg:isters have a value which is a-t leas-t eq-ual to n, -then step -l3- is perforTned as -the nex-t step.
If this is not -the case s-tep -3_ is performed.
-11- K = m ? If register K has reached a pre-de-termined value m, s-tep -l2- is performed as -the ne~{t step. If this is no-t the case, proceed to PHN 9548 - 18 - 18.7.80 le~end description step -4-.
-13 - CWN The code word thus de-termined is read;
-14- STP Stop.
The embodiment of the me-thod of Figure 6 has the a~atnage, compared with the embodiment of the method of ~igure 4,that in the former only 8(~2)counters mus-t be re-adjusted, whereas in the latter 16(~2)counters wi-th the method of ~igure 6 two data blocks of N bits must be c~mpared, which is not necessary in the method of ~igure 4, but this is only a minor extension, as this comparison may be carrier ou-t by checking whether the difference in the code words of data blocks is 0.
-7- l~ 1 Register I is increased by one uni-t;
-8- I=THR ? The conten-t of register I is compared with a threshold value THR. I-t is has not reached this value step -10- is performed as the next s-tep. If I has reached this value then step -13- is performed as the next step.
20 ~9- I: =0 Register I is given the value zero;
_10- T1 :=T1~ b1 The regis-ter values T1, T2,.T
N N- N are increased by one unit or reduced by one unit, depending on whether the associated bit posi-tion b1, b2 ... bN has a first or a second binary value;
-12- T1'T2'--TN ~n ? The con-tent of the registers T1 .. TN is compared with a threshold value n.When all the reg:isters have a value which is a-t leas-t eq-ual to n, -then step -l3- is perforTned as -the nex-t step.
If this is not -the case s-tep -3_ is performed.
-11- K = m ? If register K has reached a pre-de-termined value m, s-tep -l2- is performed as -the ne~{t step. If this is no-t the case, proceed to PHN 9548 - 18 - 18.7.80 le~end description step -4-.
-13 - CWN The code word thus de-termined is read;
-14- STP Stop.
The embodiment of the me-thod of Figure 6 has the a~atnage, compared with the embodiment of the method of ~igure 4,that in the former only 8(~2)counters mus-t be re-adjusted, whereas in the latter 16(~2)counters wi-th the method of ~igure 6 two data blocks of N bits must be c~mpared, which is not necessary in the method of ~igure 4, but this is only a minor extension, as this comparison may be carrier ou-t by checking whether the difference in the code words of data blocks is 0.
Claims (9)
1. A method of detecting a message in the form of a digital code word, the digital code word containing a sequence of a predetermined number of bits and being included a few times consecutively and sequentially in a bit stream, characterized in that - the bit stream is randomly divided into data blocks, each data block having a number of bits which is equal to the number of bits of the digital code word;
- the digital bit state is determined and recorded for each bit position in the data block;
- the recorded data of each bit position are accumulated for a plurality of consecutive data blocks;
- the accumulated value of the recorded data of each bit position for a plurality of data blocks is compared with a threshold value;
- the digital code word is detected from the digital state of the accumulated values when the threshold value for each bit position in a plurality of data blocks has at least been reached.
- the digital bit state is determined and recorded for each bit position in the data block;
- the recorded data of each bit position are accumulated for a plurality of consecutive data blocks;
- the accumulated value of the recorded data of each bit position for a plurality of data blocks is compared with a threshold value;
- the digital code word is detected from the digital state of the accumulated values when the threshold value for each bit position in a plurality of data blocks has at least been reached.
2. A method of detecting a digital code word as claimed in Claim l, characterized in that the code word and the bit stream contain binary data.
3. A method of detecting a digital code word as claimed in Claim 2, characterized in that the number of times first digital state of each bit of the data block is deter-mined is accumulated by a first accumulator and that the number of times a second digital state of each bit of the data block is determined is accumulated by a second accumu-lator.
4. A method of detecting a digital code word as claimed in Claim 2, characterized in that a first digital state of each bit of the data block is accumulated with a positive sign and that a second digital state of each bit of the data block is accumulated with a negative sign.
PHN. 9548 20
PHN. 9548 20
5. A method of detecting a digital code word as claimed in Claim 4, characterized in that:
- a data block is compared with a preceding data block;
- the number of times data blocks are consecutively and sequentially identical is accumulated; and - when a threshold value is reached by the accumulated value, the code word is identical to the data block.
- a data block is compared with a preceding data block;
- the number of times data blocks are consecutively and sequentially identical is accumulated; and - when a threshold value is reached by the accumulated value, the code word is identical to the data block.
6. A code detector for detecting a message in the form of a digital code word, the digital code word contain-ing a sequence of a predetermined number of bits and being included at least two times consecutively and sequentially in a bit stream comprising: a shift resister having a number of sections equal to the number of bits (N) of the digital code word, each section having an output means for randomly dividing the bit stream into data blocks of N bits, these data blocks being applied to an input of the shift register, the output of each section being coupled to associated counting means for determining the number of times that the same digital state of the bits has occurred in each section in a plurality of data blocks, and the code detector further comprising threshold devices each having a first input for receiving a threshold value and a second input con-nected to the associated counting means, and an output, the outputs of the threshold devices providing signal values, which are a representation of the digital code word, when the threshold value of each threshold device is exceeded.
7. A code detector as claimed in Claim 6, charac-terized in that the counting means comprise a first and a second group of N counters, one counter of each group being coupled to one of the sections of the shift register, the first group of counters accumulating the number of times the first digital state of the bits of the data block in a pre-ceding number of data blocks has been determined, and the second group of counters accumulating the number of times the other digital state of the bits of the data block in the preceding number of data blocks has been determined.
8. A code detector as claimed in Claim 6, charac-terized in that the counting means comprise a group of N
PHN. 9548 21 counters, each section of the shift register being coupled to the associated counter, the count of the counters being increased by one unit when the first digital state of the data block has been determined and reduced by one unit when the second digital state of the data block has been determined.
PHN. 9548 21 counters, each section of the shift register being coupled to the associated counter, the count of the counters being increased by one unit when the first digital state of the data block has been determined and reduced by one unit when the second digital state of the data block has been determined.
9. A code detector as claimed in Claim 8, charac-terized in that the code detector comprises a further shift register having N sections each having an output, that the corresponding outputs of the two shift registers are connected to exclusive OR-gate circuits to determine bit agreement in the corresponding sections, that outputs of the N exclusive OR-gate circuits are connected to inputs of a NAND-gate circuit, and that an output of the NAND-gate circuit is connected to a counting element for accumu-lating the number of times consecutively sequential data blocks are identical.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL7905968 | 1979-08-03 | ||
| NL7905968A NL7905968A (en) | 1979-08-03 | 1979-08-03 | METHOD FOR DETECTING A DIGITAL CODE WORD AND CODE DETECTOR FOR CARRYING OUT THE METHOD |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1161168A true CA1161168A (en) | 1984-01-24 |
Family
ID=19833644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000357379A Expired CA1161168A (en) | 1979-08-03 | 1980-07-31 | Digital code word detection |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US4375102A (en) |
| JP (1) | JPS6034300B2 (en) |
| AU (1) | AU533659B2 (en) |
| BE (1) | BE884614A (en) |
| CA (1) | CA1161168A (en) |
| DE (1) | DE3027579A1 (en) |
| FR (1) | FR2463550A1 (en) |
| GB (1) | GB2056226B (en) |
| NL (1) | NL7905968A (en) |
| SE (1) | SE447186B (en) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5817745A (en) * | 1981-07-17 | 1983-02-02 | Victor Co Of Japan Ltd | Synchronism detecting system |
| JPS5841460U (en) * | 1981-09-11 | 1983-03-18 | 株式会社東芝 | refrigerator |
| US4489420A (en) * | 1983-03-09 | 1984-12-18 | General Electric Company | Clear channel detector for binary digital data transmission system |
| US4596024A (en) * | 1983-05-23 | 1986-06-17 | At&T Bell Laboratories | Data detector using probabalistic information in received signals |
| US4696008A (en) * | 1983-12-02 | 1987-09-22 | Canon Kabushiki Kaisha | Data storing device having position determining means |
| US4611336A (en) * | 1984-02-21 | 1986-09-09 | Calculagraph Company | Frame synchronization for distributed framing pattern in electronic communication systems |
| US4866666A (en) * | 1984-10-29 | 1989-09-12 | Francisco Michael H | Method for maintaining data integrity during information transmission by generating indicia representing total number of binary 1's and 0's of the data |
| US4688215A (en) * | 1985-06-05 | 1987-08-18 | Calculagraph Company | Demultiplexer for two-stage framing |
| JPH0719205B2 (en) * | 1986-06-27 | 1995-03-06 | 安藤電気株式会社 | Continuous data detection circuit |
| US4879731A (en) * | 1988-08-24 | 1989-11-07 | Ampex Corporation | Apparatus and method for sync detection in digital data |
| US4977596A (en) * | 1989-03-15 | 1990-12-11 | The United States Of America As Represented By The United States Department Of Energy | Cryptographic synchronization recovery by measuring randomness of decrypted data |
| JPH02299324A (en) * | 1989-05-15 | 1990-12-11 | Mitsubishi Electric Corp | Vocoder |
| US5289391A (en) * | 1992-02-10 | 1994-02-22 | Aerometrics, Inc. | Method and apparatus for optimum signal burst detection |
| US5606563A (en) * | 1995-05-18 | 1997-02-25 | Pmc-Sierra, Inc. | Programmable jump window for sonet compliant bit error monitoring |
| US5968197A (en) * | 1996-04-01 | 1999-10-19 | Ericsson Inc. | Method and apparatus for data recovery |
| CA2197263A1 (en) * | 1997-02-11 | 1998-08-11 | Dan Burke | Method of detecting signal degradation fault conditions within sonet and sdh signals |
| US6560745B1 (en) * | 2000-07-21 | 2003-05-06 | The United States Of America As Represented By The National Security Agency | Method of identifying boundary of markerless codeword |
| US7079856B2 (en) * | 2002-04-05 | 2006-07-18 | Lucent Technologies Inc. | Data flow control between a base station and a mobile station |
| US10795571B2 (en) * | 2017-09-28 | 2020-10-06 | The Toronto-Dominion Bank | System and method to perform an undo operation using a continuous gesture |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1288126B (en) * | 1965-04-06 | 1969-01-30 | CSF-Compagnie Generale de TeIegraphie Sans FiI, Paris | Variable threshold comparison circuitry for identifying a group of cyclically repeated signals |
| DE2228875C3 (en) * | 1972-06-14 | 1980-03-06 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Circuit arrangement for the transmission of dialing and switching indicators in message transmission systems with delta modulation |
| AU482164B2 (en) * | 1972-11-13 | 1975-05-15 | Lm ERICSSON PTY. LTD | TIME DIVISION MULTIPLEXED Specification DIGITAL SWITCHING APPARATUS V |
| FR2309101A1 (en) * | 1975-04-22 | 1976-11-19 | Labo Cent Telecommunicat | Telephone number identification system - numbers are represented by cyclic codes modulated on voice frequency carrier |
| NL176035C (en) * | 1976-08-06 | 1985-02-01 | Nederlanden Staat | DEVICE FOR RECOGNIZING SIGNALING INFORMATION. |
| US4271520A (en) * | 1979-06-25 | 1981-06-02 | Motorola, Inc. | Synchronizing technique for an error correcting digital transmission system |
-
1979
- 1979-08-03 NL NL7905968A patent/NL7905968A/en not_active Application Discontinuation
-
1980
- 1980-07-21 DE DE19803027579 patent/DE3027579A1/en active Granted
- 1980-07-29 US US06/173,309 patent/US4375102A/en not_active Expired - Lifetime
- 1980-07-30 GB GB8024942A patent/GB2056226B/en not_active Expired
- 1980-07-31 SE SE8005482A patent/SE447186B/en not_active IP Right Cessation
- 1980-07-31 AU AU60950/80A patent/AU533659B2/en not_active Ceased
- 1980-07-31 CA CA000357379A patent/CA1161168A/en not_active Expired
- 1980-08-01 FR FR8017107A patent/FR2463550A1/en active Granted
- 1980-08-01 BE BE0/201637A patent/BE884614A/en not_active IP Right Cessation
- 1980-08-04 JP JP55107067A patent/JPS6034300B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| SE447186B (en) | 1986-10-27 |
| BE884614A (en) | 1981-02-02 |
| JPS5624845A (en) | 1981-03-10 |
| GB2056226B (en) | 1983-11-23 |
| AU6095080A (en) | 1981-02-05 |
| FR2463550B1 (en) | 1982-12-10 |
| SE8005482L (en) | 1981-02-04 |
| US4375102A (en) | 1983-02-22 |
| JPS6034300B2 (en) | 1985-08-08 |
| GB2056226A (en) | 1981-03-11 |
| DE3027579A1 (en) | 1981-02-19 |
| NL7905968A (en) | 1981-02-05 |
| DE3027579C2 (en) | 1989-07-20 |
| AU533659B2 (en) | 1983-12-01 |
| FR2463550A1 (en) | 1981-02-20 |
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