CA1163341A - Error-correcting data transmission system - Google Patents
Error-correcting data transmission systemInfo
- Publication number
- CA1163341A CA1163341A CA000377619A CA377619A CA1163341A CA 1163341 A CA1163341 A CA 1163341A CA 000377619 A CA000377619 A CA 000377619A CA 377619 A CA377619 A CA 377619A CA 1163341 A CA1163341 A CA 1163341A
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- CA
- Canada
- Prior art keywords
- words
- data
- check
- series
- word
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1806—Pulse code modulation systems for audio signals
- G11B20/1809—Pulse code modulation systems for audio signals by interleaving
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1876—Interpolating methods
Abstract
PHQ.80-009 10.3.81 ABSTRACT
"An error-correcting data transmission method, a device encompassing such error-correcting data transmission method, a data carrier produced by executing such error correcting data transmission method, a decoder for use with such error-correcting data transmission method, and a device encompassing such decoder"
In an error correctable data transmission method a plurality of serial to parallel converted data words is, in a first arranging state, fed to a first error correcting coder (8) to generate a plurality of check words. Next, the check words and data words are delayed by mutually different delay intervals (9) and fed to a second error correcting coder (10). In this way a further plurality of check words is produced. Next, the two groups of check words and the data words are parallel to serial converted to a data block. Further delay elements (11) will transpose certain data words and/or check words to adjacent data blocks. The error correcting code allows both for correcting burst errors and random errors.
"An error-correcting data transmission method, a device encompassing such error-correcting data transmission method, a data carrier produced by executing such error correcting data transmission method, a decoder for use with such error-correcting data transmission method, and a device encompassing such decoder"
In an error correctable data transmission method a plurality of serial to parallel converted data words is, in a first arranging state, fed to a first error correcting coder (8) to generate a plurality of check words. Next, the check words and data words are delayed by mutually different delay intervals (9) and fed to a second error correcting coder (10). In this way a further plurality of check words is produced. Next, the two groups of check words and the data words are parallel to serial converted to a data block. Further delay elements (11) will transpose certain data words and/or check words to adjacent data blocks. The error correcting code allows both for correcting burst errors and random errors.
Description
~ 3 3 ~ 1 PHQ.80-oO9 1 10.3.81 "An error-correcting data transmission method, a device encompassing such error-correcting data transmission method7 a data carrier produced by executing such error correcting data transmission method, a decoder for use with such error-correcting data transmission method, and a device encompassing such decoder"
The present invention relates to a data trans-mission method which has a high error-correcting capability for both burst errors and random errors. An earlier proposal ~or a data transmission method encompassing capability for correcting burst errors has used a so-called "cross-interleave feature". In this cross-interleave, a PCM (pulse code modulated) word of each ofa plurality of parallel channels arranged in a first arranging state is ~`ed to a first error correcting coder to generate therefrom a ~irst check word series; this first check word series and the PCM data series of the plural channels are converted to a second arranging state;
and one word contained in each of the PCM data series of the plural channels in the second arranging state is fed to a second error correcting cocler thereby to generate a second check word series, whereby a double interleave (re-arrangement) is carried out per word unit. The inter-leave serves to reduce the number of erroneous words contained in a common error correcting block when the check word contained in the common error correcting block and the PCM data are transmitted after being dispersed and they are returned to the original arrangement thereof at the receiving side. In other words, when a burst error ~ is generated during transmission, the burst error can be ; dispersed. If the above mentioned interleave is per~ormed twice, the first and second check words each form an error correcting block. For example, even if an error cannot be corrected by the first chec~ words, the error can be corrected by the second check words, and vice versa.
Therefore, the error correcting capability is improved.
3 3 4 -~
PHQ. 80-009 2 Even when in the aforementioned data transmission method a word con-tains only one erroneous bit, the whole word is considered erroneous. Therefore, when received data including relati~ely large numbers of random errors have to be dealt with, the above-mentioned cross-interleave does not always have a sufficient error correcting ability.
It is an object of the present invention to provide an error correcting data transmission method having both burst error and random error correcting capability. The object of the invention is realized by an error correcting data transmission method comprising the steps of:
receiving a data stream by receiving each time one data word of a data word series on each of a first plurality of parallel channels according to a first arranging state;
applying one word on each of said first plurality of parallel channels to a first error correcting coder to generate a first check word.series~
delaying said first check word series and the words of said data word series, after application to said first error correcting coder by mutually different delay times to convert them to a second arranging state:
applying one word on each of said first plurality of channels and said first check word series in said second arranging state to a second error correcting coder to generate a second check word series;
transmitting each time one data word on each of a plura-lity of output channels e~ual to said first plurality and one first check word series and one second check word series on each of a second plurality of output channels;
wherein the generation of a check word series of k check words is based upon the following parity detection matrix H, wherein in said first and second correcting coders each word is formed of m.bits and a check word series formed in an encoder completes the error correctable block to a total of n words, wherein n ~ 2m-1:
,~
~ ~ ~33~
PHQ. so-oog 3 10 . 3 . 81 1 1 1 ~ 1 1 l 1 ~ 2 j~ 3 ~n-1 ,~
~2 ~4 ,~6 ~2(n-l) ~2n H=
~k-1 ~(k-1)2 X(k-1)3 (k-1)(n~ (k-l)r or 101 1 1 --~
1 ~ ~x2 _____ ~ n-2 ~ n-1 1 ~X 2 ,~4 _____ ~ 2(n-2) X 2(n-1) H=
l5 .
1 ~ k-1 ~(k-1)2 (k-1)(n-2)(k-l~(n~
where ~ is a root which satis~ies F(x) = O when F(x) is an irreducible and primitive polynomial of degree m over a field GF(2). Obviously, ~or the second error correctin~
coder the value o~ n is larger than ~or the ~irst error correcting coder.
It has been ~ound that the transmission method ; ~ according to the present invention (a kind o~ so-called "adjacent codes" or "b-adjacent code") has a hi~h error correcting capability and may correct up to two word errors in one block. ~190, 3 word errors or 4 ~ord errors can be corrected when the position o~ an error can be known, if combined with the abo~e mentioned multi-inter-leave. Further, when the error detecting codq is used tocorrect only a one-word error, a decoder used there~ore can be much simplified in construction.
The invention also relates to a device encompas-! sing an error-correcting data transmission method as mentioned hereabove, said device comprisin~:
~irst means ~or receiving an audio signal and generating there~rom a sequence o~ odd and even digitized samples;
second means ~or distributing each even digitized sample .
J 16334 ~
PHQ.8O-OO9 4 10.3.81 into two even data words and distributing each odd digiti~ed sample into two odd data words, and third means ~or presenting said odd and even data words to said first plurality o~ parallel channels. Thus a simple encoding device is ad~antageously provided.
The inventlon also relates to a data carrier produced by executing a method as indicated hereabove, the data carrier comprising a sequence of blocks each block comprising a sequence of: a third plurality, equal t~ hal~ said first plurality, of words derived from even data words of said data word series; a fourth plurality of words derived ~rom said first check word series;
a further third plurality of words derived ~rom odd data ; words of said data word series, and a further ~ourth plurality of words derived from said second check word series. In this way a carrier for error-correcting data storage has been provided, for example ~or storing very-high quality audio signals.
The invention also relates to a decoder for use with an error-correcting data transmission method as mentioned hereabove, which decoder comprises:
a) input means for each time receiving on a plurality equal to said first plurality of receiving channels a data word series and in parallel therewith on a plurality equal to said second plurality o~ receiving channels a first check word series and a second check word series, b) a ~irst de~oder means for under control o~ said second check word series reproducing each time a first plurality o~ data words and a first check word series by means o~ a first syndrome generated therein;
c) delaying means for realigning said data words and first check word series by mutually di~ferent delay times thereamong;
d) a second decoder means for under control of said first checlc word series reproducing each time a firs-t plurality of data words by means of a second syndrome generated therein;
~ ~33~ ~
PHQ.80-oog 5 10.3.81 e) output means ~or each tlme outputting on a plurality o~ channels equal to said ~irst plurality o~ outputting channels a data-word o~ a series o~ data words, a sequence of data words representing a data stream. In this way an advantageous and straight~orwardly operating decoder has been provided.
The invention also relates to a device including a decoder as described hereabove, which device ~urther-more comprises:
fourth means ~or receiving a serial data stream and ~or generating there~rom parallel data for each of the respec-tive channels o~ said input means;
parallel to serial reconverting means ~or serializing the data words outputted on said outputting channels, and digital to analog converting means ~or therefrom generating a continuous audio signal. Such device may represent, ~or example, a hifi record player of superior quality than the type hitherto in general use.
In the following, first, an error code suitable for use in this invention will be described. Therea~ter, the invention will be more extensively described according '; to the following diagrammatic clrawings, which show the ~ollowing pre~erred embodiments without therewith imply-ing any restriction to the scope of the invention:
Fig. 1 shows a block diagram showing an example of an 0rror correcting encoder to which the present ~ invention is applied.
,~ Fig. 2 shows a block diagram showing an arrange-ment upon transmission;
Fig. 3 shows a block diagram showing an example of an error correcting decoder;
Figs. 4 and ~ are respectively diagrams used to explain the operation o~ the error correcting decoder.
Fig. 6 is a block diagram o~ a second encoder;
Fig. 7 is a block diagram of a second decoder;
Fig. 8 is a block diagram o~ a -third encoder;
Fig. 9 is a block diagram o~ a third decoder;
33~ 1 PHQ~80-oog 6 10.3.81 Figo 10 is a block diagram o~ a ~ourth encoder;
Fig. 11 is a block dia~ram o~ a ~our-th decoder.
Now, ~or explaining the error correcting code use is made o~ a vector representation or cyclic group representation. In the first place, an irreducible and primitive m'th order polynomial F(x) is considered over a Galois ~ield GF(2). The theory of Galois ~ieldsis standard and will not be reconsidered here. The ~ield GF(2) consists only of the elements "0" and "1". Suppose there exists a root ~ , which satisfies F(x) = 0. Now, an extension field ~F(2 ) which consists o~ 2m di~erent elements can be constructed by means of the quantities ~ ~ ~X 1 9 1~ 2 ... ~ m 1, each being a dif~erent power o~
the root ~ (the set o~ these quantities is called the "base" o~ the ~ield GF(2 ). Note that the ~ield GF(2m) also contains the zero element. The extension ~ield GF(2 ) is a polynominal ring with anmlth order irreducible polynominal F(x) over the ~ield GF(2) as a modulo. Each element o~ GF(2m) can be expressed as a linear combination f ~ = 19 ~ = {X~9 ~ 2 = {x23, ___ ~ m 1 =~xm 1~.
The general ~orm o~ this expression is:
aO + a 1 {X} i a2 {X 3 ~ + am_ 11~ ,}
= ~0 + a1~ + a2~ + ~~~ a 1 ~ m-1 or ( m-1' am-2' -- a2~ a1~ ac)) m-1' am~2' '8- a1' aO are elements of GF(2).
As an example, GF(2 ) is considered; wherein the primitive and irreducible polynomial F(x) is, ~or example~
F(x) -- x + x + x3 + x2 ~ 1. All eight-bi-ts data words may be axpressed as follows:
a7x7 + a6x6+a5x5+a4x4~a3x3+a2x2+a1x~aO or (a7~ a69 a59 a49 a39 a29 al 9 ) There~ore, by way o~ example, a7 i5 assigned to the ~ISB (most signi~icant bi-t) side and aO i3 assigned to the LSB (least signi~icant bit) side, respectively.
` 7~ 34~
PHQ.80-oog 7 l0.3.81 Since aj belongs to GF(2), its element is 0 or 1.
Further, from the polynominal F(x) the following matrix T of (m x m) may be derived:
0 0 ----- 0 aO
1 0 -~--- a1 0 1 ~~~~ ~2 T=
.
. . , . .
O 0 1 am-1~
Alternatively, the elements o~ GF(2 ) may be expressed by using a cyclic group, by considering that the reminder of GF(2 ) except zero element~forms a multiplicative group wit7n the order 2m . If the elements of GF(2m) are expressed by using such cyclic group, the following is obtained.
1 (- ~2m-1) ~ ~2 o~3 ~2m-2 In the present invention, w7nen m bits form 1 - word and n words form 1 block, k check words are generated based upon the :~ollowing parity check matrix H.
. ~1 ~2 ~3 ~n-1 ~n ~ 25~2 ~4 ~ 6 ~2(n-1) ~2n : H= .
. . . . , .
. ~k-1 ~(k-1)2 ~(k-1)3 ~(k-1)(n-1) ~(k-1)n The parity check matrix H can be equally expressed by using the matrix T as follows:
I I I ----- I I
T1 T2 T3 ~~~~~ Tn~1 T
; T2 T4 T6 ~~~~~ T2(n~1) T2n 35 H= .
Tk-1 T(k~1)2 T(k-1)3 T(k-1)(n-1) T(k 1)nJ
~ i~3341 PHQ. 80-009 8 10.3.81 where I is a unit matri~ of (m x m) elements.
As described above, the expressions using the root~
are fundamentally the same as that using a generating matri~.
In this case, it is possible that al~ elements of the firs-t column o~ each matrix are selected a~i 1 or I and the last column o~ each matri~ can be omitted.
The error correcting code will be described in deta~
for an e~ample wherein ~our (k=4) _heck words are used. In this case, i~ 1 block of r0ceived data is taken as a column ( 1~ 2~ W3, -. Wn~, 4 syndromes, S , S S
and SL~ are generated at the rec~iving side in accordance wi~:
~4~ = H.VT
l5 , ~_ n
The present invention relates to a data trans-mission method which has a high error-correcting capability for both burst errors and random errors. An earlier proposal ~or a data transmission method encompassing capability for correcting burst errors has used a so-called "cross-interleave feature". In this cross-interleave, a PCM (pulse code modulated) word of each ofa plurality of parallel channels arranged in a first arranging state is ~`ed to a first error correcting coder to generate therefrom a ~irst check word series; this first check word series and the PCM data series of the plural channels are converted to a second arranging state;
and one word contained in each of the PCM data series of the plural channels in the second arranging state is fed to a second error correcting cocler thereby to generate a second check word series, whereby a double interleave (re-arrangement) is carried out per word unit. The inter-leave serves to reduce the number of erroneous words contained in a common error correcting block when the check word contained in the common error correcting block and the PCM data are transmitted after being dispersed and they are returned to the original arrangement thereof at the receiving side. In other words, when a burst error ~ is generated during transmission, the burst error can be ; dispersed. If the above mentioned interleave is per~ormed twice, the first and second check words each form an error correcting block. For example, even if an error cannot be corrected by the first chec~ words, the error can be corrected by the second check words, and vice versa.
Therefore, the error correcting capability is improved.
3 3 4 -~
PHQ. 80-009 2 Even when in the aforementioned data transmission method a word con-tains only one erroneous bit, the whole word is considered erroneous. Therefore, when received data including relati~ely large numbers of random errors have to be dealt with, the above-mentioned cross-interleave does not always have a sufficient error correcting ability.
It is an object of the present invention to provide an error correcting data transmission method having both burst error and random error correcting capability. The object of the invention is realized by an error correcting data transmission method comprising the steps of:
receiving a data stream by receiving each time one data word of a data word series on each of a first plurality of parallel channels according to a first arranging state;
applying one word on each of said first plurality of parallel channels to a first error correcting coder to generate a first check word.series~
delaying said first check word series and the words of said data word series, after application to said first error correcting coder by mutually different delay times to convert them to a second arranging state:
applying one word on each of said first plurality of channels and said first check word series in said second arranging state to a second error correcting coder to generate a second check word series;
transmitting each time one data word on each of a plura-lity of output channels e~ual to said first plurality and one first check word series and one second check word series on each of a second plurality of output channels;
wherein the generation of a check word series of k check words is based upon the following parity detection matrix H, wherein in said first and second correcting coders each word is formed of m.bits and a check word series formed in an encoder completes the error correctable block to a total of n words, wherein n ~ 2m-1:
,~
~ ~ ~33~
PHQ. so-oog 3 10 . 3 . 81 1 1 1 ~ 1 1 l 1 ~ 2 j~ 3 ~n-1 ,~
~2 ~4 ,~6 ~2(n-l) ~2n H=
~k-1 ~(k-1)2 X(k-1)3 (k-1)(n~ (k-l)r or 101 1 1 --~
1 ~ ~x2 _____ ~ n-2 ~ n-1 1 ~X 2 ,~4 _____ ~ 2(n-2) X 2(n-1) H=
l5 .
1 ~ k-1 ~(k-1)2 (k-1)(n-2)(k-l~(n~
where ~ is a root which satis~ies F(x) = O when F(x) is an irreducible and primitive polynomial of degree m over a field GF(2). Obviously, ~or the second error correctin~
coder the value o~ n is larger than ~or the ~irst error correcting coder.
It has been ~ound that the transmission method ; ~ according to the present invention (a kind o~ so-called "adjacent codes" or "b-adjacent code") has a hi~h error correcting capability and may correct up to two word errors in one block. ~190, 3 word errors or 4 ~ord errors can be corrected when the position o~ an error can be known, if combined with the abo~e mentioned multi-inter-leave. Further, when the error detecting codq is used tocorrect only a one-word error, a decoder used there~ore can be much simplified in construction.
The invention also relates to a device encompas-! sing an error-correcting data transmission method as mentioned hereabove, said device comprisin~:
~irst means ~or receiving an audio signal and generating there~rom a sequence o~ odd and even digitized samples;
second means ~or distributing each even digitized sample .
J 16334 ~
PHQ.8O-OO9 4 10.3.81 into two even data words and distributing each odd digiti~ed sample into two odd data words, and third means ~or presenting said odd and even data words to said first plurality o~ parallel channels. Thus a simple encoding device is ad~antageously provided.
The inventlon also relates to a data carrier produced by executing a method as indicated hereabove, the data carrier comprising a sequence of blocks each block comprising a sequence of: a third plurality, equal t~ hal~ said first plurality, of words derived from even data words of said data word series; a fourth plurality of words derived ~rom said first check word series;
a further third plurality of words derived ~rom odd data ; words of said data word series, and a further ~ourth plurality of words derived from said second check word series. In this way a carrier for error-correcting data storage has been provided, for example ~or storing very-high quality audio signals.
The invention also relates to a decoder for use with an error-correcting data transmission method as mentioned hereabove, which decoder comprises:
a) input means for each time receiving on a plurality equal to said first plurality of receiving channels a data word series and in parallel therewith on a plurality equal to said second plurality o~ receiving channels a first check word series and a second check word series, b) a ~irst de~oder means for under control o~ said second check word series reproducing each time a first plurality o~ data words and a first check word series by means o~ a first syndrome generated therein;
c) delaying means for realigning said data words and first check word series by mutually di~ferent delay times thereamong;
d) a second decoder means for under control of said first checlc word series reproducing each time a firs-t plurality of data words by means of a second syndrome generated therein;
~ ~33~ ~
PHQ.80-oog 5 10.3.81 e) output means ~or each tlme outputting on a plurality o~ channels equal to said ~irst plurality o~ outputting channels a data-word o~ a series o~ data words, a sequence of data words representing a data stream. In this way an advantageous and straight~orwardly operating decoder has been provided.
The invention also relates to a device including a decoder as described hereabove, which device ~urther-more comprises:
fourth means ~or receiving a serial data stream and ~or generating there~rom parallel data for each of the respec-tive channels o~ said input means;
parallel to serial reconverting means ~or serializing the data words outputted on said outputting channels, and digital to analog converting means ~or therefrom generating a continuous audio signal. Such device may represent, ~or example, a hifi record player of superior quality than the type hitherto in general use.
In the following, first, an error code suitable for use in this invention will be described. Therea~ter, the invention will be more extensively described according '; to the following diagrammatic clrawings, which show the ~ollowing pre~erred embodiments without therewith imply-ing any restriction to the scope of the invention:
Fig. 1 shows a block diagram showing an example of an 0rror correcting encoder to which the present ~ invention is applied.
,~ Fig. 2 shows a block diagram showing an arrange-ment upon transmission;
Fig. 3 shows a block diagram showing an example of an error correcting decoder;
Figs. 4 and ~ are respectively diagrams used to explain the operation o~ the error correcting decoder.
Fig. 6 is a block diagram o~ a second encoder;
Fig. 7 is a block diagram of a second decoder;
Fig. 8 is a block diagram o~ a -third encoder;
Fig. 9 is a block diagram o~ a third decoder;
33~ 1 PHQ~80-oog 6 10.3.81 Figo 10 is a block diagram o~ a ~ourth encoder;
Fig. 11 is a block dia~ram o~ a ~our-th decoder.
Now, ~or explaining the error correcting code use is made o~ a vector representation or cyclic group representation. In the first place, an irreducible and primitive m'th order polynomial F(x) is considered over a Galois ~ield GF(2). The theory of Galois ~ieldsis standard and will not be reconsidered here. The ~ield GF(2) consists only of the elements "0" and "1". Suppose there exists a root ~ , which satisfies F(x) = 0. Now, an extension field ~F(2 ) which consists o~ 2m di~erent elements can be constructed by means of the quantities ~ ~ ~X 1 9 1~ 2 ... ~ m 1, each being a dif~erent power o~
the root ~ (the set o~ these quantities is called the "base" o~ the ~ield GF(2 ). Note that the ~ield GF(2m) also contains the zero element. The extension ~ield GF(2 ) is a polynominal ring with anmlth order irreducible polynominal F(x) over the ~ield GF(2) as a modulo. Each element o~ GF(2m) can be expressed as a linear combination f ~ = 19 ~ = {X~9 ~ 2 = {x23, ___ ~ m 1 =~xm 1~.
The general ~orm o~ this expression is:
aO + a 1 {X} i a2 {X 3 ~ + am_ 11~ ,}
= ~0 + a1~ + a2~ + ~~~ a 1 ~ m-1 or ( m-1' am-2' -- a2~ a1~ ac)) m-1' am~2' '8- a1' aO are elements of GF(2).
As an example, GF(2 ) is considered; wherein the primitive and irreducible polynomial F(x) is, ~or example~
F(x) -- x + x + x3 + x2 ~ 1. All eight-bi-ts data words may be axpressed as follows:
a7x7 + a6x6+a5x5+a4x4~a3x3+a2x2+a1x~aO or (a7~ a69 a59 a49 a39 a29 al 9 ) There~ore, by way o~ example, a7 i5 assigned to the ~ISB (most signi~icant bi-t) side and aO i3 assigned to the LSB (least signi~icant bit) side, respectively.
` 7~ 34~
PHQ.80-oog 7 l0.3.81 Since aj belongs to GF(2), its element is 0 or 1.
Further, from the polynominal F(x) the following matrix T of (m x m) may be derived:
0 0 ----- 0 aO
1 0 -~--- a1 0 1 ~~~~ ~2 T=
.
. . , . .
O 0 1 am-1~
Alternatively, the elements o~ GF(2 ) may be expressed by using a cyclic group, by considering that the reminder of GF(2 ) except zero element~forms a multiplicative group wit7n the order 2m . If the elements of GF(2m) are expressed by using such cyclic group, the following is obtained.
1 (- ~2m-1) ~ ~2 o~3 ~2m-2 In the present invention, w7nen m bits form 1 - word and n words form 1 block, k check words are generated based upon the :~ollowing parity check matrix H.
. ~1 ~2 ~3 ~n-1 ~n ~ 25~2 ~4 ~ 6 ~2(n-1) ~2n : H= .
. . . . , .
. ~k-1 ~(k-1)2 ~(k-1)3 ~(k-1)(n-1) ~(k-1)n The parity check matrix H can be equally expressed by using the matrix T as follows:
I I I ----- I I
T1 T2 T3 ~~~~~ Tn~1 T
; T2 T4 T6 ~~~~~ T2(n~1) T2n 35 H= .
Tk-1 T(k~1)2 T(k-1)3 T(k-1)(n-1) T(k 1)nJ
~ i~3341 PHQ. 80-009 8 10.3.81 where I is a unit matri~ of (m x m) elements.
As described above, the expressions using the root~
are fundamentally the same as that using a generating matri~.
In this case, it is possible that al~ elements of the firs-t column o~ each matrix are selected a~i 1 or I and the last column o~ each matri~ can be omitted.
The error correcting code will be described in deta~
for an e~ample wherein ~our (k=4) _heck words are used. In this case, i~ 1 block of r0ceived data is taken as a column ( 1~ 2~ W3, -. Wn~, 4 syndromes, S , S S
and SL~ are generated at the rec~iving side in accordance wi~:
~4~ = H.VT
l5 , ~_ n
2 i=1
3 i = 1 S4 = ~ T3il~i Each block contains 4 check words (p = Wn 3, q Wn-2~ r = Wn_1~ s ~ Wn). These check words are generated at the transmitting side according to:
P ~ q ~ r + s = ~ W
n-3 Tn~2q ~ Tn~1r ~ Tns = ~ T W
T2n-6 T2n~4q + T2n-2r + T2ns = ~T2i 3n-9 T3n 6q ~ T3n~nr + T3ns -~--T3 Wi P + q + r ~ s = ~ Wi = a p + Tq ~ T2r + T3s = ~ Ti-n+3 W = b p + T q + T4r + T6s =~ T2(i-n+3)w = c 35 p + T3q ~ T6r + T9S = ~ T3(i-n~3)W = d n_L~
where ~ is ~ .
i= 'I
1633~ ~
PHQ 80-009 9 10.3.81 The check worcls can be obtained by solving these simul-taneous equations. The calculation is de~inecl in G~(2m) and the result is as ~ollows:
5 ~p = T a +~ ~T +T ~T51b + (T~T2+T ~ + d (1-~T) (1+T ) (1+T3) T5 _+ (T +T3+,r5)b + ~ +T ~T3~c + d r T4a + (T+T3 ~ b +¦ 1+T+T3 ~ + d . lO T (1+T ) ~5 T3a + ~+T +T3~b ~ (1+T+T )c +_d T3(1+T) (1+T2) (1+T3) P = LT ~Wi ~ T+T )-{~ T ~ 1~i + ~ T2(i n+3)+1 W.
i~ (1+T) 1. (1+T2)-1 q =[T5~ W + (l+T+T3)~ Ti-rl+5 Wi + (1~T +T3) .
~ T2(i-n~3) W + ~ T3(i~n+3) Wi] . T 2.(1~T ) 20 ~ =LT4~Wi ~ (1+T2+T3)~ Ti n~4 . Wi ~ T+T3) .
.~ T ( +3) Wi + ~T3(i n+3) Wi~ T 3 .(1+T4) 1 ;
s =~T3 ~ Wi ~ (1+T+T2){Ti n+4 Wi + ~ T ( +3) W
25 ~ ll. T . ( 1 +T ) 1 . (1+T2)-1 ( 3 Next 5 an error correction will be described when the da-ta including the check words genera-ted as above are transmitted and then received. In this case, it is assumed that a pointer representing an error position 30 is not used.
(1) I~ there is no error, S1 = S2 = S3 = S4 = O.
(2) I~ there is one word error (an error pa-ttern is taken a~ ei), S1 = ei, S2 = T ei, S3 = T ei and S4 = T3 ei.
Thus, the ~ollowing equations are established.
~ ~)334 1 PHQ.80-009 10 10.3.81 T S1 = S2 2 s3 I _ 3 4 At this time, the syndrome S1 is the error pattern ei itself.
(3) In the case of 2 word errors (ei and ej):
l S1 = ei + ej ; 10 S2 = T ei + Tiej S3 = T2iei + T2iej ¦ S4 = T3 ei ~ T3iej The above equations can be modified as ~ollows:
TiS1 + S2 = (Ti + Ti) ei I TiS2 + S3 = T (T + Ti) ei TjS3 + S4 = T (T + Ti) ei Accordingl~, if the following equations are established, 2 word errors are discrimina-ted.
fT (T S1 + S2) = TiS2 + S3 T (T S2 + S3)= TiS3 + S4 The error patterns at this time are e~pressed as follows:
ei = ~ ~ , ej = ~ j
P ~ q ~ r + s = ~ W
n-3 Tn~2q ~ Tn~1r ~ Tns = ~ T W
T2n-6 T2n~4q + T2n-2r + T2ns = ~T2i 3n-9 T3n 6q ~ T3n~nr + T3ns -~--T3 Wi P + q + r ~ s = ~ Wi = a p + Tq ~ T2r + T3s = ~ Ti-n+3 W = b p + T q + T4r + T6s =~ T2(i-n+3)w = c 35 p + T3q ~ T6r + T9S = ~ T3(i-n~3)W = d n_L~
where ~ is ~ .
i= 'I
1633~ ~
PHQ 80-009 9 10.3.81 The check worcls can be obtained by solving these simul-taneous equations. The calculation is de~inecl in G~(2m) and the result is as ~ollows:
5 ~p = T a +~ ~T +T ~T51b + (T~T2+T ~ + d (1-~T) (1+T ) (1+T3) T5 _+ (T +T3+,r5)b + ~ +T ~T3~c + d r T4a + (T+T3 ~ b +¦ 1+T+T3 ~ + d . lO T (1+T ) ~5 T3a + ~+T +T3~b ~ (1+T+T )c +_d T3(1+T) (1+T2) (1+T3) P = LT ~Wi ~ T+T )-{~ T ~ 1~i + ~ T2(i n+3)+1 W.
i~ (1+T) 1. (1+T2)-1 q =[T5~ W + (l+T+T3)~ Ti-rl+5 Wi + (1~T +T3) .
~ T2(i-n~3) W + ~ T3(i~n+3) Wi] . T 2.(1~T ) 20 ~ =LT4~Wi ~ (1+T2+T3)~ Ti n~4 . Wi ~ T+T3) .
.~ T ( +3) Wi + ~T3(i n+3) Wi~ T 3 .(1+T4) 1 ;
s =~T3 ~ Wi ~ (1+T+T2){Ti n+4 Wi + ~ T ( +3) W
25 ~ ll. T . ( 1 +T ) 1 . (1+T2)-1 ( 3 Next 5 an error correction will be described when the da-ta including the check words genera-ted as above are transmitted and then received. In this case, it is assumed that a pointer representing an error position 30 is not used.
(1) I~ there is no error, S1 = S2 = S3 = S4 = O.
(2) I~ there is one word error (an error pa-ttern is taken a~ ei), S1 = ei, S2 = T ei, S3 = T ei and S4 = T3 ei.
Thus, the ~ollowing equations are established.
~ ~)334 1 PHQ.80-009 10 10.3.81 T S1 = S2 2 s3 I _ 3 4 At this time, the syndrome S1 is the error pattern ei itself.
(3) In the case of 2 word errors (ei and ej):
l S1 = ei + ej ; 10 S2 = T ei + Tiej S3 = T2iei + T2iej ¦ S4 = T3 ei ~ T3iej The above equations can be modified as ~ollows:
TiS1 + S2 = (Ti + Ti) ei I TiS2 + S3 = T (T + Ti) ei TjS3 + S4 = T (T + Ti) ei Accordingl~, if the following equations are established, 2 word errors are discrimina-ted.
fT (T S1 + S2) = TiS2 + S3 T (T S2 + S3)= TiS3 + S4 The error patterns at this time are e~pressed as follows:
ei = ~ ~ , ej = ~ j
(4) In the case o~ 3 word errors (ei, ej and ek):
S1 = ei + ej + ek S2 = T ei + Tiej + T ek S3 = T2iei + T2iej + T2k k ~S4 = T ei + T3iej ~ T3kek The above equations can be modified as follows-T S1 + S2 = (T + T )ei + (Ti + T ) e T S2 + S3 = T (Ti ~ Tk)ei + Ti (Ti ~ Tk) e T S3 ~ S4 = T2i(Ti ~ Tk)ei ~ T2i (Ti k) ) ~334~
PHQ.8o-oo9 11 10.3.81 Accordingly, i~ the ~ollowing equation is established, 3 word errors can be discriminated since the condi-tions $1 ~ ' S2 ~ ~ S3 ~ 0 are satis~ied.
Tj(T S1~S2)~(T S2-~S3) = T~ (T S2 -~ S3) + (T S3 ~ S4) The respective error patterns at -this time are expressed as f`ollows:
rei = 1_ ( + T )-S2 ( 1~Ti j)( l~-Ti-k) 1 + (T + T i) S ~ T-k-iS
ej = ~ 3 (1~TJ i) (~,~,Tj_ 1 ~ (T ~ T i)S ~ T-i-ek = ----- (1+Tk-i) (1 ~- Tk-i) As described above, all 3-word errors can be corrected without using the pointer.
If the pointer is used and error positions (i, j, k, l) are known thereby, 4 word errors can also be corrected.
Further, i~ the number k o~ the check words is increased, the error correcting ability can be improved even further.
Now, an example of the present invention will be described with re~erence to the a-t-tached drawing in which the invention is applied to the recording and reproducing o~ an audio PCM signal.
Fig. 1 shows, as a whole, an error correcting encoder provided in the recording system whose input side is supplied with an audio PCM signal. The audio PCM signal is provided in such a manner that left and right stereo signals are respectively sampled at a sampling ~requency fs (for example 7 44.1 k~Iz) and each sampled value is con-verted into a sixteen-bit number expressed in two's complement notation. Accordinglv, the left audio channel provides a string of 16-bits PCM data (L0, L1, L2 ...) and ~ ~633A~1 PHQ.80-009 12 10.3.81 the right audio channel provides a further s-tring o~
16-bits PCM data (R0, R1, R2 ...). The PCM data of the left and right audio channels are each multiplexed-by-word by a device not shown, cyclically over a respective plurality of six encoding channels. Therefor~, -totally 12 channels of PCM data series are input to the error correcting encoder. At a given or predetermined ins-tant, e.g. 12 numbers such as L , R L R L
6n 6n9 6n+1' 6n+l' 6n+2' 6n+2' 6n+3' 6n-~3' 6n~4' R6n+4' L6n+5' R6n+5 are iIlput~
In the example each 16-bit number is divided into eight more significant bits and eight less signi~icant bits.
These eight-bit groups will be called "words" herein-after. Consequently, the twelve numbers are processed ;~ 15 according to twenty-four parallel channels. Now, one 16-bit number of the PCM data series is indicated as Wi, its upper 8 bits are expressed as Wii A and its lower bits are expressed as Wi B respectively. For example, the number L6n is divided into two words W12n A and W12n B.
Note also the earlier use of n as a di~ension of the ; matrixes H.
The PC~I data series of 24 channels are firstly fed to an even and odd interleaver 1. If n = 0, 1, 2, ---~the words L6n (i-e- W12n~ A and W12n,B)' 6n ( 25 12n+1,A 12n+1~B)' 6n+2 (i.e. ~12n+4,A a~ W12n~4 B)' 6n+2 12n~5,A and W12n~5 B)~ L6 4 (i-e~ W
and W 8 B) and R6n+~ e- W12n~9~A 12n+9,B
constitute the even order words, while the other words likewise are odd order words. The PCM data series consisting of even order words are respectively delayed through respective delay circuits or delay lines 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A and 7B of the even and odd in-terleaver 1 by a one word interval. ~urther, in the even and odd interleaver 1 such a conversion is carried out that 12 data series consisting of even order words occupy 1st to 12th transmission channels and 12 data series consisting of odd order words occupy 13th -to 24th transmission channels, respectively.
J l~33~
PHQ.80-oo9 13 10.3.81 The even and odd interleaver 1 serves to avoid the situation 1~herein more than two adjacent numbers o~
any (left or right) audio channel would be erroneous and the errors would then be incorrectable. This can be under-stood as ~ollows. Three adjacent numbers Li 1~ Li, Li+1will be considered b~ wa~ of` example. Irhere the number Li is erroneous and non-correctable~ the number Li 1 or Li+1, or both, should be correct. In this way, the erroneous number Li may be restored by replacing it by lO the directly preceding number Li 1 or by the directly following number Li~1 or by the average value o~ Li 1 and Li+1. In many instances this provides an acceptable approximation o~ -the "true" value o~ Li. The dela~v lines 2A, 2B ... 7A, 7B o~ the even and odd interleaver 1 are 15 provided for adjacent ~ords to be contained in di~eren-t error correcting blocks. Further, the reason wh~v the transmission channels for each o~ the data series consisting of the even order words and the data series consis-ting o~
; odd order words are gathered is that when the data series 20 are interleaved, the distance between the recording positions o~ the adjacent even and odd order words are selected as ~ar apart as possible.
At the output of the even and odd interleaver 1, the PCM data series o~ 24 channels appear in a first 25 arranging state. The words that have been delayed by a one word interval have been indicated by an index that is twelve points lower at the output of interleaver 1.
From the respective PCM data series, each time ~our ~irst d Q12n~ Q12n*1~ Q12n~2~ Q12n~3 are de iv d m 30 an error correcting block o~ data words. Thi.s error correcting block there~ore comprises the words:
(W12n-12,A; W12n-12,13; W12n~1-12,A; W12n+1-12,B;
12n~4-12,A; 12n+4-12,B; 12n~5-12,A; 12n+5-12,B;
12n+8-12,A; 12n~8-12,B; 12n+9-12,A; 12n+9-12,B;
12n+2,A; 12n~2,B; 12n~3,A; 12n+3,B; 12n~6,A;
12n+6,B; 12n+7,A; 12n~7,B; W12n+10,A; 12n+10,B;
` ~ ~6334~
PHQo 80-009 14 10~ 3~ 81 12n~ A; W12n+11,B; Q12n; Q12n+l~ Q12n+2 Ql2rl~3)-In the ~irst coder ~ therefore, twenty-~our data words of 8 bits each are encoded to yield four check words. Conse-quently, the ~ixed parameter values of the code used here - are n = 28, m = 8, k = 4.
24 PCM data series and 4 check word series are ~ed to a second interleaver 9. ~n this in-terleaver 9, the positions ofthe transmission channels are changed such that the check word series are located between the PCM data series consisting o~ the even order words and the PCM data series consis-ting of the odd order words t ; and thereafter the delay pracess for this interleaving is performed, This delay process is such that 27 trans-mission channels except the first transmission channel are delayed by delay lines with delay amounts of lD, 2D, 3D, 4D, --- 26D and 27D (where D is a unit delay amount), respectively.
At the output o~ the interleaver 9 28 data series in a second arranging state appear. From the respective data series, the data words are derived one ~y one. Then, the words are fed to a coder 10 which then produces ` second check words P12n~ P12n+1' P12n+2 and P12n+3- A
error correcting block including the second check words and consisting o~ 32 words is listed herea~ter. Note that a delay by jD in a coding channel will decrcase the value o~ the index of W by an amount of 12.j.D:
12n-12,A ; W12n-12(D~1),B;
12n+1-12(2D+1),A; 1r12n+1-12(3D~1),B;
12n+4-12(4D+1),A; 12n+4-12(5D+1), B;
W12n+5-12(6D+1),A; ...
12n+9-12(10D+1), A; W12n~9-12(11D~1), B;
Q12n-12(12D); Q12n+1-12(13D); Q12n+2-12(14D); Q12n+3-12(15D~
1 ~ ~33~ ~
pHQ.so-oog 15 10.3.81 W12n~2-12(16D) ;
12n~ 12(26D); 12n~11-12(27D);
12n; P12n+1; 12n~2; 12n+3 An interleaver 11 is provided which includes delay lines providing 1 word delay period for the even order transmission channels of 32 data series including the first and second check words, and also inverters 12, 13, 14 and 15 are provided for -the second check word series. The interleaver 11 serves to avoid such a defec-t that a burst error interval which during transmission would cross the boundarybetween adjacent blocks would also be ap-t to in~luence so many words in an error correct-ing block that the correction thereof would be rendered impossible, The inverters 12, 13, 14 and 15 serve to avoid such an erroneous operation that all the data in one block are made ~0" by a drop-out during transmission and this is discriminated correct in the raproducing ; system, for example, as an interval of silence in the audio representation. Such silence interval would there-fore yield a second check word series di~erent from zero.
The finall~ produced code words are listed in the last column of the ~igure inclusive of there respective delays now incurred.
The finally produced block of 24 PCM data words and 8 check words is serialized by a parallel to ~erial converter not shown. A synchronizing signal of 16 bits is added at the beginning thereof to form one transmission block as shown in Fig. 2 and then the block thus made is transmitted. In Fig. 2, for the sake of brevity, a word derived from the i'th transmission channel is shown as u Practical examples of the transmission system, may be magnetic recording and reproducing apparatus, rotary disc apparatus and so on.
~ ~ ~33~1 ~
,, PHQ.80-009 16 10.3.81 The above coder 8 relates to the above-mentioned error correcting code wherein the values o~ -the ~ived code parameters are m = 8, n = 28 and k = 4. For the encoder 10 the corresponding ~ixed code parameters have the values m = 8, n = 32 and k = 4. Thus the complete block o~ Fig. 2 comprises 32 x 8 + 16 = 272 bi-ts.
At the decoding station, ~irst -the synchroni-zation header is removed by a device not shown. The remaining reproduced 32 code words of each transmission block , are applied to the input o~ an error correcting decoder shown in Fig. 3. Due to the reproducing process there is a possibility that the reproduced data contain an error. I~ there is no error~ 32 words ~ed to the input o~ the decoder are identical to the 32 words that had appeared at the output o~ the error correc-ting encoder. At the error correcting decoder, the de-inter-leave process complementing the interleave process at the encoder is per~ormed to return the order of the data to the original order and then the error correcting process is carried out.
At first, as shown in Fig. 3, a de-interleaver 16 is provided in which delay lines, each having a delay period o~ 1 word, are provided ~or the odd order trans-mission channels and inverters 17, 18, 19 and 20 areprovided ~or the second check word series. The outputs ~rom the de-interleaver 16 and inverters 17 -to 20 are ~ed to a ~irst decoder 21. At this decoder 21, syndromes S11, S12, S13 and S14 are generated from a parity detection matrix HC1 and inpu-t 32 words V- as shown in Fig. 4, and the above-mentioned error correction is per~ormed based upon the syndromes. In Fig. 4, ~ is an element o~ GF(2 ), being a root o~ -the primitive and irreducible polynominal o~ degree m, F(x) = x ~x ~x3+x +1. From the decoder 21 24 PCM data series and 4 check word series are derived.
At every word o~ the data series, a pointer (at least 1 bit) is added which shows whether or not there is an error. The pointer bit or bits are transported in similar i ~33~ 3 PHQ. 80-oog 17 10.3.81 way as the further bits of data words and check words.
The output da-ta series from the decoder 21 are fed to a de-:interleaver 22 which serves to cancel the effects of delay process performed by the interleaver 9 in the error correcting encoder and in which delay lines with different delay periods of 27D, 26D, 25~, --- 2D
and 1D are provided for the 1st to 27th transmission channels. The output f`rom the de-interleaver 22 is fed to a second decoder 23 in which syndromes S21, S22, S23 and S24 are generated from a parity detection matrix ~I 2 and input 28 words V as shown in Fig. 5 and the above-mentioned error correction is carried out based upon -the syndromes. In the decoder 23, the pointer relating to a word whose error is corrected is erased, but the pointer relating to a word whose error cannot be corrected by the decoder 23 is not erased.
The data series appearing at the output of the decoder 23 are fed to an even and odd de-interleaver 24, in which the PCM data series consisting of the even order words and the PCM data series consisting of the odd order words are re-arranged such that they are positioned at the alternative transmission channels and delay lines of 1 word delay amount that are provided for the PCM data series consisting of the odd order words. At the output of the even and odd de-interleaver 24, the PCM data series which have the arrangement and predetermined order transmission channels entirely the same as those fed to the input o~ the error correcting encoder are obtained.
Though not shown in Fig. 3, a correcting circuit is provided at the next stage of the even and odd de-inter-leavsr 24 to carry out a correction, for example, mean value interpolation so that the error, which is not corrected by the decoders 21 and 23 is made inconspicuous.
In the error correcting decoder shown in ~ig. 3, the error correction using the ~irst check words P12, P12n+1' P12n+2 and P12n~3 and the error correc-tion using the second check words Q12n~ Q12n+l~ Q12n~2 12n+3 3 ~ ~
PHQ.80-oo9 18 10.3.81 are respectively carried out one -ti~le. I~ the above error corrections are respectively carried out more than twice, the error correcting capability is increased and ~ewer errors remain uncorrected.
In the embodiment described the delay intervals in interleaver 9 differ by each time an amount D in successive channels, but it is possible to employ an irregular variation in delay amount other than the above regular sequence. Further, similar to the second chec~ words Pi which are calculated by using not only the PC~I data but also the first check words Qi' also the first check words Qi may be codetermined by the second check words Pi. This may be e~ected by ~eeding back the second check words to an input o~ the coder producing the ~irst chec~ words.
The error correction code described hereabove may correct, for example, up to two word errors without using the pointer showing the error position, and a burst error is dispersed by the cross-interleave, so that both the random errors and burst errors can be ef~ectively corrected.
Furthermore, as -the number o~ correctable error words increases, the decoding algorithm becomes more complicated. When only 1 word error is correctable, a very simple construction of the decoder is enough. Accor-dingly, it becomes clear that error correcting decoders having respective correcting abilities ~rom low error correcting ability to high error correcting ability or may be constructed.
The apparatus and method as shown and explained herebefore may be modi~ied in several ways that may o~er speci~ic ad~antages:
a) In Fig. 1 the parity words Q(12n), Q(12n+1), Q(12n+2)~ Q(12n+3) may be inverted in the same way as parity words P(12n) through P(12n~3); however, the encoder 10 would still receive the non-inverted parity words Q(12n) through Q(12n~3). In corresponding manner, ~ ~3~
PHQ. 80-oog 19 10. 3, 81 the decoder o~ Fig. 3 would receive the inverted parity _ _ , . = . .
12n_12(12D) ... through Q12n+3 -l2(15D 1)- These would be re-inverted again before entering decoder (21).
b) In Fig. 4 the second row may be changed from 32 31 3 ~2 ~) into ( ~31,~X3 , ..., ~ , ~ 1, 1~. In Fig. 5, in correspondlng manner,the second row may be changed from ( ~ , ~27, . . ~ 3, ( 27 ~26 ~2 ~1, 1). Furthermore in both Figs. 4, 5 the matrix in ~ may have front side and back side reversed. In that way, the second through fourth rows would start with low powers of ~ and end with high powers of ~ .
c) The apparatus and method may advantageously be used in a high-fidelity system. The encoding is executed first. The data may be stored on an audio disc, audio -tape, or the like. Alternatively, or in combination therewith, the data may be transmitted via a communication channel, or broadcasted. At a receiving end, the decoding method and apparatus are operated, and possible errors are corrected. Finally, high-fidelity amplification and reproduction are effected.
Figs. 6, 7 show a block diagram of a second encoder and second decoder, respectively. The main difference between Fig. 1 and Fig. 6 lies in interleavcr 30, which now has respective dela~s over two word inter-vals as indicated by the numerals "2". Furthermore, the cyclic transposition of the coding channels is different.
- At the input side, each time two channels are rearranged together, while after 8 channels a next cycle is started.
Thus three cycles of 8 channels are presen~. At the output side, after 6 channels a new cycle is started. Thus, four cycles of 6 channels each are present. A second difference occurs relative to encoder 32, which .s situated in the middle between the two groups of code channels. In this way the number of crossings is dimi-nished: ele~ent 34 now comprises delay elements only.
For example D = 6 word in-tervals. Delay element 38 has ~ 1~33~ ~
PHQ.80-Oo9 20 10.3.81 delay introduced in the odd channels as in contradistinc-tion to Fig. 1. Finally, all check words are inverted.
Fig. 7 again ~ollows directly ~rom the arrangement o~
Fig. 6.
Flgs. 8, 9 show a block diagram o~ a third encoder and third decoder, respectively. Fig. 8 is identical to Fig. 6, except for the interleaver 40. Here, the ~irst six channels are delayed by two word intervals, and also the third group o~ six channels is delayed by two word intervals. The other coding channels are not delaye-d in interleaver 40. Furthermore, the transposition of the coding channels is dif~erent. At the input side, each time two channels are rearranged together, while the next cycle is only started a~ter twelve coding channels.
Thus two cycles of twelve channels are present.
At the output side, a~ter ~our channels a new i cycle is started. Thus 9 SiX cycles of ~our channe~s are present. Again the arrangement o~ Fig. 9 ~ollows directly from the arrangement of Fig. 8.
Figs. 10 , 11 show a block diagram o~ a fourth encoder and fourth decoder, respectively. Fig. 10 is identical to Fig. 8, exc~pt ~or the interleaver 42. Here~
the coding channels are distributed over three groups.
The coding channels o~ the first group are not delayed in the interleaver 42. The channels of the second group ` comprise a delay element over one word interval. The coding channels o~ the third group comprise a delay element over two word intervals. No rearrangement o~ the channels is executed. Again the arrangement o~ Fig. 11 follows directly ~rom the arrangement o~ Fig. 10.
In this way changing between Figs. 7, 9, 11 or 6, 8, 10 requires only the modification of a part o~ the arrangement. In this respect, Figs. 6/7 show an arrange-ment that is m~t suitable ~or use with two audio channels (stereophonic use), Figs. 8/9 show an arrangement that is most suitable for use with three audio channels and Figs. 10/11 show an arrangement that is most suitable i lB~34 l PHQ.80-009 21 10.3.81 for use with four audio channels (quadrophonic use). In each of these cases, the interpolation of irrecovered audio signals betwe~n correct audio signals offers an advantageous remedy.
S1 = ei + ej + ek S2 = T ei + Tiej + T ek S3 = T2iei + T2iej + T2k k ~S4 = T ei + T3iej ~ T3kek The above equations can be modified as follows-T S1 + S2 = (T + T )ei + (Ti + T ) e T S2 + S3 = T (Ti ~ Tk)ei + Ti (Ti ~ Tk) e T S3 ~ S4 = T2i(Ti ~ Tk)ei ~ T2i (Ti k) ) ~334~
PHQ.8o-oo9 11 10.3.81 Accordingly, i~ the ~ollowing equation is established, 3 word errors can be discriminated since the condi-tions $1 ~ ' S2 ~ ~ S3 ~ 0 are satis~ied.
Tj(T S1~S2)~(T S2-~S3) = T~ (T S2 -~ S3) + (T S3 ~ S4) The respective error patterns at -this time are expressed as f`ollows:
rei = 1_ ( + T )-S2 ( 1~Ti j)( l~-Ti-k) 1 + (T + T i) S ~ T-k-iS
ej = ~ 3 (1~TJ i) (~,~,Tj_ 1 ~ (T ~ T i)S ~ T-i-ek = ----- (1+Tk-i) (1 ~- Tk-i) As described above, all 3-word errors can be corrected without using the pointer.
If the pointer is used and error positions (i, j, k, l) are known thereby, 4 word errors can also be corrected.
Further, i~ the number k o~ the check words is increased, the error correcting ability can be improved even further.
Now, an example of the present invention will be described with re~erence to the a-t-tached drawing in which the invention is applied to the recording and reproducing o~ an audio PCM signal.
Fig. 1 shows, as a whole, an error correcting encoder provided in the recording system whose input side is supplied with an audio PCM signal. The audio PCM signal is provided in such a manner that left and right stereo signals are respectively sampled at a sampling ~requency fs (for example 7 44.1 k~Iz) and each sampled value is con-verted into a sixteen-bit number expressed in two's complement notation. Accordinglv, the left audio channel provides a string of 16-bits PCM data (L0, L1, L2 ...) and ~ ~633A~1 PHQ.80-009 12 10.3.81 the right audio channel provides a further s-tring o~
16-bits PCM data (R0, R1, R2 ...). The PCM data of the left and right audio channels are each multiplexed-by-word by a device not shown, cyclically over a respective plurality of six encoding channels. Therefor~, -totally 12 channels of PCM data series are input to the error correcting encoder. At a given or predetermined ins-tant, e.g. 12 numbers such as L , R L R L
6n 6n9 6n+1' 6n+l' 6n+2' 6n+2' 6n+3' 6n-~3' 6n~4' R6n+4' L6n+5' R6n+5 are iIlput~
In the example each 16-bit number is divided into eight more significant bits and eight less signi~icant bits.
These eight-bit groups will be called "words" herein-after. Consequently, the twelve numbers are processed ;~ 15 according to twenty-four parallel channels. Now, one 16-bit number of the PCM data series is indicated as Wi, its upper 8 bits are expressed as Wii A and its lower bits are expressed as Wi B respectively. For example, the number L6n is divided into two words W12n A and W12n B.
Note also the earlier use of n as a di~ension of the ; matrixes H.
The PC~I data series of 24 channels are firstly fed to an even and odd interleaver 1. If n = 0, 1, 2, ---~the words L6n (i-e- W12n~ A and W12n,B)' 6n ( 25 12n+1,A 12n+1~B)' 6n+2 (i.e. ~12n+4,A a~ W12n~4 B)' 6n+2 12n~5,A and W12n~5 B)~ L6 4 (i-e~ W
and W 8 B) and R6n+~ e- W12n~9~A 12n+9,B
constitute the even order words, while the other words likewise are odd order words. The PCM data series consisting of even order words are respectively delayed through respective delay circuits or delay lines 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A and 7B of the even and odd in-terleaver 1 by a one word interval. ~urther, in the even and odd interleaver 1 such a conversion is carried out that 12 data series consisting of even order words occupy 1st to 12th transmission channels and 12 data series consisting of odd order words occupy 13th -to 24th transmission channels, respectively.
J l~33~
PHQ.80-oo9 13 10.3.81 The even and odd interleaver 1 serves to avoid the situation 1~herein more than two adjacent numbers o~
any (left or right) audio channel would be erroneous and the errors would then be incorrectable. This can be under-stood as ~ollows. Three adjacent numbers Li 1~ Li, Li+1will be considered b~ wa~ of` example. Irhere the number Li is erroneous and non-correctable~ the number Li 1 or Li+1, or both, should be correct. In this way, the erroneous number Li may be restored by replacing it by lO the directly preceding number Li 1 or by the directly following number Li~1 or by the average value o~ Li 1 and Li+1. In many instances this provides an acceptable approximation o~ -the "true" value o~ Li. The dela~v lines 2A, 2B ... 7A, 7B o~ the even and odd interleaver 1 are 15 provided for adjacent ~ords to be contained in di~eren-t error correcting blocks. Further, the reason wh~v the transmission channels for each o~ the data series consisting of the even order words and the data series consis-ting o~
; odd order words are gathered is that when the data series 20 are interleaved, the distance between the recording positions o~ the adjacent even and odd order words are selected as ~ar apart as possible.
At the output of the even and odd interleaver 1, the PCM data series o~ 24 channels appear in a first 25 arranging state. The words that have been delayed by a one word interval have been indicated by an index that is twelve points lower at the output of interleaver 1.
From the respective PCM data series, each time ~our ~irst d Q12n~ Q12n*1~ Q12n~2~ Q12n~3 are de iv d m 30 an error correcting block o~ data words. Thi.s error correcting block there~ore comprises the words:
(W12n-12,A; W12n-12,13; W12n~1-12,A; W12n+1-12,B;
12n~4-12,A; 12n+4-12,B; 12n~5-12,A; 12n+5-12,B;
12n+8-12,A; 12n~8-12,B; 12n+9-12,A; 12n+9-12,B;
12n+2,A; 12n~2,B; 12n~3,A; 12n+3,B; 12n~6,A;
12n+6,B; 12n+7,A; 12n~7,B; W12n+10,A; 12n+10,B;
` ~ ~6334~
PHQo 80-009 14 10~ 3~ 81 12n~ A; W12n+11,B; Q12n; Q12n+l~ Q12n+2 Ql2rl~3)-In the ~irst coder ~ therefore, twenty-~our data words of 8 bits each are encoded to yield four check words. Conse-quently, the ~ixed parameter values of the code used here - are n = 28, m = 8, k = 4.
24 PCM data series and 4 check word series are ~ed to a second interleaver 9. ~n this in-terleaver 9, the positions ofthe transmission channels are changed such that the check word series are located between the PCM data series consisting o~ the even order words and the PCM data series consis-ting of the odd order words t ; and thereafter the delay pracess for this interleaving is performed, This delay process is such that 27 trans-mission channels except the first transmission channel are delayed by delay lines with delay amounts of lD, 2D, 3D, 4D, --- 26D and 27D (where D is a unit delay amount), respectively.
At the output o~ the interleaver 9 28 data series in a second arranging state appear. From the respective data series, the data words are derived one ~y one. Then, the words are fed to a coder 10 which then produces ` second check words P12n~ P12n+1' P12n+2 and P12n+3- A
error correcting block including the second check words and consisting o~ 32 words is listed herea~ter. Note that a delay by jD in a coding channel will decrcase the value o~ the index of W by an amount of 12.j.D:
12n-12,A ; W12n-12(D~1),B;
12n+1-12(2D+1),A; 1r12n+1-12(3D~1),B;
12n+4-12(4D+1),A; 12n+4-12(5D+1), B;
W12n+5-12(6D+1),A; ...
12n+9-12(10D+1), A; W12n~9-12(11D~1), B;
Q12n-12(12D); Q12n+1-12(13D); Q12n+2-12(14D); Q12n+3-12(15D~
1 ~ ~33~ ~
pHQ.so-oog 15 10.3.81 W12n~2-12(16D) ;
12n~ 12(26D); 12n~11-12(27D);
12n; P12n+1; 12n~2; 12n+3 An interleaver 11 is provided which includes delay lines providing 1 word delay period for the even order transmission channels of 32 data series including the first and second check words, and also inverters 12, 13, 14 and 15 are provided for -the second check word series. The interleaver 11 serves to avoid such a defec-t that a burst error interval which during transmission would cross the boundarybetween adjacent blocks would also be ap-t to in~luence so many words in an error correct-ing block that the correction thereof would be rendered impossible, The inverters 12, 13, 14 and 15 serve to avoid such an erroneous operation that all the data in one block are made ~0" by a drop-out during transmission and this is discriminated correct in the raproducing ; system, for example, as an interval of silence in the audio representation. Such silence interval would there-fore yield a second check word series di~erent from zero.
The finall~ produced code words are listed in the last column of the ~igure inclusive of there respective delays now incurred.
The finally produced block of 24 PCM data words and 8 check words is serialized by a parallel to ~erial converter not shown. A synchronizing signal of 16 bits is added at the beginning thereof to form one transmission block as shown in Fig. 2 and then the block thus made is transmitted. In Fig. 2, for the sake of brevity, a word derived from the i'th transmission channel is shown as u Practical examples of the transmission system, may be magnetic recording and reproducing apparatus, rotary disc apparatus and so on.
~ ~ ~33~1 ~
,, PHQ.80-009 16 10.3.81 The above coder 8 relates to the above-mentioned error correcting code wherein the values o~ -the ~ived code parameters are m = 8, n = 28 and k = 4. For the encoder 10 the corresponding ~ixed code parameters have the values m = 8, n = 32 and k = 4. Thus the complete block o~ Fig. 2 comprises 32 x 8 + 16 = 272 bi-ts.
At the decoding station, ~irst -the synchroni-zation header is removed by a device not shown. The remaining reproduced 32 code words of each transmission block , are applied to the input o~ an error correcting decoder shown in Fig. 3. Due to the reproducing process there is a possibility that the reproduced data contain an error. I~ there is no error~ 32 words ~ed to the input o~ the decoder are identical to the 32 words that had appeared at the output o~ the error correc-ting encoder. At the error correcting decoder, the de-inter-leave process complementing the interleave process at the encoder is per~ormed to return the order of the data to the original order and then the error correcting process is carried out.
At first, as shown in Fig. 3, a de-interleaver 16 is provided in which delay lines, each having a delay period o~ 1 word, are provided ~or the odd order trans-mission channels and inverters 17, 18, 19 and 20 areprovided ~or the second check word series. The outputs ~rom the de-interleaver 16 and inverters 17 -to 20 are ~ed to a ~irst decoder 21. At this decoder 21, syndromes S11, S12, S13 and S14 are generated from a parity detection matrix HC1 and inpu-t 32 words V- as shown in Fig. 4, and the above-mentioned error correction is per~ormed based upon the syndromes. In Fig. 4, ~ is an element o~ GF(2 ), being a root o~ -the primitive and irreducible polynominal o~ degree m, F(x) = x ~x ~x3+x +1. From the decoder 21 24 PCM data series and 4 check word series are derived.
At every word o~ the data series, a pointer (at least 1 bit) is added which shows whether or not there is an error. The pointer bit or bits are transported in similar i ~33~ 3 PHQ. 80-oog 17 10.3.81 way as the further bits of data words and check words.
The output da-ta series from the decoder 21 are fed to a de-:interleaver 22 which serves to cancel the effects of delay process performed by the interleaver 9 in the error correcting encoder and in which delay lines with different delay periods of 27D, 26D, 25~, --- 2D
and 1D are provided for the 1st to 27th transmission channels. The output f`rom the de-interleaver 22 is fed to a second decoder 23 in which syndromes S21, S22, S23 and S24 are generated from a parity detection matrix ~I 2 and input 28 words V as shown in Fig. 5 and the above-mentioned error correction is carried out based upon -the syndromes. In the decoder 23, the pointer relating to a word whose error is corrected is erased, but the pointer relating to a word whose error cannot be corrected by the decoder 23 is not erased.
The data series appearing at the output of the decoder 23 are fed to an even and odd de-interleaver 24, in which the PCM data series consisting of the even order words and the PCM data series consisting of the odd order words are re-arranged such that they are positioned at the alternative transmission channels and delay lines of 1 word delay amount that are provided for the PCM data series consisting of the odd order words. At the output of the even and odd de-interleaver 24, the PCM data series which have the arrangement and predetermined order transmission channels entirely the same as those fed to the input o~ the error correcting encoder are obtained.
Though not shown in Fig. 3, a correcting circuit is provided at the next stage of the even and odd de-inter-leavsr 24 to carry out a correction, for example, mean value interpolation so that the error, which is not corrected by the decoders 21 and 23 is made inconspicuous.
In the error correcting decoder shown in ~ig. 3, the error correction using the ~irst check words P12, P12n+1' P12n+2 and P12n~3 and the error correc-tion using the second check words Q12n~ Q12n+l~ Q12n~2 12n+3 3 ~ ~
PHQ.80-oo9 18 10.3.81 are respectively carried out one -ti~le. I~ the above error corrections are respectively carried out more than twice, the error correcting capability is increased and ~ewer errors remain uncorrected.
In the embodiment described the delay intervals in interleaver 9 differ by each time an amount D in successive channels, but it is possible to employ an irregular variation in delay amount other than the above regular sequence. Further, similar to the second chec~ words Pi which are calculated by using not only the PC~I data but also the first check words Qi' also the first check words Qi may be codetermined by the second check words Pi. This may be e~ected by ~eeding back the second check words to an input o~ the coder producing the ~irst chec~ words.
The error correction code described hereabove may correct, for example, up to two word errors without using the pointer showing the error position, and a burst error is dispersed by the cross-interleave, so that both the random errors and burst errors can be ef~ectively corrected.
Furthermore, as -the number o~ correctable error words increases, the decoding algorithm becomes more complicated. When only 1 word error is correctable, a very simple construction of the decoder is enough. Accor-dingly, it becomes clear that error correcting decoders having respective correcting abilities ~rom low error correcting ability to high error correcting ability or may be constructed.
The apparatus and method as shown and explained herebefore may be modi~ied in several ways that may o~er speci~ic ad~antages:
a) In Fig. 1 the parity words Q(12n), Q(12n+1), Q(12n+2)~ Q(12n+3) may be inverted in the same way as parity words P(12n) through P(12n~3); however, the encoder 10 would still receive the non-inverted parity words Q(12n) through Q(12n~3). In corresponding manner, ~ ~3~
PHQ. 80-oog 19 10. 3, 81 the decoder o~ Fig. 3 would receive the inverted parity _ _ , . = . .
12n_12(12D) ... through Q12n+3 -l2(15D 1)- These would be re-inverted again before entering decoder (21).
b) In Fig. 4 the second row may be changed from 32 31 3 ~2 ~) into ( ~31,~X3 , ..., ~ , ~ 1, 1~. In Fig. 5, in correspondlng manner,the second row may be changed from ( ~ , ~27, . . ~ 3, ( 27 ~26 ~2 ~1, 1). Furthermore in both Figs. 4, 5 the matrix in ~ may have front side and back side reversed. In that way, the second through fourth rows would start with low powers of ~ and end with high powers of ~ .
c) The apparatus and method may advantageously be used in a high-fidelity system. The encoding is executed first. The data may be stored on an audio disc, audio -tape, or the like. Alternatively, or in combination therewith, the data may be transmitted via a communication channel, or broadcasted. At a receiving end, the decoding method and apparatus are operated, and possible errors are corrected. Finally, high-fidelity amplification and reproduction are effected.
Figs. 6, 7 show a block diagram of a second encoder and second decoder, respectively. The main difference between Fig. 1 and Fig. 6 lies in interleavcr 30, which now has respective dela~s over two word inter-vals as indicated by the numerals "2". Furthermore, the cyclic transposition of the coding channels is different.
- At the input side, each time two channels are rearranged together, while after 8 channels a next cycle is started.
Thus three cycles of 8 channels are presen~. At the output side, after 6 channels a new cycle is started. Thus, four cycles of 6 channels each are present. A second difference occurs relative to encoder 32, which .s situated in the middle between the two groups of code channels. In this way the number of crossings is dimi-nished: ele~ent 34 now comprises delay elements only.
For example D = 6 word in-tervals. Delay element 38 has ~ 1~33~ ~
PHQ.80-Oo9 20 10.3.81 delay introduced in the odd channels as in contradistinc-tion to Fig. 1. Finally, all check words are inverted.
Fig. 7 again ~ollows directly ~rom the arrangement o~
Fig. 6.
Flgs. 8, 9 show a block diagram o~ a third encoder and third decoder, respectively. Fig. 8 is identical to Fig. 6, except for the interleaver 40. Here, the ~irst six channels are delayed by two word intervals, and also the third group o~ six channels is delayed by two word intervals. The other coding channels are not delaye-d in interleaver 40. Furthermore, the transposition of the coding channels is dif~erent. At the input side, each time two channels are rearranged together, while the next cycle is only started a~ter twelve coding channels.
Thus two cycles of twelve channels are present.
At the output side, a~ter ~our channels a new i cycle is started. Thus 9 SiX cycles of ~our channe~s are present. Again the arrangement o~ Fig. 9 ~ollows directly from the arrangement of Fig. 8.
Figs. 10 , 11 show a block diagram o~ a fourth encoder and fourth decoder, respectively. Fig. 10 is identical to Fig. 8, exc~pt ~or the interleaver 42. Here~
the coding channels are distributed over three groups.
The coding channels o~ the first group are not delayed in the interleaver 42. The channels of the second group ` comprise a delay element over one word interval. The coding channels o~ the third group comprise a delay element over two word intervals. No rearrangement o~ the channels is executed. Again the arrangement o~ Fig. 11 follows directly ~rom the arrangement o~ Fig. 10.
In this way changing between Figs. 7, 9, 11 or 6, 8, 10 requires only the modification of a part o~ the arrangement. In this respect, Figs. 6/7 show an arrange-ment that is m~t suitable ~or use with two audio channels (stereophonic use), Figs. 8/9 show an arrangement that is most suitable for use with three audio channels and Figs. 10/11 show an arrangement that is most suitable i lB~34 l PHQ.80-009 21 10.3.81 for use with four audio channels (quadrophonic use). In each of these cases, the interpolation of irrecovered audio signals betwe~n correct audio signals offers an advantageous remedy.
Claims (16)
1. An error correctable data transmission method in serially transmitted data words accompanied by parity words, wherein the parity words have been added to the data words according to the following method steps:
a. receiving a data stream by receiving each time one data word of a data word series on each of a first plurality of parallel channels according to a first arranging state, b. applying one word on each of said first plurality of parallel channels to a first error correcting coder to gen-erate on the basis of a first generator matrix (G1) a first check word series, c. delaying said first check word series and the words of said data word series, after application to said first error correcting coder by mutually different delay times to con-vert them to a second arranging state, d. applying one word on each of said first plurality of channels and said first check word series in said second arranging state to a second error correcting coder to gener-ate a second check word series on the basis of a second generator matrix (G2), e. outputting each time one data word on each of a plurality of output channels equal to said first plurality and the respective check words of first check word series and said check word series each on one of a second plurality of output channels, wherein in the first and the second error correct-ing coder each word consists of m bits and the series of check words generated in any coder completes the error cor-recting block to a respective amount of n words, wherein n ? 2m-1, f. the wordwise parallel to serial conversion for transmitting the data words and check words, by means of a medium having at least a predetermined global relaxation time, which error correctable data transmission method is charac-terized in that at the receiving side after wordwise serial to parallel conversion to a number of parallel channels equal PHQ. 80.009 23 to the sum of said first and second pluralities, for recon-struction the said second arrangement, the following method steps are executed:
g. the reproduction or correcting reproduction, respectively, according to a parity check matrix (H2) which is defined by (G2)x(H2)=0 of a number of data words equal to said first plurality and a number of check words equal to the number of said first series, h. the delaying of the reproduced data words and check words by mutually different delay times to reconstruct the said first arranging state, i. the reproduction or correcting reproduction, respectively according to a parity check matrix (H1), which is defined by (G1)x(H1)=0 of a number of data words equal to said first plurality, j. the outputting of the reproduced data words, wherein the parity check matrices are shaped according to or wherein ? is a root of F(x) = 0, F(x) being an irreducible and primitive polynomial of degree n over a Galois Field GF(2).
a. receiving a data stream by receiving each time one data word of a data word series on each of a first plurality of parallel channels according to a first arranging state, b. applying one word on each of said first plurality of parallel channels to a first error correcting coder to gen-erate on the basis of a first generator matrix (G1) a first check word series, c. delaying said first check word series and the words of said data word series, after application to said first error correcting coder by mutually different delay times to con-vert them to a second arranging state, d. applying one word on each of said first plurality of channels and said first check word series in said second arranging state to a second error correcting coder to gener-ate a second check word series on the basis of a second generator matrix (G2), e. outputting each time one data word on each of a plurality of output channels equal to said first plurality and the respective check words of first check word series and said check word series each on one of a second plurality of output channels, wherein in the first and the second error correct-ing coder each word consists of m bits and the series of check words generated in any coder completes the error cor-recting block to a respective amount of n words, wherein n ? 2m-1, f. the wordwise parallel to serial conversion for transmitting the data words and check words, by means of a medium having at least a predetermined global relaxation time, which error correctable data transmission method is charac-terized in that at the receiving side after wordwise serial to parallel conversion to a number of parallel channels equal PHQ. 80.009 23 to the sum of said first and second pluralities, for recon-struction the said second arrangement, the following method steps are executed:
g. the reproduction or correcting reproduction, respectively, according to a parity check matrix (H2) which is defined by (G2)x(H2)=0 of a number of data words equal to said first plurality and a number of check words equal to the number of said first series, h. the delaying of the reproduced data words and check words by mutually different delay times to reconstruct the said first arranging state, i. the reproduction or correcting reproduction, respectively according to a parity check matrix (H1), which is defined by (G1)x(H1)=0 of a number of data words equal to said first plurality, j. the outputting of the reproduced data words, wherein the parity check matrices are shaped according to or wherein ? is a root of F(x) = 0, F(x) being an irreducible and primitive polynomial of degree n over a Galois Field GF(2).
2. A method as claimed in Claim 1, characterized in that after transmission the second check word series is rein-verted.
3. A method as claimed in Claim 1, characterized in that after retransmission the first check word series is PHQ. 80.009 24 reinverted.
4. A method as claimed in Claim 1, characterized in that in step h. a first group of the first plurality of data words is given delays in a first set of delay time values (OD-11D), in that the first check word series is given delays in a second set of delay time values (12D-15D), in that a second group of data words equal in number to the first group is given delays in a third set of delay time values (16D-27D), wherein each element of the third set has a value that is larger than the value of each element of the second set and each element of the second set has a value that is larger than the value of each element of the first set.
5. A method as claimed in Claim 1, characterized in that after the reproduction by means of the matrix (H1) mutually equal, relative delays over a predetermined number of word intervals are introduced between the odd-numbered data words and the even numbered data words.
6. A method as claimed in Claim 1, characterized in that after transmission mutually equal, relative delays over a predetermined number of word intervals are introduced between the words entered into the even channels and those introduced into the odd channels.
7. Encoder use with an error correcting data transmis-sion method as claimed in Claim 1, comprising:
a. input means for receiving a serial data stream and for recurrently multiplexing the words of said data stream over said first plurality of parallel channels;
b. a first encoder means for recurrently generating a first check word series associated with a plurality of data words equal to said first plurality by means of implementing said first generator matrix;
c. delay means fed by said first encoder means for producing said second arranging state;
d. a second encoder means for recurrently generating a second check word series associated with a plurality of data words equal to said first plurality and a plurality of check word series equal to the number in said first check word series by means of implementing said second generator matrix;
PHQ. 80.009 25 e. output means for outputting in parallel a second plur-ality of data words and check words.
a. input means for receiving a serial data stream and for recurrently multiplexing the words of said data stream over said first plurality of parallel channels;
b. a first encoder means for recurrently generating a first check word series associated with a plurality of data words equal to said first plurality by means of implementing said first generator matrix;
c. delay means fed by said first encoder means for producing said second arranging state;
d. a second encoder means for recurrently generating a second check word series associated with a plurality of data words equal to said first plurality and a plurality of check word series equal to the number in said first check word series by means of implementing said second generator matrix;
PHQ. 80.009 25 e. output means for outputting in parallel a second plur-ality of data words and check words.
8. An apparatus comprising an encoder as claimed in Claim 7 furthermore comprising a parallel to serial recon-verting means fed by said output means and an output ampli-fier fed by said parallel to serial reconverting means.
9. Decoder for use with an error correctable data transmission method as claimed in Claim 1, characterized in that the decoder comprises the following elements:
a. input means for recurrently receiving a series of data words in a number of input channels equal to said first plurality and in parallel therewith in a number of input channels equal to said second plurality of a first check word series and a second check word series, b. a first decoder for the reproduction of each time a first plurality of data words and a first check word series by means of a first syndrome quantity generated therein, c. delay means for realigning the data words and the first check word series by means of mutually different delay times, d. a second decoder for the reproduction of each time a first plurality of data words by means of a second syndrome quantity generated therein, e. output means for outputting each time a data word of a data word series in a number of output channels equal to said first plurality, wherein a data word series represents a data stream.
a. input means for recurrently receiving a series of data words in a number of input channels equal to said first plurality and in parallel therewith in a number of input channels equal to said second plurality of a first check word series and a second check word series, b. a first decoder for the reproduction of each time a first plurality of data words and a first check word series by means of a first syndrome quantity generated therein, c. delay means for realigning the data words and the first check word series by means of mutually different delay times, d. a second decoder for the reproduction of each time a first plurality of data words by means of a second syndrome quantity generated therein, e. output means for outputting each time a data word of a data word series in a number of output channels equal to said first plurality, wherein a data word series represents a data stream.
10. Decoder as claimed in Claim 9, characterized in that said input means comprise reinverting means responsive to inverted check words received.
11. Decoder as claimed in Claim 9, characterized in that said input means comprise second delaying means for compensating the relative delays incurred between even data channels and odd data channels.
12. Decoder as claimed in Claim 9, characterized in that said outputs means comprise third delaying means for compensating the relative delays incurred between even data words and odd data words.
13. An apparatus comprising a decoder as claimed in PHQ. 80.009 26 Claim 9, characterized in that said apparatus furthermore comprises means for accommodating a drivable audio disc, pick-up means for interrogating said audio disc, serial to parallel converting means having an input connected to said pick-up means for therefrom receiving a serial data stream and a plurality of outputs each connected to a respective channel of said input means, and parallel to serial reconverting means having a plurality of parallel inputs each connected to a respective data word channel of said output means, and furthermore digital to analog conversion means for converting a serial data stream to a continuous audio signal.
14. An apparatus comprising a decoder as claimed in Claim 9, characterized in that said apparatus furthermore comprises means for accommodating a drivable storage disc, pick-up means for interrogating said storage disc, serial to parallel converting means having an input connected to said pick-up means for therefrom receiving a serial data stream and a plurality of outputs each connected to a respective channel of said input means, and parallel to serial recon-verting means having a plurality of parallel inputs each con-nected to a respective data word channel of said output means.
15. A data carrier for cooperating with a decoder as claimed in Claim 9, or with an apparatus as claimed in Claim 13 or 14 wherein the data carrier comprises a sequence of blocks, each block comprising a sequence of a third plurality (U1-U12), equal to one half said first plurality, of words derived from even data words of said data word series, a fourth plurality of words derived from said first check word series (U13-U16), and a further third plurality of words derived from odd data words of said data word series (U17-U24) and a further fourth plurality of words derived from said second check word series (U20-U32).
16. A data carrier for cooperating with a decoder as claimed in Claim 9, or with an apparatus as claimed in Claim 13 or 14 wherein the data carrier comprises a sequence of blocks, each block comprising a sequence of a third plur-ality (U1-U12), equal to one half said first plurality, of words derived from even data words of said data word series, PHQ. 80.009 27 a fourth plurality of words derived from said first check word series (U13-U16), and a further third plurality of words derived from odd data words of said data word series (U17-U24) and a further fourth plurality of words derived from said second check word series (U20-U32), and wherein said block furthermore comprises a synchronization header (SYNC).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6760880A JPS574629A (en) | 1980-05-21 | 1980-05-21 | Data transmitting method capable of correction of error |
| JP67608-80 | 1980-05-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1163341A true CA1163341A (en) | 1984-03-06 |
Family
ID=13349812
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000377619A Expired CA1163341A (en) | 1980-05-21 | 1981-05-14 | Error-correcting data transmission system |
Country Status (30)
| Country | Link |
|---|---|
| US (1) | US4413340A (en) |
| JP (1) | JPS574629A (en) |
| KR (1) | KR850001023B1 (en) |
| AT (1) | AT395794B (en) |
| AU (1) | AU549076B2 (en) |
| BE (1) | BE888891A (en) |
| BR (1) | BR8103074A (en) |
| CA (1) | CA1163341A (en) |
| CH (1) | CH659354A5 (en) |
| CS (1) | CS276335B6 (en) |
| DD (1) | DD159930A5 (en) |
| DE (1) | DE3119669A1 (en) |
| DK (1) | DK155399C (en) |
| ES (1) | ES502320A0 (en) |
| FI (1) | FI77757C (en) |
| FR (1) | FR2483148A1 (en) |
| GB (1) | GB2076569B (en) |
| HK (1) | HK27485A (en) |
| IN (1) | IN154622B (en) |
| IT (1) | IT1135849B (en) |
| NL (1) | NL185123C (en) |
| NO (1) | NO162000C (en) |
| NZ (1) | NZ197132A (en) |
| PL (1) | PL231274A1 (en) |
| SE (1) | SE458080B (en) |
| SG (1) | SG51984G (en) |
| SU (1) | SU1271382A3 (en) |
| TR (1) | TR21315A (en) |
| YU (1) | YU42402B (en) |
| ZA (1) | ZA813156B (en) |
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-
1981
- 1981-05-12 ZA ZA00813156A patent/ZA813156B/en unknown
- 1981-05-13 IN IN507/CAL/81A patent/IN154622B/en unknown
- 1981-05-14 CA CA000377619A patent/CA1163341A/en not_active Expired
- 1981-05-18 GB GB8115163A patent/GB2076569B/en not_active Expired
- 1981-05-18 NO NO811687A patent/NO162000C/en not_active IP Right Cessation
- 1981-05-18 CH CH3237/81A patent/CH659354A5/en not_active IP Right Cessation
- 1981-05-18 DK DK218781A patent/DK155399C/en not_active IP Right Cessation
- 1981-05-18 NZ NZ197132A patent/NZ197132A/en unknown
- 1981-05-18 FI FI811526A patent/FI77757C/en not_active IP Right Cessation
- 1981-05-18 SE SE8103081A patent/SE458080B/en not_active IP Right Cessation
- 1981-05-18 IT IT21784/81A patent/IT1135849B/en active
- 1981-05-18 BR BR8103074A patent/BR8103074A/en not_active IP Right Cessation
- 1981-05-18 DE DE19813119669 patent/DE3119669A1/en active Granted
- 1981-05-18 AT AT0221581A patent/AT395794B/en not_active IP Right Cessation
- 1981-05-19 AU AU70804/81A patent/AU549076B2/en not_active Expired
- 1981-05-19 ES ES502320A patent/ES502320A0/en active Granted
- 1981-05-19 NL NLAANVRAGE8102441,A patent/NL185123C/en not_active IP Right Cessation
- 1981-05-20 YU YU1299/81A patent/YU42402B/en unknown
- 1981-05-20 PL PL23127481A patent/PL231274A1/xx unknown
- 1981-05-20 SU SU813288050A patent/SU1271382A3/en active
- 1981-05-20 BE BE0/204856A patent/BE888891A/en not_active IP Right Cessation
- 1981-05-20 FR FR8110009A patent/FR2483148A1/en active Granted
- 1981-05-20 CS CS813751A patent/CS276335B6/en not_active IP Right Cessation
- 1981-05-21 KR KR1019810001795A patent/KR850001023B1/en active
- 1981-05-21 TR TR21315A patent/TR21315A/en unknown
- 1981-05-21 DD DD81230158A patent/DD159930A5/en not_active IP Right Cessation
- 1981-11-12 US US06/320,492 patent/US4413340A/en not_active Expired - Lifetime
-
1984
- 1984-07-20 SG SG519/84A patent/SG51984G/en unknown
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1985
- 1985-04-04 HK HK274/85A patent/HK27485A/en not_active IP Right Cessation
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