CA1163721A - Apparatus for the dynamic in-circuit testing of electronic digital circuit elements - Google Patents
Apparatus for the dynamic in-circuit testing of electronic digital circuit elementsInfo
- Publication number
- CA1163721A CA1163721A CA000358461A CA358461A CA1163721A CA 1163721 A CA1163721 A CA 1163721A CA 000358461 A CA000358461 A CA 000358461A CA 358461 A CA358461 A CA 358461A CA 1163721 A CA1163721 A CA 1163721A
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- CA
- Canada
- Prior art keywords
- terminal
- test
- signal
- signals
- library
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31915—In-circuit Testers
Abstract
Abstract of the Disclosure Apparatus for the dynamic in-circuit testing of digital electronic devices employs a hardware testing circuit that is set by a microcomputer which takes no direct part in the test, so that the test hardware speed is not limited by the computer speed. The apparatus comprises a library of devices corres-ponding to the devices to be tested, the library including a ROM containing the information regarding the devices needed by the microcomputer for its purpose. An internal interface or router receives signals from the test device that are input signals to its terminals and routes them directly to the corres-ponding selected device in the library where it becomes an input to that device also. Signals from the test device that are output signals are routed instead to a comparison block where they are compared with the respective output signals from the library reference device. The signals at each corresponding pin of the two devices are compared and upon the presence of a fault the apparatus stops and identifies the pin or pins on which a fault has been detected. An external interface is provided to shift the signal levels as required between the test device and the TTL logic devices of the apparatus. The signals are sampled.
during timed periods to account for different propagation times through the apparatus, and different operating speeds of the devices. Provision is made for external or internal clocks, reset and ground connections.
during timed periods to account for different propagation times through the apparatus, and different operating speeds of the devices. Provision is made for external or internal clocks, reset and ground connections.
Description
7 ~ 1 APPARATUS FOR THE DYNAMIC IN-CIRCUIT TESTING OF ELECTRONIC
DIGITAL CIRCUIT ELEMENTS ``
Field of the Invention This invention is concerned with apparatus for the dy~namic in-circuit testing of electronic digital circuit elements.
Review of the Prior Art The continuing development of electronic digital circuit elements, and electronic circuits including such elements, of greater diversity and complexity is accompanied by corresponding increases in the difficulty and expense of testing them quickly and adequately, either during assembly of the circuit or sub-sequently after the circuit has been in use for some time. Such testing is important commercially, since the sale of equipment with too high an incidence of faults will result in loss of reputation for quality, while if the testing is unduly difficult and time-consuming, requiring expensive skilled manpower for its implementation, then the resultant increase in the servicing cost may be unacceptable.
Traditional forms of test gear such as oscilloscopes and logic analyzers require a high degree of skill in the test operator. In the application of another technique known as signature analysis a known bit stream is passed through the digital circuit and the resultant "signature" produced by that blt-stream examined for response at different points in the circuit. In a further technique a microprocessor or the like under test is replaced with an emulating microprocessor which , ' ' '~ .
i ~ti37'~1 controls the circuit in its place; such a system can only indicate that a malfunction exists in the devices on the bus but not the location of the malfunction. Simple replacement of an entire faulty circuit board is also employed, but is expensive in inventory, and subsequently the faulty board must be examined for repair.
It is of course known to test a circuit element by direct comparison with a pre-tested sample of the same element, since this reduces the amount of information required to determine whether or not the tested element is satisfactory. However, such testing has been difficult and time-consuming with known arrangements. A typical circuit board will carry a wide variety of different elements to be tested, all of which usually are operative with different parameters that must be pre-set before the particular element can be tested. If a number of similar boards are to be tested, the same element on all the boards can be examined one after the other while the test equipment is set for that element, but this then involves moving from board to board between each test.
Definition of the Invention It is therefore an object of the invention to provide a new apparatus for the dynamic in-circuit testing of electronic digital circuit elements.
It isa more specific object to provide such apparatus with which an element is tested rapidly by direct comparison with the same element provided by the testing apparatus.
i ~63721 Description of the Dra~ings..
Test apparatus which is a particular preferred embodiment of the invention will now be described, by way of example, with reference to the accompanying ~h~matic drawings, wherein:
FIGURE 1 iS a generalised block diagram of the preferred embodiment, FIGURE 2 iS a more detailed schematic diagram of the external interface block of the perferred embodiment, FIGURE 3 iS a more detailed schematic diagram of the internal interface block, FIGURE 4 is a more detailed schematic diagram of the library block, FIGURE 5 is a more detailed schematic diagram of the comparison and fault detection block, FIGURE 6 is a timing diagram to illustrate the tlming . .
system used in the comparison and fault detection block, and FIGURE 7 iS a logic diagram to show the operation of the control block in controlling the operation of the other blocks of the preferred embodiment.
i ~ 63721 Description of the Preferred E~odlment .
The test apparatus illustrated ls'intended for the testing of elements made under current industry manufacturing standards wherein each element has the form of a rectangular block of either 7.5 mm or 15 mm width, provided along its two longer parallel sides with two respective rows of uniformly-spaced metal terminal pin~s. Currently'such elements have from 14 to 4~ pins, each of which depending upon the internal architecture may be a signal input terminal, a signal output terminal, or be bi-directional. For testing purposes with this embodiment an element is temporarily connected to the test apparatus by use of a known type of spring-jawed clip, the opposed jaws of which carry respe,ctive sets of electric contacts each arranged to engage a respective pin when the clip is clamped on the element. A multi-wire cable carries signalsifrom the jaw contacts and thus,to and from the respective pins.
In addition to the clip the apparatus provides five other leads as follows:
1) A ground lead for connection to the ground of the board on which the device is mounted,
DIGITAL CIRCUIT ELEMENTS ``
Field of the Invention This invention is concerned with apparatus for the dy~namic in-circuit testing of electronic digital circuit elements.
Review of the Prior Art The continuing development of electronic digital circuit elements, and electronic circuits including such elements, of greater diversity and complexity is accompanied by corresponding increases in the difficulty and expense of testing them quickly and adequately, either during assembly of the circuit or sub-sequently after the circuit has been in use for some time. Such testing is important commercially, since the sale of equipment with too high an incidence of faults will result in loss of reputation for quality, while if the testing is unduly difficult and time-consuming, requiring expensive skilled manpower for its implementation, then the resultant increase in the servicing cost may be unacceptable.
Traditional forms of test gear such as oscilloscopes and logic analyzers require a high degree of skill in the test operator. In the application of another technique known as signature analysis a known bit stream is passed through the digital circuit and the resultant "signature" produced by that blt-stream examined for response at different points in the circuit. In a further technique a microprocessor or the like under test is replaced with an emulating microprocessor which , ' ' '~ .
i ~ti37'~1 controls the circuit in its place; such a system can only indicate that a malfunction exists in the devices on the bus but not the location of the malfunction. Simple replacement of an entire faulty circuit board is also employed, but is expensive in inventory, and subsequently the faulty board must be examined for repair.
It is of course known to test a circuit element by direct comparison with a pre-tested sample of the same element, since this reduces the amount of information required to determine whether or not the tested element is satisfactory. However, such testing has been difficult and time-consuming with known arrangements. A typical circuit board will carry a wide variety of different elements to be tested, all of which usually are operative with different parameters that must be pre-set before the particular element can be tested. If a number of similar boards are to be tested, the same element on all the boards can be examined one after the other while the test equipment is set for that element, but this then involves moving from board to board between each test.
Definition of the Invention It is therefore an object of the invention to provide a new apparatus for the dynamic in-circuit testing of electronic digital circuit elements.
It isa more specific object to provide such apparatus with which an element is tested rapidly by direct comparison with the same element provided by the testing apparatus.
i ~63721 Description of the Dra~ings..
Test apparatus which is a particular preferred embodiment of the invention will now be described, by way of example, with reference to the accompanying ~h~matic drawings, wherein:
FIGURE 1 iS a generalised block diagram of the preferred embodiment, FIGURE 2 iS a more detailed schematic diagram of the external interface block of the perferred embodiment, FIGURE 3 iS a more detailed schematic diagram of the internal interface block, FIGURE 4 is a more detailed schematic diagram of the library block, FIGURE 5 is a more detailed schematic diagram of the comparison and fault detection block, FIGURE 6 is a timing diagram to illustrate the tlming . .
system used in the comparison and fault detection block, and FIGURE 7 iS a logic diagram to show the operation of the control block in controlling the operation of the other blocks of the preferred embodiment.
i ~ 63721 Description of the Preferred E~odlment .
The test apparatus illustrated ls'intended for the testing of elements made under current industry manufacturing standards wherein each element has the form of a rectangular block of either 7.5 mm or 15 mm width, provided along its two longer parallel sides with two respective rows of uniformly-spaced metal terminal pin~s. Currently'such elements have from 14 to 4~ pins, each of which depending upon the internal architecture may be a signal input terminal, a signal output terminal, or be bi-directional. For testing purposes with this embodiment an element is temporarily connected to the test apparatus by use of a known type of spring-jawed clip, the opposed jaws of which carry respe,ctive sets of electric contacts each arranged to engage a respective pin when the clip is clamped on the element. A multi-wire cable carries signalsifrom the jaw contacts and thus,to and from the respective pins.
In addition to the clip the apparatus provides five other leads as follows:
1) A ground lead for connection to the ground of the board on which the device is mounted,
2), A lead ~EX CLK~ to connect to the external clock or it~ equivalent on the test ~oard,
3), A lead (INT CLK) to provide an internal clock from the apparatus to the test board if such is a clock needed, or if the test clock i5 too fast far the apparatus,
4~ A lead ~INT CLK~ providing the complement of 3), and
5)An external laad for giving a reset signal to re~tart a programmable device or board operation when required.
i 1 fi37~1 Turning now to Figure 1, the jaw contacts of such a cli.p 10 are connected via a ca~le 12 to corresponding contacts of an external interface (E.I.) block 14, which is in turn connected to an internal interface (I.I.) block 16. Signals from the I.I. block m~y pass dixectl~ to a comparison and fault detector (C.F.D.~ ~lock 18, or may go to a library ~loc~ 20, as will be described belo~ Signals also pass from the library block 20 to the C.F.D. block 18 and signals indicating the "status" of each of the pins of an element under test are passed from the C.F.D. ~.lock 18 to a disp~y block 22, which in this embodiment gives a visual display. It will be understood that for example in an em~odiment employed in an automatic test facility such a visual display may not be necessary and may be omitted or replaced by some other unit as required by the purchaser for indicating that the tested element has passed or failed the test and/or taking some action depending upon pass or failure of the test.
Certain control functions to be described below, particularly those required during a test, are performed by a control block 24, which has direct access to the I.I. block 16 and C.F.D. block 18, while other functions required in preparation for and following a test are performed by a microcomputer 26, which has direct access to all of the block with the exoeption of the display block 22. Microcomputer 26 also has access to a user interface block 28 including a keyboard and alphanumeric display by which a human operator can insert necessary information into the apparatus and also receive information, prompts and commands therefrom. As with display block 22, the configuration of the ~ ~fi;~7~1 user interface block 28 will also depend upon whether a human operator is required, or whether the test apparatus is being run by a machlne. The function of each of the above-described blocks and their inter-relation with one another will be described below.
The operation of apparatus of the inventlon depends upon the presence in the library block 20 of a device or element that is a duplicate of the device to ~e tested, or that can be made to operate as if it were a duplicate of the tested device. -Such duplication of the tested device may be for example by adjustment of the voltage levels and/or timing of the input/
output signals involved. This may ~e contrasted with test apparatus of the kind employing a microcomputer in which the microcomputer software or firmware is written so that the micro-computer will simulate the device under test, requiring complete and detailed information as to the operation of the device as well as the signals involved in its operation.
The library block consists of at least one board, usually a plurality of boards, each of which has connected to the busbars thereof a plurality of devices that are to be tested, all wired to the busbars to permit in-dividual access to each element and also to the pins of each element as required. Each such board can consist, for example, of a group of dissimilar elements all from the same manufacturer, or a group of similar elements, one from each of the available manufacturers, or a group of devices all of the same technology e.g. TTL; MOS; CMOS;
DTL; ECL, etc. Again, each iibrary board can be as identical as possible in content and layout to a circuib board that is I 3~3721 to be tested, and this is particularly valuable in ensuring that heating conditions, time delays, intercouplings, leakages, etc.
will be as nearly as possible the same.
Each library board also includes a read only memory means connected to appropriate busbars of the board and containing necessary information for each element on the board, such as its index number for operator identification, the identi-fication of the board on which it is mounted, the library board bus coordinates that must be enabled and accessed to power the element and access its terminals, the status of each of the terminals of the element ~.e. whether it is an input, output or bidirectional terminal), the voltage bias levels required for operation, the speed of operation and the corresponding time delays that may be required for its signals to be compared with those of the test device, and the time required for a complete test of its operation. For economy in manufacture this memory preferably is a single central unit for the whole board, but of a type that can be re-prQgrammed when required if any of the devices on the board is replaced by a different device.
Let it first be assumed that a human operator is to teP-t a single element on a board having a clock signal that is directly usable by the test apparatus and of a kind that does not require a reset signal for its operation. Before commencing the test the operator will interrogate the test apparatus via the user interface 28 to determine whether or not the same or an equivalent device is in the library block. Each device to be , ~ 6372 1 tested and the refer~nce device are identified to the operator by the above-mentioned identiflcation number stored in the respective library board memory. The operator supplies this number to the microcomputer 26 via a numerical keypad 30 in the user interface 28 and then presses the search (SRCB) key`32, causing the microcomputer to search the library memories and display on an alpanumeric di~play unit 34 in the user interface ~8 whether or not the device is in the library, and if so the library board on which it is located. If the search does not find a device with'this id,entification the computer will provide the display unit 34 w;th`an appropriate display such as "not available".
Once assured that the device can be tested the operator now connects EX CLK lead 35 to the board on which the device is mounted to receive the clGck signal, connects ground lead 36 to the board bround, puts clip 10 on to the device and presses enter key 37 to enter the device i ~ tification data as sh ~ on the display 34.
The microcomputer now interrogates the respective library memory unit for the pertinent information on the selected device and also powers the selected device, so that it is in the same condit~on of operation as the external test device. At the same time the data about the selected device is employed by the micro-computer to set the E.I. block 14 to provide the required bias voltages; ~o set the I.I. block 16 so that it will properly route the signals it reoeives, as will be described below, and to set the control block 24 so that the latter will initiate and control a testing cycle for the selected device. This data i ~fi3721 about the selected devicè will be stored in suitable registers which may be provided in the microcomputer block or in the respective block to which the data has been transferred. If the register is in the respective block then once the data has been transferred to it the microcomputer can disable itself from further access to that register until there is a need to replace the data for a new test device. Having performed these functions the microcomputer enters on the display 34 an indication that a test is possible and then, except forvarious ao~sory functions described below, disables itself from taking any further part in the test per se.
The test element is in active condition in its circuit, which must bç powered up for the test to be possible, so that the element is receiving the input signals and power supply or supplies that are available to it from its own board; the element will also be delivering output signals to the respective output terminals which, if the element is functioning properly, are appropriate for the input signals and power that it is receiving. As described above the signal at a particular terminal pin of the test element will be supplied via clip 10 to the external interface, ~here its level will be changed if necessary as previously set by the microcomputer. If it is an input signal it is routed automatically by the I.I. block 16 to the C.F.D. block and also to the corresponding terminal pin of the library reference device and becomes an input to that device. If it is an output signal it is routed automatically by the I.I. block 16 to the C.F.D. block 18 and is prevented from g access to the library reference element. If the signal is chlanging from input to output then in input mode it will be routed as above for an input signal while in output mode it will be routed as above for an output signal under control of a "toggle"
signal supplied to the I.I. block 16.
Upon the operator pressing the test key 38 the control block 24 will now operate the I.I. block 16, the library block 20, and the C.F.D. block 18 to scan synchronously and simultaneously the pins of the external device and the same pins of the library device. The input signal on any input pin of the test device will be routed by the I.I. block 16 to the library reference device, while the output signal on any output pin of the test device will be routed directly to the C.F.D.
block 18 to be compared with the signal from the same pin of the library reference device. It is usually preferred for a complete test to scan over a relatively large number of cycles since, in general, each such cycle takes only a small fraction of a second and the total time for an exhaustive test is very small-as co~red with the time required to move the clip 10 from one element to another. In the ~ e when one or more of the pins are bi-directional a plurality of scans will be required until the device has been tested in all possible states, the I.I. block 16 routing the signal as required in dependence upon whether it is an input or an output.
The C.F.D. block 18 comprises a bank of combinatorial logic elements, forty in this particular embodiment since forty pin devices are to be tested, each of which compares the signal from the respective pin of the test device with that from the corresponding pin o~ the library reference device and feeds any i 1 6372 1 output to a respective one of forty indicator devices 40 in the display block 22. Thus, if any one of the combination logic ele!ments is fed two different digital signals the respective indicator will be actuated to show a fault condition on that pin, whereupon the operator will know not only that the device is faulty, but the pin or pins at which the fault or faults is occurring~ An audible signal may also be employed to alert the operator that a fault is present. The clip can then be moved to another similar device and the test button 38 again pressed to obtain a test of the new device, an~ so on. At any time the status of the pins and whether or not a fault is present can be read by the microcomputer and this information supplied to the interface 28 or some other external apparatus.
It was assumed abcve that the device under test emplcyed the clock signal from its cwn b~, but fre~uently this is not the case, and a clock signal or oomplementary clock signal can be supplied from the micro-o~puter via the E.I. blo~k 14 thr~ugh respective leads 42 and 43, while a reset signal is supplied when required from the same block under control of the microcomputer through a lead 44. The direction of the clock signal to be supplied from the test apparatus is selectable, depending upon whether triggering occurs on the rising or falling edge of the clock pulse. The information as to what clock signal is required will be in the library memory, but needs to be fed to the microprocessor as an instruction. The operator therefore presses a clock key 46, whereupon the microprocessor will display the clock requirement for the device and a menu for operation of the numeric pad 30 i ~ 6372 1 to obtain the necessary signal; for example the menu will instruct the operator to press"l" for the microprocessor interna~
clock to supply the device with a clock signal of one polarity;
press "2" for an internal clock signal with opposite polarity;
ancl press "3" if an external clock signal is already provided.
It may be found that the external clock signal is too fast to be usable or for convenience in testing, in which case the internal clock will be used at a speed set by the micro-processor and determined from the information in the library.
The library information conveniently is stored therein in the form of the preferred frequency and preferred number of cycles for the test; upon reading this information the microcomputer will cal~ate the test duration required and terminate the test cycle upon expiry of this time. The microcomputer includes a frequency counter unit which is actuated by operation of a frequency key (FREQI 48, whereupon the display 34 will display the actual frequency and polarity of the clock that is in use.
Upon the operator pressing a time key 50 the microcomputer will show on the display 34 the duration of the test to be made and a menu to change the time if this is not satisfactory. The required test duration is selected by keying the number of milliseconds via the numerical pad 30 and then pressing the enter key 36. This feature is used, for example, if the fault is known to be-intermittent, or if a longer test time than usual is required, e.g. for a soaking test.
The circuits and logic arrangement of the various blocks 1 ~ 63 ~ ~ ~
will now be described in greater detail/ other features of the appalratus also being described wh~re this is appropriate.
External Interface Block 14 This constitutes a buffer of high input impedance between the test apparatus and the device being tested, so as not to unduly affect the operation of the test device, and also acts as a level translator to enable the test apparatus to deal with families of devices other than those used in the apparatus blocks. Thus, this particular preferred embodiment predominantly employs TTL logic devices in its construction and in the absence of the interface block 14 could only conveniently test other TTL logic devices, since other types requixing different logic thresholds might not give signals that could be handled by the test apparatus. Part of the information stored in the library memory on each library board and supplied by the microcomputer to the external interface block is the bias level offset required to translate the digital signals received and transmitted by the E.I. block to the standard levels for TTL logic devices of a maximum of 0.8 volts for "O" and a minimum of 2.4 volts for "1". The operator presses a bias key 52 to be told the offset that has been given to the E.I. block by the microcomputer for the test device together with a menu for change if this should prove to be necessary.
If necessary the number of millivolts of change required is set by the key pad 30 and entered by pressing the enter key 36.
Referring now to Figure 2, which shows in greater detail the circuit of the external interface block, the forty leads in the cable 12 and the single clock lead 3~ feed their signals to . . .
, l 63721 respective high input impedance buffers 54, while the corres-ponding forty one separate output leads 56 feed their signals to respective offset modules 58, each of which will accept the digital signal received on lead 56 and feed the corresponding TTL logic signal out on its output lead 60 to the I.I. block 16.
An internal power bnit (not shown) provides each offset module on input leads 62 and 64 respectively with the voltages appropriate to produce a TTL logic "1" or "O" on the output lead 60. The offset data from the microcomputer is also fed via a lead 66 to a shift register,68, which controls the output of a digita~
analog converter and driver 70 to produce a ground reference voltage for the signals from the offset modules. This analog ground signal is fed to a ground detector 72 which is also connected to the external ground lead 36. Upon detection of current flow ,between the two grounds the detector transmits a signal via lead 76 to the microcomputer that a ground refer-ence is available and the test may proceed, and otherwise not.
Internal Interface Block 16 Referring now to Figure 3, which shows in greater detail the circuit of the I.I. or routing block 16, each output lead 60 from E.I. block 14 constitutes an input lead to a respective set af three contro,lled switch devices 80 (designated Cl, C2 and C3 respectively) which set is controlled by a respective control block 82. The input to each control block 82 is from two separate 40-bit registers 84 and 86, .~
`i 16372t called respectively the Y and Z register, which are supplied with the required information as to the status of the respective de~rice pin from the library memory via the microcomputer 26.
The! bit signals received by each control block 82 from the X
an~ Y registers is used in combination with a toggle signal received from the library block via lead 88 to issue the necessary control signals to the switches Cl, C2 and C3. The two bit YZ
input specifies whether the signal is an input or an output or a toggle, and the incoming toggle signal will in the latter case make the final determination between input and output as .
required. Thus, if the incoming signal is an input then the two switches C2 and C3 are closed while the switch Cl is open and the signal is fed via leads 90 and 92 to the C.F.D. blo~k 18 and via lead 94 to the library block 20. If the incoming signal is an output then the two switches C2 and C3 are open and the switch Cl is closed, whereupon the signal from the E.I. block 14 cannot access the lihrary devioe, but can~3ccess the C.F.D. block 18 via lead 92, while the oorresp~nding output signal from the l;brary device can return to the I.I. block via lead 94 and access the C.F.D. block via the lead 90.
A special situation arises when the device to be tested is of a kind, such as a shift register, which must be synchronised with the library device. In such case each control device 82 is issued a "synchronous mode" signal via lead 96; in this mode with an input signal the switches Cl and C3 are now open while switch C2 i5 closed so that the signal can only input the C.F.D. block 18 via leads 90 and 9 and is blocked from the library devioe via lead 94, while with an output si~ the switch Cl is cloæd and i 16372:t ~)th switches C2 and C3 are open 80 that access to the library device from the E.l. block is a~ain prevented while the library device can feed to the C.F.D. block 18 via leads 94 and 90. m e library device is therefore inactive in a specific pattern and the C.F.D. block will detect this as a fault~since it is immaterial to that block whether the "fault" is in the test device or the library device; the test device will cycle through different patterns and upon achieving a pattern corresponding to the "frozen" pattern of the library device the "fault" indication will disappear and the two devices now operate in synchronism. The C.F.D. block is controlled by the control block to ignore this "fault" for a predetermined period of time and if synchronisation i8 not achieved with ~his period the control block 24 then issues a restart signal to the cycle control to indicate this failure and put the apparatus in standby mode; at the same time the micro-computer block will provide an instruction "failure to synchronise"
on the display 34, since the most li~ely reason is of course a faulty device.
Librar~y ~lock 20 Figure 4 is a more detailed circuit drawing of a part of one library board in the library block although, as will be understood, a typical embodiment of the invention will usually comprise a number of different boards. ~s described above each board 98 includes a read only memory 100 connected by leads 102 and ~04 respectively to the address and data busses of the micro-computer so that it can be interrogated and transfer its stored information to the microcomputer for utilisation and display.
When the computer block has identified the device to be selected, either by a preset program to be described below, or by an operator feeding this information to the computer block, the computer block will issue a "select board" signal on S lead 106 to a control logic device 108 that will in turn close a switch 110 permitting po~er to be supplied to the board.
At the same time the computer block issues a "select device"
signal on lead 112 to a register 114 that in turn will cause closing of a respective switch 116 that will permit the powering up of the selected library device 118 corresponding to the test device. Each library device ;5 connected via a board bus 119 to a library block bus 120 and ~y the leads 94 to the I.I. block 16. If the selected device is of a type in which one or more of the pins is bidirectional then the board also carries a respective toggle logic block 121 arranged for that device and which is selected by closing of the respective switch 116, this block feed-ing the toggle signal as described above on leads 88 to the I.I.
block 16.
Since the test apparatus itself employs TIL logic devices such devices in the library are immediately compatible with the test apparatus circuits and can be connected directly to the board bus 119 and thence to the library bus 120. Devices such as device 122, corresponding to test devices that require offset voltages to be provided by the E.I. block 14, cannot be directly connected in this manner because of th1s inherent incompatability;
instead they are connected to a sub-bus 123 that is connected to the board bus 119 via driver 124 providing to the sub-bus 123 i ~6:~721 the voltages required for proper operation of the device, this driver being enabled by the ~oard select signal.
C.F.D. Block 18 Turning now to Figures 5 and ~ the C.F.D. block receives signals from the library block 20 via leads 90, and from the I.I. block 16 via leads 92; these signals are fed to respective high speed memDry elements (latches) 126 and 128, also labelled Ll and L2, and thence to a respective combinatorial logic element 130. The output from each element 130 is fed to a respective high speed memory element (latch) 132, also labelled L3.
If the digital signals received by an element 130 do not correspond it detects the lack of correspondence as a fault and activates a driver 134 that lights the respective lamp 40 in the display block 22. The outputs of all of the elements 130 are fed to a combination detector device 136 that feeds a "fault detected" signal on lead 138 to the microcomputer, so that it will give an indication of a fault detection. The device feeds a corresponding signal on lead 139 to the C.F.D. block, so as to "stop" the test immediately with the fault or faults indicated, since otherwise the test might move on to a situation where there is no fault and the fault indication would be lost.
At the same time all the outputs are fed to a m~ltiplex detector register 140 that can be interrogated by themicrocomputer via leads 142 to de~ermine which of the device pins have been detected as faulty and provide a read-out either on the display 34 or some i ~ 6372 1 equivalent unit, e.g. a printer.
Owing to the high speed at which the apparatu~ operates it is necessary to control the operation of the latches 126, 128 and 132 so that the signals are sampled during precisely controlled time periods. This arrangement also permits com-pensation for the differing propagation times of signals through the various components from which the apparatus itself is assembled. It also w;dens the test capability of the apparatus in that devices of the same configuration but of different families, and thereof of different response speeds, can be tested without the need for exact correspondence between the test and library devices. For example a TTL library device can be used to test a Schottky (fast TTL) device of the same configuration.
A high speed clock 144 feeds a ripple counter 146 which produces the necessary large number of uniform pulses. Inform-ation as to the time delays tdl, td2 and td3 required for the particular device are supplied by the microcomputer block to a register 148 after this information has been extracted by it from the R.O.M.100 in the respective library board. The counter 146 and register 148 feed a comparator 150 which in turn feeds the selected pulses to a control logic module 152 that is also fed with the appropriate clock signal tc synchronise its operation with,the test device. Referring to Figure 6 a pulse is fed after time delay tdl from the start of the respect-ive clock cycle to open latches Ll and the signals from the I.I. block 16 are sampled during the period Pl. Latches L2 - i9 I ~ fi37 '~ 1 are opened for another period P2 that occurs after time delay td2 to sample the signals from the library block 20, while latches L3 are opened ~or a last period P3 that occurs after time delay td3 to sample the outputs of the combinatorial logic devices 130. All three pulses occur within one clock cycle and there is no overlap between them, so that the actual speed of operation of the tested device and the propagation times through the apparatus are immaterial as long as this condition can be fulfilled. In a particular preferred embodiment operating 1~ at 10 Mhz the length of one clock cycle will be 100 nanoseconds and each pulse will typically have a duration of 15 nanoseconds.
Control Block 24 Referring now to Figure 7 which is a logic diagram to show the manner in which the control block is employed to control the other blocks of the apparatus and to issue control signals to those other block as required. The control block of the preferred embodiment is of pulsed asynchronous logic configuration employing TTL Schottky NAND ~ogic gates of the 74S-family e.g.
74S00; 74S04; 74S10; 74S20 and 74S30. Other families and other logic systems can of course be employed, as will be fully apparent to those skilled in the art.
Upon powering-up of the apparatus it is required to be in standby mode represented by state 1. If the apparatus is not already in this state then the required prompt is not provided by the microcomputer and accordingly it is driven to the state by the operator pressing a reset key 166, whereupon the micro-computer will issue the necessary instruction signal to the logic. If the operator now presses the test key 38 the micro-computer ~ill issue its test signal that will cause the logic ' ~6~721 to move asynchronously ~o state 2, al~o called system reset I.
In this second state the input/outputs to the library block are enabled and those to the C.F.D. block are disabled; also an external reset signal is applied to the test device if it is of the type that requires such a signal.
For devices not requiring an external reset signal, such as simple logic gates, the logic can move directly to Test state 7 in which all inputs/outputs are enabled together with the C.F.D. block 18, provided the following conditions are met:
a) a test has previously been initiated (TEST) b) the external system clock is at logic zero (SYSCLK~,and c) the device has been determined previously by examin-ation of the library block memory to be of the type not requiring an external reset (SYN~.
Assuming that the logic is now in state 7, if now a fault is detected, the logic moves,to state 8 in which all the inputs/
outputs are disabled to stop or "freeze" the apparatus in the fault condition, while all accumulated information from the cycle with regard to the fault is held! so that it can be examined anddisplayed by the slower-operating microcomputer.
A return to standby state 1 is only obtained by issue of the reset signal, for example by the operator. If no fault is detected then upon expiry of the test period the logic issues a reset signal to return to state 1.
If synchronisation is required at state 2 then the necessary information comes from the library block as described above and with the presence of only conditions a~ and b) above 37~ 1 the logic i~ now moved to state 4, whe~e the neces~ary check is made for synchronisation. As described above the lack of "synchronisation" is detected as a "fault", but the logic is not armed to drive the apparatus into n fault state" as in the asynchronous loop containing state 8. Upon detection of this "fault" the logic drives immediately asynchronously to state 3, which is also called system restart 2. In this state 3, as was described above, all inputs into the libra,ry block are disabled, but all outputs are enabled and compared, so that the library device is "inacti~e". As soon as synchronisation is obtained there is no "fault" detected and with the system clock at logic zero the logic returns to state 4; this loop can of course repeat and also s,tates 5 and 6 are employed to confirm that synchronism has been achieved, to take account for example of "glitches" on the clock lines giving false clock indications.
States 5 and 6 are operative on opposite levels of the clock signal and if a "fault" is still present at either of these stations the logic will return immediately to station 3 and the cycle repeated. If there is no "fault" indication at state 6 2a and the system clock is at the required higher level then the logic passes immediately to state 7 and the test takes place.
To avoid "lock-out'l of the logic in any of the states provision is made for the appli~ation of a reset signal at each station that will drive the logic to standby state 1 for the sequence to be repeated.
. .
i l 63721 Microcomputer Block As will be apparent to those ~killed in the art from the description of the apparatus the performance required for the microcomputer block is well within the capability of many currently available units. The particular preferred embodiment described employs an Intel 8085 based central processor unit together with four No. 2716 EPROMS each of two kilobytes capacity; four No.
2114 static RAMS each of two kilob~tes capacity: and three No.
8155 static RAMS each of 1.5 kilobytes capacity and 16 I/O ports to provide a total of 48 I/O ports.
It will be seen that all of the different blocks of the apparatus can be constructed using hardware only, since their individual functions are fixed~ and the only software and/or firmware needed i8 in the microcomputer, which can be a readily available unit. Moreover the speed of operation of the various blocks, and therefore of the complete apparatUs,is independent of the speed of operation of the microcomputer, which typically i5 much slower than is possible with a hardware-only block.
For example, as described above a preferred minimum speed of operation of the hardware of the preferred embodiment during a test i8 at 10 Megaherz; the operating speed of a suitable microcomputer i5 about 4 Megaherz, but each instruction of the microcomputer requires at least several machine cycles for its execution, so that its actual operating speed is only a frac~ion of the speed of which the test apparatus is capable. This slower speed of the computed block is immaterial since the testing by the hardware portion of the apparatus is independent of the computer. The .
, ~fi3721 resultant apparatus can therefore readily be provided as a "turn-key" unit not requiring any software programming by the user.
A particularly advantageous characteristic of the apparatus of the invention is that it is not necessary to know the internal construction or mode of operation of the test d,evice for it to be tested successfully, as long as information is available as to the status of its pins during operation.
The apparatus can therefore be used to test a proprietory or military device for which the manufacturer is unwilling or unable to provide information as to its operation, and used to test a batch of devices whose operation is unknown as long as one can be sure that a correctly functioning device can be selected to serve as the library device.
Because of the possibilities described above of testing external devices making use of an internal library device that is equivalent but of a different family, the library device having one identification may also be identified as corresponding to a number of different configurations, usually referred to as packages. This information is stored in the respective library R.O.M. 100 and will be displayed by the microcomputer block on the display 34 upon interrogation of the memory, which will show that the device in the library is of "packa~e" type. A
package (PKG) key 154 is then pressed, whereupon the micro-computer will present a menu for selection via the numeric pad of the different packages that are available. Such selection actuates the microcomputer block to provide the offsets and time delays required to make the internal device equivalent to , .... .. .
~ 1 6372 ~
the external device, and to set th`e test period that will result in a satisfactory test.
The use of microcomputer control of the hardware segments of the test apparatus also permits the storage of a test sequence, as is required for example for the examination of a circuit board carrying a number of different devices. This can be accomplished using a "scratchpad" random access memory ~RAM) of the computer block, in which case the test sequence that is entered will be lost when the apparatus is powered down. Alter-natively, if the apparatus is employed frequently or principally to test a particular board then that test sequence can be stored in the computer block by a programmable read only nem~ry unlt (P~0M).
If the operator wishes to test with a PROM stored test sequence it is only necessary to press a sequence (SEQ) key 156 when a sequence identification will be produced by the micro-computer on display 34, or a menu will appear if more than one sequence is stored. In this sequence mode the operator places the clip 10 on the first te~t device and presses test key 38 whereupon the device will be tested. Once the device passes or fails the test the clip is passed to the next device and the next and test keys are pressed again. It will be seen therefore that such a sequence can be conducted by a relatively unskilled operator using only an assem~ly diagram from which the necessary information has been pre-inserted into the PROM.
A temporary test sequence or program is inserted by operation of program (PROG~ key 158, when the display 34 will advise that the apparatus is ready to accept the program ~ ~63721 .
Microcomputer Block Ag will be apparent to those skilled in the art from the description of the apparatus the performance required for the microcomputer block is well,within the capability of many currently available unitq. The particular preferred embodiment described employs an Intel 8085 based central processor unit together with four No. 2716 EPROMS each of two kilobytes capacity four No.
2114 static RAMS each of two kilo~tes capacity; and three No.
8155 static RAMS each of 1.5 kilobytes capacity and 16 I/O por~s 0 to provide a to~al of 48 I/O ports.
rt will be seen that all of the different blocks of the apparatus can be constructed using hardware only, since their individual functions are fixed9 and the only software and/or Lirmware needed is in the microcomputer, which can be a readily available unit. Moreover the speed o~ operation of the various blocks, and therefore of the complete apparatUs,is independent of the cpeed of operation of the microcomputer, which typically is much slo~er than is po~si~le with a hardware-on~y block.
For e~ample, as described above a preferred minimum speed of operation of the hardware of the pre~erred embodiment during a test iB at 10 Megaherz; the operating speed of a suitable microcomputer is about 4 Megaherz, but each instruction of the microcompu~er requires at least several machine cycles for its execution, so that its actual operating speed is only a fraction of the speed of which the test apparatus is capable. This slower speed of the computed block is immaterial since the testing by the hardware portion of the apparatus i8 independent of the computer. The i 1 637~ 1 Drawin~s accompanyin~ Supplementar~ Disclosure FIGURE 8 is a detailea logic circuit for implementing the logic diagram of Figure 7, FIGURE 9 is a detail from the external interface block of Figure 2 and also illustrates an alternative embodi-ment for obtaining offset of the input logic signals, FIGURE 10 is a detail from the internal interface block of Figure 3 to show a specific structure for control blocks therein, and FIGURE 11 is a detail from the library block of Figure 4 to show the generation of a toggle signal from a toggle logic block thereof.
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i 3 6372 1 `; SUPPLEMENTARY DISCLOSURE
; Fig~lre ~ illustrates one form of logic circuit to implement ; the lo~ic ~iac~ram of Fi~ure 7`; ~s indicated above, in practice ! therc are m~ny different w.~ys in which the circuit can be arranged ! depending upon the logic chosen by the de~igner. Thi~ circuit uses Il 5 21 multi-input NAND module~ 184 through to 224, 12 inverters 226 ! through to 248 and 4 NOR module~ 250 through to 256 connected as shown. Since all of the elements are interactive a step-by-~tep explanation of its function would be prolix and ~ unnece~sary for those skilled in the art~ The circuit consists essentially of three set/reset regi~ter~ identified by the initials K, L and M.
Register K con~ists of modules 202 and 204, register L consist~ of modules 208 and 210, while register M consists of modules 222 and i 224, the remaining modules serving for the control of the,se regi~ters. The following table correlate~ the 8etting~ of the three regi~ter~ with the numbered ~tate~ in the loglc di~gram of Figure 7. , , State X L M
2~ 0 0 3 0 1 1 .`
4 0 1 0 ' 1 1 0 "
7~ 1 0 25, 8 ~, 1 0 0 .
' J 6 ~
, Tl~ it w~ll lc ~ n ~ t to mova from ~t~t~ 1 to ~t~te 2 thc r~qi~tcrs K and L rem~in unchanged ~0) while-regi~ter M i9 set (1). ~gain to move from state 3 to ~tate 4 registers K and L
remain respectively in their unchanged (O) ~orm and set (1) state~
Il 5 while register M must be reset from (1) to (O).
The setting and re~etting of the register3 also require~
the following relation~ to be pre~ent, among the variou~ ~lgnals, `.
the period between symbol~ indicating ~or":-SET K = L-M-FAULT-SYSCLK + L-M-TEST-SYNCH-SYSCLX
. 10 RESET X = RESET + L-FAULT
SET L = K-M-TEST-SYNCH-SYSCLK
RF,SET L = RESET + K-M-FAULT-SYSCLK
SET M ~ K-L-TEST + L-FAULT + K-L-FAULT-SYSCLR
RESET M 3 RESET ~ K-L~FAULT ~ X-L-FAULT-SYSCLX
. !~
, . . . ..
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' 3 7 2 ~
!
ferrin~ now to ~i~ure 9 a preferred form of amplifier 54 for tl~e external intcrfac~ block con~ist~ of a field effect transister (FET) 160 which receive~ the input from a respective pin of the clip 10, inverts it and feeds it to an NPN transister 162, the output of which feed~ on line 56 to the offset modules 5~ or, in an alternative embodiment illu~trated by thi~ flgure, directly on the output line 60 to the I.I~ block 16. The ~i~nal level changing module~ 58 can for example consi~t of output devices ! that are ~witched on and off by the input signal~ thereto and i 10 produce corresponding output ~ignals of the required TTL logic levels. Such an arrangement permits individual control of the signal levels from each pin but may not be nece~ary, when the simpler system of Figure 8 can be adopted. Thu~, the off~et data ~I from the microproce~or 2fi take~ the form of an eight bit string, ¦ 15 and upon selection of the respective device to be tested, this 3 is fed to a shift regi~ter 164, the output of which feeds a ¦ digital/analog converter 166, the output of which is fed to an amplifier 168. The amplifier output i~ fed to the ground of the board o~n which the device being teYted is mounted and shift~
the ground voltage of that board to a valve such that the signa~s fed to all of the amplifiers 54 are within the requir~d logic level~ to be handled thereby.
Referring now to Figure 10, which illu~trates a specific circuit for the control blocks 82 of Figure 3, each of the 3witches 80 therein consists for example of an individually controllable tri~tate buffer guch ag the 74126 device sold by ~exas ~nstruments.
The Y and Z r~gi~ters feed respective dua~ input NOR gates ~70 ,~ ' . .
I 1 6 3 -, 2 1 .
~n~ 172, the to~gle sign~l ~rom control block 24 being fed to . gate 170 with the Y bit, while th~ output of gate 170 i8 fed to ~ate 172 with the Z bit. ~n inverter 174 i3 connected between the control terminals of switches Cl and C2. The setting for an input signal i~ a positive bit from the Z regi~ter 80 that the , o~tput of NOR gate 172 is low and Cl i~ disabled; the low 8ignal Ii is inverted by inverter 174 and C2 and C3 are enabled; the ~ presence of a bit from Y is immaterial. The setting for a pure ,, output signal i~ Z=0 and Y=l when NOR 172 has an output enabling Cl and disabling C2 and C3. With both Z=0 and Y=0 then the state of the switches Cl to C3 depends entirely upon the toggle signal supplied to gate 170. Syetem restart II for synchronisation is obtained by applying the signal via diode 176 to disable.switch C3 and thereby prevent the input signals from accessing the library block. . ~ .
. , .;
Referring now to Figure 11, any device to be tested of the type which any of the pins can be alternatively input or output requiree a respective toggle logic block.121 to generate the toggle ~ignal that is to be supplied to the internal interface block 16. The arrangement of one such block will now be deecribed.
By way of example only it is a~sumed that the device to be tested is logically ~imple, in which outputs are obtained on its output pin~, such ae pin 10, only when signals Sl and S2 on its contro}
pins 1 and 2 are both zero; if Sl or 52 or both are 1 then the output pin 10 i~ "tristate" i.e. of very high impedance, B0 that any signal~ applied thereto from other devices on the bus wil} ~e ignored. The ~logic block~ 121 for such an example reducee to n ..
- 31 _ .~ ' , ,i ~lfi3~21 ¦ si~ N(?l~ ~l<~te 17û llnvinc3 its inl~uts contlected to the p.ins Sl ~ ~n~ S ~lnd its output fed to a controllable tri~tate buffer 180 .; 2 ¦ which is powered wllen the respective device is powered and permitaIl the to~gle sign~l ~o be fed to the internal interface block. The il S lo~iic block therefore produces a toggle signal logic "1"- when ¦ thc two input signal Sl and 52 are zero, and at all other time~
I will produce toggle signal logic zero to be fed to the gates !i 170 of Figurc 10.
i! Tlle high speed memory latches of the C.F.D. block 18 are for example the D-~lip-Flop~ Type 74273 of Texas In~truments ¦ which upon receipt of a signal will hold that signal by remaining in the state to which it was changed by it. The comparator gates are exclusive OR modules type 74~6 of Texas Instruments, while the forty element detectors are assembled using for each eight 5-input NOR modules e~ch feeding the input of an ~ input NAND module.
. l' ,.
..
~.
.
_ 3~ _ .. ..
~1~
,, i .
i 1 fi37~1 Turning now to Figure 1, the jaw contacts of such a cli.p 10 are connected via a ca~le 12 to corresponding contacts of an external interface (E.I.) block 14, which is in turn connected to an internal interface (I.I.) block 16. Signals from the I.I. block m~y pass dixectl~ to a comparison and fault detector (C.F.D.~ ~lock 18, or may go to a library ~loc~ 20, as will be described belo~ Signals also pass from the library block 20 to the C.F.D. block 18 and signals indicating the "status" of each of the pins of an element under test are passed from the C.F.D. ~.lock 18 to a disp~y block 22, which in this embodiment gives a visual display. It will be understood that for example in an em~odiment employed in an automatic test facility such a visual display may not be necessary and may be omitted or replaced by some other unit as required by the purchaser for indicating that the tested element has passed or failed the test and/or taking some action depending upon pass or failure of the test.
Certain control functions to be described below, particularly those required during a test, are performed by a control block 24, which has direct access to the I.I. block 16 and C.F.D. block 18, while other functions required in preparation for and following a test are performed by a microcomputer 26, which has direct access to all of the block with the exoeption of the display block 22. Microcomputer 26 also has access to a user interface block 28 including a keyboard and alphanumeric display by which a human operator can insert necessary information into the apparatus and also receive information, prompts and commands therefrom. As with display block 22, the configuration of the ~ ~fi;~7~1 user interface block 28 will also depend upon whether a human operator is required, or whether the test apparatus is being run by a machlne. The function of each of the above-described blocks and their inter-relation with one another will be described below.
The operation of apparatus of the inventlon depends upon the presence in the library block 20 of a device or element that is a duplicate of the device to ~e tested, or that can be made to operate as if it were a duplicate of the tested device. -Such duplication of the tested device may be for example by adjustment of the voltage levels and/or timing of the input/
output signals involved. This may ~e contrasted with test apparatus of the kind employing a microcomputer in which the microcomputer software or firmware is written so that the micro-computer will simulate the device under test, requiring complete and detailed information as to the operation of the device as well as the signals involved in its operation.
The library block consists of at least one board, usually a plurality of boards, each of which has connected to the busbars thereof a plurality of devices that are to be tested, all wired to the busbars to permit in-dividual access to each element and also to the pins of each element as required. Each such board can consist, for example, of a group of dissimilar elements all from the same manufacturer, or a group of similar elements, one from each of the available manufacturers, or a group of devices all of the same technology e.g. TTL; MOS; CMOS;
DTL; ECL, etc. Again, each iibrary board can be as identical as possible in content and layout to a circuib board that is I 3~3721 to be tested, and this is particularly valuable in ensuring that heating conditions, time delays, intercouplings, leakages, etc.
will be as nearly as possible the same.
Each library board also includes a read only memory means connected to appropriate busbars of the board and containing necessary information for each element on the board, such as its index number for operator identification, the identi-fication of the board on which it is mounted, the library board bus coordinates that must be enabled and accessed to power the element and access its terminals, the status of each of the terminals of the element ~.e. whether it is an input, output or bidirectional terminal), the voltage bias levels required for operation, the speed of operation and the corresponding time delays that may be required for its signals to be compared with those of the test device, and the time required for a complete test of its operation. For economy in manufacture this memory preferably is a single central unit for the whole board, but of a type that can be re-prQgrammed when required if any of the devices on the board is replaced by a different device.
Let it first be assumed that a human operator is to teP-t a single element on a board having a clock signal that is directly usable by the test apparatus and of a kind that does not require a reset signal for its operation. Before commencing the test the operator will interrogate the test apparatus via the user interface 28 to determine whether or not the same or an equivalent device is in the library block. Each device to be , ~ 6372 1 tested and the refer~nce device are identified to the operator by the above-mentioned identiflcation number stored in the respective library board memory. The operator supplies this number to the microcomputer 26 via a numerical keypad 30 in the user interface 28 and then presses the search (SRCB) key`32, causing the microcomputer to search the library memories and display on an alpanumeric di~play unit 34 in the user interface ~8 whether or not the device is in the library, and if so the library board on which it is located. If the search does not find a device with'this id,entification the computer will provide the display unit 34 w;th`an appropriate display such as "not available".
Once assured that the device can be tested the operator now connects EX CLK lead 35 to the board on which the device is mounted to receive the clGck signal, connects ground lead 36 to the board bround, puts clip 10 on to the device and presses enter key 37 to enter the device i ~ tification data as sh ~ on the display 34.
The microcomputer now interrogates the respective library memory unit for the pertinent information on the selected device and also powers the selected device, so that it is in the same condit~on of operation as the external test device. At the same time the data about the selected device is employed by the micro-computer to set the E.I. block 14 to provide the required bias voltages; ~o set the I.I. block 16 so that it will properly route the signals it reoeives, as will be described below, and to set the control block 24 so that the latter will initiate and control a testing cycle for the selected device. This data i ~fi3721 about the selected devicè will be stored in suitable registers which may be provided in the microcomputer block or in the respective block to which the data has been transferred. If the register is in the respective block then once the data has been transferred to it the microcomputer can disable itself from further access to that register until there is a need to replace the data for a new test device. Having performed these functions the microcomputer enters on the display 34 an indication that a test is possible and then, except forvarious ao~sory functions described below, disables itself from taking any further part in the test per se.
The test element is in active condition in its circuit, which must bç powered up for the test to be possible, so that the element is receiving the input signals and power supply or supplies that are available to it from its own board; the element will also be delivering output signals to the respective output terminals which, if the element is functioning properly, are appropriate for the input signals and power that it is receiving. As described above the signal at a particular terminal pin of the test element will be supplied via clip 10 to the external interface, ~here its level will be changed if necessary as previously set by the microcomputer. If it is an input signal it is routed automatically by the I.I. block 16 to the C.F.D. block and also to the corresponding terminal pin of the library reference device and becomes an input to that device. If it is an output signal it is routed automatically by the I.I. block 16 to the C.F.D. block 18 and is prevented from g access to the library reference element. If the signal is chlanging from input to output then in input mode it will be routed as above for an input signal while in output mode it will be routed as above for an output signal under control of a "toggle"
signal supplied to the I.I. block 16.
Upon the operator pressing the test key 38 the control block 24 will now operate the I.I. block 16, the library block 20, and the C.F.D. block 18 to scan synchronously and simultaneously the pins of the external device and the same pins of the library device. The input signal on any input pin of the test device will be routed by the I.I. block 16 to the library reference device, while the output signal on any output pin of the test device will be routed directly to the C.F.D.
block 18 to be compared with the signal from the same pin of the library reference device. It is usually preferred for a complete test to scan over a relatively large number of cycles since, in general, each such cycle takes only a small fraction of a second and the total time for an exhaustive test is very small-as co~red with the time required to move the clip 10 from one element to another. In the ~ e when one or more of the pins are bi-directional a plurality of scans will be required until the device has been tested in all possible states, the I.I. block 16 routing the signal as required in dependence upon whether it is an input or an output.
The C.F.D. block 18 comprises a bank of combinatorial logic elements, forty in this particular embodiment since forty pin devices are to be tested, each of which compares the signal from the respective pin of the test device with that from the corresponding pin o~ the library reference device and feeds any i 1 6372 1 output to a respective one of forty indicator devices 40 in the display block 22. Thus, if any one of the combination logic ele!ments is fed two different digital signals the respective indicator will be actuated to show a fault condition on that pin, whereupon the operator will know not only that the device is faulty, but the pin or pins at which the fault or faults is occurring~ An audible signal may also be employed to alert the operator that a fault is present. The clip can then be moved to another similar device and the test button 38 again pressed to obtain a test of the new device, an~ so on. At any time the status of the pins and whether or not a fault is present can be read by the microcomputer and this information supplied to the interface 28 or some other external apparatus.
It was assumed abcve that the device under test emplcyed the clock signal from its cwn b~, but fre~uently this is not the case, and a clock signal or oomplementary clock signal can be supplied from the micro-o~puter via the E.I. blo~k 14 thr~ugh respective leads 42 and 43, while a reset signal is supplied when required from the same block under control of the microcomputer through a lead 44. The direction of the clock signal to be supplied from the test apparatus is selectable, depending upon whether triggering occurs on the rising or falling edge of the clock pulse. The information as to what clock signal is required will be in the library memory, but needs to be fed to the microprocessor as an instruction. The operator therefore presses a clock key 46, whereupon the microprocessor will display the clock requirement for the device and a menu for operation of the numeric pad 30 i ~ 6372 1 to obtain the necessary signal; for example the menu will instruct the operator to press"l" for the microprocessor interna~
clock to supply the device with a clock signal of one polarity;
press "2" for an internal clock signal with opposite polarity;
ancl press "3" if an external clock signal is already provided.
It may be found that the external clock signal is too fast to be usable or for convenience in testing, in which case the internal clock will be used at a speed set by the micro-processor and determined from the information in the library.
The library information conveniently is stored therein in the form of the preferred frequency and preferred number of cycles for the test; upon reading this information the microcomputer will cal~ate the test duration required and terminate the test cycle upon expiry of this time. The microcomputer includes a frequency counter unit which is actuated by operation of a frequency key (FREQI 48, whereupon the display 34 will display the actual frequency and polarity of the clock that is in use.
Upon the operator pressing a time key 50 the microcomputer will show on the display 34 the duration of the test to be made and a menu to change the time if this is not satisfactory. The required test duration is selected by keying the number of milliseconds via the numerical pad 30 and then pressing the enter key 36. This feature is used, for example, if the fault is known to be-intermittent, or if a longer test time than usual is required, e.g. for a soaking test.
The circuits and logic arrangement of the various blocks 1 ~ 63 ~ ~ ~
will now be described in greater detail/ other features of the appalratus also being described wh~re this is appropriate.
External Interface Block 14 This constitutes a buffer of high input impedance between the test apparatus and the device being tested, so as not to unduly affect the operation of the test device, and also acts as a level translator to enable the test apparatus to deal with families of devices other than those used in the apparatus blocks. Thus, this particular preferred embodiment predominantly employs TTL logic devices in its construction and in the absence of the interface block 14 could only conveniently test other TTL logic devices, since other types requixing different logic thresholds might not give signals that could be handled by the test apparatus. Part of the information stored in the library memory on each library board and supplied by the microcomputer to the external interface block is the bias level offset required to translate the digital signals received and transmitted by the E.I. block to the standard levels for TTL logic devices of a maximum of 0.8 volts for "O" and a minimum of 2.4 volts for "1". The operator presses a bias key 52 to be told the offset that has been given to the E.I. block by the microcomputer for the test device together with a menu for change if this should prove to be necessary.
If necessary the number of millivolts of change required is set by the key pad 30 and entered by pressing the enter key 36.
Referring now to Figure 2, which shows in greater detail the circuit of the external interface block, the forty leads in the cable 12 and the single clock lead 3~ feed their signals to . . .
, l 63721 respective high input impedance buffers 54, while the corres-ponding forty one separate output leads 56 feed their signals to respective offset modules 58, each of which will accept the digital signal received on lead 56 and feed the corresponding TTL logic signal out on its output lead 60 to the I.I. block 16.
An internal power bnit (not shown) provides each offset module on input leads 62 and 64 respectively with the voltages appropriate to produce a TTL logic "1" or "O" on the output lead 60. The offset data from the microcomputer is also fed via a lead 66 to a shift register,68, which controls the output of a digita~
analog converter and driver 70 to produce a ground reference voltage for the signals from the offset modules. This analog ground signal is fed to a ground detector 72 which is also connected to the external ground lead 36. Upon detection of current flow ,between the two grounds the detector transmits a signal via lead 76 to the microcomputer that a ground refer-ence is available and the test may proceed, and otherwise not.
Internal Interface Block 16 Referring now to Figure 3, which shows in greater detail the circuit of the I.I. or routing block 16, each output lead 60 from E.I. block 14 constitutes an input lead to a respective set af three contro,lled switch devices 80 (designated Cl, C2 and C3 respectively) which set is controlled by a respective control block 82. The input to each control block 82 is from two separate 40-bit registers 84 and 86, .~
`i 16372t called respectively the Y and Z register, which are supplied with the required information as to the status of the respective de~rice pin from the library memory via the microcomputer 26.
The! bit signals received by each control block 82 from the X
an~ Y registers is used in combination with a toggle signal received from the library block via lead 88 to issue the necessary control signals to the switches Cl, C2 and C3. The two bit YZ
input specifies whether the signal is an input or an output or a toggle, and the incoming toggle signal will in the latter case make the final determination between input and output as .
required. Thus, if the incoming signal is an input then the two switches C2 and C3 are closed while the switch Cl is open and the signal is fed via leads 90 and 92 to the C.F.D. blo~k 18 and via lead 94 to the library block 20. If the incoming signal is an output then the two switches C2 and C3 are open and the switch Cl is closed, whereupon the signal from the E.I. block 14 cannot access the lihrary devioe, but can~3ccess the C.F.D. block 18 via lead 92, while the oorresp~nding output signal from the l;brary device can return to the I.I. block via lead 94 and access the C.F.D. block via the lead 90.
A special situation arises when the device to be tested is of a kind, such as a shift register, which must be synchronised with the library device. In such case each control device 82 is issued a "synchronous mode" signal via lead 96; in this mode with an input signal the switches Cl and C3 are now open while switch C2 i5 closed so that the signal can only input the C.F.D. block 18 via leads 90 and 9 and is blocked from the library devioe via lead 94, while with an output si~ the switch Cl is cloæd and i 16372:t ~)th switches C2 and C3 are open 80 that access to the library device from the E.l. block is a~ain prevented while the library device can feed to the C.F.D. block 18 via leads 94 and 90. m e library device is therefore inactive in a specific pattern and the C.F.D. block will detect this as a fault~since it is immaterial to that block whether the "fault" is in the test device or the library device; the test device will cycle through different patterns and upon achieving a pattern corresponding to the "frozen" pattern of the library device the "fault" indication will disappear and the two devices now operate in synchronism. The C.F.D. block is controlled by the control block to ignore this "fault" for a predetermined period of time and if synchronisation i8 not achieved with ~his period the control block 24 then issues a restart signal to the cycle control to indicate this failure and put the apparatus in standby mode; at the same time the micro-computer block will provide an instruction "failure to synchronise"
on the display 34, since the most li~ely reason is of course a faulty device.
Librar~y ~lock 20 Figure 4 is a more detailed circuit drawing of a part of one library board in the library block although, as will be understood, a typical embodiment of the invention will usually comprise a number of different boards. ~s described above each board 98 includes a read only memory 100 connected by leads 102 and ~04 respectively to the address and data busses of the micro-computer so that it can be interrogated and transfer its stored information to the microcomputer for utilisation and display.
When the computer block has identified the device to be selected, either by a preset program to be described below, or by an operator feeding this information to the computer block, the computer block will issue a "select board" signal on S lead 106 to a control logic device 108 that will in turn close a switch 110 permitting po~er to be supplied to the board.
At the same time the computer block issues a "select device"
signal on lead 112 to a register 114 that in turn will cause closing of a respective switch 116 that will permit the powering up of the selected library device 118 corresponding to the test device. Each library device ;5 connected via a board bus 119 to a library block bus 120 and ~y the leads 94 to the I.I. block 16. If the selected device is of a type in which one or more of the pins is bidirectional then the board also carries a respective toggle logic block 121 arranged for that device and which is selected by closing of the respective switch 116, this block feed-ing the toggle signal as described above on leads 88 to the I.I.
block 16.
Since the test apparatus itself employs TIL logic devices such devices in the library are immediately compatible with the test apparatus circuits and can be connected directly to the board bus 119 and thence to the library bus 120. Devices such as device 122, corresponding to test devices that require offset voltages to be provided by the E.I. block 14, cannot be directly connected in this manner because of th1s inherent incompatability;
instead they are connected to a sub-bus 123 that is connected to the board bus 119 via driver 124 providing to the sub-bus 123 i ~6:~721 the voltages required for proper operation of the device, this driver being enabled by the ~oard select signal.
C.F.D. Block 18 Turning now to Figures 5 and ~ the C.F.D. block receives signals from the library block 20 via leads 90, and from the I.I. block 16 via leads 92; these signals are fed to respective high speed memDry elements (latches) 126 and 128, also labelled Ll and L2, and thence to a respective combinatorial logic element 130. The output from each element 130 is fed to a respective high speed memory element (latch) 132, also labelled L3.
If the digital signals received by an element 130 do not correspond it detects the lack of correspondence as a fault and activates a driver 134 that lights the respective lamp 40 in the display block 22. The outputs of all of the elements 130 are fed to a combination detector device 136 that feeds a "fault detected" signal on lead 138 to the microcomputer, so that it will give an indication of a fault detection. The device feeds a corresponding signal on lead 139 to the C.F.D. block, so as to "stop" the test immediately with the fault or faults indicated, since otherwise the test might move on to a situation where there is no fault and the fault indication would be lost.
At the same time all the outputs are fed to a m~ltiplex detector register 140 that can be interrogated by themicrocomputer via leads 142 to de~ermine which of the device pins have been detected as faulty and provide a read-out either on the display 34 or some i ~ 6372 1 equivalent unit, e.g. a printer.
Owing to the high speed at which the apparatu~ operates it is necessary to control the operation of the latches 126, 128 and 132 so that the signals are sampled during precisely controlled time periods. This arrangement also permits com-pensation for the differing propagation times of signals through the various components from which the apparatus itself is assembled. It also w;dens the test capability of the apparatus in that devices of the same configuration but of different families, and thereof of different response speeds, can be tested without the need for exact correspondence between the test and library devices. For example a TTL library device can be used to test a Schottky (fast TTL) device of the same configuration.
A high speed clock 144 feeds a ripple counter 146 which produces the necessary large number of uniform pulses. Inform-ation as to the time delays tdl, td2 and td3 required for the particular device are supplied by the microcomputer block to a register 148 after this information has been extracted by it from the R.O.M.100 in the respective library board. The counter 146 and register 148 feed a comparator 150 which in turn feeds the selected pulses to a control logic module 152 that is also fed with the appropriate clock signal tc synchronise its operation with,the test device. Referring to Figure 6 a pulse is fed after time delay tdl from the start of the respect-ive clock cycle to open latches Ll and the signals from the I.I. block 16 are sampled during the period Pl. Latches L2 - i9 I ~ fi37 '~ 1 are opened for another period P2 that occurs after time delay td2 to sample the signals from the library block 20, while latches L3 are opened ~or a last period P3 that occurs after time delay td3 to sample the outputs of the combinatorial logic devices 130. All three pulses occur within one clock cycle and there is no overlap between them, so that the actual speed of operation of the tested device and the propagation times through the apparatus are immaterial as long as this condition can be fulfilled. In a particular preferred embodiment operating 1~ at 10 Mhz the length of one clock cycle will be 100 nanoseconds and each pulse will typically have a duration of 15 nanoseconds.
Control Block 24 Referring now to Figure 7 which is a logic diagram to show the manner in which the control block is employed to control the other blocks of the apparatus and to issue control signals to those other block as required. The control block of the preferred embodiment is of pulsed asynchronous logic configuration employing TTL Schottky NAND ~ogic gates of the 74S-family e.g.
74S00; 74S04; 74S10; 74S20 and 74S30. Other families and other logic systems can of course be employed, as will be fully apparent to those skilled in the art.
Upon powering-up of the apparatus it is required to be in standby mode represented by state 1. If the apparatus is not already in this state then the required prompt is not provided by the microcomputer and accordingly it is driven to the state by the operator pressing a reset key 166, whereupon the micro-computer will issue the necessary instruction signal to the logic. If the operator now presses the test key 38 the micro-computer ~ill issue its test signal that will cause the logic ' ~6~721 to move asynchronously ~o state 2, al~o called system reset I.
In this second state the input/outputs to the library block are enabled and those to the C.F.D. block are disabled; also an external reset signal is applied to the test device if it is of the type that requires such a signal.
For devices not requiring an external reset signal, such as simple logic gates, the logic can move directly to Test state 7 in which all inputs/outputs are enabled together with the C.F.D. block 18, provided the following conditions are met:
a) a test has previously been initiated (TEST) b) the external system clock is at logic zero (SYSCLK~,and c) the device has been determined previously by examin-ation of the library block memory to be of the type not requiring an external reset (SYN~.
Assuming that the logic is now in state 7, if now a fault is detected, the logic moves,to state 8 in which all the inputs/
outputs are disabled to stop or "freeze" the apparatus in the fault condition, while all accumulated information from the cycle with regard to the fault is held! so that it can be examined anddisplayed by the slower-operating microcomputer.
A return to standby state 1 is only obtained by issue of the reset signal, for example by the operator. If no fault is detected then upon expiry of the test period the logic issues a reset signal to return to state 1.
If synchronisation is required at state 2 then the necessary information comes from the library block as described above and with the presence of only conditions a~ and b) above 37~ 1 the logic i~ now moved to state 4, whe~e the neces~ary check is made for synchronisation. As described above the lack of "synchronisation" is detected as a "fault", but the logic is not armed to drive the apparatus into n fault state" as in the asynchronous loop containing state 8. Upon detection of this "fault" the logic drives immediately asynchronously to state 3, which is also called system restart 2. In this state 3, as was described above, all inputs into the libra,ry block are disabled, but all outputs are enabled and compared, so that the library device is "inacti~e". As soon as synchronisation is obtained there is no "fault" detected and with the system clock at logic zero the logic returns to state 4; this loop can of course repeat and also s,tates 5 and 6 are employed to confirm that synchronism has been achieved, to take account for example of "glitches" on the clock lines giving false clock indications.
States 5 and 6 are operative on opposite levels of the clock signal and if a "fault" is still present at either of these stations the logic will return immediately to station 3 and the cycle repeated. If there is no "fault" indication at state 6 2a and the system clock is at the required higher level then the logic passes immediately to state 7 and the test takes place.
To avoid "lock-out'l of the logic in any of the states provision is made for the appli~ation of a reset signal at each station that will drive the logic to standby state 1 for the sequence to be repeated.
. .
i l 63721 Microcomputer Block As will be apparent to those ~killed in the art from the description of the apparatus the performance required for the microcomputer block is well within the capability of many currently available units. The particular preferred embodiment described employs an Intel 8085 based central processor unit together with four No. 2716 EPROMS each of two kilobytes capacity; four No.
2114 static RAMS each of two kilob~tes capacity: and three No.
8155 static RAMS each of 1.5 kilobytes capacity and 16 I/O ports to provide a total of 48 I/O ports.
It will be seen that all of the different blocks of the apparatus can be constructed using hardware only, since their individual functions are fixed~ and the only software and/or firmware needed i8 in the microcomputer, which can be a readily available unit. Moreover the speed of operation of the various blocks, and therefore of the complete apparatUs,is independent of the speed of operation of the microcomputer, which typically i5 much slower than is possible with a hardware-only block.
For example, as described above a preferred minimum speed of operation of the hardware of the preferred embodiment during a test i8 at 10 Megaherz; the operating speed of a suitable microcomputer i5 about 4 Megaherz, but each instruction of the microcomputer requires at least several machine cycles for its execution, so that its actual operating speed is only a frac~ion of the speed of which the test apparatus is capable. This slower speed of the computed block is immaterial since the testing by the hardware portion of the apparatus is independent of the computer. The .
, ~fi3721 resultant apparatus can therefore readily be provided as a "turn-key" unit not requiring any software programming by the user.
A particularly advantageous characteristic of the apparatus of the invention is that it is not necessary to know the internal construction or mode of operation of the test d,evice for it to be tested successfully, as long as information is available as to the status of its pins during operation.
The apparatus can therefore be used to test a proprietory or military device for which the manufacturer is unwilling or unable to provide information as to its operation, and used to test a batch of devices whose operation is unknown as long as one can be sure that a correctly functioning device can be selected to serve as the library device.
Because of the possibilities described above of testing external devices making use of an internal library device that is equivalent but of a different family, the library device having one identification may also be identified as corresponding to a number of different configurations, usually referred to as packages. This information is stored in the respective library R.O.M. 100 and will be displayed by the microcomputer block on the display 34 upon interrogation of the memory, which will show that the device in the library is of "packa~e" type. A
package (PKG) key 154 is then pressed, whereupon the micro-computer will present a menu for selection via the numeric pad of the different packages that are available. Such selection actuates the microcomputer block to provide the offsets and time delays required to make the internal device equivalent to , .... .. .
~ 1 6372 ~
the external device, and to set th`e test period that will result in a satisfactory test.
The use of microcomputer control of the hardware segments of the test apparatus also permits the storage of a test sequence, as is required for example for the examination of a circuit board carrying a number of different devices. This can be accomplished using a "scratchpad" random access memory ~RAM) of the computer block, in which case the test sequence that is entered will be lost when the apparatus is powered down. Alter-natively, if the apparatus is employed frequently or principally to test a particular board then that test sequence can be stored in the computer block by a programmable read only nem~ry unlt (P~0M).
If the operator wishes to test with a PROM stored test sequence it is only necessary to press a sequence (SEQ) key 156 when a sequence identification will be produced by the micro-computer on display 34, or a menu will appear if more than one sequence is stored. In this sequence mode the operator places the clip 10 on the first te~t device and presses test key 38 whereupon the device will be tested. Once the device passes or fails the test the clip is passed to the next device and the next and test keys are pressed again. It will be seen therefore that such a sequence can be conducted by a relatively unskilled operator using only an assem~ly diagram from which the necessary information has been pre-inserted into the PROM.
A temporary test sequence or program is inserted by operation of program (PROG~ key 158, when the display 34 will advise that the apparatus is ready to accept the program ~ ~63721 .
Microcomputer Block Ag will be apparent to those skilled in the art from the description of the apparatus the performance required for the microcomputer block is well,within the capability of many currently available unitq. The particular preferred embodiment described employs an Intel 8085 based central processor unit together with four No. 2716 EPROMS each of two kilobytes capacity four No.
2114 static RAMS each of two kilo~tes capacity; and three No.
8155 static RAMS each of 1.5 kilobytes capacity and 16 I/O por~s 0 to provide a to~al of 48 I/O ports.
rt will be seen that all of the different blocks of the apparatus can be constructed using hardware only, since their individual functions are fixed9 and the only software and/or Lirmware needed is in the microcomputer, which can be a readily available unit. Moreover the speed o~ operation of the various blocks, and therefore of the complete apparatUs,is independent of the cpeed of operation of the microcomputer, which typically is much slo~er than is po~si~le with a hardware-on~y block.
For e~ample, as described above a preferred minimum speed of operation of the hardware of the pre~erred embodiment during a test iB at 10 Megaherz; the operating speed of a suitable microcomputer is about 4 Megaherz, but each instruction of the microcompu~er requires at least several machine cycles for its execution, so that its actual operating speed is only a fraction of the speed of which the test apparatus is capable. This slower speed of the computed block is immaterial since the testing by the hardware portion of the apparatus i8 independent of the computer. The i 1 637~ 1 Drawin~s accompanyin~ Supplementar~ Disclosure FIGURE 8 is a detailea logic circuit for implementing the logic diagram of Figure 7, FIGURE 9 is a detail from the external interface block of Figure 2 and also illustrates an alternative embodi-ment for obtaining offset of the input logic signals, FIGURE 10 is a detail from the internal interface block of Figure 3 to show a specific structure for control blocks therein, and FIGURE 11 is a detail from the library block of Figure 4 to show the generation of a toggle signal from a toggle logic block thereof.
,~ .
i 3 6372 1 `; SUPPLEMENTARY DISCLOSURE
; Fig~lre ~ illustrates one form of logic circuit to implement ; the lo~ic ~iac~ram of Fi~ure 7`; ~s indicated above, in practice ! therc are m~ny different w.~ys in which the circuit can be arranged ! depending upon the logic chosen by the de~igner. Thi~ circuit uses Il 5 21 multi-input NAND module~ 184 through to 224, 12 inverters 226 ! through to 248 and 4 NOR module~ 250 through to 256 connected as shown. Since all of the elements are interactive a step-by-~tep explanation of its function would be prolix and ~ unnece~sary for those skilled in the art~ The circuit consists essentially of three set/reset regi~ter~ identified by the initials K, L and M.
Register K con~ists of modules 202 and 204, register L consist~ of modules 208 and 210, while register M consists of modules 222 and i 224, the remaining modules serving for the control of the,se regi~ters. The following table correlate~ the 8etting~ of the three regi~ter~ with the numbered ~tate~ in the loglc di~gram of Figure 7. , , State X L M
2~ 0 0 3 0 1 1 .`
4 0 1 0 ' 1 1 0 "
7~ 1 0 25, 8 ~, 1 0 0 .
' J 6 ~
, Tl~ it w~ll lc ~ n ~ t to mova from ~t~t~ 1 to ~t~te 2 thc r~qi~tcrs K and L rem~in unchanged ~0) while-regi~ter M i9 set (1). ~gain to move from state 3 to ~tate 4 registers K and L
remain respectively in their unchanged (O) ~orm and set (1) state~
Il 5 while register M must be reset from (1) to (O).
The setting and re~etting of the register3 also require~
the following relation~ to be pre~ent, among the variou~ ~lgnals, `.
the period between symbol~ indicating ~or":-SET K = L-M-FAULT-SYSCLK + L-M-TEST-SYNCH-SYSCLX
. 10 RESET X = RESET + L-FAULT
SET L = K-M-TEST-SYNCH-SYSCLK
RF,SET L = RESET + K-M-FAULT-SYSCLK
SET M ~ K-L-TEST + L-FAULT + K-L-FAULT-SYSCLR
RESET M 3 RESET ~ K-L~FAULT ~ X-L-FAULT-SYSCLX
. !~
, . . . ..
`'' ' ' '"'`- '.
' 3 7 2 ~
!
ferrin~ now to ~i~ure 9 a preferred form of amplifier 54 for tl~e external intcrfac~ block con~ist~ of a field effect transister (FET) 160 which receive~ the input from a respective pin of the clip 10, inverts it and feeds it to an NPN transister 162, the output of which feed~ on line 56 to the offset modules 5~ or, in an alternative embodiment illu~trated by thi~ flgure, directly on the output line 60 to the I.I~ block 16. The ~i~nal level changing module~ 58 can for example consi~t of output devices ! that are ~witched on and off by the input signal~ thereto and i 10 produce corresponding output ~ignals of the required TTL logic levels. Such an arrangement permits individual control of the signal levels from each pin but may not be nece~ary, when the simpler system of Figure 8 can be adopted. Thu~, the off~et data ~I from the microproce~or 2fi take~ the form of an eight bit string, ¦ 15 and upon selection of the respective device to be tested, this 3 is fed to a shift regi~ter 164, the output of which feeds a ¦ digital/analog converter 166, the output of which is fed to an amplifier 168. The amplifier output i~ fed to the ground of the board o~n which the device being teYted is mounted and shift~
the ground voltage of that board to a valve such that the signa~s fed to all of the amplifiers 54 are within the requir~d logic level~ to be handled thereby.
Referring now to Figure 10, which illu~trates a specific circuit for the control blocks 82 of Figure 3, each of the 3witches 80 therein consists for example of an individually controllable tri~tate buffer guch ag the 74126 device sold by ~exas ~nstruments.
The Y and Z r~gi~ters feed respective dua~ input NOR gates ~70 ,~ ' . .
I 1 6 3 -, 2 1 .
~n~ 172, the to~gle sign~l ~rom control block 24 being fed to . gate 170 with the Y bit, while th~ output of gate 170 i8 fed to ~ate 172 with the Z bit. ~n inverter 174 i3 connected between the control terminals of switches Cl and C2. The setting for an input signal i~ a positive bit from the Z regi~ter 80 that the , o~tput of NOR gate 172 is low and Cl i~ disabled; the low 8ignal Ii is inverted by inverter 174 and C2 and C3 are enabled; the ~ presence of a bit from Y is immaterial. The setting for a pure ,, output signal i~ Z=0 and Y=l when NOR 172 has an output enabling Cl and disabling C2 and C3. With both Z=0 and Y=0 then the state of the switches Cl to C3 depends entirely upon the toggle signal supplied to gate 170. Syetem restart II for synchronisation is obtained by applying the signal via diode 176 to disable.switch C3 and thereby prevent the input signals from accessing the library block. . ~ .
. , .;
Referring now to Figure 11, any device to be tested of the type which any of the pins can be alternatively input or output requiree a respective toggle logic block.121 to generate the toggle ~ignal that is to be supplied to the internal interface block 16. The arrangement of one such block will now be deecribed.
By way of example only it is a~sumed that the device to be tested is logically ~imple, in which outputs are obtained on its output pin~, such ae pin 10, only when signals Sl and S2 on its contro}
pins 1 and 2 are both zero; if Sl or 52 or both are 1 then the output pin 10 i~ "tristate" i.e. of very high impedance, B0 that any signal~ applied thereto from other devices on the bus wil} ~e ignored. The ~logic block~ 121 for such an example reducee to n ..
- 31 _ .~ ' , ,i ~lfi3~21 ¦ si~ N(?l~ ~l<~te 17û llnvinc3 its inl~uts contlected to the p.ins Sl ~ ~n~ S ~lnd its output fed to a controllable tri~tate buffer 180 .; 2 ¦ which is powered wllen the respective device is powered and permitaIl the to~gle sign~l ~o be fed to the internal interface block. The il S lo~iic block therefore produces a toggle signal logic "1"- when ¦ thc two input signal Sl and 52 are zero, and at all other time~
I will produce toggle signal logic zero to be fed to the gates !i 170 of Figurc 10.
i! Tlle high speed memory latches of the C.F.D. block 18 are for example the D-~lip-Flop~ Type 74273 of Texas In~truments ¦ which upon receipt of a signal will hold that signal by remaining in the state to which it was changed by it. The comparator gates are exclusive OR modules type 74~6 of Texas Instruments, while the forty element detectors are assembled using for each eight 5-input NOR modules e~ch feeding the input of an ~ input NAND module.
. l' ,.
..
~.
.
_ 3~ _ .. ..
~1~
,, i .
Claims (13)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. Apparatus for the dynamic in-circuit testing of an electronic digital circuit element comprising:
means for accessing the terminals of a test element to be tested for the receipt of the respective electric signals at at least the operative terminals of the test element;
library means including a reference digital electronic element corresponding to the test element to be tested;
signal comparison means for comparing the signals at the said operative terminals of the test element with the corresponding signals at the respective terminals of the reference element and for producing a fault indication if the comparison indicates the presence of a fault;
means for feeding an input signal at a terminal of the test element from said accessing means to the corresponding terminal of the reference element, and for feeding an output signal at a terminal of the test element to the signal comparison means; and means for feeding an output signal at a terminal of the reference element to the signal comparison means for comparison with the respective output signal from the test element.
means for accessing the terminals of a test element to be tested for the receipt of the respective electric signals at at least the operative terminals of the test element;
library means including a reference digital electronic element corresponding to the test element to be tested;
signal comparison means for comparing the signals at the said operative terminals of the test element with the corresponding signals at the respective terminals of the reference element and for producing a fault indication if the comparison indicates the presence of a fault;
means for feeding an input signal at a terminal of the test element from said accessing means to the corresponding terminal of the reference element, and for feeding an output signal at a terminal of the test element to the signal comparison means; and means for feeding an output signal at a terminal of the reference element to the signal comparison means for comparison with the respective output signal from the test element.
2. Apparatus as claimed in claim 1, wherein said library means includes a memory means having therein information as to the operating parameters of the reference element, and said apparatus includes computer means for interrogating the memory means and for subsequently powering the element in accordance with the said information read by the computer means in the memory means.
3. Apparatus as claimed in claim 1, wherein said library means include a plurality of different reference elements and memory means having therein information as to the operating parameters of each of the said reference elements, and the said apparatus includes computer means for interrogating the memory means and subsequently powering a selected reference element in accordance with the said information read by the computer means in the memory means for the selected reference element.
4. Apparatus as claimed in any one of claims 1 to 3, wherein said feeding means feeds an input signal at a terminal of the test element to the corresponding terminal of the reference element, feeds an output signal at a terminal of the test element to the signal comparison means for comparison with the corresponding output signal from the corresponding terminal of the reference element, and prevents the feeding of an output signal at a terminal of the test element to the corresponding terminal of the reference element.
5. Apparatus as claimed in any one of claims 1 to 3, and including external interface means connecting the said accessing means and the remainder of the apparatus, and means for shifting in the external interface means the voltage level of each signal received from the terminals of the test element to make the resulting output signal from the external interface means compatible with the test apparatus.
6. Apparatus as claimed in any one of claims 1 to 3, and including means for supplying a clock signal to the test element via the said accessing means.
7. Apparatus as claimed in any one of claims 1 to 3, and including means for supplying a reset signal to the test element via the said accessing means.
8. Apparatus as claimed in any one of claims 1 to 3, and including an indicator for each terminal which is accessible by the said accessing means, and actuating means for each indicator responsive to an indication of the presence of a fault by the said signal comparison means to actuate the respective indicator.
9. Apparatus as claimed in any one of claims 1 to 3, including timing means for sampling during a first time interval the signals from the terminals of the test element to be tested, for sampling during a second time interval the signals from the terminals of the reference element, and for comparing during a third time interval the said signals from the terminals of the test element and the signals from the terminals of the reference element.
10. Apparatus as claimed in any one of claims 1 to 3, including timing means for sampling during a first time interval the signals from the terminals of the test element to be tested, for sampling during a second time interval the signals from the terminals of the reference element, and for comparing during a third time interval the said signals from the terminals of the test element and the signals from the terminals of the reference element, and wherein the said timing means produce the said first, second and third time intervals during a single clock timing period, and there are provided means for selecting the times of occurrence of the said time intervals during the clock timing period.
11. Apparatus as claimed in any one of claims 1 to 3, wherein the said feeding means comprise switch means for each terminal of the test element and the corresponding terminal of the library element, and means for controlling the said switch means in accordance with the status of each terminal of the test device as an input terminal, an output terminal or bidirectional.
12. Apparatus as claimed in any one of claims 1 to 3, wherein the said feeding means comprise switch means for each terminal of the test element and the corresponding terminal of the library element, and means for controlling the said switch means in accordance with the status of each terminal of the test device as an input terminal, an output terminal or bidirectional, wherein the said controlling means includes means providing signals indicating the status of each terminal of the test: device as an input terminal or an output terminal, and there are provided toggle signal generating means providing a signal to the controlling means for final status of a bidirectional terminal as an input or output terminal.
13. Apparatus as claimed in any one of claims 1 to 3, wherein the said feeding means comprise switch means for each terminal of the test element and the corresponding terminal of the library element, and means for controlling the said switch means in accordance with the status of each terminal of the test device as an input terminal, an output terminal or bidirectional, wherein the said controlling means includes means providing signals indicating the status of each terminal of the test device as an input terminal or an output terminal, and there are provided toggle signal generating means providing a signal to the controlling means for final status of a bidirectional terminal as an input or output terminal, and wherein the said library means includes a logic means having therein information as to the toggle signal required for the reference element, and the said apparatus includes means for powering the reference element and its logic means to generate the said toggle signal.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000358461A CA1163721A (en) | 1980-08-18 | 1980-08-18 | Apparatus for the dynamic in-circuit testing of electronic digital circuit elements |
| US06/291,727 US4484329A (en) | 1980-08-18 | 1981-08-10 | Apparatus for the dynamic in-circuit element-to-element comparison testing of electronic digital circuit elements |
| EP81303755A EP0046404B1 (en) | 1980-08-18 | 1981-08-18 | Apparatus for the dynamic in-circuit testing of electronic digital circuit elements |
| JP56128272A JPS5760269A (en) | 1980-08-18 | 1981-08-18 | Tester for inside of dynamic circuit for electronically digital circuit elements |
| AT81303755T ATE14939T1 (en) | 1980-08-18 | 1981-08-18 | APPARATUS FOR DYNAMIC IN-CIRCUIT KEYING OF ELECTRONIC DIGITAL CIRCUIT ELEMENTS. |
| DE8181303755T DE3171811D1 (en) | 1980-08-18 | 1981-08-18 | Apparatus for the dynamic in-circuit testing of electronic digital circuit elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000358461A CA1163721A (en) | 1980-08-18 | 1980-08-18 | Apparatus for the dynamic in-circuit testing of electronic digital circuit elements |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000444462A Division CA1197323A (en) | 1983-12-29 | 1983-12-29 | Apparatus for the dynamic in-circuit testing of electronic digital circuit elements |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1163721A true CA1163721A (en) | 1984-03-13 |
Family
ID=4117670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000358461A Expired CA1163721A (en) | 1980-08-18 | 1980-08-18 | Apparatus for the dynamic in-circuit testing of electronic digital circuit elements |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4484329A (en) |
| EP (1) | EP0046404B1 (en) |
| JP (1) | JPS5760269A (en) |
| AT (1) | ATE14939T1 (en) |
| CA (1) | CA1163721A (en) |
| DE (1) | DE3171811D1 (en) |
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| US7757144B2 (en) * | 2007-11-01 | 2010-07-13 | Kingtiger Technology (Canada) Inc. | System and method for testing integrated circuit modules comprising a plurality of integrated circuit devices |
| US7848899B2 (en) * | 2008-06-09 | 2010-12-07 | Kingtiger Technology (Canada) Inc. | Systems and methods for testing integrated circuit devices |
| US8356215B2 (en) * | 2010-01-19 | 2013-01-15 | Kingtiger Technology (Canada) Inc. | Testing apparatus and method for analyzing a memory module operating within an application system |
| US8918686B2 (en) | 2010-08-18 | 2014-12-23 | Kingtiger Technology (Canada) Inc. | Determining data valid windows in a system and method for testing an integrated circuit device |
| US9003256B2 (en) | 2011-09-06 | 2015-04-07 | Kingtiger Technology (Canada) Inc. | System and method for testing integrated circuits by determining the solid timing window |
| JP5200198B1 (en) * | 2011-10-03 | 2013-05-15 | パナソニック株式会社 | Operation check support device and operation check support method |
| US8724408B2 (en) | 2011-11-29 | 2014-05-13 | Kingtiger Technology (Canada) Inc. | Systems and methods for testing and assembling memory modules |
| US9117552B2 (en) | 2012-08-28 | 2015-08-25 | Kingtiger Technology(Canada), Inc. | Systems and methods for testing memory |
| US8732630B1 (en) * | 2013-03-15 | 2014-05-20 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language |
| US9501592B1 (en) | 2013-03-15 | 2016-11-22 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language |
| US8949753B1 (en) | 2013-03-15 | 2015-02-03 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language |
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| US3684960A (en) * | 1969-05-15 | 1972-08-15 | Ibm | Probe and guide assembly for testing printed circuit cards |
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| US4290015A (en) * | 1979-10-18 | 1981-09-15 | Fairchild Camera & Instrument Corp. | Electrical validator for a printed circuit board test fixture and a method of validation thereof |
-
1980
- 1980-08-18 CA CA000358461A patent/CA1163721A/en not_active Expired
-
1981
- 1981-08-10 US US06/291,727 patent/US4484329A/en not_active Expired - Fee Related
- 1981-08-18 AT AT81303755T patent/ATE14939T1/en not_active IP Right Cessation
- 1981-08-18 JP JP56128272A patent/JPS5760269A/en active Pending
- 1981-08-18 EP EP81303755A patent/EP0046404B1/en not_active Expired
- 1981-08-18 DE DE8181303755T patent/DE3171811D1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE3171811D1 (en) | 1985-09-19 |
| EP0046404B1 (en) | 1985-08-14 |
| JPS5760269A (en) | 1982-04-12 |
| US4484329A (en) | 1984-11-20 |
| EP0046404A1 (en) | 1982-02-24 |
| ATE14939T1 (en) | 1985-08-15 |
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