CA1165000A - System for processing audio pcm digital signals - Google Patents
System for processing audio pcm digital signalsInfo
- Publication number
- CA1165000A CA1165000A CA000364680A CA364680A CA1165000A CA 1165000 A CA1165000 A CA 1165000A CA 000364680 A CA000364680 A CA 000364680A CA 364680 A CA364680 A CA 364680A CA 1165000 A CA1165000 A CA 1165000A
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- 238000012545 processing Methods 0.000 title claims abstract description 13
- 230000003111 delayed effect Effects 0.000 claims description 10
- 125000004122 cyclic group Chemical group 0.000 claims description 2
- 238000012937 correction Methods 0.000 description 28
- 238000010586 diagram Methods 0.000 description 5
- 230000033458 reproduction Effects 0.000 description 5
- 230000005236 sound signal Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000875 corresponding effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 208000011580 syndromic disease Diseases 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000003935 attention Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- -1 periodO Chemical class 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1806—Pulse code modulation systems for audio signals
- G11B20/1809—Pulse code modulation systems for audio signals by interleaving
Abstract
Abstract of the Disclosure A processing system for reproduced audio digital signals used in an audio PCM (pulse code modulation) recording/reproducing system using a recording/reproducing apparatus such as a video tape recorder having a dropout-compensation circuit is disclosed. The reproduced signal processing system is connected to receive digital information signals repro-duced through the dropout compensation circuit from a recording medium on which audio information signals are recorded in the form of digital data words and includes circuit means for detecting whether a reproduced digital signal is dropout-compensated or not and circuit means for adding an error pointer to a reproduced digital signal which is detected as being dropout-compensated.
Description
t 1~5~0(~
System for Processing Audio PCM Digital Signals The invention relates to a digital signal pro-cessing system and, more porticularly~ to a digital signal processing system used with a reproduction apparatus having a dropout compensation function for reproducing audio information signals recorded on a -recording medium in the form of digital data words together with television synchronizing signals.
A digital audio system for recording and repro-ducing digital audio information in a format like that of a video signal using an existing home-use video tape recorder or a video disk apparatus, has attracted atten-tion recently. The recording/reproducing system, generally called a PCM (pulse code madulation) audio recording/reproducing system, can remarkably improve noise, distortion, wow-flutter and the like. In the system, however, due to scratches of a magnetic tape or a disk or dirts thereon the signal dropouts often occur during a signal reproduction. In preparation for the dropout, the recording/reproducing apparatus such as a video tape recorder is usually provided with a dropout compensation circuit which interpolates a dropped out signal with a signal before one horizontal scanning line. The dropout compensation is based on the fact that a video signal such as a television signal has an extremely high correlation between siynals on adjacent , o~
horizontal scanning lines. Unlike the video signal, however, an audio signal conversely is extremely lo~ in such a correlation. If the technique of the dropout compensation for video signal is applied to the audio signal dropout compensation, a dropped out audio signal is interpolated by a signal which is not correlated to the dropped out signal, leading to signal quality deterioration such as increase in noises.
The PCM recording/reproducing apparatus has an error correction/revision circuit arranged -to detect whether a digital word reproduced is in error or not by an error detecting code, and correct the erroneous word when an error is detected, or revise or conceal the erroneous word by an average value of correct words which are adjacent to the erroneous word and have a high correlation therebetween if the correction is impossible. In the PCM recording/repeoducing system using the above-mentioned recording/reproducing appara-tus having the dropout-compensation circuit, when the signal dropout takes place, the error detection is impossible, since no error is contained in the data word interpolated with the data word before one horizontal line period. Therefore, the error correction/revision circuit cannot revise the 1nterpolated data word as an erroneous data wordO When a dropout-compensated data word is present, there is` a great possibility that the error correction/rivision circuit erroneously corrects other erroneous data. The dropout compensation function of the video tape recorder or the video disk apparatus is almost ineffective for the PCM audio system. For the PCM audio recording/reproducing system using the appara-tus with such a dropout compensation function, it is desirable to be able to detect the dropout compensation and to cause the error correction/rivision circuit to properly correct or revise erroneous data words.
Accordingly, an object of the present invention is to provide a reproduced signal processing system which is used for reproducing an audio information si~nal recorded on a record medium in the form of digital data words by using an reproduction apparatus having a dro-pout~compensating circuit, and enables an error correction/revision circuit to properly operate regardless of the dropout-compensation.
The reproduced digital signal processing system according to the invention is characterized by comprising circuit means for detecting whether a digital audio signal reproduced through the dropout-compensation circuit is dropout-compensated or not, and circuit means for adding an error pointer to a reproduced signal detected as being dropout-compensated.
The dropout-compensation is detected in a manner that a reproduced digital signal is delayed by a time substantially equal to a delay time used in the dropout-compensation and then bit patterns of non-delayed and delayed digital signals are compared with each other.
Advantages provided by the present invention resi-des in that an error correction/revision circuit can properly revise data whose probability of dropout-compensation is great and prevent an erroneous correc-tion of other erroneous data.
This invention can be more fully understood from the following detailed description when taken in con-junction with the accompanying drawings, in which:
Fig. 1 is a diagram useful in explaining the dropout-compensation of data reproduced through a dropout-compensation circuit from a recording emdium;
Fig. 2 is a block diagram of the dropout-compensation circuit used in a conventional video tape recorder;
Fig. 3 is a block diagram of a reproduced digital signal processing system according to an embodiment of this invention;
Fig. 4 is a PCM record data format to ~hich a digi-tal signal processing system according to another ~ ~50()(~
embodiment of this invention is applied;
Fig. 5 is a block diagram of a system for forming the PC~ record data format shown in Fig. 4;
Fig. 6 is a block diagram of a PCM reproducing system including the digital signal processing system of this invention' Fig. 7 is an error pointer signal adding circuit used in the system shown in Fig. 6;
As shown in Fig. 1, PCM signals may be recorded on a recording medium in such a format that eight data words Dl to ~8 (D9 to D16) having the same number of bits, respectively, are followed by error-detecting codes or parity check codes Cl to C8 (C8 to C16) within one horizontal scanning line period (lH period). If the data words D13 and D14 and the error-detecting codes C13 and C14 on the (~+l)th line are dropped out, the data words and the error-detecting codes, respectively, are interpolated with the data words D5 and D6 and the error-detecting codes C5 and C6 on the ~th line before lH period by a dropout-compensating circuit as described later. Accordingly, the data arrangement on the (~l)th line becomes greatly different from the original data arrangement.
For this reason, a PCM reproducing apparatus is required to detect that the data D5 and D6 on the (~+l)th line have been interpolated, and revise those data. In this case, however, the interpolate~ data D5 and D6 are followed by the correct error-detecting codes C5 and C6, with the result that no error is detected.
Therefore, the PCM recording/reproducing apparatus is - desirably constructed to be able to detect the dropout-compensation and revise data whose probability of dropout-compensation is great.
Turning now to Fig. 2, there is shown a dropout compensation circuit which is normally incorporated into existing video tape recorders. The dropout of signals applied to an input terminal 1 is detected by a dropout ,$0~1 detecting circuit 2. When no dropout is det~cted, the signals applied to the input terminal 1 are transferred to an output terminal 4 through a switch circuit 3. On the other hand, when the ~ropout is detected, the switch circuit 3 is switched to allo~ output signals of a lH
delay circuit 5 having an in~ut connected to the output of switch circuit 3 for providing a dela~ time of one horizontal scanning total line period (63.5 ~) to be delivered to the output terminal 4. It will be understood that, through the dropout-compensation cir-cuit, the dropped-out data words D13 and D14 are inter-polated with the data words D5 and D6 before one hori-zontal scanning total line period.
Referring to Fig. 3, there is shown a PCM reproduc-tion apparatus which includes a digital signal pro-cessing system according to an embodiment of this inven-tion and is applied to the data format as shown in Fig.
1. In this figure, reference numeral 11 designates an existing video tape recorder (VTR~ having a dropout-compensation circuit as shown in Fig. 2. The PCM audiorecording/reproducing apparatus may be used in the form of an adaptor for the existing video tape recorder.
The PCM output signal DiCi reproduced by the video tape recorder 11 is supplied through a demodulator cir-cuit 12 to a serial-parallel (S/P) converter 13 where the arrangement of data is converted from a serial form to a parallel form. The output signal DiCi of the demo-dulator 12 is led to a switch circuit 14 where it is separated into a data word Di and an error-detecting code Ci. The data word Di is applied to a parity calcu-lator circuit 15. The parity calculator circuit lS
forms an error-detecting code or a parity bit Ci' on the basis of the data word Di supplied. The error detecting code Ci' is formed so as to be identical with the recorded error-detecting code Ci, when the reproduced data word Di has no error. The error-detecting codes Ci' and Ci are supplied to a comparator circuit 16. As ~ ~50~
a result of the comparison, when the Ci' and Ci are coincident with each other, it is consi~ered that neither the data word Di nor the detecting code Ci is in error, and the comparator circuit 16 produces an output signal Cei of a logical level 0. When the error detecting codes Ci' and Ci are not coincident, it is considered that the data word Di and/or the detecting code Ci is in error, and the comparator circuit 16 pro-duces an output signal Cei of a logical level l. The output signal Cei of the comparator circuit 16 is applied to an OR circuit 17.
An output signal of the S/P converting circuit 13 is applied to a delay circuit 18 where it is delayed by a delay time ~1sed for the dropout-compensation, i.e. a delay time corresponding tc one horizontal scanning line period (lH). The output signal of the ~/P converting circuit 13 is applied to a comparator circuit l9 where it is compared with the delayed output signal from the delay circuit 18.
In the case of audio information, the correlation between samples separated from each other by several words is small. In general two samples separated by one horizontal period are not coincident with each other except those dropout-compensated. When the non-delayed signal and the delayed signal applied to the comparator 19 are not coincident with each other, it may be con sidered that no dropout compensation of signal is made.
In this case, the comparator circuit l9 produces an out-put signal Si of a logical level 0. When the two signals applied to the comparator 18 are coincident with each other, it may be considered that the data word has been subjected to the dropout compensation in a high probabi-lity, that is, the data word is in erro.. In this case, the comparator circuit l9 produces an output signal Si of a logical level l. The output signal Si o~ the comparator circuit l9 is applied to the OR circuit 17 through an AND circuit 20.
The reason why the AND circuit 20 is used follows.
There is a case where digital data wo~ds Gf all 0s are recorded with one horizontal period apart. As a m~tter of course, the data words of all ~s are not dropout-compensated. Also in this conditi~n where data words of all 0s are separated by one horizontal scannig line time, the comparator circuit 19 will produce an output signal of logical level 1 because a coincidence occurs between the two data words of all 0s. In this case, the AND circuit 20 is disabled by an ou-tput signal of logical level 0 of an OR circuit 21 for detecting an all-bit-zero data word. Accordingly, the output signal Si of logical level 1 from the comparator circuit 19 is inhibited from being applied to the OR circuit 17.
It is to be noted that circuits such as the AND circuit 20 and OR circuit 21 are provided so as to inhibit an output signal of logical level 1 produced by the com-parator 19 to a specific state of data words, such as all-bit-zero, from being applied to an error correction circuit through the OR circuit 27 as an error pointer signal.
As seen from the foregoing description, the OR cir-cuit 17 produces an output signal ei of logical level 1 representing the presence of error when a reproduced data word or error-detecting code is in error or when a reproduced data word has been dropout-compensated, and produces an outpu~ signal ei f logical level 0 when no error is contained in a reproduced data word or error-detecting code.
The output signal of the OR circuit 17, together with the output signal DiCi from the S/P converting cir-cuit 13, is applied to an error correction/revision cir-cuit 22. When the error correction control signal or error pointer signal ei from the OR circuit 17, which is to be added to the data word Di from the S/P converter 13, is lo~ (logic level 0), the data word Di is supplied to an output terminal 23 without being subject to 5~ f~
correction or revision. When the control signal ei is high (logic level 1), the data word ~i is applied to the output terminal 23 after being corrected or revised.
The data word taken out from the output terminal 23 is then subjected to digital-to-analog conversion and used to drive a loudspeaker.
As described above, according to the present inven-tion, even when the dropout compensation is made, an error pointer signal may be added to the data word.
The circuit of Fig. 3 may be modified such that the output signals of the AND circuit 20 and the comparator circuit 16 are applied as the revision control signal and the correction control signal to the correction/
revision circuit 22, with no provision of the OR circuit 16. Namely, the correction/revision circuit 22 revises the data when the revision control signal is high, and corrects the erroneous data word when the correction control signal is high.
Recently, a PCM audio recording reproducting system has been standardized in Japan, in which six audio data words and two error-correcting words or parity signals P
and Q, which cooperate to form one data block within one horizontal scanning line period, are subjected to a delay interleaving before being recorded and subjected to a delay deinterleaving after being reproduced.
Through the interleaving and deinterleaving processes, burst errors occurring in one data block may be remarkably reduced.
Fig. 4 illustrates a data assignment to one hori-zontal segment. Interleaved data words An, Bn-3D, Anfl-6D, Bn+1-9D, An+2-12D, Bn+2-15D, Pn-18D, and Qn-21D are each Eormed of 14 bits. A cyclic redundancy check (CRC) code is formed on the basis of the eight data words within one data block and consists of 16 bits. An interval between the adjacent horizontal synchronizing signals HS, that is, the lH period, corresponds to 168 bits. The interleaving of D = 16 blocks (16H) is 50~) equivalent to the word interleaving of 3D = 48 words.
In the Figure, A and B designate audio information on left and right channels, for example.
The formation of the PCM record signal as shown in Fig. 4 will be described referring to Fig. 5. The input signals A and B applied to input terminals 31 and 32 are multiplexed by a multiplexer 33 in a time-sharing manner and then are alternately subjected to an analog~to-digital conversion by an analog-to-digi-tal tA/D) con-verter 34. Each sample of the audio information signalis converted into a digital word of 14 bits. The serial data words derived from the A/D converter 34 are arranged into parallel data words by a S/P converter 35 and subjected to a time-base compression. The S/P con-verter 35 provides three data words for each channel,i.e. six data words An, Bn, An+l, sn+l, An+2 and Bn+2 totally. The data words from the S/P converter 35 are applied to a parity signal forming circuit 36 to form error-correcting words Pn and Qn each consisting of 14 bits.
The output data word An from the S/P converting circuit 35 is directly applied to a parallel-to-serial (P/S) converting circuit 37 while the remaining output data words and the error-correcting words are applied through a delay interleaving circui-t 38 to the P/S con-verting circuit 37. The delay interleaving circuit 38 is so constructed as to provide time delays in incre-ments of a unit delay amount D (= 16H) to the data words Bn, An+l, Bn+l, An+2, Bn+2, Pn and Qn in this order.
Therefore, supplied to the P/S converter 37 are the interleaved data words An, Bn-3D, An+1-6D, Bn+l-9D, An+2-12D, Bn+2-15D, Pn-18D and Qn 21D.
The P/S converting circuit 37 arranges the input data words into a serial form and supplies the serial data words through a switch circuit 39 to a modulation circuit 40 in the order of An, Bn-3D, An+1-6D, Bn~ 9D, An+2-12D, Bn+2-15D, Pn~18D and Qn-21D, and also to a CRC
.
o~) ~ 10 -code forming circuit ~2. After the final output data word Qn-21D from the P/S converting circuit 37 is supplied to the modulatlon circuit 40, the switch cir-cuit 3~ is switched, so that the CRC code of 16 bits generaged by the circuit 42 is supplied to the modula~
tion circuit 40. In this way, one data bloc~ is formed.
In the modulation circui-t 40, the data words are pro-perly combined with television synchronizing signals and then applied through an output terminal 41 to a PCM
recording apparatus such as a home-use video tape recorder to be recorded on a recording medium such as a magnetic tape.
A PC~ audio reproduction system will be described referring to Fig. 6. A PCM signal reproduced from the magnetic tape by the video tape recorder is applied through an input terminal 51 to a wave-shaping circuit 52 where the PCM signal is wave-s~aped and the data words are extracted. The data words are applied to an S/P converting circuit 53 and a block error-detecting circuit 54. The S/P converting circuit 53 arranges eight serial data words An+21D, Bn+18D, An+1+12D, An+2+9D, Bn+2+6D, Pn+3D, and Qn into a parallel form.
The block error-detecting circuit detects a block error on the basis of the CRC code, and produces an error pointer signal Ep which goes high (logical level 1) when an error is detected and goes low (logical level 0) when no error is detected. The output data words from the S/P converting circuit 53 and the error pointer signal Ep from the block error-detecting circuit 54 are supplied to a buffer memory 55 to be subjected to a time-base expansion and jitter absorption. The data words An+21D, Bn+18D, An+1+15D, Bn+1+12D, An+2+9D, Bn+2+6D and Pn+3D from the buffer memory 55 are dein-terleaved by a deinterleaving circuit 56 with a delay characteristic which is complementary to that of the interleaving circuit 38 shown in Fig. 5. Note here that the data words An, Bn, An+l, Bn+l, An+2, and Bn~2 and B ~ V V (~
the error-correcting word Pn frorn the deinterleaving circuit 56 and the error-correcting word Qn from -the buffer memory 55 are the data words and the error-correcting words before interleaved in Fig. 5.
The data words An, Bn, An+l, Bn+1, An+2, ~n+2, and the error-correcting words Pn and Qn are applied to an error-correction/revision control circuit 57 where syndromes are calculated.
The error pointer signal Ep from the buffer memory 55 is supplied to a 7 bit x D delay circuit 58 through an ~R circuit 59. The delay circuit 58 is comprised of seven one-bit delay circuits 58A to 58G each having a delay time o~ D, which are arranged in parallel as shown in Fig. 7. The error pointer signal Ep supplied through the OR circuit 59 is supplied to the delay circuit 58A
and is also used as an error pointer signal QnEp for the error-correcting word Qn.
The delay circuits 58A to 58G are so arranged that an output of a delay circuit is coupled to an input of another delay circuit disposed just above the former as shown. With such a connection, the delay circuits 58A
to 58G may provide error pointer signals, AnEp, BnEp, An+lEp, Bn+lEp, An+2Ep, Bnf2Ep, and PnEp to the seven words An, Bn, An+l, Bn+l, An+2, Bn+2 and Pn concurrently appearing at the outputs of the deinterleaving circuit 56. This indicates that when the block error detecting circuit 54 detects an error in one data block consisting of An+21D, Bn+18D, An~ 15D, Bn+1+12D, An+2+9D, Bn+2+6D, Pn+3D and Qn error pointers are added to the respective words of the data block. The error pointer signals AnEp to QnEp are applied to the error correction/revision control circuit 57 where an error pattern of the words An to Qn is detected.
The audio data words An to Bn+2 from the dein-terleaving circuit 56 are supplied to a multiplexer cir-cuit 61 through a delay circuit 50 which provides a delay time substantially corresponding to the delay time ~ ~e~o~(~
used for the dropout compensation, i.e. lH periodO In practice, the delay time provided b~ the delay cir-cuit 60 is somewhat longer than the lH period due to ~he time-base expansion. In the multiplexer circuit 61, the data words are multiplexed in a time~sharing manner.
The data words multiplexed are sequentially supplied to an error correction/revision circuit ~2.
The error-correcting word Qn is supplied ~rom the bu~er memory 55 to the lH delay circuit 60 and a com-parator circuit 63. The comparator circuit 63 comparesthe error-correcting word Qn with the error-correcting word Qn-3 delayed by the delay circuit 60. As a result of comparison, the comparator 63 produces an output signal Si which goes high when a coincidence occurrs between the bit patterns of the words Qn and Qn-3 and goes low when the coincidence does not occur.
The output signal Si of the comparator 63 is applied to the error correction/revision control circuit 57 and an AND circuit 64 having an output connected to the OR circuit 5gO The AND circuit 64 is enabled or disabled by the error correction/revision control cir-cuit 57.
The error correction/revision control circuit 57 controls the error correction/revision circuit 62 so as to correct or revise one or two data words ha~ing an error on the basis of an error pattern indicated by the error pointer signals AnEp ~ QnEp and syndromes calcu-lated from the words An, Bn, An+l, Bn+l, An+2, Bn~2, Pn and Qn. Since two error-correcting words are used, up to two erroneous data may be corrected. The correction/
revision circuit 62 responds to a correcting data word Dc, an error revision command signal ER and an error correction command signal Ec, which are supplied from the control circuit 57, to correct or rivise the erroneous data word supplied from the multiplexer 61, and supplies error-free data words directly to a utilization circuit.
The erroneo~ls data (indicated by an error pointer 6~0~) signal) is corrected by using the other correct data words, and the error-correcting words Pn and/or Qn.
Accordingly, in correcting data words it is necessary to check an output state of the compariator circuit 63.
Suppose now that an erroneous data word or words among the data words An to Bn~-2 are indicated by an error pointer signal or signals and QnEp - 0 (the error-correcting word Qn is not in error). ~nder this con-dition, when the output signal Si of comparator 63 is low there arises no problem even if the erroneous data is corrected using the error-correcting ~ord Qn. On the other hand, when the output signal Si of the comparator - 63 is high, the error-correcting word Qn has been possibly dropout-compensated and therefore if the erro-neous data is corrected using the correcting word Qn, an erroneous correction will be made. However, in the pre-sent invention, the control circuit 57 is responsive to the output state of the comparator 63 to cause the error correction/revision circuit 62 to revise the erroneous data word instead of correcting it. Thus, in such a case, the control circuit 57 enables the ~D circuit 6~, so that the output signal Si of logical level l from the comparator 63 is supplied through the OR circuit i9 to the delay circuit 58. In other words, error pointers may be added to the other data words in a data block in which the dropout-compensated error-correcting word Qn is included for the purpose of subsequent correction or revision of the other data words.
System for Processing Audio PCM Digital Signals The invention relates to a digital signal pro-cessing system and, more porticularly~ to a digital signal processing system used with a reproduction apparatus having a dropout compensation function for reproducing audio information signals recorded on a -recording medium in the form of digital data words together with television synchronizing signals.
A digital audio system for recording and repro-ducing digital audio information in a format like that of a video signal using an existing home-use video tape recorder or a video disk apparatus, has attracted atten-tion recently. The recording/reproducing system, generally called a PCM (pulse code madulation) audio recording/reproducing system, can remarkably improve noise, distortion, wow-flutter and the like. In the system, however, due to scratches of a magnetic tape or a disk or dirts thereon the signal dropouts often occur during a signal reproduction. In preparation for the dropout, the recording/reproducing apparatus such as a video tape recorder is usually provided with a dropout compensation circuit which interpolates a dropped out signal with a signal before one horizontal scanning line. The dropout compensation is based on the fact that a video signal such as a television signal has an extremely high correlation between siynals on adjacent , o~
horizontal scanning lines. Unlike the video signal, however, an audio signal conversely is extremely lo~ in such a correlation. If the technique of the dropout compensation for video signal is applied to the audio signal dropout compensation, a dropped out audio signal is interpolated by a signal which is not correlated to the dropped out signal, leading to signal quality deterioration such as increase in noises.
The PCM recording/reproducing apparatus has an error correction/revision circuit arranged -to detect whether a digital word reproduced is in error or not by an error detecting code, and correct the erroneous word when an error is detected, or revise or conceal the erroneous word by an average value of correct words which are adjacent to the erroneous word and have a high correlation therebetween if the correction is impossible. In the PCM recording/repeoducing system using the above-mentioned recording/reproducing appara-tus having the dropout-compensation circuit, when the signal dropout takes place, the error detection is impossible, since no error is contained in the data word interpolated with the data word before one horizontal line period. Therefore, the error correction/revision circuit cannot revise the 1nterpolated data word as an erroneous data wordO When a dropout-compensated data word is present, there is` a great possibility that the error correction/rivision circuit erroneously corrects other erroneous data. The dropout compensation function of the video tape recorder or the video disk apparatus is almost ineffective for the PCM audio system. For the PCM audio recording/reproducing system using the appara-tus with such a dropout compensation function, it is desirable to be able to detect the dropout compensation and to cause the error correction/rivision circuit to properly correct or revise erroneous data words.
Accordingly, an object of the present invention is to provide a reproduced signal processing system which is used for reproducing an audio information si~nal recorded on a record medium in the form of digital data words by using an reproduction apparatus having a dro-pout~compensating circuit, and enables an error correction/revision circuit to properly operate regardless of the dropout-compensation.
The reproduced digital signal processing system according to the invention is characterized by comprising circuit means for detecting whether a digital audio signal reproduced through the dropout-compensation circuit is dropout-compensated or not, and circuit means for adding an error pointer to a reproduced signal detected as being dropout-compensated.
The dropout-compensation is detected in a manner that a reproduced digital signal is delayed by a time substantially equal to a delay time used in the dropout-compensation and then bit patterns of non-delayed and delayed digital signals are compared with each other.
Advantages provided by the present invention resi-des in that an error correction/revision circuit can properly revise data whose probability of dropout-compensation is great and prevent an erroneous correc-tion of other erroneous data.
This invention can be more fully understood from the following detailed description when taken in con-junction with the accompanying drawings, in which:
Fig. 1 is a diagram useful in explaining the dropout-compensation of data reproduced through a dropout-compensation circuit from a recording emdium;
Fig. 2 is a block diagram of the dropout-compensation circuit used in a conventional video tape recorder;
Fig. 3 is a block diagram of a reproduced digital signal processing system according to an embodiment of this invention;
Fig. 4 is a PCM record data format to ~hich a digi-tal signal processing system according to another ~ ~50()(~
embodiment of this invention is applied;
Fig. 5 is a block diagram of a system for forming the PC~ record data format shown in Fig. 4;
Fig. 6 is a block diagram of a PCM reproducing system including the digital signal processing system of this invention' Fig. 7 is an error pointer signal adding circuit used in the system shown in Fig. 6;
As shown in Fig. 1, PCM signals may be recorded on a recording medium in such a format that eight data words Dl to ~8 (D9 to D16) having the same number of bits, respectively, are followed by error-detecting codes or parity check codes Cl to C8 (C8 to C16) within one horizontal scanning line period (lH period). If the data words D13 and D14 and the error-detecting codes C13 and C14 on the (~+l)th line are dropped out, the data words and the error-detecting codes, respectively, are interpolated with the data words D5 and D6 and the error-detecting codes C5 and C6 on the ~th line before lH period by a dropout-compensating circuit as described later. Accordingly, the data arrangement on the (~l)th line becomes greatly different from the original data arrangement.
For this reason, a PCM reproducing apparatus is required to detect that the data D5 and D6 on the (~+l)th line have been interpolated, and revise those data. In this case, however, the interpolate~ data D5 and D6 are followed by the correct error-detecting codes C5 and C6, with the result that no error is detected.
Therefore, the PCM recording/reproducing apparatus is - desirably constructed to be able to detect the dropout-compensation and revise data whose probability of dropout-compensation is great.
Turning now to Fig. 2, there is shown a dropout compensation circuit which is normally incorporated into existing video tape recorders. The dropout of signals applied to an input terminal 1 is detected by a dropout ,$0~1 detecting circuit 2. When no dropout is det~cted, the signals applied to the input terminal 1 are transferred to an output terminal 4 through a switch circuit 3. On the other hand, when the ~ropout is detected, the switch circuit 3 is switched to allo~ output signals of a lH
delay circuit 5 having an in~ut connected to the output of switch circuit 3 for providing a dela~ time of one horizontal scanning total line period (63.5 ~) to be delivered to the output terminal 4. It will be understood that, through the dropout-compensation cir-cuit, the dropped-out data words D13 and D14 are inter-polated with the data words D5 and D6 before one hori-zontal scanning total line period.
Referring to Fig. 3, there is shown a PCM reproduc-tion apparatus which includes a digital signal pro-cessing system according to an embodiment of this inven-tion and is applied to the data format as shown in Fig.
1. In this figure, reference numeral 11 designates an existing video tape recorder (VTR~ having a dropout-compensation circuit as shown in Fig. 2. The PCM audiorecording/reproducing apparatus may be used in the form of an adaptor for the existing video tape recorder.
The PCM output signal DiCi reproduced by the video tape recorder 11 is supplied through a demodulator cir-cuit 12 to a serial-parallel (S/P) converter 13 where the arrangement of data is converted from a serial form to a parallel form. The output signal DiCi of the demo-dulator 12 is led to a switch circuit 14 where it is separated into a data word Di and an error-detecting code Ci. The data word Di is applied to a parity calcu-lator circuit 15. The parity calculator circuit lS
forms an error-detecting code or a parity bit Ci' on the basis of the data word Di supplied. The error detecting code Ci' is formed so as to be identical with the recorded error-detecting code Ci, when the reproduced data word Di has no error. The error-detecting codes Ci' and Ci are supplied to a comparator circuit 16. As ~ ~50~
a result of the comparison, when the Ci' and Ci are coincident with each other, it is consi~ered that neither the data word Di nor the detecting code Ci is in error, and the comparator circuit 16 produces an output signal Cei of a logical level 0. When the error detecting codes Ci' and Ci are not coincident, it is considered that the data word Di and/or the detecting code Ci is in error, and the comparator circuit 16 pro-duces an output signal Cei of a logical level l. The output signal Cei of the comparator circuit 16 is applied to an OR circuit 17.
An output signal of the S/P converting circuit 13 is applied to a delay circuit 18 where it is delayed by a delay time ~1sed for the dropout-compensation, i.e. a delay time corresponding tc one horizontal scanning line period (lH). The output signal of the ~/P converting circuit 13 is applied to a comparator circuit l9 where it is compared with the delayed output signal from the delay circuit 18.
In the case of audio information, the correlation between samples separated from each other by several words is small. In general two samples separated by one horizontal period are not coincident with each other except those dropout-compensated. When the non-delayed signal and the delayed signal applied to the comparator 19 are not coincident with each other, it may be con sidered that no dropout compensation of signal is made.
In this case, the comparator circuit l9 produces an out-put signal Si of a logical level 0. When the two signals applied to the comparator 18 are coincident with each other, it may be considered that the data word has been subjected to the dropout compensation in a high probabi-lity, that is, the data word is in erro.. In this case, the comparator circuit l9 produces an output signal Si of a logical level l. The output signal Si o~ the comparator circuit l9 is applied to the OR circuit 17 through an AND circuit 20.
The reason why the AND circuit 20 is used follows.
There is a case where digital data wo~ds Gf all 0s are recorded with one horizontal period apart. As a m~tter of course, the data words of all ~s are not dropout-compensated. Also in this conditi~n where data words of all 0s are separated by one horizontal scannig line time, the comparator circuit 19 will produce an output signal of logical level 1 because a coincidence occurs between the two data words of all 0s. In this case, the AND circuit 20 is disabled by an ou-tput signal of logical level 0 of an OR circuit 21 for detecting an all-bit-zero data word. Accordingly, the output signal Si of logical level 1 from the comparator circuit 19 is inhibited from being applied to the OR circuit 17.
It is to be noted that circuits such as the AND circuit 20 and OR circuit 21 are provided so as to inhibit an output signal of logical level 1 produced by the com-parator 19 to a specific state of data words, such as all-bit-zero, from being applied to an error correction circuit through the OR circuit 27 as an error pointer signal.
As seen from the foregoing description, the OR cir-cuit 17 produces an output signal ei of logical level 1 representing the presence of error when a reproduced data word or error-detecting code is in error or when a reproduced data word has been dropout-compensated, and produces an outpu~ signal ei f logical level 0 when no error is contained in a reproduced data word or error-detecting code.
The output signal of the OR circuit 17, together with the output signal DiCi from the S/P converting cir-cuit 13, is applied to an error correction/revision cir-cuit 22. When the error correction control signal or error pointer signal ei from the OR circuit 17, which is to be added to the data word Di from the S/P converter 13, is lo~ (logic level 0), the data word Di is supplied to an output terminal 23 without being subject to 5~ f~
correction or revision. When the control signal ei is high (logic level 1), the data word ~i is applied to the output terminal 23 after being corrected or revised.
The data word taken out from the output terminal 23 is then subjected to digital-to-analog conversion and used to drive a loudspeaker.
As described above, according to the present inven-tion, even when the dropout compensation is made, an error pointer signal may be added to the data word.
The circuit of Fig. 3 may be modified such that the output signals of the AND circuit 20 and the comparator circuit 16 are applied as the revision control signal and the correction control signal to the correction/
revision circuit 22, with no provision of the OR circuit 16. Namely, the correction/revision circuit 22 revises the data when the revision control signal is high, and corrects the erroneous data word when the correction control signal is high.
Recently, a PCM audio recording reproducting system has been standardized in Japan, in which six audio data words and two error-correcting words or parity signals P
and Q, which cooperate to form one data block within one horizontal scanning line period, are subjected to a delay interleaving before being recorded and subjected to a delay deinterleaving after being reproduced.
Through the interleaving and deinterleaving processes, burst errors occurring in one data block may be remarkably reduced.
Fig. 4 illustrates a data assignment to one hori-zontal segment. Interleaved data words An, Bn-3D, Anfl-6D, Bn+1-9D, An+2-12D, Bn+2-15D, Pn-18D, and Qn-21D are each Eormed of 14 bits. A cyclic redundancy check (CRC) code is formed on the basis of the eight data words within one data block and consists of 16 bits. An interval between the adjacent horizontal synchronizing signals HS, that is, the lH period, corresponds to 168 bits. The interleaving of D = 16 blocks (16H) is 50~) equivalent to the word interleaving of 3D = 48 words.
In the Figure, A and B designate audio information on left and right channels, for example.
The formation of the PCM record signal as shown in Fig. 4 will be described referring to Fig. 5. The input signals A and B applied to input terminals 31 and 32 are multiplexed by a multiplexer 33 in a time-sharing manner and then are alternately subjected to an analog~to-digital conversion by an analog-to-digi-tal tA/D) con-verter 34. Each sample of the audio information signalis converted into a digital word of 14 bits. The serial data words derived from the A/D converter 34 are arranged into parallel data words by a S/P converter 35 and subjected to a time-base compression. The S/P con-verter 35 provides three data words for each channel,i.e. six data words An, Bn, An+l, sn+l, An+2 and Bn+2 totally. The data words from the S/P converter 35 are applied to a parity signal forming circuit 36 to form error-correcting words Pn and Qn each consisting of 14 bits.
The output data word An from the S/P converting circuit 35 is directly applied to a parallel-to-serial (P/S) converting circuit 37 while the remaining output data words and the error-correcting words are applied through a delay interleaving circui-t 38 to the P/S con-verting circuit 37. The delay interleaving circuit 38 is so constructed as to provide time delays in incre-ments of a unit delay amount D (= 16H) to the data words Bn, An+l, Bn+l, An+2, Bn+2, Pn and Qn in this order.
Therefore, supplied to the P/S converter 37 are the interleaved data words An, Bn-3D, An+1-6D, Bn+l-9D, An+2-12D, Bn+2-15D, Pn-18D and Qn 21D.
The P/S converting circuit 37 arranges the input data words into a serial form and supplies the serial data words through a switch circuit 39 to a modulation circuit 40 in the order of An, Bn-3D, An+1-6D, Bn~ 9D, An+2-12D, Bn+2-15D, Pn~18D and Qn-21D, and also to a CRC
.
o~) ~ 10 -code forming circuit ~2. After the final output data word Qn-21D from the P/S converting circuit 37 is supplied to the modulatlon circuit 40, the switch cir-cuit 3~ is switched, so that the CRC code of 16 bits generaged by the circuit 42 is supplied to the modula~
tion circuit 40. In this way, one data bloc~ is formed.
In the modulation circui-t 40, the data words are pro-perly combined with television synchronizing signals and then applied through an output terminal 41 to a PCM
recording apparatus such as a home-use video tape recorder to be recorded on a recording medium such as a magnetic tape.
A PC~ audio reproduction system will be described referring to Fig. 6. A PCM signal reproduced from the magnetic tape by the video tape recorder is applied through an input terminal 51 to a wave-shaping circuit 52 where the PCM signal is wave-s~aped and the data words are extracted. The data words are applied to an S/P converting circuit 53 and a block error-detecting circuit 54. The S/P converting circuit 53 arranges eight serial data words An+21D, Bn+18D, An+1+12D, An+2+9D, Bn+2+6D, Pn+3D, and Qn into a parallel form.
The block error-detecting circuit detects a block error on the basis of the CRC code, and produces an error pointer signal Ep which goes high (logical level 1) when an error is detected and goes low (logical level 0) when no error is detected. The output data words from the S/P converting circuit 53 and the error pointer signal Ep from the block error-detecting circuit 54 are supplied to a buffer memory 55 to be subjected to a time-base expansion and jitter absorption. The data words An+21D, Bn+18D, An+1+15D, Bn+1+12D, An+2+9D, Bn+2+6D and Pn+3D from the buffer memory 55 are dein-terleaved by a deinterleaving circuit 56 with a delay characteristic which is complementary to that of the interleaving circuit 38 shown in Fig. 5. Note here that the data words An, Bn, An+l, Bn+l, An+2, and Bn~2 and B ~ V V (~
the error-correcting word Pn frorn the deinterleaving circuit 56 and the error-correcting word Qn from -the buffer memory 55 are the data words and the error-correcting words before interleaved in Fig. 5.
The data words An, Bn, An+l, Bn+1, An+2, ~n+2, and the error-correcting words Pn and Qn are applied to an error-correction/revision control circuit 57 where syndromes are calculated.
The error pointer signal Ep from the buffer memory 55 is supplied to a 7 bit x D delay circuit 58 through an ~R circuit 59. The delay circuit 58 is comprised of seven one-bit delay circuits 58A to 58G each having a delay time o~ D, which are arranged in parallel as shown in Fig. 7. The error pointer signal Ep supplied through the OR circuit 59 is supplied to the delay circuit 58A
and is also used as an error pointer signal QnEp for the error-correcting word Qn.
The delay circuits 58A to 58G are so arranged that an output of a delay circuit is coupled to an input of another delay circuit disposed just above the former as shown. With such a connection, the delay circuits 58A
to 58G may provide error pointer signals, AnEp, BnEp, An+lEp, Bn+lEp, An+2Ep, Bnf2Ep, and PnEp to the seven words An, Bn, An+l, Bn+l, An+2, Bn+2 and Pn concurrently appearing at the outputs of the deinterleaving circuit 56. This indicates that when the block error detecting circuit 54 detects an error in one data block consisting of An+21D, Bn+18D, An~ 15D, Bn+1+12D, An+2+9D, Bn+2+6D, Pn+3D and Qn error pointers are added to the respective words of the data block. The error pointer signals AnEp to QnEp are applied to the error correction/revision control circuit 57 where an error pattern of the words An to Qn is detected.
The audio data words An to Bn+2 from the dein-terleaving circuit 56 are supplied to a multiplexer cir-cuit 61 through a delay circuit 50 which provides a delay time substantially corresponding to the delay time ~ ~e~o~(~
used for the dropout compensation, i.e. lH periodO In practice, the delay time provided b~ the delay cir-cuit 60 is somewhat longer than the lH period due to ~he time-base expansion. In the multiplexer circuit 61, the data words are multiplexed in a time~sharing manner.
The data words multiplexed are sequentially supplied to an error correction/revision circuit ~2.
The error-correcting word Qn is supplied ~rom the bu~er memory 55 to the lH delay circuit 60 and a com-parator circuit 63. The comparator circuit 63 comparesthe error-correcting word Qn with the error-correcting word Qn-3 delayed by the delay circuit 60. As a result of comparison, the comparator 63 produces an output signal Si which goes high when a coincidence occurrs between the bit patterns of the words Qn and Qn-3 and goes low when the coincidence does not occur.
The output signal Si of the comparator 63 is applied to the error correction/revision control circuit 57 and an AND circuit 64 having an output connected to the OR circuit 5gO The AND circuit 64 is enabled or disabled by the error correction/revision control cir-cuit 57.
The error correction/revision control circuit 57 controls the error correction/revision circuit 62 so as to correct or revise one or two data words ha~ing an error on the basis of an error pattern indicated by the error pointer signals AnEp ~ QnEp and syndromes calcu-lated from the words An, Bn, An+l, Bn+l, An+2, Bn~2, Pn and Qn. Since two error-correcting words are used, up to two erroneous data may be corrected. The correction/
revision circuit 62 responds to a correcting data word Dc, an error revision command signal ER and an error correction command signal Ec, which are supplied from the control circuit 57, to correct or rivise the erroneous data word supplied from the multiplexer 61, and supplies error-free data words directly to a utilization circuit.
The erroneo~ls data (indicated by an error pointer 6~0~) signal) is corrected by using the other correct data words, and the error-correcting words Pn and/or Qn.
Accordingly, in correcting data words it is necessary to check an output state of the compariator circuit 63.
Suppose now that an erroneous data word or words among the data words An to Bn~-2 are indicated by an error pointer signal or signals and QnEp - 0 (the error-correcting word Qn is not in error). ~nder this con-dition, when the output signal Si of comparator 63 is low there arises no problem even if the erroneous data is corrected using the error-correcting ~ord Qn. On the other hand, when the output signal Si of the comparator - 63 is high, the error-correcting word Qn has been possibly dropout-compensated and therefore if the erro-neous data is corrected using the correcting word Qn, an erroneous correction will be made. However, in the pre-sent invention, the control circuit 57 is responsive to the output state of the comparator 63 to cause the error correction/revision circuit 62 to revise the erroneous data word instead of correcting it. Thus, in such a case, the control circuit 57 enables the ~D circuit 6~, so that the output signal Si of logical level l from the comparator 63 is supplied through the OR circuit i9 to the delay circuit 58. In other words, error pointers may be added to the other data words in a data block in which the dropout-compensated error-correcting word Qn is included for the purpose of subsequent correction or revision of the other data words.
Claims (4)
1. A reproduced digital audio information signal processing system used with a reproducing system having a dropout compensation circuit for reproducing audio information signals recorded on a recording medium in the form of digital data words through said dropout com-pensation circuit comprising:
dropout compensation detecting means for detecting whether a said reproduced digital signal is dropout-compensated or not; and means responsive to said dropout detected means to add an error pointer signal to reproduced digital signal when said reproduced digital signal is detecting as being dropout-compensated.
dropout compensation detecting means for detecting whether a said reproduced digital signal is dropout-compensated or not; and means responsive to said dropout detected means to add an error pointer signal to reproduced digital signal when said reproduced digital signal is detecting as being dropout-compensated.
2. A system according to claim 1, wherein said dropout compensation detecting means includes a delay circuit for delaying a reproduced digital signal by a delay time used in the dropout compensation, and a com-parator circuit for comparing the reproduced digital signal delayed by said delay circuit with the reproduced digital signal before being delayed.
3. A system according to claim 2, wherein said delay time is substantially equal to one horizontal scanning total line time in a television signal.
4. A PCM recording/reproducing system in which a plurality of digital words delay-interleaved and a cyclic redundancy check code formed on the basis of the digital words are recorded on a recording medium in one data block, the data block is reproduced through a dro-pout compensation circuit, and the digital words repro-duced are delay-deinterleaved, said system comprising:
dropout compensation detecting means for detecting whether a data block is dropout-compensated or not on the basis of one data word in the reproduced data block; and means responsive to said dropout compensation detecting means to add an error pointer signal to the remaining data words within said data block when said data word is as being dropout-compensated.
dropout compensation detecting means for detecting whether a data block is dropout-compensated or not on the basis of one data word in the reproduced data block; and means responsive to said dropout compensation detecting means to add an error pointer signal to the remaining data words within said data block when said data word is as being dropout-compensated.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP147663/79 | 1979-11-16 | ||
| JP54147663A JPS5815843B2 (en) | 1979-11-16 | 1979-11-16 | Playback signal processing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1165000A true CA1165000A (en) | 1984-04-03 |
Family
ID=15435446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000364680A Expired CA1165000A (en) | 1979-11-16 | 1980-11-14 | System for processing audio pcm digital signals |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4403263A (en) |
| EP (1) | EP0029226B1 (en) |
| JP (1) | JPS5815843B2 (en) |
| CA (1) | CA1165000A (en) |
| DE (1) | DE3068721D1 (en) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56105310A (en) * | 1980-01-22 | 1981-08-21 | Akai Electric Co Ltd | Pcm signal processing device |
| DE3022541A1 (en) * | 1980-06-16 | 1982-01-07 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | SYSTEM FOR PROCESSING AND TRANSMITTING PCM SIGNALS |
| JPS5753806A (en) * | 1980-09-16 | 1982-03-31 | Toshiba Corp | Processor of digital signal |
| JPS5753807A (en) * | 1980-09-16 | 1982-03-31 | Toshiba Corp | Processsor of digital signal |
| JPS5760576A (en) * | 1980-09-26 | 1982-04-12 | Hitachi Ltd | Pcm recorder |
| JPS5792411A (en) * | 1980-11-28 | 1982-06-09 | Sony Corp | Pcm signal processor |
| JPS5837809A (en) * | 1981-08-28 | 1983-03-05 | Matsushita Electric Ind Co Ltd | Pcm sound recorder and reproducer |
| JPS5845613A (en) * | 1981-09-11 | 1983-03-16 | Hitachi Ltd | Pulse code modulation recorder |
| JPS5885909A (en) * | 1981-11-14 | 1983-05-23 | Sony Corp | Disk player |
| JPS58188307A (en) * | 1982-04-27 | 1983-11-02 | Matsushita Electric Ind Co Ltd | Recorder and reproducer |
| JPS59140738A (en) * | 1983-01-31 | 1984-08-13 | Sony Corp | Processor for pcm signal |
| JPS6084038A (en) * | 1983-05-31 | 1985-05-13 | Fujitsu Ltd | Code error control system |
| JPS60132551U (en) * | 1984-02-09 | 1985-09-04 | 株式会社コロナ | Pot type oil combustion device |
| US4689022A (en) * | 1984-04-30 | 1987-08-25 | John Peers | System for control of a video storage means by a programmed processor |
| JPS6169286A (en) * | 1984-09-13 | 1986-04-09 | Sony Corp | Drop-out compensating device |
| AU604807B2 (en) * | 1986-12-19 | 1991-01-03 | Sony Corporation | Data recorder and method |
| US4943865A (en) * | 1987-10-08 | 1990-07-24 | The Boeing Company | Method and system for recording standard pulse code modulated serial data using video signal recorders |
| DE3888126T2 (en) * | 1987-12-14 | 1994-08-18 | Sony Corp | Device and method for recording a digital signal. |
| US5218454A (en) * | 1989-03-28 | 1993-06-08 | Canon Kabushiki Kaisha | Apparatus for improved recording of signals having video and audio components |
| US5172363A (en) * | 1989-04-13 | 1992-12-15 | Philip Greenspun | Method and apparatus for automatic recording of marker during information recording |
| JP2553743B2 (en) * | 1990-07-05 | 1996-11-13 | 松下電器産業株式会社 | Digital signal magnetic recording / reproducing device |
| US5222069A (en) * | 1990-09-20 | 1993-06-22 | Ampex Systems Corporation | Miscorrection arrangement for the concealment of misdetected or miscorrected digital signals |
| US5491702A (en) * | 1992-07-22 | 1996-02-13 | Silicon Graphics, Inc. | Apparatus for detecting any single bit error, detecting any two bit error, and detecting any three or four bit error in a group of four bits for a 25- or 64-bit data word |
| US6047036A (en) * | 1997-05-02 | 2000-04-04 | Advanced Micro Devices, Inc. | System and method for implementing a mute voice signal upon reception of a ADPCM zero nibble in wireless communications |
| WO2012073071A1 (en) * | 2010-12-02 | 2012-06-07 | Freescale Semiconductor, Inc. | Error correcting device, method for monitoring an error correcting device and data processing system |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3639900A (en) * | 1970-05-27 | 1972-02-01 | Ibm | Enhanced error detection and correction for data systems |
| US3774154A (en) * | 1972-08-21 | 1973-11-20 | Ibm | Error control circuits and methods |
| JPS5529482B2 (en) * | 1974-04-01 | 1980-08-04 | ||
| US3982226A (en) * | 1975-04-03 | 1976-09-21 | Storage Technology Corporation | Means and method for error detection and correction of digital data |
| US3958220A (en) * | 1975-05-30 | 1976-05-18 | International Business Machines Corporation | Enhanced error correction |
| US4146099A (en) * | 1976-08-17 | 1979-03-27 | Christopher Scientific Company | Signal recording method and apparatus |
| GB1599156A (en) * | 1976-12-24 | 1981-09-30 | Indep Broadcasting Authority | Recording digital signals |
| JPS53142208A (en) * | 1977-05-18 | 1978-12-11 | Teac Corp | Method of recording pcm signal |
| JPS6025818B2 (en) * | 1977-11-21 | 1985-06-20 | 株式会社日立製作所 | PCM recorder |
| US4281355A (en) * | 1978-02-01 | 1981-07-28 | Matsushita Electric Industrial Co., Ltd. | Digital audio signal recorder |
| JPS54137204A (en) * | 1978-04-17 | 1979-10-24 | Sony Corp | Digital signal transmission method |
-
1979
- 1979-11-16 JP JP54147663A patent/JPS5815843B2/en not_active Expired
-
1980
- 1980-11-13 DE DE8080107015T patent/DE3068721D1/en not_active Expired
- 1980-11-13 EP EP80107015A patent/EP0029226B1/en not_active Expired
- 1980-11-14 US US06/206,833 patent/US4403263A/en not_active Expired - Lifetime
- 1980-11-14 CA CA000364680A patent/CA1165000A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5815843B2 (en) | 1983-03-28 |
| EP0029226B1 (en) | 1984-07-25 |
| US4403263A (en) | 1983-09-06 |
| EP0029226A1 (en) | 1981-05-27 |
| JPS5671808A (en) | 1981-06-15 |
| DE3068721D1 (en) | 1984-08-30 |
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