CA1169596A - Solid-state imaging device - Google Patents
Solid-state imaging deviceInfo
- Publication number
- CA1169596A CA1169596A CA000376105A CA376105A CA1169596A CA 1169596 A CA1169596 A CA 1169596A CA 000376105 A CA000376105 A CA 000376105A CA 376105 A CA376105 A CA 376105A CA 1169596 A CA1169596 A CA 1169596A
- Authority
- CA
- Canada
- Prior art keywords
- switching elements
- vertical
- scanning
- circuit
- pulses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000003384 imaging method Methods 0.000 title claims abstract description 10
- 230000005669 field effect Effects 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract 2
- 230000000694 effects Effects 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 6
- 239000000969 carrier Substances 0.000 description 3
- AMHIJMKZPBMCKI-PKLGAXGESA-N ctds Chemical compound O[C@@H]1[C@@H](OS(O)(=O)=O)[C@@H]2O[C@H](COS(O)(=O)=O)[C@H]1O[C@H]([C@@H]([C@H]1OS(O)(=O)=O)OS(O)(=O)=O)O[C@H](CO)[C@H]1O[C@@H](O[C@@H]1CO)[C@H](OS(O)(=O)=O)[C@@H](OS(O)(=O)=O)[C@@H]1O[C@@H](O[C@@H]1CO)[C@H](OS(O)(=O)=O)[C@@H](OS(O)(=O)=O)[C@@H]1O[C@@H](O[C@@H]1CO)[C@H](OS(O)(=O)=O)[C@@H](OS(O)(=O)=O)[C@@H]1O[C@@H](O[C@@H]1CO)[C@H](OS(O)(=O)=O)[C@@H](OS(O)(=O)=O)[C@@H]1O[C@@H](O[C@@H]1CO)[C@H](OS(O)(=O)=O)[C@@H](OS(O)(=O)=O)[C@@H]1O2 AMHIJMKZPBMCKI-PKLGAXGESA-N 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 206010010099 Combined immunodeficiency Diseases 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000001360 collision-induced dissociation Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- PNDPGZBMCMUPRI-UHFFFAOYSA-N iodine Chemical compound II PNDPGZBMCMUPRI-UHFFFAOYSA-N 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
Abstract
Abstract:
A solid-state imaging device has a plurality of photodiodes arrayed in two dimensions on an identical semiconductor body. A group of horizontal switching elements and a group of vertical switching elements pick up the photodiodes. A horizontal scanning circuit and a vertical scanning circuit impress scanning pulses on the horizontal and vertical switching elements respec-tively. An interlaced scanning mechanism picks up a plurality of vertical scanning lines by means of inter-lace switching elements so as to permit horizontal scanning of scanning lines of a plurality of rows. The device is characterized in that the interlaced scanning mechanism includes insulated-gate field effect transistors for recovering voltage levels of the scanning pulses having undergone voltage drops due to the interlace switching elements. The result is enhancement of the dynamic range of the device.
A solid-state imaging device has a plurality of photodiodes arrayed in two dimensions on an identical semiconductor body. A group of horizontal switching elements and a group of vertical switching elements pick up the photodiodes. A horizontal scanning circuit and a vertical scanning circuit impress scanning pulses on the horizontal and vertical switching elements respec-tively. An interlaced scanning mechanism picks up a plurality of vertical scanning lines by means of inter-lace switching elements so as to permit horizontal scanning of scanning lines of a plurality of rows. The device is characterized in that the interlaced scanning mechanism includes insulated-gate field effect transistors for recovering voltage levels of the scanning pulses having undergone voltage drops due to the interlace switching elements. The result is enhancement of the dynamic range of the device.
Description
I J 6959~
Solid-state imaging device ~, This invention relates to a solid-state imaging device, and more particularly to means for enhancing the dynamic range of such a device.
To enable the prior art to be explained with the aid of a diagram, all the figures of drawing will first ~e described.
Figure 1 is a schematic circuit diagram showing the construction of a prior-art, MOS type solid-state imaging device, Figure 2 i5 a schematic circuit diagram showing an example of an interlace circuit in Figure 1, Figure 3 is a circuit block diagram showing an : embodiment of a solid-state imaging device of thls invention, Figure 4 is a schematic circuit diagram showing an example of an interlace circuit as well as a vertical buffer circuit in Figure 3, and Figure 5 is a pulse timing chart showing pulses at various nodes and vertical buffer circuit-control pulses ~Bl and ~B2 in Figure 4- .
Figure 1 shows a typical example of a prior-art solid-state imaging device (hereinbelow, termed "photo-sensor"). It illustrates the fundamental circuit arrangement of a MOS-type photosensor in which picture elements employing insulated-gate field effect transistors (hereinbelow, termed "MOSTs") as vertical switching ' , ~ .
~ J 6959G
elements and employing the source junctions of the MOSTs as photodiodes are arrayed in the form of a matrix. Numeral 1 designates a shift register which serves as a horizontal scanning circuit, numeral 2 a shift register which serves as a vertical scanning circuit, numeral 3 an interlace circuit, numeral 4 a vertical scanning line (vertical gate line) for addressing in the Y direction, numeral 5 a photogate which serves as a vertical switching elernent, numeral 6 a photodiode, numeral 7 a vertical signal output line, numeral 8 a horizontal switching element for execut-ing sequential addressing in the X direction with an output from the horizontal shift register 1, numeral 10 a'horizontal signal output line, numeral 11 output terminals, and numeral 12 a region of a photodiode array.
Figure 2 shows a specific example of the interlace circuit indicated at 3 in Figure 1. Numeral 21 designates the vertical shift register, numeral 22 the interlacl~
circuit, and numeral 23 the region of the photo~iode array.
The operation o-E the circuitry in Figure 2 will now be described. When a Eield pulse F1 enters a terminal 24, the delivery of an output pulse from the vertical shit register 21 to an output line 26 results in vertical gate lines 28 and 29 being simultaneously picked up in response thereto. When an output pulse is subsequently delivered to an output line 27, vertical gate lines 30 and 31 are simultaneously picked up. On the other hand, when a field pulse F2 enters a terminal 25, the pairs of vertical gate lines that are picked up in response to output pulses from the vertical shift register 21 to the output lines 26 and 27 are the lines 29 and 3Q, and 31 and 32, respectively. That is, the set of the vertical gate lines picked up is shifted by the change-over of the field pulses, whereby interlacing is achieved.
The photosensor of the circuit arrangement shown in Figures 1 and 2 encounters the problem of reduction of its dynamic range when it is desired to achieve a photosensor of high packaging density having a comparatively small size enabling it to be fabricated on a mass-production basis, I 16959~
while still having a number of picture elements sufficient to attain a resolution of practical level. The packaging density of the photosensor discussed above exceeds the scale of a device being presently developed as a VLSI (Very Large Scale Integration). It requires fine patterning technology and results in an inevitable lowering of the supply voltage with eEects on the device breakdown and reliability. This point is discussed in detail in, for example, H. Masuda et al., "Characteristics and Limitation of Scaled Down MOSFET~s Due to Two-Dimensional Field Effect", IEEE Trans., Electron Devices, ED-26, 6, p. 980, June 1979.
In the photosensor of the circuit arrangement~shown in Figures 1 and 2, interlace switches formed of MOSTs 201 are employed in the interlace circuit portion, and hence voltage drops based on a threshold voltage VT are unavoidably caused. Even if a voltage kept intact at a supply voltage VDD is fed from the vertical shift register, only a voltage (VDD - VT) will be applied to the vertical gate lines. In this case, the threshold voltage VT often has a large value, on account of the substrate effect, and it is not uncommon that (VDD - VT) is smaller than VDD by as much as 20 - 30 %.
The dynamic range of the photosensor is given by (VDD - VT -VT') where VT' denotes the threshold voltage of the photogate 5. Therefore, the reduction of the dynamic range due to the threshold voltages becomes nearly as much as 50 % of the supply voltage VDD, which incurs the serious problem that the dynamic range becomes much lower than the supply voltage VDD which is low itself, as described before. For example, in a case where the supply voltage VDD is made 5 Vr as used in a recent high-packaged MOSLSI, the dynamic range becomes less than approximately 1.5 V on the supposition that VT ~ 2.0 V and VT' ~ 1.5 V (VT and VT' become great on account of the presence of the substrate ~ffect). This is not practical in that, with a high contrast scene, the white level is limited to render the reproduced image unsatisfactory.
Summar of the Invention y This invention aims to improve this problem, having the ~ ~ 69~
,~, object of providing a photosensor of wide dynamic range.
In other words, the invention aims to provide a photosensor that can supply a predetermined driving voltage to vertical gate lines.
Accordingly, the invention is characterized by means for restoring the voltage level of the scanning pulses a~ter this level has undergone a voltage ~rop due ~o the interlace switching elements.
In the preferred embodiment a buf~er circuit is disposed between the interlace circuit and the photodiode array, the high level voltage of the vertical driving pulse which had undergone a voltage drop in the interlace circuit being recovered by the buffer circuit.
Descri tion of the Preferred Embodiments P . . _ _ Figure 3 is a circuit block diagram showing an embodiment of a solid-state imaging device according to this invention.
Numeral 41 designates a block into which a horizontal shiEt register and horiæontal switching elements are combined, numeral 42 a vertical shift register, numeral 43 an interlace 2Q circuit, numeral 44 a photodiode array, numeral 45 an output terminal (a plurality o~ output terminals may well be used), numeral 46 a vertical buffer circuit, numeral 47 a photogate, numeral 48 a vertical signal output line, and numeral 49 a photodiode.
In the arrangement of Figure 3, the vertical buffer circuit 46 raises an output pulse from the vertical register 42 having undergone a voltage drop by passing through the interlace circuit 43, up to a predetermined high level of a driving pulse for a vertical gate line, recovering the voltage 3~ enough to apply the highest value (VDD) to the photogate 47.
A photosensor of wide dynamic range is thus obtained.
Figure 4 shows a specific example of the vertical buffer circuit in Figure 3. Numeral 51 designates a unit circuit which constitutes one stage of the vertical shift register 50, numeral 52 the interlace circuit, numeral 53 the vertical buffer circuit, and numeral 54 the photodiode array. Figure 5 shows an example of an operating timing chart of the circuit arrangement in Figure 4.
1 3 ~9~
It is assumed that in the arrangement of Figure 4, the output pulse (voltage VDD) from the vertical shift register 50,51 is impressed on a node A of an output line 55 as shown at 81 in Figure 5. Field pulses ~Fl and ~F2 are respectively applied to terminals 58 and 59. The latter pulse ~F2 is assumed to be at a high level (supposed to be VDD) and the former pulse ~Fl to be at a low level (in the converse case, the following situation similarly holds). ~t nodes B and B' ;of output lines indicated by numerals 63 and 63', a voltage (VDD - VT) appears as shown at 86 in a waveform 84 of Figure 5 (VT indicates the magnitude of the threshold voltages of MOSTs 56 and 57). Subsequently, a pulse ~Bl is impressed on a terminal 60 at a timing illustrated at 82 in Figure 5.
Then, as shown,at 87 ~n Figure 5, the voltage of the nodes B and B' becomes suf~iciently higher than the voltage VDD
owing to the bootstrap effect through the capacitances (parasitic capacitances or additional capacitances) 70 and 71 betweon the gates and sources of respective buEEer MOSTs 66 and 67. In conse~uence, at nodes C and C' of vertical scannlng lines (vertical gate lines) 64 and 65 connected to photogates 72 and 73 respectively, the high level VDD of the pulse ~Bl is applied as it is, as illustrated at 85 in Figure 5. In this way, the sufficiently high voltages VDD ~ree from the threshold voltage drops are applied to the photogates 72 and 73, so that the dynamic range of the photosensor is improved.
In the embodiment shown in Figures 4 and 5, a pulse ~B2 is impressed on a terminal 61 at a timing illustrated at 83 in Figure 5, whereby the voltages of the vertical gate lines 64 and 65 leading to the respective photogates 72 and 73 are lowered again. By this method, even when the voltage of the low level of the pulse ~Bl is somewhat above O V, the voltages of the vertical gate lines leading to the photogates can be exactly brought down to a voltage Vs (for example, O V) of a terminal 62. When the pulse ~B2 is kept at the high level during one horizontal scanning period, the photogate can be held at a low impedance, and a condition of immunity to interfering noise can be established.
~ ~ ~i959~) -- 6 ~
Especially the arrangement is effective Eor preventing carr-iers from flowing as a tailing current underneath the photogate due to the overflow of the photodiode.
By repeating the cycles stated above, signals are read out in succession from the picture elements.
As will be understood from the embodiments described above, this invention is applicable to any photosensor of the X-Y addressing type that includes an interlace circuit and a vertical scanning circuit composed of MOSTs etc.
For example, the horizontal scanning circuit of the block 41 in Figure 3 is not restricted to a digital shift register which is composed of MOSTs, but may be composed of~charge transfer devices (hereinbelow, abbreviated to "CTDs"3 that handle analog signals. In this case, the block 41 becomes a circuit which includes the CTDs and switching elements for transmitting signals rom the vertical signal output lines ~8 to the CTDs.
In Figure 3, a MOS type photosensor having the array ~4 of p-n junckion diodes has been exempliEied. Elowever, this is not restrictive, bu~ CIDs (Charge Injection Devices;
also of the X-Y addressing type~ may be used instead.
The positions of the horizontal and vertical registers, etc., in Figure 3 are not restricted to -the upper and left parts. For example, the vertical circuits may be disposed on the right side. The horizontal register may be disposed on the lower side, or divided into upper and lower portions that are alternately used.
In the embodiments of this invention described above, the case where electrons are signal carriers (n-channel) is assumed. However, this is not restrictive, the invention being similarly applicable to a case employing holes as the signal carriers ~p-channel) by, for example, inverting the polarities of the pulses and the conductivity types of regions of the MOSTs and the diodes.
Solid-state imaging device ~, This invention relates to a solid-state imaging device, and more particularly to means for enhancing the dynamic range of such a device.
To enable the prior art to be explained with the aid of a diagram, all the figures of drawing will first ~e described.
Figure 1 is a schematic circuit diagram showing the construction of a prior-art, MOS type solid-state imaging device, Figure 2 i5 a schematic circuit diagram showing an example of an interlace circuit in Figure 1, Figure 3 is a circuit block diagram showing an : embodiment of a solid-state imaging device of thls invention, Figure 4 is a schematic circuit diagram showing an example of an interlace circuit as well as a vertical buffer circuit in Figure 3, and Figure 5 is a pulse timing chart showing pulses at various nodes and vertical buffer circuit-control pulses ~Bl and ~B2 in Figure 4- .
Figure 1 shows a typical example of a prior-art solid-state imaging device (hereinbelow, termed "photo-sensor"). It illustrates the fundamental circuit arrangement of a MOS-type photosensor in which picture elements employing insulated-gate field effect transistors (hereinbelow, termed "MOSTs") as vertical switching ' , ~ .
~ J 6959G
elements and employing the source junctions of the MOSTs as photodiodes are arrayed in the form of a matrix. Numeral 1 designates a shift register which serves as a horizontal scanning circuit, numeral 2 a shift register which serves as a vertical scanning circuit, numeral 3 an interlace circuit, numeral 4 a vertical scanning line (vertical gate line) for addressing in the Y direction, numeral 5 a photogate which serves as a vertical switching elernent, numeral 6 a photodiode, numeral 7 a vertical signal output line, numeral 8 a horizontal switching element for execut-ing sequential addressing in the X direction with an output from the horizontal shift register 1, numeral 10 a'horizontal signal output line, numeral 11 output terminals, and numeral 12 a region of a photodiode array.
Figure 2 shows a specific example of the interlace circuit indicated at 3 in Figure 1. Numeral 21 designates the vertical shift register, numeral 22 the interlacl~
circuit, and numeral 23 the region of the photo~iode array.
The operation o-E the circuitry in Figure 2 will now be described. When a Eield pulse F1 enters a terminal 24, the delivery of an output pulse from the vertical shit register 21 to an output line 26 results in vertical gate lines 28 and 29 being simultaneously picked up in response thereto. When an output pulse is subsequently delivered to an output line 27, vertical gate lines 30 and 31 are simultaneously picked up. On the other hand, when a field pulse F2 enters a terminal 25, the pairs of vertical gate lines that are picked up in response to output pulses from the vertical shift register 21 to the output lines 26 and 27 are the lines 29 and 3Q, and 31 and 32, respectively. That is, the set of the vertical gate lines picked up is shifted by the change-over of the field pulses, whereby interlacing is achieved.
The photosensor of the circuit arrangement shown in Figures 1 and 2 encounters the problem of reduction of its dynamic range when it is desired to achieve a photosensor of high packaging density having a comparatively small size enabling it to be fabricated on a mass-production basis, I 16959~
while still having a number of picture elements sufficient to attain a resolution of practical level. The packaging density of the photosensor discussed above exceeds the scale of a device being presently developed as a VLSI (Very Large Scale Integration). It requires fine patterning technology and results in an inevitable lowering of the supply voltage with eEects on the device breakdown and reliability. This point is discussed in detail in, for example, H. Masuda et al., "Characteristics and Limitation of Scaled Down MOSFET~s Due to Two-Dimensional Field Effect", IEEE Trans., Electron Devices, ED-26, 6, p. 980, June 1979.
In the photosensor of the circuit arrangement~shown in Figures 1 and 2, interlace switches formed of MOSTs 201 are employed in the interlace circuit portion, and hence voltage drops based on a threshold voltage VT are unavoidably caused. Even if a voltage kept intact at a supply voltage VDD is fed from the vertical shift register, only a voltage (VDD - VT) will be applied to the vertical gate lines. In this case, the threshold voltage VT often has a large value, on account of the substrate effect, and it is not uncommon that (VDD - VT) is smaller than VDD by as much as 20 - 30 %.
The dynamic range of the photosensor is given by (VDD - VT -VT') where VT' denotes the threshold voltage of the photogate 5. Therefore, the reduction of the dynamic range due to the threshold voltages becomes nearly as much as 50 % of the supply voltage VDD, which incurs the serious problem that the dynamic range becomes much lower than the supply voltage VDD which is low itself, as described before. For example, in a case where the supply voltage VDD is made 5 Vr as used in a recent high-packaged MOSLSI, the dynamic range becomes less than approximately 1.5 V on the supposition that VT ~ 2.0 V and VT' ~ 1.5 V (VT and VT' become great on account of the presence of the substrate ~ffect). This is not practical in that, with a high contrast scene, the white level is limited to render the reproduced image unsatisfactory.
Summar of the Invention y This invention aims to improve this problem, having the ~ ~ 69~
,~, object of providing a photosensor of wide dynamic range.
In other words, the invention aims to provide a photosensor that can supply a predetermined driving voltage to vertical gate lines.
Accordingly, the invention is characterized by means for restoring the voltage level of the scanning pulses a~ter this level has undergone a voltage ~rop due ~o the interlace switching elements.
In the preferred embodiment a buf~er circuit is disposed between the interlace circuit and the photodiode array, the high level voltage of the vertical driving pulse which had undergone a voltage drop in the interlace circuit being recovered by the buffer circuit.
Descri tion of the Preferred Embodiments P . . _ _ Figure 3 is a circuit block diagram showing an embodiment of a solid-state imaging device according to this invention.
Numeral 41 designates a block into which a horizontal shiEt register and horiæontal switching elements are combined, numeral 42 a vertical shift register, numeral 43 an interlace 2Q circuit, numeral 44 a photodiode array, numeral 45 an output terminal (a plurality o~ output terminals may well be used), numeral 46 a vertical buffer circuit, numeral 47 a photogate, numeral 48 a vertical signal output line, and numeral 49 a photodiode.
In the arrangement of Figure 3, the vertical buffer circuit 46 raises an output pulse from the vertical register 42 having undergone a voltage drop by passing through the interlace circuit 43, up to a predetermined high level of a driving pulse for a vertical gate line, recovering the voltage 3~ enough to apply the highest value (VDD) to the photogate 47.
A photosensor of wide dynamic range is thus obtained.
Figure 4 shows a specific example of the vertical buffer circuit in Figure 3. Numeral 51 designates a unit circuit which constitutes one stage of the vertical shift register 50, numeral 52 the interlace circuit, numeral 53 the vertical buffer circuit, and numeral 54 the photodiode array. Figure 5 shows an example of an operating timing chart of the circuit arrangement in Figure 4.
1 3 ~9~
It is assumed that in the arrangement of Figure 4, the output pulse (voltage VDD) from the vertical shift register 50,51 is impressed on a node A of an output line 55 as shown at 81 in Figure 5. Field pulses ~Fl and ~F2 are respectively applied to terminals 58 and 59. The latter pulse ~F2 is assumed to be at a high level (supposed to be VDD) and the former pulse ~Fl to be at a low level (in the converse case, the following situation similarly holds). ~t nodes B and B' ;of output lines indicated by numerals 63 and 63', a voltage (VDD - VT) appears as shown at 86 in a waveform 84 of Figure 5 (VT indicates the magnitude of the threshold voltages of MOSTs 56 and 57). Subsequently, a pulse ~Bl is impressed on a terminal 60 at a timing illustrated at 82 in Figure 5.
Then, as shown,at 87 ~n Figure 5, the voltage of the nodes B and B' becomes suf~iciently higher than the voltage VDD
owing to the bootstrap effect through the capacitances (parasitic capacitances or additional capacitances) 70 and 71 betweon the gates and sources of respective buEEer MOSTs 66 and 67. In conse~uence, at nodes C and C' of vertical scannlng lines (vertical gate lines) 64 and 65 connected to photogates 72 and 73 respectively, the high level VDD of the pulse ~Bl is applied as it is, as illustrated at 85 in Figure 5. In this way, the sufficiently high voltages VDD ~ree from the threshold voltage drops are applied to the photogates 72 and 73, so that the dynamic range of the photosensor is improved.
In the embodiment shown in Figures 4 and 5, a pulse ~B2 is impressed on a terminal 61 at a timing illustrated at 83 in Figure 5, whereby the voltages of the vertical gate lines 64 and 65 leading to the respective photogates 72 and 73 are lowered again. By this method, even when the voltage of the low level of the pulse ~Bl is somewhat above O V, the voltages of the vertical gate lines leading to the photogates can be exactly brought down to a voltage Vs (for example, O V) of a terminal 62. When the pulse ~B2 is kept at the high level during one horizontal scanning period, the photogate can be held at a low impedance, and a condition of immunity to interfering noise can be established.
~ ~ ~i959~) -- 6 ~
Especially the arrangement is effective Eor preventing carr-iers from flowing as a tailing current underneath the photogate due to the overflow of the photodiode.
By repeating the cycles stated above, signals are read out in succession from the picture elements.
As will be understood from the embodiments described above, this invention is applicable to any photosensor of the X-Y addressing type that includes an interlace circuit and a vertical scanning circuit composed of MOSTs etc.
For example, the horizontal scanning circuit of the block 41 in Figure 3 is not restricted to a digital shift register which is composed of MOSTs, but may be composed of~charge transfer devices (hereinbelow, abbreviated to "CTDs"3 that handle analog signals. In this case, the block 41 becomes a circuit which includes the CTDs and switching elements for transmitting signals rom the vertical signal output lines ~8 to the CTDs.
In Figure 3, a MOS type photosensor having the array ~4 of p-n junckion diodes has been exempliEied. Elowever, this is not restrictive, bu~ CIDs (Charge Injection Devices;
also of the X-Y addressing type~ may be used instead.
The positions of the horizontal and vertical registers, etc., in Figure 3 are not restricted to -the upper and left parts. For example, the vertical circuits may be disposed on the right side. The horizontal register may be disposed on the lower side, or divided into upper and lower portions that are alternately used.
In the embodiments of this invention described above, the case where electrons are signal carriers (n-channel) is assumed. However, this is not restrictive, the invention being similarly applicable to a case employing holes as the signal carriers ~p-channel) by, for example, inverting the polarities of the pulses and the conductivity types of regions of the MOSTs and the diodes.
Claims (7)
1. A solid-state imaging device having enhanced dynamic range and including a plurality of photodiodes arrayed in two dimensions on an identical semiconductor body, a group of horizontal switching elements and a group of vertical switching elements for gating signal outputs from the photodiodes, and a horizontal scanning circuit and a vertical scanning circuit for impressing scanning pulses having a given voltage level on the horizontal and vertical switching elements respectively, and having an interlaced scanning mechanism for addressing a plurality of vertical scanning lines by means of interlace switching elements so as to permit horizontal scanning of scanning lines of a plurality of rows; characterized in that said interlaced scanning mechanism includes means to restore said voltage level of the scanning pulses after said level has undergone a voltage drop due to the interlace switching elements.
2, A device according to claim 1, wherein said inter-laced scanning mechanism includes an interlace circuit which changes over a combination of the vertical scanning lines to be addressed by means of said interlace switching elements for every field, and a vertical buffer circuit for restoring the voltage level of the scanning pulses having passed through said interlace circuit.
3. A device according to claim 2, wherein said vertical buffer circuit includes insulated-gate field effect transistors for restoring voltage drops which are disposed at the respective vertical scanning lines, which receive output signals from said interlace circuit as their gate inputs and which are driven by driving pulses synchronous with output pulses of said vertical scanning circuit, capacitances contributive to the bootstrap effect being located between the gates and sources of said insulated-gate field effect transistors for restoring voltage drops.
4. A device according to claim 2, wherein said interlace circuit includes first to fourth switching elements which consist of insulated-gate field effect transistors connected at outputs of respective stages of unit circuits constituting said vertical scanning circuit and which permit the simultaneous horizontal scanning of the scanning lines of two rows, first and second field pulses being respectively impressed on a set of said first and second switching elements and a set of said third and fourth switching elements and said first and second switching elements being operated in a first field and said third and fourth switching elements in a second field by the use of output pulses provided from said vertical scanning circuit in time sequence and said field pulses, thereby to generate gate input pulses of said insulated-gate field effect transistors for restoring voltage drops.
5. A device according to claim 2, wherein the sources (or drains) of said first to fourth switching elements are connected to the outputs of the respective stages of said unit circuits constituting said vertical scanning circuit, the drain (or source) of said first switching element, the drains (or sources) of said second and third switching elements and the drain (or source) of said fourth switching element are respectively connected to the gates of the insulated-gate field effect transistors for restoring voltage drops of the vertical scanning lines of a first row, second row and third row corresponding to the stages of said unit circuits; the field pulses being impressed on the gates of said first to fourth switching elements; the drains (or sources) of said insulated-gate field effect transistors for restoring voltage drops being connected to a first common line, on which driving pulses synchronous with output pulses provided from said vertical scanning circuit in time sequence are impressed; and the sources (or drains) of said insulated-gate field effect transistors for restoring voltage drops being connected to the respective vertical scanning lines.
6. A device according to claim 5, wherein the drains (or sources) of insulated-gate field effect transistors for resetting whose gates are connected to a second common line and whose sources (or drains) are connected to a third common line are connected to the sources (or drains) of said insulated-gate field effect transistors for restoring voltage drops, a reset pulse being impressed on said second common line, and said third common line being grounded.
7. A solid-state imaging device according to claim 2, 3 or 4, wherein said vertical and horizontal switching elements are constructed of insulated-gate field effect transistors, and source junctions of said vertical switching elements being employed as said photodiodes.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54158/1980 | 1980-04-25 | ||
| JP5415880A JPS56152382A (en) | 1980-04-25 | 1980-04-25 | Solid image pickup element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1169596A true CA1169596A (en) | 1984-06-19 |
Family
ID=12962731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000376105A Expired CA1169596A (en) | 1980-04-25 | 1981-04-23 | Solid-state imaging device |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4392158A (en) |
| EP (1) | EP0039177B1 (en) |
| JP (1) | JPS56152382A (en) |
| CA (1) | CA1169596A (en) |
| DE (1) | DE3162013D1 (en) |
Families Citing this family (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57109488A (en) * | 1980-12-26 | 1982-07-07 | Matsushita Electric Ind Co Ltd | Solid color image pickup device |
| JPS57203387A (en) * | 1981-06-10 | 1982-12-13 | Toshiba Corp | Color television image pickup device |
| DE3138294A1 (en) * | 1981-09-25 | 1983-04-14 | Siemens AG, 1000 Berlin und 8000 München | TWO-DIMENSIONAL SEMICONDUCTOR IMAGE SENSOR WITH CONTROL OR REGULATION OF THE INTEGRATION TIME |
| DE3280187D1 (en) * | 1982-03-31 | 1990-07-05 | Ibm Deutschland | FIXED BODY TELEVISION CAMERA. |
| CA1199400A (en) * | 1982-04-07 | 1986-01-14 | Norio Koike | Solid-state imaging device |
| JPS5930376A (en) * | 1982-08-13 | 1984-02-17 | Olympus Optical Co Ltd | Solid-state image pickup device |
| JPS5952974A (en) * | 1982-09-20 | 1984-03-27 | Hitachi Ltd | Solid-state image pickup device |
| JPS5966277A (en) * | 1982-10-07 | 1984-04-14 | Toshiba Corp | Solid-state image sensor |
| JPS59108463A (en) * | 1982-12-14 | 1984-06-22 | Olympus Optical Co Ltd | Solid-state image pickup device |
| EP0130103A1 (en) * | 1983-06-21 | 1985-01-02 | FAIRCHILD CAMERA & INSTRUMENT CORPORATION | Charge-coupled device image sensor and method for asynchronous readout |
| JPS60149266A (en) * | 1984-01-13 | 1985-08-06 | Matsushita Electronics Corp | Solid state image pickup device |
| US4639788A (en) * | 1984-12-07 | 1987-01-27 | New York Institute Of Technology | Video display method and apparatus |
| US4641193A (en) * | 1984-12-07 | 1987-02-03 | New York Institute Of Technology | Video display apparatus and method |
| US4620232A (en) * | 1985-03-15 | 1986-10-28 | Fuji Photo Film Co., Ltd. | Reset circuit for MOS imager array |
| FR2599920B1 (en) * | 1985-08-02 | 1988-12-09 | Trt Telecom Radio Electr | ELECTRONIC INTERLEAVING METHOD FOR HORIZONTAL SCANNING THERMAL CAMERA |
| JPH0695735B2 (en) * | 1985-12-25 | 1994-11-24 | キヤノン株式会社 | Solid-state imaging device |
| JP2656475B2 (en) * | 1986-10-01 | 1997-09-24 | 株式会社日立製作所 | Solid-state imaging device |
| JPH0687590B2 (en) * | 1986-10-14 | 1994-11-02 | 富士写真フイルム株式会社 | Method of reading solid-state image sensor |
| JP2559407B2 (en) * | 1987-05-25 | 1996-12-04 | キヤノン株式会社 | Scanning circuit |
| US5200634A (en) * | 1988-09-30 | 1993-04-06 | Hitachi, Ltd. | Thin film phototransistor and photosensor array using the same |
| US5400072A (en) * | 1988-12-23 | 1995-03-21 | Hitachi, Ltd. | Video camera unit having an airtight mounting arrangement for an image sensor chip |
| EP0493455B1 (en) * | 1989-09-23 | 1994-11-23 | Vlsi Vision Limited | I.c. sensor |
| JP3173851B2 (en) * | 1992-04-13 | 2001-06-04 | 三菱電機株式会社 | CSD type solid-state imaging device |
| US5790191A (en) * | 1996-03-07 | 1998-08-04 | Omnivision Technologies, Inc. | Method and apparatus for preamplification in a MOS imaging array |
| JP4723994B2 (en) * | 2005-12-19 | 2011-07-13 | 株式会社東芝 | Solid-state imaging device |
| US11551028B2 (en) | 2017-04-04 | 2023-01-10 | Hailo Technologies Ltd. | Structured weight based sparsity in an artificial neural network |
| US11238334B2 (en) | 2017-04-04 | 2022-02-01 | Hailo Technologies Ltd. | System and method of input alignment for efficient vector operations in an artificial neural network |
| US11615297B2 (en) | 2017-04-04 | 2023-03-28 | Hailo Technologies Ltd. | Structured weight based sparsity in an artificial neural network compiler |
| US11544545B2 (en) | 2017-04-04 | 2023-01-03 | Hailo Technologies Ltd. | Structured activation based sparsity in an artificial neural network |
| US10387298B2 (en) | 2017-04-04 | 2019-08-20 | Hailo Technologies Ltd | Artificial neural network incorporating emphasis and focus techniques |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4001501A (en) * | 1973-05-02 | 1977-01-04 | Rca Corporation | Signal processing circuits for charge-transfer, image-sensing arrays |
| JPS5389617A (en) * | 1977-01-19 | 1978-08-07 | Hitachi Ltd | Driving method of solid image pickup element |
| JPS5853830B2 (en) * | 1977-07-13 | 1983-12-01 | 株式会社日立製作所 | Color solid-state imaging device |
| JPS585627B2 (en) * | 1977-08-10 | 1983-02-01 | 株式会社日立製作所 | solid state imaging device |
-
1980
- 1980-04-25 JP JP5415880A patent/JPS56152382A/en active Granted
-
1981
- 1981-04-15 DE DE8181301670T patent/DE3162013D1/en not_active Expired
- 1981-04-15 EP EP81301670A patent/EP0039177B1/en not_active Expired
- 1981-04-23 CA CA000376105A patent/CA1169596A/en not_active Expired
- 1981-04-24 US US06/257,461 patent/US4392158A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6161586B2 (en) | 1986-12-26 |
| EP0039177B1 (en) | 1984-01-25 |
| US4392158A (en) | 1983-07-05 |
| JPS56152382A (en) | 1981-11-25 |
| EP0039177A2 (en) | 1981-11-04 |
| EP0039177A3 (en) | 1981-12-30 |
| DE3162013D1 (en) | 1984-03-01 |
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