CA1171138A - Self-synchronization circuit for a ffsk and msk demodulator - Google Patents

Abstract

TITLE
SELF-SYNCHRONIZATION CIRCUIT FOR A FFSK OR MSK DEMODULATOR
INVENTORS
Rudi de Buda Charles E. Jagger ABSTRACT OF THE DISCLOSURE
The self-synchronization circuit splits the incoming sig-nal into two circuit paths where the signals are frequency shifted by a frequency signal equal to the carrier frequency so as to pro-vide an in-phase signal in one circuit path and a quadrature signal in the other circuit path. The frequency shifting circuit includes at least a controllable oscillator. The output of a first multi-plier which multiplies the in-phase and quadrature signals, is fed to a clock recovery circuit which determines the clock frequency.
A second multlplier multiplies the output of the first multiplier with the clock recovery circuit output to provide a signal which controls the controllable oscillator. In addition, a frequency discriminator utilizes the in-phase and quadrature signals to ini-tially coarse control the controllable oscillator frequency. The frequency shifting signals may be obtained from the controllable oscillator feeding phase shifting circuits, or they may be obtained from a combined circuit including a fixed oscillator with phase shifting circuits together with the controllable oscillator and appropriate mixing circuits.

Description

~ J 71~38 Background of the Invention This inven~ion relates to a special Frequency Shift Keying (FSK) system that is known as the "Fast FSK", and in parti-cular it provides an improved self-synchronizing receiver for demo-~ulating "Fast FSK" radio signals.
~ he "Fast FSK" system uses a phase continuous FSK modu-lator where the two keyed frequencies differ by one half ~he bit rate. This modulation method is particularly suitable for the transmission of digital data over a noisy radio channel whose chan-nel bandwidth is between 0.6 times and 0.9 times the bit rate of the data. For optimal demodulation of the data, coherent demodu-lation of an in-phase and of a quadrature channel is a necessity.
In turn, coherent demodulation requires self-synchronization cir-cuits for recovery of the clock reference signal and the r.f.
carrier reference signal of correct frequency and phase~ These reference signals are conventionally der~ived after a frequency doubling stage, as descrihed in Canadian Patent 1,066,371 entitled "Demodulator For Erequency-Shift Keying 5ystem" which was issued on November 13, 1979 to R. de Buda, assignee to Canadian General Electric Company Limited.
A modulation system with si~ilar properties as the Fast FSK system i9 the MSK system described in the publication "Th2 Effect of Tandem Band and Amplltude Limiting on the Eb/No Per-formance of MSK" by H.R. Mathwich et al, IEEE Transactions Communi-cations, Vol. COM-22, pp 1525-1540, October 1974, While the MSK
system modulates a particular message differently, a random data stream creates for the MSK system the same power spectru~ as for the Fast FSK system, and therefore, the same self-synchronization circuits can be used for either system. Hence, and without further -1- ~

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reference, all the description which will be given for self-synchronization of the Fast FSK system should be understood to apply also to the self-synchronization of the MSK system.
Self-synchronization recovers the suppressed carrier from a signal in which all the transmitted power is used to transmit the messages 50 that the receiver must recover the carrier reference signal from the messages. 8efore carrier recovery has taken place3 the messages must be considered as random data. Now it is known that random data, as transmitted by the Fast FSK system, represents a statistical process that has a continuous spectrum, and that such an unprocessed continuous spectrum is not suitable for carrier recovery, for which spectral lines are needed.
A bounded lineàr transforma~ion of such a process having a continuous spectrum cannot give one wi~h a line spectrum. There-fore, linear transformations alone (and this would include any combination of delays, multiplications with a fixed function, e.g.
gating, and all ilters) are not suitable for providing a spectrum from which selE-synchronization can be achieved.
This shows that any method that can recover carrier and clock reference signals from a random data modulated Fast FSK, cannot be linear but must contain some non-linear circuit. A prac-tical, simple and efficient method of providing such a non-linear circuit is to frequency double the signal in the self-synchronizing stage as described in the above Canadian Patent 1,066,371, because, as it has been noted in the paper "Coherent Demodulation of FSK
with Low Deviation Ratio", by R. de Buda, IEEE Transactions Commun-ications, Vol. COM-20, pp. 429-435, the spectrum at the output of the frequency doubler contains two components: one is a continuous spectrum, the other a line spectrum with lines at frequencies 2fS
and 2fm when the Fast FSK alternates randomly between the "mark"

frequency E~ and the "space" frequency fs~ (fs ~ fm).

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Two phase locked loops can now be used to extract the two lines ~rom the frequency doubler output. The frequency doubling circuit in this case is then that non-linear clrcuit which, as discussed above, is an essential part of the self-synchronization circuits.
The oscillators in the phase-locked loops may be at 2fS
and 2fm but other combinations of oscilla~or frequencies are also possible. In particular, it may be of advantage to have one oscil-lator at fs + fm and the other at fs ~ fm~ (which is a much lower frequency) snd then to compare the output of the doubler with that of a mixer having the two oscillator signals as inputs and generating reference signals at:
(fs+ fm)~(fs~ fm) = 2fS and 2fm. More complex frequency plans are possible. Also, it is not required to frequency double the incoming r.f. signal, which may be quite impractical, but the incoming signal could first be frequency shifted to a useful i.f.
and there frequency doubled. If f is the frequency of the lncoming signal and fO is the fre~uency of the local oscillator that is employed for frequency shifting to the i.f., then the above can be sùmmarized by the identity:

2(f - fO) = 2f - 2fo~ i.e. first frequency shifting by fQ and then doubling is the same as first doubling and then requency shlfting by 2fo. These comments are included only for complete-ness of the description. They are stateof-the-art and not novel.
In previously used~circultry~ the frequency doubling ls usually performed ~y a dlode with square-law characteristic, or by a linear multiplier with the same signal appliea to both inputs.
In either case, second harmonics are generated as indicated by the identi~y: 2cos2~t - 1 ~ cos 2~t. A zonal filter rejects the dc and low Prequency parts of the output and retalns the second harmonic.
If however, the self-synchronl2ation circuits are not designed with analog circuit elements, and the restrlction is added

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that the circuit should be built mainly fro~ logic gates, then it is found that many of the circuit elements can be readily replaced by gates alone. After all, any FSK signal is a constant amplitude signal, and the hard limiting which the gates provide retains the phase information.
However, the square of a hard limited signal is useless for this purpose, because it does not generate a second har~onic9 since (_1)2 = 1, and a different self-synchronization method must be provided.
Summary of the Invention It is therefore an object oP the present invention to provide a non-linear self-synchronization circuit for a Fast FSK or MSK demodulator which provides the carrier reference signal and can be i~plemented with an improved circuit requiring only logic gates.
These and other ob~ects are achleved in a self-synchroni-zation circuit for a receiver that demodulates an incoming Fast FSK
or MSK signal. The circuit includes a local oscillator circuit for frequency shifting the incolning signal by two outputs 90 apart resulting in one in-phase and one quadrature signal; and a multi- ;
plier responsive to the in-phase and quadrature signals for effec~
tively produclng a frequency doubled slgnal for recovering a clock reference signal and for controlling the local oscillator circuit to provide a carrier reference signal.
In accordance ~fith another aspect of this invention, the self-synchronization circuit for the demodulating receiver has two circuit paths. The incoming signal is coupled into the two circuit paths where it is frequency shifted by a frequency sign~l subs~an-tially equal to the carrier frequency so as to have an in-phase signal in one circuit path and a quaarature signal in the other circuit path. The frequency shifting circuit includes at least one osclllator controllable in ~requency. A flrst multiplier circuit

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multiplies the in-phase and quadrature signals, a clock recovery circuit determines the clock frequency from the output of the first multiplier, and a second multipller multiplies the output of the first multiplier and the clock recovery circuit to provide a control signal to the controllable oscillator.
In accordance with a further aspect of the invention, a frequency discriminator utilizes the in-phase and quadrature sig-nals to control the controllable oscillator frequency to improve the initial signal acquisi~ion time for carrier frequency offsets relative to the controllable oscillator frequency.
In accordance with ano~her aspect of this invention~ ehe frequency shifting signals may be obtained from the controllable oscillator feeding phase shifting circuits, or they may be obtained from a combined circuit including a fixed oscillator with phase shifting circults together with the controllable oscillator and the appropriate mixing circuits.
Many other objects and aspects of the invention will be clear from the detailed description of the drawings.
Brief Description of the Drawings In the drawings:
Figure 1 is a schematic of a Fast FSK demodulator; and Figure 2 is a schematic of the carrier recovery circu1t in accordance with the present; invention.
Detailed Description As illustrated in figure 1, the received l.f. signal is amplified in amplifier 10 and directed to both a self-synchroni-zation circuit 11 and a coherent receiver 12. The selE-synchroni-zation circuit 11 operates on the input signal to provide a clock signal at rate 1/T, where T is the signalling interval and a car-rier reference signal with phase information, to a coherent recei-ver 12 w~ere the i.f. signal is demodulated ~o provide the data output.

In the carrier recovery circuit shown in figure 2, the Fast FSK signal sA(t) which is on a suitable i.f. carrie ~c is applied to the input port 20. A ha~d limiter 21 hard li~ts the signal ~hich is then directed along two paths. The signal in each path is fed to a first mixer or down converter 22, 23. The second inputs to the down converter 22, 23 are two sinusoids with the same angular frequency ~1 but in phase quadrature to one another.
Using the convention that w/a denotes a sinusoid of (angular) fre-quency ~, and phase , the two sinusoids are ~1/ and ~1/9-In a digital circuit as slown in figure 2, the two phases would be generated from a source 24 at angular frequency 4~1 and a frequency divider 25 to divide by 4. Analog circuits would nor-mally start with a sinusoid ~1/45 fed into +45 phase shifters, for the same result.
The outputs of the down converters 22 and 23 are sent ~ `
into a second pair of down converters 26 and 27. The second inputs of both 26 and 27 are fed by the same sinusoid ~2/~- ~This~sinu- ;
soid is obtained from voltage-controlled oscillator (VCO) 28 whose control will be described below.
The outputs of the down conver~ers 26 and 27 are fed through low pass filters 29 and 30 in the two paths. The values of the angular frequencies ~1 and ~2 have been selected in rela-tion to ~c such that the down converted signaIs at points I and Q
are baseband slgnals. Other filters that are normally part of a down conversion have been omitted from the diagram for simplicity.
The circuit shown in figure 2 is only one of several pos-sible circuits useful for generating from sA(t) the signals I and .
Q, ~hich combine to the comple~ signal I~jQ, from which sA(t) can be recovered. Por example, converters 22 9 23, divider 25 and oscil-lator 24 can be eliminated if a VCO 28 at frequency ~2 ~c is available and if 90 phase shifts of this signal can be implemented.

~71138 In figure 2, the signals at I and Q are next hard llmited by limiters 31 and 32 and are ~ed to two circuits: a frequency dis-criminator 33 and a mixer 34. It is the purpose of the frequency discrim nator 33 to provide a control signal which sets the fre-quency of the oscillator 28 that is initially free running, into the vicinity of the value ~2 on which it will later lock.
The frequency discriminator 33 is a digital implementa-tion of the principle thae 1/2 the number of zero crossings per second is equal to the spectrally weighted average of the frequen-cies of the incoming process~ By deriving an error signal from the diference of this weighted average and the VCO 28 that is control-led by the error, the feedback sets the VCO 28 in accordance with the centre frequency oE the filter 29, 30 as long as the slgnal in the filter 29, 30 is only noise, and when Fast FSK is received, the VCO 28 is in accordance with half the spectral weighted average frequency of the frequency doubled Fas~ FSK signal.
This average frequency must be between fm and fs-As soon as the VC0 28 is phase locked to the incoming slgnal, the frequency discriminator 33 is no longer needed. For practical reasons, the frequency discrimlnator 33 is simply switched off as soon as more accurate phase lock i8 obtained from VCO 28.
While the AFC of frequency discriminator 33 holds the VC0 28 close to (but not exactly on} the correct frequency, the mixer 34 generates a signal which contains features that per~it precise carrier lock, as will be shown below. This signal is used for two purposes: it is sent into a conventional edge detecting clock recovery circuit 35 from which the clock reference signal of the data stream is recovered, and it i6 also mlxed in a further mixer 36, with a square wave at half the clock signal frequency which comes from the clock recovery circuit 35.

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The output of mixer 36 is a slowly varying signal which is added to the control signal of the requency discriminator 33 in a summing network 37.
Once lock is achieved and the control signal of frequency discriminator 33 is disabled, the output of mixer 36 alone controls the VCO 28. It will be shown next that the output of mixer 36 controls the VCO 28 in such a way that VCO 28 is phase locked to the incoming carrier ~c-In order to show that from random data the circuit of figure 2 generates a spectrum with a line to which an oscillator can be locked, it will be necessary to follow the signal in figure 2 from point A to points I and Q, to point B and then to point C, using the equations for the signals at these points. To derive these equations, higher frequency components are ignored, as is usual in the description of down converter circuits.
At point A, a Fast FSK signal sA(t) arrives, withcarrier of angular frequency ~c and angular frequency deviation ~hjT (h = 1/2 for Fast FSK) and unknown phase ~(n) at the start of the nth bit interval, t a n. This signal ~c+ ~h/T/~(n), is in detail:
sA(t) = cos[(~c ~ ~h/T)t -~ ~(n)] (1) where ~(n) = ~0 or = ~0 ~ ~ (2) = ~(0) T = duration of one bit t = time Which of the two values ~(n) takes depends on the history of the data. This 180 ambiguity is typical for a Fast FSK signal with random data.
This signal is hard limited in limiter 21, which destroys all amplitude information and retains only the zero crossings and is then split into two paths where it is down converted twice in _~_ 1 3 71 ~38 each path by mixers 22,26 and 23,27, respectively. The first down conversion being with a fixe~ reference ~l/Y~ where Y = O in the one path and Y = ~/2 in the other path, and the second down conversion being with the output ~2/~ of the voltage-controlled oscillator VCO 28.
Only the lowest-frequency components pass lowpass filters associated with each mixer. The usual formulas for converting apply, na~ely:
2cos x cos y = cos(x - y) + higher frequency terms.
Assume, without loss of generality, ~1 > WC. Then in ~he first down-conversion:
2cos[~ t + ~ht/T + ~n)] cos(~lt ~ y) = cos[(~ c)t +~ht/T ~ y - ~(n~] -~ higher frequency terms (3) The higher frequency terms may be removed by either a filter in each path which are not shown in figure 2, or by a frequency plan that in effect prevents the higher frequency terms from interfering with the second down converter.
Assume now that the VCO 28 is sufficiently close to lock-on frequency, so that:
~ c ~ ~2~< ~h/T (4) This condition is enforced by the AFC loop using frequency d~scriminator 33 which ensures that the frequencies fl and f2 when mixed result in a frequency between fs and m. This is - identical with the condition expressed by equation (4), because:
2~fs = ~c ~ ~h/T
and 2~ fm = ~c ~ ~h/T

Down-converting a second time with the output of VCO 28 at ~2/~ gives a low frequency component that will be rewritten so 9_ l ~ 71 13~

as to show a positive frequency, assuming equation (4) to be fulfilled:
2cos[(~ c)t + Trht/T ~ y ~ ~(n)~ cos(~2t ~
= cosE(~ 2)t + ~Tht/T + y - ~(n) - ~] + higher frequency 1 c terms (5) = cos~TTht/T +[(~1- ~ ~ ~2~t ~ (~(n) + ~ ~ Y~ (6) after filtering by the low pass filters 29 and 30.
Following the usual nomenclature, the upper path is identified by I (in-phase) and the lower path by Q (quadrature).
The above equation (6) is valid for signals in figure 2 at points:
I with Y - ~; and Q with y = 90.
Both I and Q signals are hard limited ln limiters 31 and 32, respectively, and then fed to frequency discriminator 33 and mixer 34. The frequency discriminator 33 is a coarse AFC to set the VC0 28 initially into the desired frequency range as in equation (4), thus reducing the initial frequency offset of the loop before it is locked. The mixer 34 is used as a control for VC0 28. It is noted that in equation (6), Y = 0 for signal I and y = Tr/2 for signal Q, but otherwise signals I and Q have identlcal terms; and in view of the trigonometric equatiOns:
cos(x + Tr/2) - +sin x and +2sin x cos x - ~sin2x .
the output of mixer 34 at point B of figure 2 is ~except for har~onics):
SB = +sin{2T~ht/T + [2(~1 ~c 2) ~ 1 7113~

where of + and ~ either both the upper or both the lower signs are to be taken.
Thus, with one logic circuit (i.e. one exclusive OR), frequency doubling has been effectively achieved. This is evident by the destruction of the 180 ambiguities of ~(n), since, irrespective of the data, 2[~(n) + ~]~2~(n)-2~0 (mod 2~).
The frequency-doubled signal sB can be rewritten with this and 2h = 1:

sB = +sin~t/T +[2(~~ 2)t - ~ - 2~ ]} (8) It is possible to frequency demodulate the signal at B; the clock recovery circuit~35 essentially does this, then locates the edges of the data stream pulses and provides a clock signal locked to the edges. This conventional circuit is in effect fourth order nonlinear, and therefore takes~longer in providing the clock signal than would a second order non-linear circuit. However, the edge locating non-linear circuit has the advan~age of requiring much slower gates, and hence it is easier and less power-consuming to imple~ent with standard CMOS teclmology.
As described earlier, clock recovery circuit 35 derives from the data edges a square wave at half the clock signal fre-quency 1/T. This square wave sR is fed to mixer 36 where it is mixed with signal SB. The signal sR texcept for harmonics) is SR = cos(~t/T) ~ ~9)-Multiplying sR and sB and using the identity 2 cos x sin y =-sin(x-y) ~ sin(x+y) gives signal SC at the output of mixer 36, point C.
SC = 2cos(~t/T)~sB

= -sin[2(~ 2)t - 2~ - 2~(0~] ~ higher frequency ter~s -11- (10) ~.

The higher frequency terms are removed by filters in the conventional manner.
The frequency discriminator 33 is disabled as soon as lock occurs. ~hen the signal SC above controls the requency of the VC0 28, and the frequency control loop for VC0 28 is closed.
If the VC0 28 loop is stable, then the error signal SC is nulled at all times. Hence at phase lock for VC0 28:

~ 2 = ~ c (11) and -2~ = 2~(0) (mod ~) (12).
That is, it is not necessary to have the VC0 itself at double requency when locking it to the frequency-doubled signal, because with the arrangement described here the VC0 is at fundamental frequency, mixed in both the I channel and the Q channel at fundamental frequency, and the frequency difference between the ~: .
Fast FSK signal and the VC0 output is in effect frequency doubled in mixer 34, which produces signal SB. Thus we do not need to show self-synchronization w1th circuits "equivalent" to frequency doubling, since we have achieved the required frequency doubling with the novel circuit arrangement.
The essence of the function of this self-synchronization circuit is thus, that firstly, the inco~ing signal generates two i.f. signals that are in phase quadrature and part of a phase-lockea loop which pr vides the carrier reference through VC0 28;
secondly, that~the product of these two signals is taken in the mixer 34~ This non linear action results in frequency doubling according to the identity 2sin~tcos~t = sin 2~t. And thirdly~ that the frequency doubling generates spectra1~1ines from which carrier phase and clock reference signals can be recovered.
., The product of the signals can bs taken by various cir-cuits that provide multiplication of the I and Q signals. For example, if the two quadrature signals are analog signals and free ~ 1 71~38 of d.c., then a balanced modulator is a good choice. If the signals are binary, i.e. switched between two logic levels, then an exclusive OR of the two signals provides a logic product that frequency doubles.
Once frequency doubling has been achieved, there are numerous known ways of extracting the two lines separately or jointly, with and without assistance from higher order nonlinearity circuits as, for instance, deriving the clock signal fro~ locating the edges of the data stream pulses.
The circuit of figure 2 should thus be considered only as the preferred embodiment, adapted to a particular requirement whose analysis illustrates how it is not always immediately evident where frequency doubling occurs in the circuit.
Many modifications in the above described embodiment of the invention can be carried out without departing from the scope thereof and therefore, the scope of the present invention is intended to be limited only by appended claims.

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Claims (4)

CLAIMS:

1. In a demodulating receiver, a self-synchronization circuit for generating a carrier reference signal from an incoming Fast FSK or MSK signal comprising:
- first means for splitting the incoming signal into two circuit paths;
- second means for frequency shifting the incoming signal in each circuit path by a frequency signal substantially equal to the carrier frequency to provide an in-phase signal along one circuit path and a quadrature phase signal along the other circuit path, the frequency shifting means having an oscillator circuit controllable in frequency and phase, -first multiplier means for multiplying the in-phase and quadrature signals;
- clock recovery circuit means for determining the clock frequency from the output of the first multiplier means; and - second multiplier means for multiplying the output of the first multiplier means and the clock recovery circuit means for providing a carrier phase signal to the controllable oscillator circuit.

2. A self-synchronization circuit as claimed in claim 1 which further includes a frequency discriminator means controlled by the in-phase and quadrature signals for initially controlling the oscillator circuit frequency.

3. A self-synchronization circuit as claimed in claims 1 or 2 wherein the second means includes third mixer means in the one circuit path and fourth mixer means in the other circuit path, the third mixer means having a first input connected to the first means and an output connected to the first multiplier means, the fourth mixer means having a first input connected to the first means and an output connected to the multiplier means, and - means for providing signals from the controllable oscillator circuit to a second input of the third mixer means and a second input of the fourth mixer means wherein the signal to the third mixer means is shifted 90° with respect to the signal to the fourth mixer means.

4. A self-synchronization circuit as claimed in claim 1 or 2 wherein the second means includes:
- third mixer means in the one circuit path and fourth mixer means in the other circuit path, the third mlxer means having a first input and a second input, and an output connected to the first mixer means the fourth mixer means having a first input and a second input, and an output connected to the first mixer means; and means for providing signals from the controllable oscillator circuit to the second input of the third mixer means and the second input of the fourth mixer means;
- fifth mixer means having a first input connected to the first means and an output connected to the first input of the third mixer means, and sixth mixer means having a first input connected to the first means and an output connected to the first input of the fourth mixer means; and - fixed oscillator means having a frequency greater than the carrier frequency for providing a signal to a second input of the fifth mixer means and a signal to a second input of the sixth mixer means shifted by 90° with respect to the signal provided to the fifth mixer means.