CA1171527A - Semiconductor memory array - Google Patents
Semiconductor memory arrayInfo
- Publication number
- CA1171527A CA1171527A CA000379548A CA379548A CA1171527A CA 1171527 A CA1171527 A CA 1171527A CA 000379548 A CA000379548 A CA 000379548A CA 379548 A CA379548 A CA 379548A CA 1171527 A CA1171527 A CA 1171527A
- Authority
- CA
- Canada
- Prior art keywords
- bit line
- transistor
- transistors
- coupled
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 5
- 230000015654 memory Effects 0.000 claims abstract description 88
- 238000001514 detection method Methods 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000007599 discharging Methods 0.000 description 4
- HGINCPLSRVDWNT-UHFFFAOYSA-N Acrolein Chemical compound C=CC=O HGINCPLSRVDWNT-UHFFFAOYSA-N 0.000 description 1
- 241000905957 Channa melasoma Species 0.000 description 1
- 241000820057 Ithone Species 0.000 description 1
- 241001435619 Lile Species 0.000 description 1
- 208000003251 Pruritus Diseases 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N ferric oxide Chemical compound O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 230000007803 itching Effects 0.000 description 1
- QHGVXILFMXYDRS-UHFFFAOYSA-N pyraclofos Chemical compound C1=C(OP(=O)(OCC)SCCC)C=NN1C1=CC=C(Cl)C=C1 QHGVXILFMXYDRS-UHFFFAOYSA-N 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/14—Dummy cell management; Sense reference voltage generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
Abstract
ABSTRACT:
"Semiconductor memory array."
An improved read-only memory arrangement for generating a differential output signal within the memory array (11) itself incorporates a column of reference cell translators (16) and a single reference bit line (13) within the same general area occupied by the memory cell transistors (10) and memory main bit lines (12). Each word line is coupled to the gate of one of the reference cell transistors (16) as well as to the gates of the memory cell transistors (10) lying in the same row. The reference bit line voltage is maintained substantially midway between the high and low potential levels of the main bit lines to produce a differential output voltage for sensing pur-poses.
"Semiconductor memory array."
An improved read-only memory arrangement for generating a differential output signal within the memory array (11) itself incorporates a column of reference cell translators (16) and a single reference bit line (13) within the same general area occupied by the memory cell transistors (10) and memory main bit lines (12). Each word line is coupled to the gate of one of the reference cell transistors (16) as well as to the gates of the memory cell transistors (10) lying in the same row. The reference bit line voltage is maintained substantially midway between the high and low potential levels of the main bit lines to produce a differential output voltage for sensing pur-poses.
Description
PH~ 1048 l 12-3-1981 "Semiconductor memory arra~."
A semiconductor memory array including a plurali-ty of memory transistors arranged in rows and columns and a plurality of main bit lines extending parallel to said columns, each Main bi-t line coupled to a separate column of said memory cell transistors, a column of reference cell transistors and a reference bit line extending parallel to said rnemory cell trallsistor colllmns and located within the same area of the mernory array as said memory cell tran-sistors; a plurality of word lines extending parallel to said rows of memory cell transistors and coupled respec-tively to the gates of the memory cell -transistors and to the gate of the reference cell transistor lying in a given ro~; and detection means coupled between said reference bit line and each of the main bit lines to sense the presence or absence, effectively, of a memory cell transis-tor at an address determined by selec-ting a given word line and a given main bit line.
Differential sense amplifiers for ROMS are l~nown which sense the state of a memory cell b~ detecting the difference in potential between the gate of a re.erence transistor having a fixed reference potential and -the gate of another transistor coupled to a column line o~ the memory cell. U.S. Patent 3,938,108 discloses an example of such a di~ferential sense amplifier. In that patent a dummy cell of the same dimensions as thc memory cell and having its gate tied to a fixed voltage is used to provide -the reference voltage level. The dummy cell is located out-side the memory cell area. Wllile the gate of the dummy cell is held at some fixed potential between ground and supply voltage, the gate o~ -the trans~stors coupled to a selected column line will vary betweon ground and the supply voltage when the rnemory is accessed. An access time of 200-300 nanoseconds is asserted for the memory dis-~ ~7~5~7 P~IA 10~8 2 12-3-1981 closed in the patent.
Summary o~ the vention.
According to this invention an improved memory arrangement is disclosed for generating a d-ifferential out-put signal within the memory array itself. The rnemory arrayincludes not only the usual array o~ memory cell -transistors, along with intersecting main bit lines and word lines, but also incorporated within the memory arra~,T are a column of re~erence cell trans-istors and a slngle re~erence bit line ~rom which the reference voltage is derived.
Each word line is coupled not only to the gates of the memory cell transistors but also to the gate o~ a respective one of the re~erence cell transis-tors lying in the sarne row as the memory cell transistors. This con~igu-l5 ration is also substantiallr known ~rom our own US PatentApplication No. 4,112,511 dates 12.11.7~.
It is advantageous when the main bit lines have weLl defined logic levels. There~for the Memory according to the invention is characterized in that the memory array 20 ~urther includes pull-up load transistor means coupled to each o~ the main bit lines and to the re~erence bit line, pull-down transistor means coupled to each o~ said main bit lines and to said re~erence bit line, the pull-up load transistor meansl the pull-down transistor means, the 25 meMory cell transistors, and the re~erence cell transistors being so related ln size and transcollductance that with operating voltages applied to said re~erence bit line and said main bit lines through said pull-up load transistor means, a selected main bit line will assume either a high 30 potential level above the potential o~ the re*erence bit line to indicate -the absence o~ a rnemory cell transistor at the selected memory cell address or a low potential level below the potential o~ the re~erence bit line to indicate the presence o~ a memory cell transis-tor at -the 35 selected memory address.
It is advantageous -to choose an appropriate value ~or -the re-~erence bit line voltage. There~or -the memory accordin~ to the invention is characterized in that said ~ '7~S~'~
PEIA 104~ 3 -12-3-19~1 transistors and transistor means are so related that the potential of the re.erellce bit line is approximately rnidwa-5 betweell the high and low potential Levels of the selected main blt line.
I-t is advantageous to be able to select fr~m 011t-side any address within the memory us-Lng fewer terninals.
Therefor the memory array according to the invention is characteriæed :in that it further includes a plurality of column decode lines and a plurality of ro~ decode lines, said column decode lines coupled individually to at least one main bit line, each of said row decode lines coupled separately to an individual row of memory cell transjstors and to an individual reference cell transistor of saLd coluMn o~ reference cell -transistors.
It is advantageo11s to be able to select an address by rneans of the pull-up load transistor means. Therefor the menory array according to the invention is characterized in that the pull-up load transistor means includes a first transistor coupled in series with a respective main bit 20 line and a second transistor coupled in series with the reference bit line, the gates of the first transis-tors be:Lng coupled to the respective column decode lines.
The differential voltage thus developed across the reference bit line and a selected rnain bit llne may 25 be further arnplified in one or more differen-tial amplifier stages.
Fig. 1 :is a circuit diagram of a read-only memory array according -to the in~estion; and Fig. 2 is a graph of waveforms useful in explain-30 ing the operatioll o~ the invention.
In Fig. 1 there is shown a read-only meMory array according to the invention. The ~orm of memory shown is rnask programmable, which is the non-erasable kind. ~Iowever 3 the memory arrangement according to the invention may be 35 incorporated -in other kinds of non-volatile memories, such as electrica1ly programmable mermories of the non-erasable or erasable k:ind. In -this figure, a programmable memory . elemellt, such as a transistor, is sllown within a circle, S~
whereas a :fixed transistor is shown wlthout suc.h a c,ircle.
~ plurality ol columns and rows o~ programmable memory cell transistors 10 are ar:rangecl with a memory array 11. Column l:ines or main bit l:ines 12 e~-tend verti^ally betl~een the columns of meMory cell -transistors 10. While the presence or absence of a neMory cell t-rans:istor 10 at any particular mernory location r.1ay be determined before-hand, all locations of the memory cell transistors are shown filled and comlested. ~owever, i,t is understood that during lO manu~ac-ture some of these locations may be masked to e:ther e~clude a memory cell transistor 10 or to open up a con-necting linl~ to the memory cell transistor.
The sources of the memory cell transistors 10 are coupled to common ground Vss, and the drains are coupled to the main bit lines 12, The main bit l~nes 12 are coupled at one end to a voltage supply Vcc through pull-up load transistors 14 which are gated by column decode lines Y ...
Y15, and are also coupled at the opposite end to common ground Vss through pull-down transistors 15 which have their 20 gates tied to the voltage supply Vcc through a bus conduc~
tor 13. ~ach column decode line i.s coupled to two main bit lines 12.
Included witllin the memory array 11 itsel~ in close pro~imity to the area occupied by memory cell transis-tors 25 10 is a column of reference cell transistors 16 and a re-ference bit line 18. The sources o~ the reference cell translstors 16 are coupled to common ground Vss, and the drains are coupled to the reference bit line 18. The referen-ce bit line 1~ is coupled at one end t-o the voltage supply 30 Vcc through a pull-up load t:ransistor 20, whlch has its gate tied to the voltage supply Vcc~ and is also coupled at tlle opposi-te end to common ground Vss -through a pull-down transistor 22, which has its gate`tied to the voltage supply Vcc through the bus conduc-tor 13.
L~ plurality o~ word or row decode lines R
R127 e~.{tend horizontally along the rows of memory cell transistors 109 each row also including a re~erence cell transistor 16. Eacll o:f the rou decode lines is coupled to '7~ '7 ~HA 1048 5 12-3-1981 all of the gates of the memory ceLl trans:i.:3-tors 10 lying in a given row and 1;o the gate of -the reference cell transistor 16 in -the same row.
A differential sense ampli:~ier 23 recei~es diffe--rentia1 input signals from the mai.n l~it lines 12 and there~erence bi-t line 18. The input signal from the reference bit line 18 is received hy the gates of two reference input transistors '4a and 24b. The input si.gnals ~ro:n each pair o~ main bit lines served b~r a column de~ode l.ine ar~ re-ceived by the gates of a pair of maln input transistors,such as 26a, ~6b for the two bit l-ines coupled to decode line Y0, and 2~a, 28b for the two bit lines coupled to de-code line Y15.
The drai:ns o~ the two reference input transistors 15 24a, 24b are connected to a .first common drain node D, which is coupled to the voltage .supply Vcc through a depletion load transistor 30 having its gate tied to its source.
Similarly, the drains o:f the ma-n input transistors 26a, 26b, 28a, 28b are co~lected to a second commo.n drain node 20 D, which is coupled to the voltage supply Vcc through an-1 other depletion load traLlsistor 32 having its gate tied to its source.
The sources of one re~erence input transistor 24aand of corresponding main input transistors 26a, 28a, are 25 connected :in common to a first source node S and through a first gating transistor 34 to common ground Vss. Similar-l-y -the sources of the other reference input transistor 24b and of the other main input transistors 26b, 28b are con-. nected in common to a second source node S1 and through a ~ 30 second gating transistor 36 to commo:n ground Vss.
The gating t:ransistors 3~ and 36 may be gated by sw.itching vol-tage :inputs VR0 and VR1, respectively, with amplitudes equl to the suppl-y voltage Vcc. The volta~es VR0 and VR1 select one of the two main bit lines 12 s~rved by 35 each ~ the column decode lines Y~ Y15o While there are two main bit lines 12 shown ~or each colurnn decode line Yo...Y15, this is done primarily for the purpose o~ con-serving space on the die. If desired~ there may be one '7~2'7 P~l~ 1048 6 12-3-1~81 column decode line ~or each main bit line, in which case only one of -the gating trans-.stors 34 or 36 is necessary and the other one can be om-tted.
In the memory unit sho~n in thls particular ern-bodiment~ there are 16 column decode lines and 1;wo memorycell columns ror each decode line, ~or a total o~ 32 columns o~ memory cells. Also there are 128 word lines or ro1~ de-code lines, T~ith one row o~ memory cel~s :~or ea-h word llne, i~ing a total o~ l28 rows o~ memory cells. The -tota~
10 ~umber o~ memory bits is 128 ~ 32 or 4096 bits. Eight such mer.1ory units can be combined on a single chip to give a 4K x 8 (32K) memory, -~or example.
According to one arrangernent the re~erence celL
transistor 16 is about one-hal~` tlle size o~ that o~ the 15 memory cell transis-tors 10, such that the ~ormer has twice the resistance of the la-t-ter. The pull~up load transistors 14 and ~0 are equal in size and have a lower resistance than the rnemory cell transistors 10. The pull-do~n transis-tors 15 have res-istances equal to that o~ pull-do~n transis-20 tor 22 on the re~erence bit line 18. ~ccording to one alter-native, the re~erence cell transistor 16 ma-~r be the san1e size as the memory cell transistor 10 and the pull-up load transistor 14 can have about hal~ tlle resistance o~ the pull-up load transistor 20. According to another alternative, 25 re~erence cell transistor 16 may be the sar~e size as rnemory cell transistor 10, the pull-up load transistors 14 may have the same size as pull-up load transistor 20, and the pull-do-~n translstors 15 may have resistances d~ ering ~rom that o~ pull-do1~n transistor 22. The pull-up load transistor 20 30 on the reference bit line 13 has its gate(and drain) -tied to the voltage supply V while the pull-up load transis-tors 14 on the main bit line~q 12 are selected by the res-pective column decode line ~' ..Y15, wliose potential ~s at supply voltage Vcc when selected and at common ground 35 V when not selected. The pull-down transistors 15 are ~or the purpose o~ discharging of the-lr re.spcctive main bit lines to ground potential ;~hen the sta-tus o~ those bit lines changes ~rom selected into not selec-ted.
PHA 1048 7 l2-3-1981 Tlle relative resistances of the pull-up load transistors 14 and the pull-dow.n transistors 15 on the main bi.t lines 12 are chosen such that the potential on a se-lected main bit l.ine 12 is one volt lower when a rnemory cell transistor 10 Ls programmed .in, than when it is not and the corre.3pondillg row decode li.ne R~...R127 and column decode line ~ ...Y1_ are selected. Since the reference ^ell transistor 16 has about one-half the gain o~ the memory cell tra-nsistors 10 and is also ga-ted by the same row decode ine, the re~erence pote:ntial is typically mi.dway between -the two potential levels of the main bit line. ~lso the resistance o~ the pull-up load transistors 14 is chosen relatively low so that it can quickly charge up the para-s.itic capacitance on a ma n bit line 12 ~rom common ground lS up to its ~inal value when the corresponding colu~l decode line Yo...Y15 is selected.
I:n operation, suppose column decode line Y , row decode line R~, and gate input ~R0 -to -the gating transistor 34 are selected. The gating transistor 34 will conduct, 20 pulling the source line S0 to about 1 vol-t and thereby providing a current path to ground -~or all.the transistors connected to source line S0; nameLy re~erence input tran-sistor 24a and such rnain input transistors as 26a and 28a.
(The reference bit line 1~ is alwa-ys selected because it ; 25 is connected to the gates o:~ both input transistors 24a and 24b). The main bit line 1~ connected to the gate.
trans:istor 26a will be selected. As a result o-. this main bit line selection and the selection of row decode line R23 the memory cell -transis-tor 10a at the intersection o~
30 these two lines wil~ be selected.
The potential o~ the selected mai.n bit li-ne 1~a is e:ither higher or lower than the potential o~ the re~eren-ce b t line 18, depending UpOM whether -the selected memory cell -trans-istor IOa is programmed out or programmed in, 35 respectively. This results ~rom -the voltage d:ivider arrange-ment o:~ the pull~up load transi.stor 14 in series with the pull-do~l t:ransis-tor 15. The unselected main bit line shunted or not by the memory cell trans:Lstor l4 pairs are ~ :~.'7~ 7 ; PI~A 1048 ~ 12-3-1981 held at ground potential through the pull--lown transistors 15. Thus a differen-tial input si2nal applied between -the gates of input transistors 24a and 26a results in an ampli-fied clifferen-tial output signal across the drain nodes D
S and D.
Since the absolute potential of the blt lines is not importal1t~ the pull-up load transistors 14 and 20 ma~
~ be high galn transistors for fast bit line charging times.
; Also, the differential voltage developed across the referen-ce bit line 13 and the selected main bit line 12 can be as smaLl as allol/ed b~ the sensitivity of the d-f~erential amplifier.
Reference is now made to Fig. 2 which shows a cornparisol1 of bit line charglng and dlscharging waveforms 15 for a memory arrangerne}1t according ~o the prior art, curve 40 shows the charging of a main bit line from its zero (O) state to the one (1) state and curve 42 shows the dischar-ging of the main bit line .rom its one (1) state to the zero '~ (O) state. The voltage reference level ~REF is a constant 20 level between the zero and one levels. The intersection point 44 ~n the reference level ~REF represents the po nt where both curves 40 and 42 have reached the-ir transi~ion above and below the re:~erence level ~REF. The transitiOll point 44, which is the earliest time that the differential 25 amplifier can sense the differen-tial voltage, occurs at time t2 after initial time t .
For -the arrangernent according to the invention, curve 46 shows the charging of a main bit line, curve 48 shows the discharging of another main bit line, and curve 30 50 shows the ~oltage on -the refere11ce bit line. Instead of being at a fixed reference voltage level, the reference bit line voltage varies so that it is alwa~s approximatel~
midwa~ between the two voltage levels o~ -the main b-t lines.
Since the charging of a main bit line is fas-ter than the 35 discharging -the reierence voltage rises along with the charging curve 46 until -the -trans:i-tion point 52 is reached, which is the point where all three curves 56, 48, 50 inter-sect. This transition point 52 occurs at time t~ 1ich is 7~
an earlier point in -time than t2, the tralls:ition point for the prior art. The refereIlce bit line voltage varies because the reference cell transistor 16 on the re~erence bit line 1~ is gated by -the same word line voltage that gates the memory cell transistors 10 on the main bit line 1 :'.
It will be apparent from the comparison o~ the two graphs of Fig. 2 that -the memory arrangement according to -this invention provides faster access to the memory thall can be accomplished by the prior art. Acess'-times as 'ow as 100 to 150 nanoseconds can be achieved as compared ~rith 200 to 300 nanoseconds for the prior art.
W~lile the Lllustrated embodi.meIlt has described a 32K ROM, it will be apparent -to those ~skilled in the art that the invention can also be applied to memories o~ other densities and configuration. The principles of the invention can likewise be applied to EPROMS and EEPROMS, ` 25
A semiconductor memory array including a plurali-ty of memory transistors arranged in rows and columns and a plurality of main bit lines extending parallel to said columns, each Main bi-t line coupled to a separate column of said memory cell transistors, a column of reference cell transistors and a reference bit line extending parallel to said rnemory cell trallsistor colllmns and located within the same area of the mernory array as said memory cell tran-sistors; a plurality of word lines extending parallel to said rows of memory cell transistors and coupled respec-tively to the gates of the memory cell -transistors and to the gate of the reference cell transistor lying in a given ro~; and detection means coupled between said reference bit line and each of the main bit lines to sense the presence or absence, effectively, of a memory cell transis-tor at an address determined by selec-ting a given word line and a given main bit line.
Differential sense amplifiers for ROMS are l~nown which sense the state of a memory cell b~ detecting the difference in potential between the gate of a re.erence transistor having a fixed reference potential and -the gate of another transistor coupled to a column line o~ the memory cell. U.S. Patent 3,938,108 discloses an example of such a di~ferential sense amplifier. In that patent a dummy cell of the same dimensions as thc memory cell and having its gate tied to a fixed voltage is used to provide -the reference voltage level. The dummy cell is located out-side the memory cell area. Wllile the gate of the dummy cell is held at some fixed potential between ground and supply voltage, the gate o~ -the trans~stors coupled to a selected column line will vary betweon ground and the supply voltage when the rnemory is accessed. An access time of 200-300 nanoseconds is asserted for the memory dis-~ ~7~5~7 P~IA 10~8 2 12-3-1981 closed in the patent.
Summary o~ the vention.
According to this invention an improved memory arrangement is disclosed for generating a d-ifferential out-put signal within the memory array itself. The rnemory arrayincludes not only the usual array o~ memory cell -transistors, along with intersecting main bit lines and word lines, but also incorporated within the memory arra~,T are a column of re~erence cell trans-istors and a slngle re~erence bit line ~rom which the reference voltage is derived.
Each word line is coupled not only to the gates of the memory cell transistors but also to the gate o~ a respective one of the re~erence cell transis-tors lying in the sarne row as the memory cell transistors. This con~igu-l5 ration is also substantiallr known ~rom our own US PatentApplication No. 4,112,511 dates 12.11.7~.
It is advantageous when the main bit lines have weLl defined logic levels. There~for the Memory according to the invention is characterized in that the memory array 20 ~urther includes pull-up load transistor means coupled to each o~ the main bit lines and to the re~erence bit line, pull-down transistor means coupled to each o~ said main bit lines and to said re~erence bit line, the pull-up load transistor meansl the pull-down transistor means, the 25 meMory cell transistors, and the re~erence cell transistors being so related ln size and transcollductance that with operating voltages applied to said re~erence bit line and said main bit lines through said pull-up load transistor means, a selected main bit line will assume either a high 30 potential level above the potential o~ the re*erence bit line to indicate -the absence o~ a rnemory cell transistor at the selected memory cell address or a low potential level below the potential o~ the re~erence bit line to indicate the presence o~ a memory cell transis-tor at -the 35 selected memory address.
It is advantageous -to choose an appropriate value ~or -the re-~erence bit line voltage. There~or -the memory accordin~ to the invention is characterized in that said ~ '7~S~'~
PEIA 104~ 3 -12-3-19~1 transistors and transistor means are so related that the potential of the re.erellce bit line is approximately rnidwa-5 betweell the high and low potential Levels of the selected main blt line.
I-t is advantageous to be able to select fr~m 011t-side any address within the memory us-Lng fewer terninals.
Therefor the memory array according to the invention is characteriæed :in that it further includes a plurality of column decode lines and a plurality of ro~ decode lines, said column decode lines coupled individually to at least one main bit line, each of said row decode lines coupled separately to an individual row of memory cell transjstors and to an individual reference cell transistor of saLd coluMn o~ reference cell -transistors.
It is advantageo11s to be able to select an address by rneans of the pull-up load transistor means. Therefor the menory array according to the invention is characterized in that the pull-up load transistor means includes a first transistor coupled in series with a respective main bit 20 line and a second transistor coupled in series with the reference bit line, the gates of the first transis-tors be:Lng coupled to the respective column decode lines.
The differential voltage thus developed across the reference bit line and a selected rnain bit llne may 25 be further arnplified in one or more differen-tial amplifier stages.
Fig. 1 :is a circuit diagram of a read-only memory array according -to the in~estion; and Fig. 2 is a graph of waveforms useful in explain-30 ing the operatioll o~ the invention.
In Fig. 1 there is shown a read-only meMory array according to the invention. The ~orm of memory shown is rnask programmable, which is the non-erasable kind. ~Iowever 3 the memory arrangement according to the invention may be 35 incorporated -in other kinds of non-volatile memories, such as electrica1ly programmable mermories of the non-erasable or erasable k:ind. In -this figure, a programmable memory . elemellt, such as a transistor, is sllown within a circle, S~
whereas a :fixed transistor is shown wlthout suc.h a c,ircle.
~ plurality ol columns and rows o~ programmable memory cell transistors 10 are ar:rangecl with a memory array 11. Column l:ines or main bit l:ines 12 e~-tend verti^ally betl~een the columns of meMory cell -transistors 10. While the presence or absence of a neMory cell t-rans:istor 10 at any particular mernory location r.1ay be determined before-hand, all locations of the memory cell transistors are shown filled and comlested. ~owever, i,t is understood that during lO manu~ac-ture some of these locations may be masked to e:ther e~clude a memory cell transistor 10 or to open up a con-necting linl~ to the memory cell transistor.
The sources of the memory cell transistors 10 are coupled to common ground Vss, and the drains are coupled to the main bit lines 12, The main bit l~nes 12 are coupled at one end to a voltage supply Vcc through pull-up load transistors 14 which are gated by column decode lines Y ...
Y15, and are also coupled at the opposite end to common ground Vss through pull-down transistors 15 which have their 20 gates tied to the voltage supply Vcc through a bus conduc~
tor 13. ~ach column decode line i.s coupled to two main bit lines 12.
Included witllin the memory array 11 itsel~ in close pro~imity to the area occupied by memory cell transis-tors 25 10 is a column of reference cell transistors 16 and a re-ference bit line 18. The sources o~ the reference cell translstors 16 are coupled to common ground Vss, and the drains are coupled to the reference bit line 18. The referen-ce bit line 1~ is coupled at one end t-o the voltage supply 30 Vcc through a pull-up load t:ransistor 20, whlch has its gate tied to the voltage supply Vcc~ and is also coupled at tlle opposi-te end to common ground Vss -through a pull-down transistor 22, which has its gate`tied to the voltage supply Vcc through the bus conduc-tor 13.
L~ plurality o~ word or row decode lines R
R127 e~.{tend horizontally along the rows of memory cell transistors 109 each row also including a re~erence cell transistor 16. Eacll o:f the rou decode lines is coupled to '7~ '7 ~HA 1048 5 12-3-1981 all of the gates of the memory ceLl trans:i.:3-tors 10 lying in a given row and 1;o the gate of -the reference cell transistor 16 in -the same row.
A differential sense ampli:~ier 23 recei~es diffe--rentia1 input signals from the mai.n l~it lines 12 and there~erence bi-t line 18. The input signal from the reference bit line 18 is received hy the gates of two reference input transistors '4a and 24b. The input si.gnals ~ro:n each pair o~ main bit lines served b~r a column de~ode l.ine ar~ re-ceived by the gates of a pair of maln input transistors,such as 26a, ~6b for the two bit l-ines coupled to decode line Y0, and 2~a, 28b for the two bit lines coupled to de-code line Y15.
The drai:ns o~ the two reference input transistors 15 24a, 24b are connected to a .first common drain node D, which is coupled to the voltage .supply Vcc through a depletion load transistor 30 having its gate tied to its source.
Similarly, the drains o:f the ma-n input transistors 26a, 26b, 28a, 28b are co~lected to a second commo.n drain node 20 D, which is coupled to the voltage supply Vcc through an-1 other depletion load traLlsistor 32 having its gate tied to its source.
The sources of one re~erence input transistor 24aand of corresponding main input transistors 26a, 28a, are 25 connected :in common to a first source node S and through a first gating transistor 34 to common ground Vss. Similar-l-y -the sources of the other reference input transistor 24b and of the other main input transistors 26b, 28b are con-. nected in common to a second source node S1 and through a ~ 30 second gating transistor 36 to commo:n ground Vss.
The gating t:ransistors 3~ and 36 may be gated by sw.itching vol-tage :inputs VR0 and VR1, respectively, with amplitudes equl to the suppl-y voltage Vcc. The volta~es VR0 and VR1 select one of the two main bit lines 12 s~rved by 35 each ~ the column decode lines Y~ Y15o While there are two main bit lines 12 shown ~or each colurnn decode line Yo...Y15, this is done primarily for the purpose o~ con-serving space on the die. If desired~ there may be one '7~2'7 P~l~ 1048 6 12-3-1~81 column decode line ~or each main bit line, in which case only one of -the gating trans-.stors 34 or 36 is necessary and the other one can be om-tted.
In the memory unit sho~n in thls particular ern-bodiment~ there are 16 column decode lines and 1;wo memorycell columns ror each decode line, ~or a total o~ 32 columns o~ memory cells. Also there are 128 word lines or ro1~ de-code lines, T~ith one row o~ memory cel~s :~or ea-h word llne, i~ing a total o~ l28 rows o~ memory cells. The -tota~
10 ~umber o~ memory bits is 128 ~ 32 or 4096 bits. Eight such mer.1ory units can be combined on a single chip to give a 4K x 8 (32K) memory, -~or example.
According to one arrangernent the re~erence celL
transistor 16 is about one-hal~` tlle size o~ that o~ the 15 memory cell transis-tors 10, such that the ~ormer has twice the resistance of the la-t-ter. The pull~up load transistors 14 and ~0 are equal in size and have a lower resistance than the rnemory cell transistors 10. The pull-do~n transis-tors 15 have res-istances equal to that o~ pull-do~n transis-20 tor 22 on the re~erence bit line 18. ~ccording to one alter-native, the re~erence cell transistor 16 ma-~r be the san1e size as the memory cell transistor 10 and the pull-up load transistor 14 can have about hal~ tlle resistance o~ the pull-up load transistor 20. According to another alternative, 25 re~erence cell transistor 16 may be the sar~e size as rnemory cell transistor 10, the pull-up load transistors 14 may have the same size as pull-up load transistor 20, and the pull-do-~n translstors 15 may have resistances d~ ering ~rom that o~ pull-do1~n transistor 22. The pull-up load transistor 20 30 on the reference bit line 13 has its gate(and drain) -tied to the voltage supply V while the pull-up load transis-tors 14 on the main bit line~q 12 are selected by the res-pective column decode line ~' ..Y15, wliose potential ~s at supply voltage Vcc when selected and at common ground 35 V when not selected. The pull-down transistors 15 are ~or the purpose o~ discharging of the-lr re.spcctive main bit lines to ground potential ;~hen the sta-tus o~ those bit lines changes ~rom selected into not selec-ted.
PHA 1048 7 l2-3-1981 Tlle relative resistances of the pull-up load transistors 14 and the pull-dow.n transistors 15 on the main bi.t lines 12 are chosen such that the potential on a se-lected main bit l.ine 12 is one volt lower when a rnemory cell transistor 10 Ls programmed .in, than when it is not and the corre.3pondillg row decode li.ne R~...R127 and column decode line ~ ...Y1_ are selected. Since the reference ^ell transistor 16 has about one-half the gain o~ the memory cell tra-nsistors 10 and is also ga-ted by the same row decode ine, the re~erence pote:ntial is typically mi.dway between -the two potential levels of the main bit line. ~lso the resistance o~ the pull-up load transistors 14 is chosen relatively low so that it can quickly charge up the para-s.itic capacitance on a ma n bit line 12 ~rom common ground lS up to its ~inal value when the corresponding colu~l decode line Yo...Y15 is selected.
I:n operation, suppose column decode line Y , row decode line R~, and gate input ~R0 -to -the gating transistor 34 are selected. The gating transistor 34 will conduct, 20 pulling the source line S0 to about 1 vol-t and thereby providing a current path to ground -~or all.the transistors connected to source line S0; nameLy re~erence input tran-sistor 24a and such rnain input transistors as 26a and 28a.
(The reference bit line 1~ is alwa-ys selected because it ; 25 is connected to the gates o:~ both input transistors 24a and 24b). The main bit line 1~ connected to the gate.
trans:istor 26a will be selected. As a result o-. this main bit line selection and the selection of row decode line R23 the memory cell -transis-tor 10a at the intersection o~
30 these two lines wil~ be selected.
The potential o~ the selected mai.n bit li-ne 1~a is e:ither higher or lower than the potential o~ the re~eren-ce b t line 18, depending UpOM whether -the selected memory cell -trans-istor IOa is programmed out or programmed in, 35 respectively. This results ~rom -the voltage d:ivider arrange-ment o:~ the pull~up load transi.stor 14 in series with the pull-do~l t:ransis-tor 15. The unselected main bit line shunted or not by the memory cell trans:Lstor l4 pairs are ~ :~.'7~ 7 ; PI~A 1048 ~ 12-3-1981 held at ground potential through the pull--lown transistors 15. Thus a differen-tial input si2nal applied between -the gates of input transistors 24a and 26a results in an ampli-fied clifferen-tial output signal across the drain nodes D
S and D.
Since the absolute potential of the blt lines is not importal1t~ the pull-up load transistors 14 and 20 ma~
~ be high galn transistors for fast bit line charging times.
; Also, the differential voltage developed across the referen-ce bit line 13 and the selected main bit line 12 can be as smaLl as allol/ed b~ the sensitivity of the d-f~erential amplifier.
Reference is now made to Fig. 2 which shows a cornparisol1 of bit line charglng and dlscharging waveforms 15 for a memory arrangerne}1t according ~o the prior art, curve 40 shows the charging of a main bit line from its zero (O) state to the one (1) state and curve 42 shows the dischar-ging of the main bit line .rom its one (1) state to the zero '~ (O) state. The voltage reference level ~REF is a constant 20 level between the zero and one levels. The intersection point 44 ~n the reference level ~REF represents the po nt where both curves 40 and 42 have reached the-ir transi~ion above and below the re:~erence level ~REF. The transitiOll point 44, which is the earliest time that the differential 25 amplifier can sense the differen-tial voltage, occurs at time t2 after initial time t .
For -the arrangernent according to the invention, curve 46 shows the charging of a main bit line, curve 48 shows the discharging of another main bit line, and curve 30 50 shows the ~oltage on -the refere11ce bit line. Instead of being at a fixed reference voltage level, the reference bit line voltage varies so that it is alwa~s approximatel~
midwa~ between the two voltage levels o~ -the main b-t lines.
Since the charging of a main bit line is fas-ter than the 35 discharging -the reierence voltage rises along with the charging curve 46 until -the -trans:i-tion point 52 is reached, which is the point where all three curves 56, 48, 50 inter-sect. This transition point 52 occurs at time t~ 1ich is 7~
an earlier point in -time than t2, the tralls:ition point for the prior art. The refereIlce bit line voltage varies because the reference cell transistor 16 on the re~erence bit line 1~ is gated by -the same word line voltage that gates the memory cell transistors 10 on the main bit line 1 :'.
It will be apparent from the comparison o~ the two graphs of Fig. 2 that -the memory arrangement according to -this invention provides faster access to the memory thall can be accomplished by the prior art. Acess'-times as 'ow as 100 to 150 nanoseconds can be achieved as compared ~rith 200 to 300 nanoseconds for the prior art.
W~lile the Lllustrated embodi.meIlt has described a 32K ROM, it will be apparent -to those ~skilled in the art that the invention can also be applied to memories o~ other densities and configuration. The principles of the invention can likewise be applied to EPROMS and EEPROMS, ` 25
Claims (7)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A semiconductor memory array (11) including a plurality of memory transistors (10) arranged in rows and columns and a plurality of mail bit lines extending parallel to said columns, each main bit line (12) coupled to a se-parate column of said memory cell transistors (10), a column of reference cell transistors (16) and a reference bit line (18) extending parallel to said memory cell transistor columns and located within the same area of the memory array as said memory cell transistors; a plurality of word lines extending parallel to said rows of memory cell transistors (10) and coupled respectively to the gates of the memory cell transistors (10) and to the gate of the reference cell transistor (16) lying in a given row, and detection means (24a, 24b, ... 28a, 28b) coupled between said reference bit line and each of the main bit lines (12) to sense the pre-sence or absence, effectively, of a memory cell transistor (10) at an address determined by selecting a given word line and a given main bit line, characterized in that the memory array further includes pull-up load transistor means (14, 20) couplec to each of the main bit lines (12) and to the reference bit line, pull-down transistor means (15, 22) coupled to each of said main bit lines and to said reference bit line, the pull-up load transistor means (14, 20), the pull-down transistor means (15, 22), the memor cell transistors (10) and the reference cell transistors (16) being so related in size and transconductance that with operating voltages applied to said reference bit line and said main bit lines (12) through said pull-up load transistor means (14), a selected main bit line (12) will assume either a high potential level above the potential of the reference bit line (18) to indicate the absence of a memory cell transistor (10) at the selected memory cell address or a low potential level below the potential of the reference bit line to indicate the presence of a memory cell transistor (10) at the selected memory address.
2. Memory array according to Claim 1, characterized in that said transistors (10, 16) and transistor means (14, 15, 20, 22) are so related that the potential of the refer-ence bit line (18) is approximately midway between the high and low potential levels of the selected main bit line (12).
3. Memory array according to Claim 1, characterized in that it furtherincludes a plurality of column decode lines (Yo...Y15) and a plurality of row decodelines (Ro...
R127), said column decode lines (Yo...Y13) coupled individu-ally to at least one main bit line (12), each of said row decode lines (Ro...R127) coupled separately to an individual row of memory cell transistors (10) and to an individual reference cell transistor (16) of said column reference cell transistors (16).
R127), said column decode lines (Yo...Y13) coupled individu-ally to at least one main bit line (12), each of said row decode lines (Ro...R127) coupled separately to an individual row of memory cell transistors (10) and to an individual reference cell transistor (16) of said column reference cell transistors (16).
4. Memory array according to Claim 1, characterized in that the pull-up load transistor means (14, 20) includes a first transistor (14) coupled in series with a respec-tive main bit line (12) and a second transistor (20) coupled in series with the reference bit line (18), the gates of the first transistors (14) being coupled to the respective column decode lines (Yo...Y15).
5. Memory array according to Claim 4, characterized in that the first and second transistors (14, 20) coupled to the main and reference bit lines respectively have substantially equal transconductances greater than that of the memory cell transistors (10).
6. Memory array according to Claim 4 7 characterized in that the pull-down transistor means (15, 22) includes a third transistor (15) coupled in series with each of said first transistors (14), a fourth transistor (22) coupled in series with said second transistor (20) and means coupling the gates of said pull-down transistors (15, 22) in common.
7. Memory array according to Claim 1, characterized in that the detection means comprises a differential ampli-fier (24a, 26a, ...28a and 24b, 26b...28b) for sensing the differential voltage developed across the reference bit line (18) and each of the main bit lines (12) when operating potentials are applied to the memory array.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/160,725 US4342102A (en) | 1980-06-18 | 1980-06-18 | Semiconductor memory array |
US160,725 | 1980-06-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
CA1171527A true CA1171527A (en) | 1984-07-24 |
Family
ID=22578158
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA000379548A Expired CA1171527A (en) | 1980-06-18 | 1981-06-11 | Semiconductor memory array |
Country Status (7)
Country | Link |
---|---|
US (1) | US4342102A (en) |
JP (1) | JPS6016040B2 (en) |
CA (1) | CA1171527A (en) |
DE (1) | DE3123611A1 (en) |
ES (1) | ES503081A0 (en) |
FR (1) | FR2485242A1 (en) |
GB (1) | GB2078458B (en) |
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-
1980
- 1980-06-18 US US06/160,725 patent/US4342102A/en not_active Expired - Lifetime
-
1981
- 1981-06-11 CA CA000379548A patent/CA1171527A/en not_active Expired
- 1981-06-13 DE DE19813123611 patent/DE3123611A1/en active Granted
- 1981-06-15 GB GB8118372A patent/GB2078458B/en not_active Expired
- 1981-06-15 JP JP56091012A patent/JPS6016040B2/en not_active Expired
- 1981-06-16 ES ES503081A patent/ES503081A0/en active Granted
- 1981-06-16 FR FR8111829A patent/FR2485242A1/en active Granted
Also Published As
Publication number | Publication date |
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FR2485242A1 (en) | 1981-12-24 |
ES8204210A1 (en) | 1982-04-01 |
DE3123611A1 (en) | 1982-03-25 |
JPS5727496A (en) | 1982-02-13 |
GB2078458A (en) | 1982-01-06 |
ES503081A0 (en) | 1982-04-01 |
GB2078458B (en) | 1983-12-21 |
JPS6016040B2 (en) | 1985-04-23 |
DE3123611C2 (en) | 1987-08-13 |
FR2485242B1 (en) | 1984-02-24 |
US4342102A (en) | 1982-07-27 |
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