CA1172380A - Controller and method for transparent resource sharing in microcomputer systems - Google Patents
Controller and method for transparent resource sharing in microcomputer systemsInfo
- Publication number
- CA1172380A CA1172380A CA000442795A CA442795A CA1172380A CA 1172380 A CA1172380 A CA 1172380A CA 000442795 A CA000442795 A CA 000442795A CA 442795 A CA442795 A CA 442795A CA 1172380 A CA1172380 A CA 1172380A
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- microprocessor
- interface
- mass storage
- circuitry
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- 238000000034 method Methods 0.000 title claims description 8
- 238000004891 communication Methods 0.000 claims abstract description 22
- 230000004044 response Effects 0.000 claims abstract description 5
- 238000012545 processing Methods 0.000 claims description 10
- 238000012546 transfer Methods 0.000 claims description 8
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims 9
- 238000009434 installation Methods 0.000 claims 1
- 238000004088 simulation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 15
- 230000006870 function Effects 0.000 description 10
- 230000008901 benefit Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 2
- 101100490184 Drosophila melanogaster Ack gene Proteins 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
Abstract
ABSTRACT
A microprocessor controlled mass storage controller used as an interface for mass storage devices which are shared by a plurality of stand-alone microcomputer systems. The microprocessor controlled mass storage controller comprises a system interface which maintains communications with the host microcomputer: a dedicated microprocessor which maintains the internal control of the entire device and a network interface which maintains the access to the external network. Data transparency and integrity are achieved through the simulation by the controller of the mass storage device characteristics and responses.
A microprocessor controlled mass storage controller used as an interface for mass storage devices which are shared by a plurality of stand-alone microcomputer systems. The microprocessor controlled mass storage controller comprises a system interface which maintains communications with the host microcomputer: a dedicated microprocessor which maintains the internal control of the entire device and a network interface which maintains the access to the external network. Data transparency and integrity are achieved through the simulation by the controller of the mass storage device characteristics and responses.
Description
7~3~3~
The present invention relates to a device ~or transparent resource sharing in microcomputer system6, and more particularly relates to a microprocessor controlled mass storage controller which will enable microcomputer systems to access external mass storage devices and permit a transparen~
data transfer to the user.
BACKGROUND OF THE INVENTIO~
With widespread use oE stand-alone microcomputers, the need to interconnect the individual computers and to share information and resources via networks has led to the development by numerous companies of many schemes and devices to make this sharing possible. However, to date, most, if no~
all, attempts in this area have been met with a fundamental problem. The problem is the requirement for modification of all operating system software packages to run on and accommodate the network system.
A typical microcomputer consists of a keyboard, a pr~cessing unit (which will include the central processor unit, memory, and various system control units), a display unit, and a mass storage system. In most cases the mass storage system will be a floppy disk drive system. The storage system usually consists of four parts: the system interface through which the system and the storage system communicate so that the system can send reques~s for service to the storage system and data ~' ~7~
can be transferred between the compu-ter and the storage system:
the controller tin essence a dedicated microproce~or) which interprets the system reguests and executes the required operations to satisfy the requests; the mass storage device interface through which the controller interacts with the physical storage device; and the storage device itself.
In order for the operatin~ software in a microcomputer to use the storage system, there are normally two interfaces -the low level hardware interface and a higher le~el software interface.
The low level hardware interface refers to the system interface mentioned above as being part of the storage system.
Associated with the system interface is the protocol used so that commands and data can be successfully tra~sferred between computer and controller. In most microcomputers the system interface is connected directly to the microcomputer bus, in which case the protocol is the same as is used to access o~her devices on the bus. However. the storage system may be external to the computer and interfaced to the computer in a different manner. In all cases there must be a well defined physical protocol in order for the computer to communicate with the storage system.
The higher level software interface refers to the way in which software is used to command the storage controller.
The actual commands available; the order in which commands can be delivered; when data is to be ~ransferred; and how status 7~
information can be examined are e~amples of the functions of the software interface. So~ware in the computer usually calls upon established routines ("device drivers") present in the computer (either in ROM or in the operating system) to handle the software interface. ~Iowever, it is possible for software to perform its own interface if the program designer desires.
As an example, in most floppy disk systems, the hardware interface consists of a floppy disk controller module (FDC). This controller typically consists of a special purpose microprocessor control device. Communication between the FDC
and the microcomputer processing uni~ is accomplished through a well defined protocol. This protocol varies between machines.
In most cases the FDC is connected to the data/addressJcontrol bus of the microcomputer. Commands are passed to the FDC and data is transferred to and from the FDC using the protocol.
A disk is logically divided into concentric circular tracks, which are further subdivided into units called sectors. All operations performed with the disk are done in terms of these units. Typical operations include; read a sector or ~rack, write a sector or track, and format a track.
To perform the operations, the microcomputer processing unit addresses the FDC, passing it a command and any required data.
The FDC will then execute the desired command. When finished, the FDC will signal the processor and provide status information, and possibly data if necessary.
Other mass storage systems are similar in concept to 7~3~.~
the floppy disk drive system.
Other network designers have attempted to replace the software interface in order to install their hardware in~o the computers. By replacing the existing device drivers ~ith their own, the designers can make the network usable by other software that used the original device drivers. The problem with this method is that fu-ture releases of operating system6 may include new software that is not compatible with past device drivers, thus requiring that the network designer rewrite the drivers for new releases. This technique of replacing software is called "patching" and has many inherent disadvantages, future incompa-tibility being just one. The other disadvantage to "patching" the operating system is that some application programs will supply their own device drivers, and therefore will not be able to use the network. Also, the user is dependent on the network supplier to furnish the patches for any operating system the user may desire to install in his system.
Background patent references of general interest ar0:
U.S. Patent No. 4,399,50~ of Ronald L. Obermarck et al issued August 16, 1983; U.S. Patent No. 4,303,990 oE ~illiam ~I. Seipp issued December 1, 1981; U.S. Paten~ No. 3,975,712 of Edward C.
Hepworth et al issued August 17, 1976; U.S. Patent No.
4,399,503 of Kenneth R. Hawley issued August 16, 1983; Canadian Patent No. 1,124,883 of David A. Brereton et al issued June 1, 1982; Canadian Patent No. 1,145,85~ of John Vivian et al issued May 3, 1983; Canadian Patent No. 1,12~,87~ of David A. Brereton et al issued June 1, 1982 and Canadian Patent No.
1,106,073 of Richard ~. Lemay et al issued July 28, lsal. Of particular interest is U.S. Patent No. ~,399,504 of Obermarck et al which teaches a software method and means for sharing of data resources in a local multi--processing multi-programming environment by applications executing on one or more central electronic computer systems~
It is an object of the presen~ invention to provide the capability of resource and information sharing from a network system of a microcomputer ~ystem, while at the same time avoiding the problem of the need to modify the software package for the operating system to run on and accommodate the network system. It is a further object of the present invention to provide a network interface for a stand-alone microcomputer which will be invisible to application programs, thereby enabling existing software to be run unchanged on the microcomputer network system. In this way the software base available to the user is not decreased in size as would be the case in adding to the software package to accommodate the network system.
It is a fur~her object of the present invention ~o replace the storage system hardware of the microcomputer system with different interface hardware which will make the system interface function in the same manner as the Griginal interface. In this way all past, present and future software ~ ~72~
designed to work with the original storage device will work with the hardware of the pcesent invention.
SUMMARY ~F THE INVENTIO~
According to the present invention there is provided a microprocessor controlled mass storage controller for coupling a host microcomputer system to a network configuration to provide transparent resource sharing. The microprocessor comprises a system interface means for transferring input and output commands from the microcomputer systems. A dedicated microprocessor means is provided, coupled to the system interface means for processing the commands to simulate the execution of the commands. The microprocessor further provides a network interface means coupled to ~he dedicated microprocessor and associated with the network configuration to transfer data to and from the network configuration on command from the dedicated microprocessor.
As well there is provided a method for providing resource sharing to a microcomputer with a ~ystem interface means, a dedicated microprocessor means and a ne~work interface means, coupled to a network configuration. The method comprises accepting data from the microcomputer into the system interface means in a parallel data format, transferring the data to the network interface means and, if required, converting the data to a serial data format, and transmitting ' .:
7'~3~
the data in appropriate format to the network configuration.
Other data is received from the netwo~k configuration and, if necessary converted to a parallel data format and transferred in parallel format to the microcomputer. The characteristics and responses of a mass storage device are simulated by processing commands sent by the microprocessor and presenting the status to the microprocessor. Data is transmitted and received by the network interEace means to and from the network configuration by executing network commands in the network interface means.
By replacing the existing hardware interface to a mass storage medium of a microcomputer with the hardware interface controller according to the present invention, the function of which is to interface with a communications network while a~
the same time retaining the same characteristics and responses as the original, no other portion (hardware or software) of the host computer need be changed in any way to enable that computer to operate on data from sources other than its originally intended storage medium. Since the main processor is totally unaware of any difference, the desired transparency is achieved. All past and future software designed to work with the storage system will thus work with the device according to the present invention.
' ' ~7'~3~
BRIEF DESCRIPTION OF THE DRAWINGS
Other advantages and objects of the present invention will become apparent upon readi.ng the following detailed description and upon referring to the drawings in which:
FIGURE 1 is a block diagram of a transparent resource sharing device according to the present invention showing its main components;
FIGURES 2, 3 and 4 respectively are more detailed block diagrams of specific components of the device of FIGURE
1, namely, respectively, the system interface, dedicated microprocessor based controller and network interface respectively, these components being arranged for a floppy disk application of the invention:
FIGURE 5 is a logic flow diagram for the internal software that controls the dedicated processor ~ of ~IGURE 1;
FIGURE 6 is a logic flow diagram for the processing of a RECEIVE-INTERRUPT request;
FIGURE 7 i5 a logic flow diagram for the processing of a RECEIVE-END-INTERRUPT request;
FIGURE ~ is a logic flow diagram for the processing of a PRINTER-INTERRUPT request; and FIGURE 9 is a circuit diagram of an optional interface for the connection of a local storage device in addition to the simulated transparent mass storage.
While the invention will be described in conjunc~ion 3~3~
with example embodiments particular to a ~loppy di6k application, it will be understood that it is not intended to limit the invention to such embodiments or such application.
On the contrary, it is intended to cover all alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.
DETAILED DESCRIPTION O~ THE INVENTION
In the following description, similar features in the drawings have been given similar reference numerals.
Turning to FIGURE 1 there is shown a block diagram of the components making up the transparent resource sharing controller device according to the present invention. The controller consists of three major units, a system interface 2, a dedicated control processor (microcomputer) 4 and a network interface 6.
System in~erface 2 is responsible for supporting communication with the host microcompu~er shown generally as 8 in FIGURE 1. It is connected to microcomputer 8 through data bus lO. The system interface 2 is capable of handling ~he protocol required by computer 8, and exactly simulates the characteristics and responses of the normal computer hardware which it replaces. The protocol typically consists of ~he following characteristics:
some way of addressing the interface module;
- a data path so that the data can be transferred to/from the interface module;
- various control signals used to transfer data in a controlled manner with a minimum of errors.
The important portions of the system inter~ace are the data transmitter/receiver 12, the control circuit 1~, and the simulated registers 16.
Data transceiver 12 is enabled when data is to be transferred between the host computer ~ and registers 16, or between the control processor ~ and computer 8. The direction of operation of transceiver 12 is switchable and is selected - according to the source and destination of the data.
Interface control circuit 14 will accept signals from the host computer 8 and the dedicated microprocessor based controller (control processor) 4, and will transceive the required control signals needed to coordinate the operation of the data transceiver 12 and the registers 16. The interface control signals will therefore transceive signals used by the host system, the simulated register bank 16, the transceiver 12 and the control processor 4.
The simulated register bank 16 is needed in order to fully simulate the original control or hardware. The number and function of the registers will vary of course according to the type of mass storage controller being replaced by the hardware according to the present invention. Some typical 7~ 3~
registers include ~ata registers, status and control register~
and regi6ters to contain parameters of operation. In the device according to the present invention, these registers are present and behave in the same manner as the original controller. Also the onboard control processor 4 is capable of accessing registers 16.
A more detailed block diagram of system interface 2 and the interrelationship o~ its components, arranged for a floppy disk application, is shown in FIGURE 2. It will be understood that the actual circuit of system interface Z will depend on the mass storage device being simulated and the nature of the interface for any particular host system 8. The configuration switches 3~ identify the address of the controller on the communication network plus other parameters.
For any particular combination of storage devicethost system, the system interface 2 is well defined. This interface however can obviously vary greatly between com~inations.
Turning to FIGURES 1 and ~, dedicated microprocessor based controller or control processor 4 is responsible for receiving commands from the computer 8 via the system interface
The present invention relates to a device ~or transparent resource sharing in microcomputer system6, and more particularly relates to a microprocessor controlled mass storage controller which will enable microcomputer systems to access external mass storage devices and permit a transparen~
data transfer to the user.
BACKGROUND OF THE INVENTIO~
With widespread use oE stand-alone microcomputers, the need to interconnect the individual computers and to share information and resources via networks has led to the development by numerous companies of many schemes and devices to make this sharing possible. However, to date, most, if no~
all, attempts in this area have been met with a fundamental problem. The problem is the requirement for modification of all operating system software packages to run on and accommodate the network system.
A typical microcomputer consists of a keyboard, a pr~cessing unit (which will include the central processor unit, memory, and various system control units), a display unit, and a mass storage system. In most cases the mass storage system will be a floppy disk drive system. The storage system usually consists of four parts: the system interface through which the system and the storage system communicate so that the system can send reques~s for service to the storage system and data ~' ~7~
can be transferred between the compu-ter and the storage system:
the controller tin essence a dedicated microproce~or) which interprets the system reguests and executes the required operations to satisfy the requests; the mass storage device interface through which the controller interacts with the physical storage device; and the storage device itself.
In order for the operatin~ software in a microcomputer to use the storage system, there are normally two interfaces -the low level hardware interface and a higher le~el software interface.
The low level hardware interface refers to the system interface mentioned above as being part of the storage system.
Associated with the system interface is the protocol used so that commands and data can be successfully tra~sferred between computer and controller. In most microcomputers the system interface is connected directly to the microcomputer bus, in which case the protocol is the same as is used to access o~her devices on the bus. However. the storage system may be external to the computer and interfaced to the computer in a different manner. In all cases there must be a well defined physical protocol in order for the computer to communicate with the storage system.
The higher level software interface refers to the way in which software is used to command the storage controller.
The actual commands available; the order in which commands can be delivered; when data is to be ~ransferred; and how status 7~
information can be examined are e~amples of the functions of the software interface. So~ware in the computer usually calls upon established routines ("device drivers") present in the computer (either in ROM or in the operating system) to handle the software interface. ~Iowever, it is possible for software to perform its own interface if the program designer desires.
As an example, in most floppy disk systems, the hardware interface consists of a floppy disk controller module (FDC). This controller typically consists of a special purpose microprocessor control device. Communication between the FDC
and the microcomputer processing uni~ is accomplished through a well defined protocol. This protocol varies between machines.
In most cases the FDC is connected to the data/addressJcontrol bus of the microcomputer. Commands are passed to the FDC and data is transferred to and from the FDC using the protocol.
A disk is logically divided into concentric circular tracks, which are further subdivided into units called sectors. All operations performed with the disk are done in terms of these units. Typical operations include; read a sector or ~rack, write a sector or track, and format a track.
To perform the operations, the microcomputer processing unit addresses the FDC, passing it a command and any required data.
The FDC will then execute the desired command. When finished, the FDC will signal the processor and provide status information, and possibly data if necessary.
Other mass storage systems are similar in concept to 7~3~.~
the floppy disk drive system.
Other network designers have attempted to replace the software interface in order to install their hardware in~o the computers. By replacing the existing device drivers ~ith their own, the designers can make the network usable by other software that used the original device drivers. The problem with this method is that fu-ture releases of operating system6 may include new software that is not compatible with past device drivers, thus requiring that the network designer rewrite the drivers for new releases. This technique of replacing software is called "patching" and has many inherent disadvantages, future incompa-tibility being just one. The other disadvantage to "patching" the operating system is that some application programs will supply their own device drivers, and therefore will not be able to use the network. Also, the user is dependent on the network supplier to furnish the patches for any operating system the user may desire to install in his system.
Background patent references of general interest ar0:
U.S. Patent No. 4,399,50~ of Ronald L. Obermarck et al issued August 16, 1983; U.S. Patent No. 4,303,990 oE ~illiam ~I. Seipp issued December 1, 1981; U.S. Paten~ No. 3,975,712 of Edward C.
Hepworth et al issued August 17, 1976; U.S. Patent No.
4,399,503 of Kenneth R. Hawley issued August 16, 1983; Canadian Patent No. 1,124,883 of David A. Brereton et al issued June 1, 1982; Canadian Patent No. 1,145,85~ of John Vivian et al issued May 3, 1983; Canadian Patent No. 1,12~,87~ of David A. Brereton et al issued June 1, 1982 and Canadian Patent No.
1,106,073 of Richard ~. Lemay et al issued July 28, lsal. Of particular interest is U.S. Patent No. ~,399,504 of Obermarck et al which teaches a software method and means for sharing of data resources in a local multi--processing multi-programming environment by applications executing on one or more central electronic computer systems~
It is an object of the presen~ invention to provide the capability of resource and information sharing from a network system of a microcomputer ~ystem, while at the same time avoiding the problem of the need to modify the software package for the operating system to run on and accommodate the network system. It is a further object of the present invention to provide a network interface for a stand-alone microcomputer which will be invisible to application programs, thereby enabling existing software to be run unchanged on the microcomputer network system. In this way the software base available to the user is not decreased in size as would be the case in adding to the software package to accommodate the network system.
It is a fur~her object of the present invention ~o replace the storage system hardware of the microcomputer system with different interface hardware which will make the system interface function in the same manner as the Griginal interface. In this way all past, present and future software ~ ~72~
designed to work with the original storage device will work with the hardware of the pcesent invention.
SUMMARY ~F THE INVENTIO~
According to the present invention there is provided a microprocessor controlled mass storage controller for coupling a host microcomputer system to a network configuration to provide transparent resource sharing. The microprocessor comprises a system interface means for transferring input and output commands from the microcomputer systems. A dedicated microprocessor means is provided, coupled to the system interface means for processing the commands to simulate the execution of the commands. The microprocessor further provides a network interface means coupled to ~he dedicated microprocessor and associated with the network configuration to transfer data to and from the network configuration on command from the dedicated microprocessor.
As well there is provided a method for providing resource sharing to a microcomputer with a ~ystem interface means, a dedicated microprocessor means and a ne~work interface means, coupled to a network configuration. The method comprises accepting data from the microcomputer into the system interface means in a parallel data format, transferring the data to the network interface means and, if required, converting the data to a serial data format, and transmitting ' .:
7'~3~
the data in appropriate format to the network configuration.
Other data is received from the netwo~k configuration and, if necessary converted to a parallel data format and transferred in parallel format to the microcomputer. The characteristics and responses of a mass storage device are simulated by processing commands sent by the microprocessor and presenting the status to the microprocessor. Data is transmitted and received by the network interEace means to and from the network configuration by executing network commands in the network interface means.
By replacing the existing hardware interface to a mass storage medium of a microcomputer with the hardware interface controller according to the present invention, the function of which is to interface with a communications network while a~
the same time retaining the same characteristics and responses as the original, no other portion (hardware or software) of the host computer need be changed in any way to enable that computer to operate on data from sources other than its originally intended storage medium. Since the main processor is totally unaware of any difference, the desired transparency is achieved. All past and future software designed to work with the storage system will thus work with the device according to the present invention.
' ' ~7'~3~
BRIEF DESCRIPTION OF THE DRAWINGS
Other advantages and objects of the present invention will become apparent upon readi.ng the following detailed description and upon referring to the drawings in which:
FIGURE 1 is a block diagram of a transparent resource sharing device according to the present invention showing its main components;
FIGURES 2, 3 and 4 respectively are more detailed block diagrams of specific components of the device of FIGURE
1, namely, respectively, the system interface, dedicated microprocessor based controller and network interface respectively, these components being arranged for a floppy disk application of the invention:
FIGURE 5 is a logic flow diagram for the internal software that controls the dedicated processor ~ of ~IGURE 1;
FIGURE 6 is a logic flow diagram for the processing of a RECEIVE-INTERRUPT request;
FIGURE 7 i5 a logic flow diagram for the processing of a RECEIVE-END-INTERRUPT request;
FIGURE ~ is a logic flow diagram for the processing of a PRINTER-INTERRUPT request; and FIGURE 9 is a circuit diagram of an optional interface for the connection of a local storage device in addition to the simulated transparent mass storage.
While the invention will be described in conjunc~ion 3~3~
with example embodiments particular to a ~loppy di6k application, it will be understood that it is not intended to limit the invention to such embodiments or such application.
On the contrary, it is intended to cover all alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.
DETAILED DESCRIPTION O~ THE INVENTION
In the following description, similar features in the drawings have been given similar reference numerals.
Turning to FIGURE 1 there is shown a block diagram of the components making up the transparent resource sharing controller device according to the present invention. The controller consists of three major units, a system interface 2, a dedicated control processor (microcomputer) 4 and a network interface 6.
System in~erface 2 is responsible for supporting communication with the host microcompu~er shown generally as 8 in FIGURE 1. It is connected to microcomputer 8 through data bus lO. The system interface 2 is capable of handling ~he protocol required by computer 8, and exactly simulates the characteristics and responses of the normal computer hardware which it replaces. The protocol typically consists of ~he following characteristics:
some way of addressing the interface module;
- a data path so that the data can be transferred to/from the interface module;
- various control signals used to transfer data in a controlled manner with a minimum of errors.
The important portions of the system inter~ace are the data transmitter/receiver 12, the control circuit 1~, and the simulated registers 16.
Data transceiver 12 is enabled when data is to be transferred between the host computer ~ and registers 16, or between the control processor ~ and computer 8. The direction of operation of transceiver 12 is switchable and is selected - according to the source and destination of the data.
Interface control circuit 14 will accept signals from the host computer 8 and the dedicated microprocessor based controller (control processor) 4, and will transceive the required control signals needed to coordinate the operation of the data transceiver 12 and the registers 16. The interface control signals will therefore transceive signals used by the host system, the simulated register bank 16, the transceiver 12 and the control processor 4.
The simulated register bank 16 is needed in order to fully simulate the original control or hardware. The number and function of the registers will vary of course according to the type of mass storage controller being replaced by the hardware according to the present invention. Some typical 7~ 3~
registers include ~ata registers, status and control register~
and regi6ters to contain parameters of operation. In the device according to the present invention, these registers are present and behave in the same manner as the original controller. Also the onboard control processor 4 is capable of accessing registers 16.
A more detailed block diagram of system interface 2 and the interrelationship o~ its components, arranged for a floppy disk application, is shown in FIGURE 2. It will be understood that the actual circuit of system interface Z will depend on the mass storage device being simulated and the nature of the interface for any particular host system 8. The configuration switches 3~ identify the address of the controller on the communication network plus other parameters.
For any particular combination of storage devicethost system, the system interface 2 is well defined. This interface however can obviously vary greatly between com~inations.
Turning to FIGURES 1 and ~, dedicated microprocessor based controller or control processor 4 is responsible for receiving commands from the computer 8 via the system interface
2, and performs the required operations to simulate the execution of the commands, typically by accessing the network to send/receive da~a, then returning status and optional data to the computer. In the device according to the present invention processor 4 is a dedicated microprocessor configured through the use of hardware and software to operate in the
3~36~
required manner. Such a microprocessor will normally incorporate ROM 22 (which will contain the firmware for the controller), RAM 24 (which will be used to hold temporary information and buffer data while being used) and associated control circuitry 26. The processor 4 may be configured as a one-chip microcomputer (containing RAM, ROM and microprocessor in one integrated circuit) or, as a number o~ separate integrated circuits. In the extreme case, it is possible for the control processor to be a custom made VLSI with the operating software hardwired into the chip.
Control circuitry 26 is necessary in order to coordinate the operation of controller ~ and allow controlled access to the register bank 16 and the network interface 6.
Also present in the control circuit 26 is a clock generation circuit 28.
~s indicated, controller 4 is in essence a small microcomputer. It is the installed software present in R~M 22 and the control circuits 26 that configure this computer for this particular application.
Turning to ~IGURES 1 and 4, the network interface 6 is responsible for allowing the controller 4 to access network 20. The actual network technology and protocols used are immaterial, as this side of the hardware is transparent to the computer 8. Typically, the network interface ~ will consist of two parts. One part will be responsible for handling the low level protocol of the network, such as packet size, device-to-device communication, and error detection. The other part will be the actual transmitter and receiver used to generate the reguired signal characteristics for the network 20.
In some systems, it may be desirable to use both the mass storage controller of the host system and the network controller of the device according to the present invention.
This case will not be a problem ii` the host system will allow more than one storage controller to be present at a time.
However~ in those systems where only one such controller board is allowed at a time, an alternative solution is used. In these cases, the original controller hardware is modified so that the network controller accordiny to the present invention can be interfaced to the original hardware directly. Instead of using the system interface according to the present invention to transfer data between the network controller and the host system, the interface already present on the original controller is used. By adding appropriate control circuitry and software to the device according to the present invention, it can be determined whether to use the actual mass storage device or the network. When the mass storage device is desired, the original controller is enabled in order to satisfy the host system request. Whenever the network is desired, the original controller is disabled and the device according to the present invention will perform the required functions.
It is possible to simula~e more than one device at a time using the device in question. For example, a board has been developed which simulates a floppy disk controller and a printer port on the same board. To simulate more than one device the concepts are exactl~ the same as previously described herein, but the control circuitry and the software are more complex.
In addition to the transparency of the network controller device according to the present invention, it is also possible to write software that "knows" about the network and will take advantage of the network. It is therefore possible to write programs to use the network to its fullest, such as electronic mail, distributed data bases, network operating systems and the like. As well as simulating the operations of the mass storage device, the network interface 6 can also be capable of executing other commands which are particular to the network, thus allowing software ~esigned to use the network to take advantage of the device according to the present invention.
E~AMPL~ APPLICATIONS
First Application An example application for this type of network controller device according to the present invention is that of a simple disk sharing facility. This network consists of a central computer, containing a network interface and floppy .
~L~7~23~q3 disk drives. and a number of computers without local disk drives connected to the network using the device according to the present invention which simula-tes Eloppy disk controllers.
Whenever the sofware within the comput~rs wants ~o access a floppy disk, the device according to the present invention will receive the commands from their host. The commands will then be relayed to the central computer to be acted upon. ~esults will be returned and passed on to the host.
In effect, therefore, the software within the computers operate as though there are floppy disk drives local to each computer, when in fact the drives are present in external computer systems. In this way, disks (and therfore data) can be shared.
Second AP~lication A sin~le tape drive unit can be installed into a central computer. Other computers with the appropriate application of the device according to ~he present invention can be attached to the central computer. In this configuration all the other compu~ers ha~e access to the tape drive unit of the central computer as a back-up, but without the expense usually incurred by buying a tape drive unit for each user.
Third Application In a more complex application, it is possible for a number of microcomputers, each containing its own combina~ion ~5 of floppy disk drives/hard disks/tape drives, all networked together wi~h a central unit also containing these types of 23~3~
storage devices. Each computer can be configured in a number of ways so that each user has available to him, his own local and remote working storage. Also working system software and application programs can be placed in the central unit so that all users have access to them. The above configuration allows for a very flexible resource sharing network with the capability of stand-alone operation as well.
Fourth ~pplication The floppy disk controller board in an IBM Personal Computer (or PCXT) (trade mark) can be replaced with the network interface device according to the present invention.
parallel printer port may be simulated on this device.
The network will be a simple bus or daisy-chained configuration with a central controlling IBM PCXT ttrade mark) containing the floppy images that the slave computers will use. The floppy images are not physical floppys in most cases talthough they can be), but are usually files kept on the ; central hard disk that are made to look like floppys through ~he use of a resident software within the controlling 20 computer. A printer can be shared due to the simulated prin~er port, and printer output can be spooled within the central server so that ~he slave units are freed to perform other operations while the printer is busy.
As far as the slave units are concerned they have access to four floppy disk drives that appear to be local.
However, whenever the computer at~empts to access ~he floppy ` ' ' : `
, 2~
disk controller usually resident, it wiLl actually get the network controller device. Since that de~ice will respond exactly like the original floppy disk controller, the software and the hardware within the slave computer will function properly without the need for changes. In fact slave units do not need to be running the same operating systems, even thou~h they are connected to the same central server. For example, some slaves can be using PC-DOS l.l tTrade Mark), o~hers using PC-DOS 2.0 (Trade Mark), CP~-86 (Trade Mark) or any other operating system available that is able to use the floppy disk drives.
Since the network controller card is transparent tbecause it exactly simulates the floppy disk controller), anything that is designed to be used on an IBM PC with disk drives (whether hardware or software) can still be used.
Therefore, local hard disks are possible, as are RAM disks, communication devices, and even other networks from other manufacturers.
In addition to the above examples, a local floppy disk drive controller can be installed in the manner previously mentioned herein. The system interface on the device of the present invention is partially disabled so that it will not access the IBM system bus whenever the floppy disk controller does. Also the floppy disk controller integrated circuit on the controller board is taken out of that board and a small interface board is plugged in, in its place. The controller ~7;23~3~
integrated circuit is placed into this interface board. The interface board is also connected to the device of the present invention ~ia a cable. It is possibe to configure the resulting system with a number of remote floppy disk drives and a number of local floppy disk drives up to a to~al of four drives. The hardware is capable of determining ~hich drive is being accessed at any particular time and is therefore able ~o decide whether to use the actual floppy disk controller or to use the network. In any case the software and hardware in the computer will "see" all the floppys as being local devices.
FIGURE 5 is a logic flow diagram of ~he seguence of events that takes place for the control of the dedicated microprocessor 25 in FIGURE 3. The instructions are loaded from the Read Only Memory (RO~) 2~ in FIGURE 3 into the microprocessor 24. Upon receipt of a request from the host microcomputer at start step 100, the microprocessor executes instructions to initialize hardware and to start communication network functions. At step 102 the microprocessor 25 sends an interrupt to the host microcomputer after all the software register 16, in FIGURE 2 have been reset. At step 106 the disk status in the register bank 16 is set to READY state, the command and parameters which are sent from the host microcomputer are fetched from the system interface 2 to the microprocessor at step 108 the disk status in the register bank 16 is set to BUSY state and the microprocessor 25 e~ecutes instructions from ROM 22 to interpret the command. Upon 3~
receipt an INPUT command from the host microcomputer at step 110, the microprocessor 25 executes instructions from ROM 22 to transmit a RECEIVE command on the communication network at step 112 and set Random Access Memory ~RAM) 24 ready to receive data from communication network at step 114. At step 116 the data is formated to the form recognizable by the host microcomputer 2 and then output to the host microcomputer through the system interface 2 until no more data is required by the host microcomputer. At step 120 upon sending the last data to the host microcomputer, the microprocessor executes a command to reply -to the communication network with a L~ST DATA signal. At step 122, the microprocessor receives the results Erom the communication network and outputs them to the host microcomputer through the system interface 2 at step 124. Then returns to step 106 waiting to process further commands from the host microcomputer. At step 130, upon receipt of an output command, the microprocessor 25 at step 132 executes instructions resident in the ROM 22 to transmit a TRANSMIT
command to the communication network and waits for the reply status from the communication network at step 134. Upon receipt of the repl~ status from the communication netowrk, at step 136 the microprocessor executes instructions to transmit data to the communication network until the last data has been sent at step 138. At the end of the transmission the microprocessor resets itself to step 122. At step 140, upon receipt of a control command, the microprocessor 25 records the 3~3~
control information in the RAM 24 at step 142 and outputs the results to the host microcomputer at step 14~ and returns to step 106 waiting for further command to be proce6sed.
FIGURE 6 is a logic flow diagram of the sequence of events that takes place in a RECEIVE-INTERRUPT request. A~
step 200, upon receipt of the receive-interrupt request, the microprocessor 25 executes routines resident in ROM 2Z to store the data byte in RAM Z4 and updates the pointer for the RAM 24.
Turning to FIGURE 7 is a logic flow diagram of the sequence of events that take place in a RECEIVE-END-INTERRPUT
request. At step 300 the microprocessor 25 executes routines in ROM 22 to set a end of data indicator on the receive buffer in the RAM 2~. At step 302, the microprocessor 25 verifies for receive errors, and when no error has been detected the RECEIVE-END-INTERRUPT request returns control to the calling routine at step 306. At step 304 when errors have been de~ected, the microprocessor 25 executes routines in ROM 22 to send RE-TRANSMIT request to the communication network, flags the information in the R~M 2~ and then returns control to the calling routine at step 306.
Turning to FIGURE 8, is a logic flow diagram of the sequence of events that take place in a PRINTER INTERRUPT
request. At step 400, the microprocessor stores the data in the RAM 24 and updates the printer for the RAM 24. ~t step 402 the microprocessor 25 returns control to the calling routine when the RAM 24 is not full and sends a printer message to the ~ :~7,.~ 13 communication network when the R~M 2~ is full then returns control to the callin~ routine in step 406.
Turning to FIGURE 9, there is shown a circuit diagram of an optional interface 34 for the connection of a local storage device in addition to the simulated transparent mass storage. The mass storage device controller 37, for example a floppy disk controller, is moved from the socket on the floppy disk controller to the interface 3~. The floppy disk controller socket 38 is then used for the physical connection of interface 34 to the floppy disk controller board.
The tristate buffer 35 provides the interface for data between the system interface 2 and the floppy disk controller.
The 2 to 1 selector 36 selects between the simulated or local floppy disks by the appropriate rou~ing of the control signals (CS, DACK. IRQ, DRQ).
In this way, the interface 34 can selectively enable or disable the local floppy disk controler from the host microcomputer system.
It is important to realize that the present invention provides hardware, in the form of an integrated circuit board, which replaces the standard floppy disk controller of a microcomputer with a network communications device. The system interface 2, of this device, is determined by the host computer for which the particular board is being used. Once the particular computer has been specified, the interface is fairly specific. ~owever this is only true on the system side of the ~'7~
interface. The other side o~ this interface will be decided by what registers 16 are being simulated and on the configuration of the internal controlling microprocessor 25.
Even less specific is the configuration of the network interface 6. The type of network and the protocol used will determine what the interface looks like. If the interface is fairly complex, then the general block diagram will remain as shown in FIGURES 1 and ~. If however ~he network is fairly simple, it is possible to remove the communications circuit 30 and to perform its functions in software.
The actual network interface 32 can ba increased in complexity or decreased in complexity by using less or more software respectively. At one end of the extreme, it is possible for the network controller device according to the present invention to be more complex than the one indicated here, by removing the dedicated microprocessor 25 and its ~oftware and using discreet hardware instead. Or, the control functions may be incorporated into a custom made integrated cirucit which may be either a microprocessor itself or a hardware solution. At the other extreme it is possible to remove a lot of the hardware by performing as many functions as possible by software.
Thus there has been provided in accordance with the present invention a device for transparent resource sharing in microcomputer systems that fully satisfies the objects, aims and advantages set forth above. While the invention has been .~ ~'7~
described in conjunction with specific embodiments thereof, it is evident that many alteLnatives, modifications and variations will be apparen~ to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications and variations as fall within the spirit and broad scope of the appended claims.
required manner. Such a microprocessor will normally incorporate ROM 22 (which will contain the firmware for the controller), RAM 24 (which will be used to hold temporary information and buffer data while being used) and associated control circuitry 26. The processor 4 may be configured as a one-chip microcomputer (containing RAM, ROM and microprocessor in one integrated circuit) or, as a number o~ separate integrated circuits. In the extreme case, it is possible for the control processor to be a custom made VLSI with the operating software hardwired into the chip.
Control circuitry 26 is necessary in order to coordinate the operation of controller ~ and allow controlled access to the register bank 16 and the network interface 6.
Also present in the control circuit 26 is a clock generation circuit 28.
~s indicated, controller 4 is in essence a small microcomputer. It is the installed software present in R~M 22 and the control circuits 26 that configure this computer for this particular application.
Turning to ~IGURES 1 and 4, the network interface 6 is responsible for allowing the controller 4 to access network 20. The actual network technology and protocols used are immaterial, as this side of the hardware is transparent to the computer 8. Typically, the network interface ~ will consist of two parts. One part will be responsible for handling the low level protocol of the network, such as packet size, device-to-device communication, and error detection. The other part will be the actual transmitter and receiver used to generate the reguired signal characteristics for the network 20.
In some systems, it may be desirable to use both the mass storage controller of the host system and the network controller of the device according to the present invention.
This case will not be a problem ii` the host system will allow more than one storage controller to be present at a time.
However~ in those systems where only one such controller board is allowed at a time, an alternative solution is used. In these cases, the original controller hardware is modified so that the network controller accordiny to the present invention can be interfaced to the original hardware directly. Instead of using the system interface according to the present invention to transfer data between the network controller and the host system, the interface already present on the original controller is used. By adding appropriate control circuitry and software to the device according to the present invention, it can be determined whether to use the actual mass storage device or the network. When the mass storage device is desired, the original controller is enabled in order to satisfy the host system request. Whenever the network is desired, the original controller is disabled and the device according to the present invention will perform the required functions.
It is possible to simula~e more than one device at a time using the device in question. For example, a board has been developed which simulates a floppy disk controller and a printer port on the same board. To simulate more than one device the concepts are exactl~ the same as previously described herein, but the control circuitry and the software are more complex.
In addition to the transparency of the network controller device according to the present invention, it is also possible to write software that "knows" about the network and will take advantage of the network. It is therefore possible to write programs to use the network to its fullest, such as electronic mail, distributed data bases, network operating systems and the like. As well as simulating the operations of the mass storage device, the network interface 6 can also be capable of executing other commands which are particular to the network, thus allowing software ~esigned to use the network to take advantage of the device according to the present invention.
E~AMPL~ APPLICATIONS
First Application An example application for this type of network controller device according to the present invention is that of a simple disk sharing facility. This network consists of a central computer, containing a network interface and floppy .
~L~7~23~q3 disk drives. and a number of computers without local disk drives connected to the network using the device according to the present invention which simula-tes Eloppy disk controllers.
Whenever the sofware within the comput~rs wants ~o access a floppy disk, the device according to the present invention will receive the commands from their host. The commands will then be relayed to the central computer to be acted upon. ~esults will be returned and passed on to the host.
In effect, therefore, the software within the computers operate as though there are floppy disk drives local to each computer, when in fact the drives are present in external computer systems. In this way, disks (and therfore data) can be shared.
Second AP~lication A sin~le tape drive unit can be installed into a central computer. Other computers with the appropriate application of the device according to ~he present invention can be attached to the central computer. In this configuration all the other compu~ers ha~e access to the tape drive unit of the central computer as a back-up, but without the expense usually incurred by buying a tape drive unit for each user.
Third Application In a more complex application, it is possible for a number of microcomputers, each containing its own combina~ion ~5 of floppy disk drives/hard disks/tape drives, all networked together wi~h a central unit also containing these types of 23~3~
storage devices. Each computer can be configured in a number of ways so that each user has available to him, his own local and remote working storage. Also working system software and application programs can be placed in the central unit so that all users have access to them. The above configuration allows for a very flexible resource sharing network with the capability of stand-alone operation as well.
Fourth ~pplication The floppy disk controller board in an IBM Personal Computer (or PCXT) (trade mark) can be replaced with the network interface device according to the present invention.
parallel printer port may be simulated on this device.
The network will be a simple bus or daisy-chained configuration with a central controlling IBM PCXT ttrade mark) containing the floppy images that the slave computers will use. The floppy images are not physical floppys in most cases talthough they can be), but are usually files kept on the ; central hard disk that are made to look like floppys through ~he use of a resident software within the controlling 20 computer. A printer can be shared due to the simulated prin~er port, and printer output can be spooled within the central server so that ~he slave units are freed to perform other operations while the printer is busy.
As far as the slave units are concerned they have access to four floppy disk drives that appear to be local.
However, whenever the computer at~empts to access ~he floppy ` ' ' : `
, 2~
disk controller usually resident, it wiLl actually get the network controller device. Since that de~ice will respond exactly like the original floppy disk controller, the software and the hardware within the slave computer will function properly without the need for changes. In fact slave units do not need to be running the same operating systems, even thou~h they are connected to the same central server. For example, some slaves can be using PC-DOS l.l tTrade Mark), o~hers using PC-DOS 2.0 (Trade Mark), CP~-86 (Trade Mark) or any other operating system available that is able to use the floppy disk drives.
Since the network controller card is transparent tbecause it exactly simulates the floppy disk controller), anything that is designed to be used on an IBM PC with disk drives (whether hardware or software) can still be used.
Therefore, local hard disks are possible, as are RAM disks, communication devices, and even other networks from other manufacturers.
In addition to the above examples, a local floppy disk drive controller can be installed in the manner previously mentioned herein. The system interface on the device of the present invention is partially disabled so that it will not access the IBM system bus whenever the floppy disk controller does. Also the floppy disk controller integrated circuit on the controller board is taken out of that board and a small interface board is plugged in, in its place. The controller ~7;23~3~
integrated circuit is placed into this interface board. The interface board is also connected to the device of the present invention ~ia a cable. It is possibe to configure the resulting system with a number of remote floppy disk drives and a number of local floppy disk drives up to a to~al of four drives. The hardware is capable of determining ~hich drive is being accessed at any particular time and is therefore able ~o decide whether to use the actual floppy disk controller or to use the network. In any case the software and hardware in the computer will "see" all the floppys as being local devices.
FIGURE 5 is a logic flow diagram of ~he seguence of events that takes place for the control of the dedicated microprocessor 25 in FIGURE 3. The instructions are loaded from the Read Only Memory (RO~) 2~ in FIGURE 3 into the microprocessor 24. Upon receipt of a request from the host microcomputer at start step 100, the microprocessor executes instructions to initialize hardware and to start communication network functions. At step 102 the microprocessor 25 sends an interrupt to the host microcomputer after all the software register 16, in FIGURE 2 have been reset. At step 106 the disk status in the register bank 16 is set to READY state, the command and parameters which are sent from the host microcomputer are fetched from the system interface 2 to the microprocessor at step 108 the disk status in the register bank 16 is set to BUSY state and the microprocessor 25 e~ecutes instructions from ROM 22 to interpret the command. Upon 3~
receipt an INPUT command from the host microcomputer at step 110, the microprocessor 25 executes instructions from ROM 22 to transmit a RECEIVE command on the communication network at step 112 and set Random Access Memory ~RAM) 24 ready to receive data from communication network at step 114. At step 116 the data is formated to the form recognizable by the host microcomputer 2 and then output to the host microcomputer through the system interface 2 until no more data is required by the host microcomputer. At step 120 upon sending the last data to the host microcomputer, the microprocessor executes a command to reply -to the communication network with a L~ST DATA signal. At step 122, the microprocessor receives the results Erom the communication network and outputs them to the host microcomputer through the system interface 2 at step 124. Then returns to step 106 waiting to process further commands from the host microcomputer. At step 130, upon receipt of an output command, the microprocessor 25 at step 132 executes instructions resident in the ROM 22 to transmit a TRANSMIT
command to the communication network and waits for the reply status from the communication network at step 134. Upon receipt of the repl~ status from the communication netowrk, at step 136 the microprocessor executes instructions to transmit data to the communication network until the last data has been sent at step 138. At the end of the transmission the microprocessor resets itself to step 122. At step 140, upon receipt of a control command, the microprocessor 25 records the 3~3~
control information in the RAM 24 at step 142 and outputs the results to the host microcomputer at step 14~ and returns to step 106 waiting for further command to be proce6sed.
FIGURE 6 is a logic flow diagram of the sequence of events that takes place in a RECEIVE-INTERRUPT request. A~
step 200, upon receipt of the receive-interrupt request, the microprocessor 25 executes routines resident in ROM 2Z to store the data byte in RAM Z4 and updates the pointer for the RAM 24.
Turning to FIGURE 7 is a logic flow diagram of the sequence of events that take place in a RECEIVE-END-INTERRPUT
request. At step 300 the microprocessor 25 executes routines in ROM 22 to set a end of data indicator on the receive buffer in the RAM 2~. At step 302, the microprocessor 25 verifies for receive errors, and when no error has been detected the RECEIVE-END-INTERRUPT request returns control to the calling routine at step 306. At step 304 when errors have been de~ected, the microprocessor 25 executes routines in ROM 22 to send RE-TRANSMIT request to the communication network, flags the information in the R~M 2~ and then returns control to the calling routine at step 306.
Turning to FIGURE 8, is a logic flow diagram of the sequence of events that take place in a PRINTER INTERRUPT
request. At step 400, the microprocessor stores the data in the RAM 24 and updates the printer for the RAM 24. ~t step 402 the microprocessor 25 returns control to the calling routine when the RAM 24 is not full and sends a printer message to the ~ :~7,.~ 13 communication network when the R~M 2~ is full then returns control to the callin~ routine in step 406.
Turning to FIGURE 9, there is shown a circuit diagram of an optional interface 34 for the connection of a local storage device in addition to the simulated transparent mass storage. The mass storage device controller 37, for example a floppy disk controller, is moved from the socket on the floppy disk controller to the interface 3~. The floppy disk controller socket 38 is then used for the physical connection of interface 34 to the floppy disk controller board.
The tristate buffer 35 provides the interface for data between the system interface 2 and the floppy disk controller.
The 2 to 1 selector 36 selects between the simulated or local floppy disks by the appropriate rou~ing of the control signals (CS, DACK. IRQ, DRQ).
In this way, the interface 34 can selectively enable or disable the local floppy disk controler from the host microcomputer system.
It is important to realize that the present invention provides hardware, in the form of an integrated circuit board, which replaces the standard floppy disk controller of a microcomputer with a network communications device. The system interface 2, of this device, is determined by the host computer for which the particular board is being used. Once the particular computer has been specified, the interface is fairly specific. ~owever this is only true on the system side of the ~'7~
interface. The other side o~ this interface will be decided by what registers 16 are being simulated and on the configuration of the internal controlling microprocessor 25.
Even less specific is the configuration of the network interface 6. The type of network and the protocol used will determine what the interface looks like. If the interface is fairly complex, then the general block diagram will remain as shown in FIGURES 1 and ~. If however ~he network is fairly simple, it is possible to remove the communications circuit 30 and to perform its functions in software.
The actual network interface 32 can ba increased in complexity or decreased in complexity by using less or more software respectively. At one end of the extreme, it is possible for the network controller device according to the present invention to be more complex than the one indicated here, by removing the dedicated microprocessor 25 and its ~oftware and using discreet hardware instead. Or, the control functions may be incorporated into a custom made integrated cirucit which may be either a microprocessor itself or a hardware solution. At the other extreme it is possible to remove a lot of the hardware by performing as many functions as possible by software.
Thus there has been provided in accordance with the present invention a device for transparent resource sharing in microcomputer systems that fully satisfies the objects, aims and advantages set forth above. While the invention has been .~ ~'7~
described in conjunction with specific embodiments thereof, it is evident that many alteLnatives, modifications and variations will be apparen~ to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications and variations as fall within the spirit and broad scope of the appended claims.
Claims (16)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A microprocessor controlled mass storage controller for coupling a host microcomputer system to a network configuration to provide transparent resource sharing comprising:
a system interface means for transferring input and output commands from the microcomputer system;
a dedicated microprocessor means coupled to the system interface means for processing the commands to simulate the execution of the commands; and a network interface means coupled to the dedicated microprocessor and associated with the network configuration to transfer data to and from the network configuration on command from the dedicated microprocessor.
a system interface means for transferring input and output commands from the microcomputer system;
a dedicated microprocessor means coupled to the system interface means for processing the commands to simulate the execution of the commands; and a network interface means coupled to the dedicated microprocessor and associated with the network configuration to transfer data to and from the network configuration on command from the dedicated microprocessor.
2. A microprocessor controlled mass storage controller as recited in claim 1 wherein said system interface means comprises a data transceiver module coupled to a peripheral data bus of the host microcomputer system and the dedicated microprocessor for transferring the data between the host microcomputer system and the data transceiver.
3. A microprocessor controller mass storage controller as recited in claim 1 wherein the system interface means further comprises a control interface module coupled to the data transceiver module and the host microprocessor system to generate address and control signals for the host microprocessor system, and a register bank module coupled to the control interface module to provide register status storage for simulating a mass storage device status.
4. A microprocessor controlled mass storage controller as recited in claim 3 wherein the register bank module comprises:
a tristate floppy latch circuitry coupled to a pheripheral data interface circuitry and the data transceiver module; a tristate printer data latch circuitry coupled to the peripheral data interface circuitry, the tristate floppy data latch circuitry and the data transceiver module; and a tristate printer status buffer circuitry coupled to the peripheral data interface circuitry and the data transceiver module.
a tristate floppy latch circuitry coupled to a pheripheral data interface circuitry and the data transceiver module; a tristate printer data latch circuitry coupled to the peripheral data interface circuitry, the tristate floppy data latch circuitry and the data transceiver module; and a tristate printer status buffer circuitry coupled to the peripheral data interface circuitry and the data transceiver module.
5. A microprocessor controlled mass storage controller as recited in claim 3 wherein said register bank module further comprises a floppy control latch circuitry coupled to a peripheral select interface circuitry and the control interface module; a two-to-one floppy data selector buffer circuitry coupled to the peripheral select circuitry and the control select interface module; a two-to-one floppy status selector buffer circuitry coupled to the peripheral select interface circuitry.
6. A microprocessor controlled mass storage controller as recited in claim 4 wherein said register bank module further comprises a latch circuitry coupled to a peripheral select interface circuitry and the control interface module; a two-to-one printer status selector buffer circuitry coupled to the peripheral select circuitry and the control select interface module; a two-to-one floppy status selector buffer circuitry coupled to the peripheral. select interface circuitry, the two-to-one printer status selector buffer circuitry and the control interface module.
7. A microprocessor controlled mass storage controller as recited in claim 1 wherein the dedicated microprocessor means comprises a microprocessor chip having a Random Access Memory (RAM) means to store data information and identify the data information items stored in the Random Access Memory (RAM) means.
8. A microprocessor controlled mass storage controller as recited in claim 7 wherein the dedicated microprocessor means further comprises means for executing commands transferred from the system interface.
9. A microprocessor controlled mass storage controller as recited in claim 7 wherein the dedicated microprocessor means further comprises means for indicating the status of the commands to the microcomputer system.
10. A microprocessor controlled mass storage controller as recited in claim 7 wherein the dedicated microprocessor means further includes an internal bus providing a data path, address path, and control path to transfer information items between the dedicator microprocessor, the RAM and the system interface.
11. A microprocessor controlled mass storage controller as recited in claim 10 wherein the dedicated microprocessor means further includes a Read Only Memory (ROM) means storing program information and wherein the microprocessor chip is responsive to said program information for controlling said data path, address path, control path means to selectively transfer information items to and from the Random Access Memory (RAM).
12. A microprocessor controlled mass storage controller as recited in claim 7 wherein the dedicated microprocessor means further comprises a control logic circuitry means to coordinate the operation of the dedicated microprocessor and a clock generating circuitry coupled to said control logic circuitry for controlling data transfers associated with the dedicated microprocessor.
13. A microprocessor controlled mass storage controller as recited in claim 1 having an internal bus and a clock generating circuitry and wherein the network interface means comprises a communications circuitry coupled to said internal bus and said clock generating circuitry to provide transmitting and receiving means to generate signals for the the network configuration.
14. A microprocessor controlled mass storage controller as recited in claim 13 wherein the network interface means further comprises a network circuitry means coupled to the communications circuitry for providing an electrical interface with the network configuration.
15. A microprocessor controlled mass storage controller as recited in claim 1 wherein the system interface means includes an interface means for an optional local mass storage controller for the installation of an actual mass storage device to the host microprocessor system.
16. A method for providing resource sharing to a microcomputer comprising a system interface means, a dedicated microprocessor means and a network interface means coupled to a network configuration, the method comprising the steps of:
- accepting data from the microcomputer into the system interface means in a parallel data format, transferring the data to the network interface means and if necessary, converting said data to a serial data format, and transmitting the data in appropriate format to the network configuration;
- receiving other data in from the network configuration and if necessary, converting said other data to a parallel data format and transferring said other data in parallel format to the microcomputer;
- simulating the characteristics and responses of a mass storage device by processing commands sent by the microprocessor and presenting the status to said microprocessor;
- transmitting and receiving data by the network interface means to and from the network configuration by executing network commands in said network interface means.
- accepting data from the microcomputer into the system interface means in a parallel data format, transferring the data to the network interface means and if necessary, converting said data to a serial data format, and transmitting the data in appropriate format to the network configuration;
- receiving other data in from the network configuration and if necessary, converting said other data to a parallel data format and transferring said other data in parallel format to the microcomputer;
- simulating the characteristics and responses of a mass storage device by processing commands sent by the microprocessor and presenting the status to said microprocessor;
- transmitting and receiving data by the network interface means to and from the network configuration by executing network commands in said network interface means.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/556,130 US4792896A (en) | 1983-12-07 | 1983-11-29 | Storage controller emulator providing transparent resource sharing in a computer system |
| CA000442795A CA1172380A (en) | 1983-12-07 | 1983-12-07 | Controller and method for transparent resource sharing in microcomputer systems |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000442795A CA1172380A (en) | 1983-12-07 | 1983-12-07 | Controller and method for transparent resource sharing in microcomputer systems |
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|---|---|
| CA1172380A true CA1172380A (en) | 1984-08-07 |
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|---|---|---|---|
| CA000442795A Expired CA1172380A (en) | 1983-12-07 | 1983-12-07 | Controller and method for transparent resource sharing in microcomputer systems |
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| CA (1) | CA1172380A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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-
1983
- 1983-11-29 US US06/556,130 patent/US4792896A/en not_active Expired - Fee Related
- 1983-12-07 CA CA000442795A patent/CA1172380A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4792896A (en) | 1988-12-20 |
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