CA1173929A

CA1173929A - Bus system

Info

Publication number: CA1173929A
Application number: CA000406302A
Authority: CA
Inventors: Matthias Hofstetter
Original assignee: Siemens Albis AG
Current assignee: Siemens Schweiz AG
Priority date: 1981-07-10
Filing date: 1982-06-29
Publication date: 1984-09-04
Also published as: US4495574A; EP0069829B1; EP0069829A3; DE3265361D1; EP0069829A2

Abstract

Attorneys Docket No. 6999 CAN

INVENTOR: MATTHIAS HOFSTETTER
INVENTION: BUS SYSTEM

ABSTRACT OF THE DISCLOSURE

A bus system is disclosed wherein the length of the data words and the speed of change of the information represented by the data can be quite different from one another. For this purpose there is provided an interface circuit which is connected by means of a respective four-wire conductor or line with a number of sub-units. One sub-unit contains a switching stage, a control logic and a number of shift registers and the interface circuit contains a microcomputer and a coupler. The sub-units are connected by means of a respective bus with a number of modules or sub-assemblies.
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Description

~.~73~29 ' BACKGROUND OF THE INVENTION

The present invention relates to a new and improved construction of a bus system for the exchange of data between a central station or location and at least two modules or sub-assemblies.

SUMMARY OF THE INVENTION

It is a primary object of the present invention to provide an improved construction of bus system which is quite simple in construction and design and ensures for extreme reliability during the transmission of data, and wherein the length of the data words as well as the speed of change of the information represented by the data can be quite different from one another.

Now in order to implement this object and others which will become more readily apparent as the description proceeds, the bus system of the present development is manifested by the features that an interface circuit connected with the central station contains a microcomputer and a coupler. The exchange of data between the microcomputer and the coupler in the one direction is accomplished by means of a parallel-serial converter and in the other direction by means of a serial-parallel converter. The coupler is connected by ~k .

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means of separate lines in each case with a respective reversing or switching stage provided in a sub-unit. The switching stage controls by means of a control logic a status word generator and a data word-shift register in such a manner that the data of the switching stage is inputted by means of the data word-shift register to a bus connected with the module and the data of the module is inputted by means of this bus and the status word generator connected therewith to the switching or reversing stage. Between one of the branches of the switching stage and the output of the status word generator there is incorporated a status word-shift register and between one of the other branches and the control logic there is incorporated a command word-shift register.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better understood and objects other than those set forth above, will become apparent when consideration is given to the following detailed description thereof. Such description makes reference to the annexed drawings wherein:

Figure 1 is a block circuit diagram of a bus system constructed according to the present invention;

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Figure 2 is a block circuit diagram of the interface circuit of such bus system;

Figure 3 is a block circuit diagram of a sub-unit of the bus system;

Figure 4 is a block circuit diagram of a converter used therefor; and Figure 5 is a detail showing of the circuitry of Figure 1 but here containing an additional parallely connected sub-unit.
' ~ DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

.., Describing now the drawings, the exemplary embodiment of bus system depicted in Figure 1 will be seen to comprise an interface circuit RAl connected by means of a bus-line 10 and a buffer BU with a central station OS.
Connected with the interface circuit RAl, by means of further bus lines 12, is a respective sub-unit OSll, OSl2 and OSl3.
These sub-units OSll, OSl2 and OSl3 are connected by means of a respective bus-bar or so-called bus BUSl, BUS2 and BUS 3 with a converter ADll, ADl2 and ADl3 and a module or sub-assembly BGl, BG2 and BG3, respectively, wherein the module BG3 is connected by means of its related bus ~US3 with ~:i73~

a further module BG~. The modules BG1 and BG2 are connected by means of a respective further connection or line 14 and 16 with the converter ADll and ADl2, respectively, and the modules BG3 and BG4 are connected via the lines 18 and 20 with the converter AD13.

As best seen by referring to Figure 2, the interface circuit RAl shown therein will be seen to comprise a microcomputer MC connected by means of the bus-lines 10 with the buffer sU shown in Figure 1, as well as a coupler KP
connected by means of the further bus-lines 12 with the sub-units OSll, OS12, OS13 (Figure 1). The coupler KP is provided with a Manchester converter MCD1 and with six drivers TR1, TR2, TR3, TR4, TR5 and TR6 which are individually controlled by the microcomputer MC by means of a bus-line 22.
It is to be expressly understood, however, that there also could be provided more than six drivers.

The microcomputer MC is connected by means of bidirectional bus-lines 24 and a receiver control logic EKL
with the Manchester converter MCD1. The control logic EKL
controls a serial-parallel converter SPW which is connected by means of bus-lines 26 both with the microcomputer MC and also with the Manchester converter MCD1. Additionally, the microcomputer MC is connected with the aid of bidirectional bus-lines 28 by means of a transmitter control logic SKL with . .

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the Manchester converter MCD1. The transmitter control logic SKL controls a parallel-serial converter PSW which is connected by means of bus-lines 30 both with the microcomputer MC and also with the Manchester converter MCD1. The elements SPW, EKL, SKL, PSW and KP form a coupler circuit KPS.

The sub-unit OSll depicted in Figure 3 will be seen to comtain a signal processing device or signal processor SVE connected with a control logic ST. This signal processing device SVE is equipped with a Manchester converter MCD2 and a switching or reversing stage US, which are connected in each case by means of a bus-line, generally indicated by reference character 32 on the one hand, with a shift register SW for status words, and, on the other hand, with a shift register DW
for data words, and additionally, with a shift register KW for command words. A clock generator TG delivers the clock `~'i signals or pulses for the control logic ST and for the switching stage US. The control logic ST is connected, on the one hand, with the shift registers KW, DW and SW, and, on the other hand, with a status word generator SWE, an input register DLl, and an output register DLo. These registers contain three logical states, namely "1", "O" and "high-ohmic". The registers are connected with one another by means of a bus-bar or bus and with an input-output circuit or port PS (I/O-port). This bus contains 6 address lines, 3 control lines and 8 bidirectional data lines. By means of ~.~73~Z9 this bus there are t~ansmitted 8-bit wide dynamic data. Data is inputted from the input register DLl by means of the status word generator SWE ~o the shift register SW and data is inputted from the shift register DW to the output register DLO. The shift register KW for command words is connected by means of a bus-line 34 with the control logic ST and by means of a 6-bit address line 36 with the input-output port PS.
This 6-bit address line 36 forms a further output of the sub-unit OSll. The control logic ST and the input-output port PS are connected with one another by means of three control lines 38, namely a reading line, a writing line and a release line. The input-output port or circuit PS possesses 48 inputs or outputs for the static bit data. The other sub-units OS12 and OS13 can be constructed like the sub-unit OSll.

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The bus system depicted in Figures 1 to 3 functions in the following manner: the bus system transmits data from a central computer in the central station OS to the modules or sub-assemblies BG1, BG2, BG3 and sG4 and vice versa. These modules BG1, BG2, BG3 and BG4 are located at quite different places and at extremely dif~erent distances from the central station OSO The data transmission is accomplished in a serial and directionally separated fashion.
The sub-units OSll, OS12 and OS13 are merely connected by a respective dual-wire line per direction with the interface circuit RAl.

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There are present in the bus system three ; different types of interface circuits, namely the interface circuit RAl, the sub-units OSll, OS12 and OS13, and finally the converters ADll, AD12 and AD13.
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~, The interface circuit RAl forms the interface to the central computer and regulates the data traffic to the modules. The sub-units OSll, OS12 and OS13 receive data from the interface circuit RAl by means of the one related dual-wire line and make such available to the therewith associated modules BGl, sG2, BG3 and BG4, respectively, as dynamic and static data. Conversely, the interface circuit RAl recalls digital data by means of a sub-unit, this digital data being prepared by the sub-units, and transmits such by means of the other related dual-wire line to the interface circuit RAl. Analog data from a module is received by the converters ADll, AD12 and AD13, respectively, converted into digital form and inputted to the sub-units OSll, OS12 and OS13, respectively. These converters are connected by means of dynamic interfaces with the therewith operatively associated sub-units.

The dyamic interface consists of ~ address lines, 3 control lines and 8 data lines, so that the data transmission is accomplished in accordance with principles which are conventional for microcomputers. The static data is ~.~735~2S~

always applied, in other words it is always available. Such is constituted by 48-bits which are either transmitted or received by a sub-unit OSll, OS12 and OS13, respectively. I'he transmission direction is determined by the interface circuit RAl during the initializing phase at the relevant sub-unit OSll, OS12 and OS13, respectively. It is possible to define, for instance, 8-bit words as output or input information.

The interface circuit RAl possesses an interface at which there is connected the buffer BU containing two buffer storages. By means of the one buffer storage data is received from the central station OS and by means of the other buffer storage data is received from the interface circuit RAl. The data exchange between the central station OS and the interface circuit RAl therefore is accomplished directionally separate, and additionally, asynchronously. Each buffer storage has a capacity of 512 bytes.

At this point there will be considered the operation of the interface circuit RAl of Figure 2 which is as follows:

The microcomputer MC controls by means of the write line the transmitter storage and by means of the read line the receiver storage of the buffer BU (Figure 1) and receives therefrom, by means of the release line, a receipt ~735`~
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signal which indicates which of both buffer storages is free or occupied. The actual data is transmitted by means of the 8-bit lines. The microcomputer MC, at the appropriate time, retrieves data out of the buffer BU (Figure 1) and transmits such, in conjunction with a command word, to the parallel-serial converter PSW. As soon as a start si~nal is delivered from the microcomputer MC by means of the control logic SKL to the converter PSW, the latter begins to transmit such data in serial fashion to the Manchester converter MCDl, which additionally delivers at its output a Manchester-coded synchronous bit which indicates whether the following bits possess the character of data or command words. The command word not only contains addresses, but also information as to whether the interface circuit RAl should transmit or receive data.

In the first instance the command word initially indicates the addresses and the command that data should be transmitted and then arrives, for instance, in the sub-unit OSll ~Figure 3). This command functions in such a manner upon the control logic SKL that the actual data is inputted by means of the parallel-serial converter PSW to the Manchester converter MCD1, which transmits the binary coded serial data, which is Manchester-coded, in each case by means of one of the ` drivers TR provided in the coupler XP to a sub unit (Figure 3) at a frequency of, for instance, 1.25 Mbit. The interface 3~Z9 circuit RAl itself forms a buffer where the data can wait, since the 8-bit data flow does not constitute any continuous data stream, rather is sporadically transmitted or retrieved by the microcomputer. Additionally, the correct outputs of the interface circuit RAl are switched for the desired sub-units OSll, OS12 and OS13, respectively.

In the second operational mode when data should be received there is also delivered a command word which contains both an address and a control bit. This control bit provdes the command that data should be received. The data or information is deposited at the sub-unit in the form of a status word and transmitted back to the coupler circuit KPS, where the words are serial-parallel converted and inputted by means of the microcomputer MC to the buffer BU (Figure 1). In contrast to the microcomputer MC the Manchester converter MCD1 does not possess any storage capacity.

s The microcomputer MC analyses this status word and determines whether it contains error messages, indicates, for instance, whether the parity-bit has been falsely placed, or whether the module is not active, meaning does not have a potential applied thereto. In this instance it does not transmit any receipt signal, which is then interpreted as an error message or communication.
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~:173929 ; One problem which exists in a radar system is that the data can possess quite different velocities, since some data can change very rapidly and other data extremely slow.
Therefore, it would be senseless to interrogate data which only changes every second with, for instance, a frequency of 1 kHz, because then there would be interrogated 1000 times the same data and at the same time there would be blocked the processing of other data.

It is for this reason that there is provided a regulation loop in the microcomputer MC, in order to frequently interrogate modules which deliver a rapid data flow, and to less Ere~uently interroyate modules which deliver a slower data flow. This can be obtained at the microcomputer MC by appropriate programming thereof as is well known in the art.

The circuitry of Figure 3 functions in the following manner:

The data arriving in one direction from the interface circuit RAl (Figure 1) is decoded in the Manchester converter MCD2 into a binary code and transmitted further to the command word-shift register KW, and specifically then when the command bit initially transmitted in the Manchester code indicates a command word. This shift register KW is , . . .

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controlled by the switching stage US and the command word delivered thereby is divided and a portion thereof is inputted both to an appropriate input of the input-output port PS and also to the address output of the sub-unit OSll and another portion thereof is inputted to the control logic ST.
Moreover, the address of the sub~unit OSll is compared with a fixed wired address.

The control logic ST also checks ~he bit which indicates whether subsequent data is arriving, or whether the coupler or coupling circuit KPS should receive data from the modules. If there have been indicated the presence of subsequent data, then the system waits until a Manchester-coded data stream arrives at the Manchester converter MCD2, which thereafter delivers a data word. The data stream is loaded into the data word-shift register DW
which functions as a serial-parallel converter, and is further inputted in parallel to the output register DLO, where there appears the data for a certain time, during which time the control logic ST transmits a write pulse to the modules which receipt the same, whereupon the control logic ST controls the output register DLO for transmitting the dynamic data by means of the bus. Thereafter, the write line is again set to "1"
and there is produced a status word which is transmitted back as an indication of the correct transmission of the dynamic data to the coupler or coupling circuit KPS (Figure 2). In `:

~;~739;~9 the other direction the dynamic data is transmitted from the modules to the coupler circuit KPS. For this purpose the shift register KW receives a command word possessing a bit which indicates that data should be received from the module.
Thereafter, the control logic ST activates the read line to the modules. As a result, the data of the modules is delivered to the bus, which then arrives by means of the input register DLl at the status word generator SWE, from which location such is conducted b~v means of the shift register SW
activated by the control logic and operating as a parallel-serial converter and by means of the switching stage US to the Manchester converter MCD2, and thereafter such data is conducted to the interface circuit RAl (Figure 1).

The static data is transmitted or received, as the case may be, for instance in 8-bit blockwise fashion by means of the input-output port PS, which is controlled by the control logic ST. The course of the static data in the one directior., that is to say, from the coupler circuit KPS
operating as distributor to the modules, is accomplished in a manner such that initially there are transmitted address words from the coupler circuit KPS which arrive at the input-output port PS. Thereafter, data words again arrive from the coupler circuit KPS over the same path to the input-output port or circuit PS where they are deposited and maintained for such length of time until they are overwritten. The same holds . .
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true for the data flow in the other direction. Also in this case there are initially transmitted address words. The static data of the input-output port PS is read by the input register DLl and transmitted in the same manner as the dynamic data back to the coupler circuit KPS. The 48-bits appearing at the output of the input-output port PS correspond to 6 bytes. With 3 of the 6 bits delivered by the shift register KW, which are present at one input of the input-output port or circuit PS, there is selected one of these 6 bytes. With the aforementioned 6 bits there can be produced 64 addresses, of which 6 are employed for the selec-tion and 2 for the programming of the inputs-outputs. The input-output port PS
possesses 6 inputs-outputs each containing a respective 8 bits, and the data arriving by means of the output register DLO can be addrPssed either at the 8-bit input-output 1 or at one of the other 8-bit inputs-outputs 2 to 6.

:~, The modules BGl, BG2, BG3, BG4 (Figure 1) deliver digital data from different hardware circuits directly by means of the sub-units OSll, OSl2 and OS13 to the central station OS and vice versa.

- As to the static digital data such constitute condition signals which are taken over by the modules as individual bits. On the other hand, data which arrives 8-bit blockwise is dynamically processed, in order to save inputs, ~L~ 7~3~2~

which otherwise would be needed because of the large number of bits. In Figure 1 there have been randomly connected two modules sG3 and sG4. It would be possible to also connect in circuit more modules, because what is important are not the modules themselves, rather the data which they deliver.

The converter of Figure 4 is in principle an analog-to-digital converter which contains a multiplexer MUX, a sample-and~hold amplifier SHA, an analog-to-digital converter ADC, and a random access memory RAM, which are connected in series and controlled in each instance by a control circuit KS. The multiplexer MUX is provided with differential inputs for 8 channels and with simple inputs for 16 channels, and the random access memory RAM is prGvided with outputs for 8-bit data. Leading to the control circuit KS
are, for instance, 6 address lines and 3 control lines at bus-lines as well as a further stop command line.

The converter of Figure 4 is only necessary if the modules not only deliver digital data but also analog data.
In this case the data initially must be converted into digital form. The control circuit KS is structured to contain a microprocessor. The random access memory RAM serves as a buffer in order to shorten the access time from the sub-unit.
The analog data is first multiplexed in the multiplexer MUX, then coded by means of the sample-and-hold amplifler SHA and . .

35~9 the analog-to-digital converter ADC, and then deposited in the random access memory RAM. The data can be retrieved much more rapidly from the random access memory RAM than if it had to initially be converted in each instance.

Also the Manchester converters MCD1 and MCD2 are not absolutely required for the operation of the bus system.
It is namely possible to readily provide simple Manchester coders-decoders or coders-decoders of a different type, or, in fact, no coders-decoders. The advantage which is present with a Manchester coder-decoder is that the signals do not possess any direct-current voltage components. Additionally, there can be achieved a galvanic decoupling with the aid of a transmission device. Commercially available Manchester converters are usually equipped with an additional circuit which delivers a parity bit which can be used for monitoring the data traffic. To this end there is received a parity bit at the Manchester converter MCD2, which bit has been delivered by the Manchester converter MCD1, such parity bit is then checked by the Manchester converter MCD2 and further transmitted to the control logic ST. This control logic ST
then delivers a reporting back signal to the status word generator SWE when the parity bit is false. The return feed line from the control logic ST by means of the switching stage US to the Manchester converter MCD2 relates to the decoder or reconverter which reconverts the data arriving from the 73~Z~
modules. In this way there can be indicated that data is available, whereupon there is placed into operation the reconverter. As to the data arriving from the central station OS there is transmitted a report signal from the Manchester converter MCD2 to the control logic ST in order to activate one of the shift registers DW or KW.

The registers DLl and DLO are not absolutely required if the status word generator SWE and the data word-shift register DW are constructed in such a manner that ; their inputs or outputs, as the case may be, also can possess a high-ohmic condition. The presence of the registers DL1 and DLO however renders possible an automatic monitoring of the circuitry. This is accomplished in the following manner: the data which has been transmitted at a certain address is retained in the output register DLO. The register transmits the data for a certain address to the bus as soon as this address is again read~ After the reading-in of the data by means of the D-input of the register the data is sent back, whereafter the outputs are again in their high-ohmic state.
Since the data which has been retained is again read there is provided a reproduction of the data which allows testing the same.

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Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A bus system for the exchange of data between a central station and at least two modules, comprising:
a central station;
a plurality of modules;
an interface circuit connected with said central station;
said interface circuit containing:
a microcomputer;
a coupler;
a parallel-serial converter;
a serial-parallel converter;
the exchange of data between the microcomputer and the coupler occurring in one direction by means of said parallel-serial converter and in the other direction by means of said serial-parallel converter;
a plurality of sub-units connected with said interface circuit;
a respective switching stage provided for each of said sub-units;
said coupler being connected by means of separate lines at respective ones of the switching stages provided for said sub-units;

a control logic operatively connected with said switching stage of the corresponding sub-unit;
each sub-unit containing:
a status-word generator; and a data word-shift register;
said switching stage controlling by means of the control logic said status word generator and said data word-shift register in such a manner that the data of the switching stage is delivered to a bus connected with the modules by means of the data word shift register and the data of the modules is delivered by means of this bus and the status word generator connected therewith to the switching stage;
each sub-unit further containing:
a status word-shift register; and a command word-shift register; and said status word-shift register; being incorporated between one branch of the switching stage and an output of the status word generator and the command word-shift register being incorporated between another branch of the switching stage and the control logic.

2. The bus system as defined in claim 1, further including:
a respective coder-decoder unit provided for the coupler of the interface circuit and the switching stage of the sub-unit, in order to code and decode, respectively, the data before its distribution or after its concentration.

3. The bus system as defined in claim 2, whereino said coder-decoder units comprise Manchester converters.

4. The bus system as defined in claim 1, further including:
an input-output port connected with the bus and provided for the corresponding sub-unit; and the exchange of static data in the sub-unit occurring by means of said input-output port.

5. The bus system as defined in claim 1, further including:
a buffer containing a respective buffer store for both data flow directions incorporated between the central station and the microcomputer.

6. The bus system as defined in claim 1, further including:
an input register arranged between the bus and an input of the status word generator; and an output register incorporated between the bus and an output of the data word-shift register.

7. The bus system as defined in claim 1, further including:
a plurality of coupler circuits with which the microcomputer is connected in said interface circuit.

8. The bus system as defined in claim 1, wherein:
at least two sub-units are connected by means of the same lines with the interface circuit.

9. The bus system as defined in claim 1, wherein:
at least in status words of a sub-unit there are delivered data and error messages.

10. The bus system as defined in claim 1, wherein:
an analog-to-digital converter is incorporated at least between a module and a sub-unit.