CA1177563A

CA1177563A - Digital scan converter

Info

Publication number: CA1177563A
Application number: CA000373434A
Authority: CA
Inventors: Jan Aanstoot; Bernard H.M.O. Elberink
Original assignee: Thales Nederland BV
Current assignee: Thales Nederland BV
Priority date: 1980-04-15
Filing date: 1981-03-19
Publication date: 1984-11-06
Also published as: EP0038102B1; NL8002171A; EP0038102A1; DE3161223D1; JPS56163466A; JPH0136074B2; US4412220A

Abstract

Digital scan converter Abstract:
A digital scan converter is provided with a memory (1), each cell of which memory containing brightness data for presenting a radar video signal on a raster scan display (2) at a position corresponding with the respective cell; a logical unit (7) for supplying in response to the applied video signals and the brightness data stored in memory (1), new brightness data over-writing that stored in memory (1); an address conversion circuit (10) for converting the addresses established in polar coordinates into addresses expressed in Cartesian coordinates to store the new brightness data in memory (1); and with a circuit (3) connected to the memory (1) for reading out the brightness data and for presenting corresponding video signals on the raster scan display (2). To renew the stored brightness data synchronously with the radar scans such that a prefixed persistence appears on the raster scan display (2), the digital scan converter comprises a control unit (15) for supplying persistence data and azimuth values to process the persistence data and a control code register (19) for storing the persistence data in intervals between successive radar scans. Furthermore, in said interval the latter azimuth values are supplied to the address conversion circuit (10) for generating the addresses of the memory cells and the contents of said memory cells are adapted to the persistence data in the control code register (19) by means of the logical unit (7) communicating with said control code register (19).

Description

1 ~77563 Digital scan converter The invention relates to a digital scan conver-ter, which comprises a random-access memory, each cell of which memory containing bri~htness data for presenting a radar video signal 5 on a raster scan display at a position corresponding with the respective cell; a logical unit for supplying, in response to the applied video signals and the brightness data stored in memory, new brightness data overwriting that stored in memory;
an address conversion circuit -for converting the addresses established in polar coordina-tes in accordance with the radar scan pattern into addresses expressed in ~artesian coordinates to store the new brightness data in memory; and a circuit connected to the memory for reading out the brightness data and for presenting corresponding video signals on the raster scan display.
Such a digital scan converter is known from the U.S.
patent specification 4~165,506. This converter contains a timing unit, which delivers brigh-tness-reducing command si.gnals at such fixed instants o-f time, tha-t a persistence is obtained resembling that of a long-persistence phosphor on the display. The addresses pertaining to these command signals are generated in a pseudo-random sequence to effect a uniform reduction in brightness on the display. The present invention however has for i-ts obJect to provide a digital scan conver-ter, as set forth in the opening paragraph, attaining a persis-tence tha-t resembles that of a PPI
display, where the displayed radar scan shows a tangential - persistence, i.e. a persistence proceeding in i-ts clirection of motion.
According to -the invention the digital scan converter is characterised in that, to renew the stored brigh-tness da-ta synchronously with the radar scans such that a prefixed persistence appears on the raster scan display, the digital scan converter comprises a control unit for supplying persistence data and azimuth values to process the persistence data, and a con-trol code register for storing the persistence da-ta, instead of the radar video signals, in the inverval between two successive radar scans, using suitable switching means, while in said interval the ~g ' ~ 1~7~3 azimuth values are supplied to the address conversion circui-t for generating the addresses of the memory cells whose con-tents are adapted to the persistence data stored in the control code register with the aid of the logical unit connected with -the control code register.
The processing of persistence data is therefore oriented to the radar scan~ i.e. the memory cells are subJected to a brightness-reducing process in the same sequence as that in which they were stored with radar data. This sequence thus describes, like the radar scan, a radian referred to as persis-tence radian hereinafter. By processing persistence data is here meant that a persistence radian is generated. The duration of the persistence is determined by the frequency at which such persis-tence radians are generated.
The invention will now be explained with reference to the accompanying figures, of which Fig. 1 is a block diagram of an embodiment of -the digital scan converter according to the invention; and Figs 2 and 3A, 3B are diagrams useful in explaining certain properties of the digital scan converter.
In Fig. 1 the random-access memory is deno-ted by 1.
Each cell o-f this memory corresponds with a point of the raster of a raster scan display 2 and contains the information required for displaying a video signal at a corresponding position on the raster scan display The memory-stored data is read out at such a frequency that a steady flicker--free picture is generated.
A circuit 3 is thereto connected to memory 1 to read out the memory data, to process this data for the generation of video signals, and to present these video signals on display 2.
Each memory cell comprises a given number of bit positions. The contents of such a memory cell determines the intensity at which radar video signals are presented on the raster scan disolay 2 at a position corresponding with the respective memory cell; the contents of a memory cell is hereinafter termed "brightness data".
To read the brightness data out o-f memory, circuit 3 supplies the required memory addresses via line 4 and switch 5.
.

~ ~775~3 Switch 5 will then be in the R(read) position, not shown in -the -Figure. Memory 1 is fed alternately, via switch 5, with the address information of the video data processed in the scan converter and with the address information required for reading out memory 1.
With switch 5 in the RMW(read/modify/write) position, as shown in the figure, the memory cell addressed is that of which the contents must be re-established. The video data processed in the scan converter is therefore fed to a logical unit 7 Yia line 6.
This unit also receives the contents of the memory cell allocated by the associated address information. From the information applied to logical unit 7, the contents of the relevant memory cell is re-established via line 9. It should be noted -tha-t this does not imply that the contents of this memory cell differs per se from the foregoing contents of this cell.
As already stated, the contents of the memory cell consist of brightness data. The data to be processed in the scan converter, i.e.
the data applied via line 6, need not contain any brightness data itself. This will however be so when this data consists o-f a quantised and digitised radar video signal. On the other hand, the data supplied via line 6 may consist of command signals, in consequence oP which the brigh-tness da-ta in memory 1 has -to be altered.
The memory cells o-f which the conten-ts must be re-established are addressed -from the address conversion circui-t 10.
This circuit converts the adclresses established in polar coordinates in accordance with the radar scan pattern into addresses expressed in Cartesian coordinates. The address conversion circuit 10 there-to con-tains an azimuth counter 11, an adder 12, a sine/cosine generator 13 and an address reglster 14. The azimuth pulses B
indicative of the radar antenna orientation and a pulse N indica-tive of an angular re-Ference are supplied to azimuth counter 11.
This counter supplies a signal representing the angular value ~
between the direction in which the radar transmits the pulses and a selected reference direction. If desired, ~ can be increased by a signal supplied to the azimu-th counter, which signal repre-sents the angular value 0 for rota-ting the picture presented on ~ ~ 775~3 the raster scan display. The angular value p is supplied by a control unit 15. In adder 12 -the angular value ~-~0 ~rom the azimuth counter can be increased by k.0~, where k=0,1,2,....
The meaning of this will be discussed later. Control unit 15 also supplies the angular value A~. The angular value ~+ 0+k.0 is supplied to the sinejcosine generator which then produces the values sin(~+ ~+k.0~) and cos(~+ ~+k.~) and sends these values to address register 14. After receiving the range increment count pulses ~R and the radar coordinate values xO, yO from control uni-t 15, this register supplies the memory addresses x=xO+ n.~R.cos(~+ ~+ k.~) and y= yO+ n.~R.sin(~ ~0+k.o~), where n=0, 1, 2, ..., N and N.~R is the set radar range.
The video data,to which the brightness data in an addressed memory cell must be adapted, is quan-tised in the video processing unit 16 and supplied to control code register 19 via switching means 17 and delay element 18. The video data stored in control code register 19 is fed to logical unit 7 via buffer register 20. At the same -time the corresponding memory address is stored in memory 1 via register 20.
The brightness data in memory 1 should not only be adapted to the results of the radar scans but should also be sub~ected a-t certain in-tervals to a brightness reducing process.
To effect this reduction, the video data :Ls replaced by "persistence" data at a certain frequency. The process:lng of` this ~5 persistence data is oriented to the radar scans; the memory cells are subJected to the brightness-reducing process in the same sequence as -that in which they are stored with the radar data.
This sequence generates a "persistence" radian. In principle, it should be possible to generate persistence radians between two successive radar scans. With this process the -following situations occur:
1. the brightness-reducing process is executed several times each antenna revolution; several persistence radians should therefore be generated between two successive radar scans;

2. the brigh-tness-reducing process is executed once each antenna revolution; this is preferably done simultaneously with the 1 ~7~5~;3 the processing of the radar da-ta, in whieh case the generation of addresses for displaying radar seans and generating a persis-tenee radian oeeur simultaneously;

3. the brightness-reducing is executed onee each N antenna revolu-tions; this is preferably done on the Nth revolution simultaneously with the radar scan.
Control unit 15 supplies signals which determine the frequency of generation of the persistence radians, viz. N1: the number of persistence radians each antenna revolution, or N2 : the number of antenna revolutions in which a persistence radian must be generated. It will be clear that signals N1 and N2 determine the persistence period and hence the tail length of moving targets on the display. ControI unit 15 also supplies the signal A, indicative of the persistence data. The persistence data -takes the position of the radar video clata on starting -the brightness-reducing process. Finally, control unit 15 produces the "validity"
signals, viz. V1,V2= 0,0, indicating that no persistence radians may be generated, and V1,V2=1,1, indicating that the persistence radians may be generated in accordance with N1 or N2, The signals ~ , (xO,y ~, (Nl,N2), A and (Vl,V2) from control unit 15 can be determined indirectly by a computer in communication with the control unit.
The control code register 19 receives -the persistence da-ta A via switching means 17 and clelay element 18. Signal B
thereto sets switching means 17 in the position not shown in the figure; signal Bv is the azimuth pulse delayed with respect to pulse B such that a radar scan can be performed during the delay period. In the embodiment in question, the video data or the persistence data taking the position thereof in the control code register 19, is indicated by bits CDo 2. The bits CD3 5 to be written in control code register 19 are from the control code circuit 21; this circuit comprises two control circuits 22 and 23.
Control circuit 22 de-termines the bits CD3 4 after receiving signals (N1,N2) and (V1,V2). In this embodiment these bits are 1,1 if the data in control code register 19 are only to refer to a radar scan to be processed; CD3 4= 0,1 if the latter data ~ ~7~5~3 concern a combined processing of a radar scan and the generation of a persistence radian; CD3 4=1,0 if these data only concern the generation of persistence radians. Con-trol circui-t 23 determines bit CD5 after receiving signals (Nl,N2) and a signal Lref; bi.t CD5 is to prevent tha-t, in case the same x,y cell is addressed by two successive radar scans and hence by two successive persistence radians, the brightness level of this cell is reduced twice. This issue will be further discussed below.
Fig. 2 illustrates a number of radar scans where, for the part of the scans situated near the origin, addresses of points of successive scans expressed in Cartesian coordinates may be equal; for instance:
x = (n~ Rcos ~1 = (n-l)~Rcos ~2 =(n-l)aRcos ~3 and y= (n-l)~Rsin ~1 = (n-l)~Rsin~2=(n-l)~Rsin ~3.
The error made by this equalisa-tion would imply that, withou-t taking countermeasures, the brithtness data of -the memory cells corresponding with parts of the scans situated near the origin and hence those of the persistence radians would be changed at or after successive scans, whereas the brigh-tness data of the cells corresponding with parts of the scans si.tua-ted at a distance from the origin would be changed at -the frequency cletermined by Nl or N2. To prevent such an error an "adm:inis-tration" bit i.s added to each cell of memory 1. The administration bi-t indicates that a memory cell in describing a persistence radian, which may or may not be combined with a radar scan, has already been addressed.
The administra-tion bit is compared with bit CD5 from control circuit 23; the latter bit assumes the values 0,1,0,1, ...
alternately for the persistence radians generated in the pulse repetition time. In case of unequivalence o-f the administration bit and bit CD5 -the brightness data of the cell is changed and the administration bit is made equal to bit CD5. At or after a following scan the same persistence radians are again generated with the same bits CD5. If now the same memory cells are covered as at or after the previous scan, the adminis-tration bi.t and bit CD5 ~ill already be equal for each of these cells, and the -~ ~775~3 brightness data in the memory will not be subJect -to another change unless the brightness level of the video signal supplied in the last scan is greater than -that of the video signal at the previous scan, the brightness data of the latter video signal already being stored in the memory.
Fig. 3A illustrates a radar scan SW and persistence radians A1, A2 and A3. I-f a persistence radian is generated simultaneously with the processing of the radar scan, N1 =4.
The persistence radians are described at angles k.Q~ , where k =0,1,2 and 3. If for scan SW the bit CD5=1 and -the admini-stration bit of a cell covered by scan SW equals 0, the brightness data will be changed and the administration bit becomes 1.
After a period, corresponding with a quarter of an antenna revo-lution, the particular cell is covered by persistence radian A1;
for this radian CD5= 0. There is again unequivalence between CD5 and the administration bit; the brightness data is again changed and the administration bit turns 0 again. Thus after half an antenna revolution with -the generation of persistence radian A2, for which CD5=1, the administration bit returns to 1; after three quarters of an antenna revolution with the generation of persistence radian A3, for which CD5= 0, the administration bit -turns 0 again; after a complete antenna revolu-tion with the generation of the nex-t radar scan, for which CD5=1, the admini-- stration bi-t turns 1 again, etc. This process will however come to a deadlock in the case of the situa-tion shown in Fig. 3B.
If a persistence radian is generated simultaneously with the processi.ng of radar scan SW and thereafter the persistence radians A1 and A2, then N1 = 3. The persistence radians are .` generated at angles k~o~= 2k~, where k= 0,1 and 2. If again for scan SW the bit CD5=1 and the administration bit of a cell covered by this scan is 0, the brightness data will be changed and the administration bit becomes 1. After one third of an antenna revolution with -the generation of persistence radian A1, for which CD5 = 0, the administration bit is 0; after two thirds of an antenna revolution with the generation of persistence radian A2, for which CD5=1, the administration bi.t is 1.
.

I :~7~5~ 3 However, after a cornplete antenna revolution wi~h -the generation of the next scan SW, the bit CD5 is again 1. Bit C~5 is already equal to the administration bi-t and hence -the brightness data is not changed. This undesired si-tuation is prevented by changing bit CD5 each antenna revolution in the cases when an odd number of persistence radians must be generated in the pulse repeti-tion time. To achieve this, a reference signal Lref is derived from the angular value of the adding circuit 12, using an angle reference circuit Z4. Signal Lref changes bit CD5 in the con-trol circuit 23 each antenna revolu-tion.
Fig. 2 also shows that two successive points of radar scans can cover the same memory cell; for instance:
x= n~Rcos~2= (n+l)~Rcos ~2 and y= n~Rsin ~2= (n+l)~Rsin ~2.
The error made with this equalisation would imply that, without taking countermeasures, the brightness data of the same cell would be changed twice in successive range quants. To prevent this error, a comparator 25 is incorporated and the delay time of element 18 is made equal to the time in which a radar signal passes through a range quant ~R twice. Comparator 25 determines whether the stronger o-f -the video signals is i.n range quant n or in range quant n+l. Bits CDo 5 and the x, y address information of the range quant that contains the weaker video signal are blocked, while bi-ts CDo 5 and the (same) x, y address in-Formation of -the range quan-t -that con-tains -the greates-t video signal are passed to logical unit 7 and memory 1 respectively. Bu-ffer register 20 can be blocked to this ePfect by a control s;gnal from blocking circuit 26. In the adclress conditional circuit 27, connected to address register lL~, the x, y addresses of each two successive range quants are compared; in case of equi.valence a signal indicative of such a situa-tion is supplied to blocking circuit 26 that, depending on the signal from compara-tor 25, produces said control signal.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. Digital scan converter provided with a random-access memory, each cell of which memory containing brightness data for presenting a radar video signal on a raster scan display at a position corresponding with the respective cell; a logical unit for supplying, in response to the applied video signals and the brightness data stored in memory, new brightness data overwriting that stored in memory; an address conversion circuit for converting the addresses established in polar coordinates in accordance with the radar scan pattern into addresses expressed in Cartesian coor-dinates to store the new brightness data in memory; and with a cir-cuit connected to the memory for reading out the brightness data and for presenting corresponding video signals on the raster scan display, characterised in that, to renew the stored brightness data synchronously with the radar scans such that a prefixed persistence appears on the raster scan display, the digital scan converter com-prises a control unit for supplying persistence data and azimuth values to process the persistence data, and a control code register for storing the persistence data, instead of the radar video signals, in the interval between two successive radar scans, using suitable switching means, while in said interval the azimuth values are supplied to the address conversion circuit for generating the addresses of the memory cells and the contents of said memory cells are adapted to the persistence data in the control code register by means of the logical unit communicating with said control code register.

2. Digital scan converter as claimed in claim 1, character-ised in that the digital scan converter comprises a control code circuit which functions to receive signals from the control unit, which signals contain the condition for the processing of the persistence data and fix the frequency at which said data is processed, which control code circuit thereupon produces one of the following signals for delivery to the control code register:
a signal to indicate that only a radar scan must be presented on the display, a signal to indicate that simultaneously therewith persistence data must be processed, and a signal to indicate that only persistence data must be processed.

3. Digital scan converter as claimed in claim 2, character-ised in that the digital scan converter comprises: a delay element which functions to relay the data passed through said switching means to the control code register; a comparator connected to the input and the output of said delay element, which comparator functions to establish the greatest value assumed by said data in two consecutive range quants; and a blocking circuit connected to both the comparator and an address conditional circuit, where-by the address conditional circuit, in response to the memory addresses supplied by the address conversion circuit in Cartesian coordinates, establishes that the same memory address expressed in Cartesian coordinates belongs to the addresses of two conse-cutive range quants expressed in polar coordinates, whereupon the blocking circuit supplies a signal to pass only the contents of the control code register containing said largest value to the logical unit.

4. Digital scan converter as claimed in claim 2 , characterised in that the control code circuit comprises a control circuit whose output signal. is changed in value each time when new persistence data is processed in the pulse repetition time, which output signal is stored in the control code register, and that the logical unit comprises a comparator for comparing the signal from the control circuit with an administration bit added to each memory cell to indicate whether the brightness data stored in the respective memory cell has been adapted to the received persistence data, which comparator changes the value of the administration bit with each adaptation performed.

5. Digital scan converter as claimed in claim 4, character-ised in that the digital scan converter comprises an angle reference circuit connected to the address conversion circuit, which angle reference circuit functions to supply a signal to the control circuit each time when the angle register forming part of the address conversion circuit reaches a given value, which signal causes the output signal of the control circuit to be inverted each antenna revolution if in the pulse repetition time the processing of persistence data occurs an odd number of times.