CA1180396A - Pulse monitor circuit - Google Patents
Pulse monitor circuitInfo
- Publication number
- CA1180396A CA1180396A CA000416977A CA416977A CA1180396A CA 1180396 A CA1180396 A CA 1180396A CA 000416977 A CA000416977 A CA 000416977A CA 416977 A CA416977 A CA 416977A CA 1180396 A CA1180396 A CA 1180396A
- Authority
- CA
- Canada
- Prior art keywords
- pulse
- clock
- signal
- monitor circuit
- signal source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/19—Monitoring patterns of pulse trains
Abstract
TITLE
PULSE MONITOR CIRCUIT
ABSTRACT OF THE DISCLOSURE
A pulse monitor circuit which detects failure of a monitored pulse by monitoring its expected occur-rence during time intervals defined by an external reference pulse train. Failure of the reference pulse train is detected by monitoring its expected occur-rence during time intervals derived from the monitored pulse train. Detection circuits are used to detect failure of the pulse trains and storage circuits, which can be cleared by external control or reappear-ance of the monitored pulse.
PULSE MONITOR CIRCUIT
ABSTRACT OF THE DISCLOSURE
A pulse monitor circuit which detects failure of a monitored pulse by monitoring its expected occur-rence during time intervals defined by an external reference pulse train. Failure of the reference pulse train is detected by monitoring its expected occur-rence during time intervals derived from the monitored pulse train. Detection circuits are used to detect failure of the pulse trains and storage circuits, which can be cleared by external control or reappear-ance of the monitored pulse.
Description
o3~
TITLE
PULSE MONITOR CIRCUIT
:
BACKGROUND OF_THE INVENTION
(1) Field of the Invention The present invention relates to digital s~itching systems and more particularly to a pulse monitor circuit for use in such systems.
(2~ Description of _he Prior Art:
Typical digital pulse monitor circuits require complex logic circuitry and often are unreliable and subject to race conditions. A recent advancement in the state of the art was disclosed by ~1. Ballentine in an article entitled "Clock-Activity Dete~tor Uses One DIP", Electronic Design News, January 5, 1980, page 156. However this circuit is subject to the following problems: potential race condi~ions for some circuit implementations due to insufficient clear pulse widths; any detected failure signal is cleared when the monitored pulse signal reappears; and it is unable to detect reference signal failures.
Accordingly it is the object of the present invention to provide a minimum component J highly reliable pulse monitor circuit, free of any potential race problems, resettable by either an external clear signal or reappearance of the monitored pulse, and capable of detecting failures of both the monitored and reference pulse signals.
--2~
~SUMMARY OF THE INVENTION
The present invention is a circuit which detects the occurrence of monitored clock pulses during time intervals defined by an external reference pulse train~ This circuit also detects failures of the reEerence pulse signals by monitoring the occur-rence of reference pulse signals during time intervals derived from the clock pulse signals. Thus, this circuit comprises two sections, namely, a clock pulse monitor section and a reference pulse monitor section.
In the clock pulse monitor section the external reference signal clocks a storage circuit, while a detection circuit is cLocked in response to monitored pulses. The detection circuit is also rese-t by the external reference signal.
The frequency of the reference clock pulses is less than half the frequency of the monitored clock pulses. This ratio guarantees that at least one monitored clock pulse edge occurs for each reference pulse.
If a monitored clock pulse edge occurs during the reference pulse the detection circuit switches to a set state. Its output signals are then transferred into the storage circuit when that circuit is clocked by the trailing edge oE the reference pulse. This storage circuit then provides a clock detected signal.
If the monitored pulse does not appear during the reference pulse, the detection circuit does not switch out of the reset state. Its output signals are then transferred to the storage circuit when that circuit is clocked by the trailing edge of the reference pulse. The storage circuit then provides a clock failure signal.
In one mode of operation, the clock failure condition is latched and the storage circuit thus provides a failure indication even i~ the monitored clock pulse signal reappears. Therefore, a failure 3~
condltion can only be reset by an external clear signal. In an alternate mode of operation the clock failure condition is not latched. Therefore an external clear signal is not required since the failure con-dition will be cleared when the monitored pulse re-appears.
Similarly, the reference pulse monitor section detects failure of the reference. This in-sures that the absence of a monitored pulse failure signal is not due to the absence of a reference signal.
The circuitry of this section is identical to that of the clock pulse monitor section. ~oweverl in this section the reference signal is applied to the clock input of -the de~ection circuit and the reference signal for this section is a frequency divided version of the monitored clock pulse signal. The Erequency of the frequency divided signal is less than half the frequency of the reference pulse signal and there-fore less than one-fourth the frequency of -the monitored clock pulse signal. This ratio guarantees that at least one reference pulse edge occurs for each frequency divided pulse.
DESCRIPTION OF TH_ DRAWING_ The single figure of the accompanying drawing is a logic diagram of a pulse monitor circuit in accordance with the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now to the accompanying drawing, the pulse monitor circuit of the present invention is sh~wn. This circuit includes pulse monitor Ml which operates to detect failures in the monitored clock pulse train (CLK), and pulse monitor M2 which operates to detect failures in the reference pulse train (REF). These pulse trains are provided ~y external pulse sources.
~ S)3~
If a failure is detected in the CLK pulse train a clock pulse failure (-CLK F~IL) s.ignal is generated by monitor Ml. Similarly, if a failure is detected in the REF pulse train, a reference pulse failure (-REF FAIL) signal is generated by monitor M2. ~y monitoring the reference REF pulse train, monitor M2 insures that an absence of a monitored clock pulse failure (-CLK FAIL) signal is not due to a failure of the REF signal.
For monitor M1, the frequency of the ref-erence pulse train REF is chosen to be less than half the frequency of the monitored clock pulse train CI.K.
This guarantees tha~ a least one negative CLK pulse edge occurs during the high time of the REF signal.
Similarly, the reference signal for monitor M2 must also have a frequency less than half the Erequency of its clock signal (REF), in order to guarantee that at least one REF pulse occurs during the high time of its reference signal. If the CLK signal is n times the fre~uency of the REF signal (n~ 2), dividing the CLK signal by something greater than 2n, results in the signal having a frequency less than half the frequency of the REF signal. Therefore, by applying the CLK signal to an appropriate frequency divider FD, this frequency divider provides monitor M2 with reference signal REF 2 of the desired frequency.
Referring now to the circuitry of pulse monitor Ml, the Ql output of flip-flop Fl is shown connected to the K2 input of flip-flop F2. Input J2 is shown connectable to either the Ql output of flip-flop Fl or to ground. The inputs, Jl and Kl of flip-flop Fl are shown connected to 5V and ground respectively. The clear input of flip-flop Fl and a negative edge triggered clock input of flip-flop F2 are shown connected to an external reference lREF) pulse source. The negative edge triggered clock input of flip-flop Fl is then connected to the moni~ored clock pulse (CLK) source via AND gate Gl. ThiS gate --5~
is also shown connected to an external clock failure (-FAIL CLK) routining control circuit. The preset input of flip-flop F2 is shown connected to an external clear signal (-CL~ FAIL) control circuit while the Q2 output of flip-flop F2 provides a clock failure (-CLK FAIL) signal.
The frequency of the REF pulse signal is chosen to be less than half the frequency of the monitored CLK signal. This ra~io guarantees that~
during normal operation, at least one negative going CLK pulse edge occurs during the high time of the REF signalO
To initialize this circuit a logic level 0 clear signal (-CLR FAIL) is applied to the preset input of storage flip-flop F2. This causes flip-flop F2 to clear the failure detected signal ( CLK F~IL) by driving i~s Q2 output to a logic level 1. During normal operations, the routining control signals (-FAIL CLK and -FAIL REF) are at a logic level 1.
Therefore, the monitored CLK pulse is normally applied by gate Gl to the clock input of flip-flop Fl, and frequency divider FD. Similarly, reference signal REF is normally applied to the clock input of flip-flops F2 and F3 and the clear input of flip-flop Fl.
When a negative going edge of a monitored CLK pulse appears at the clock input of flip-flop Fl the logic level 1 and 0 signals, at ~he Jl and Kl irputs, are transferred to the Ql and Ql outputs, respectively, of flip-flop Fl. When the negative going edge of a REF pulse subsequently appears at the clear input of flip-flop Fl it causes this flip-flop to reset.
However, since the REF pulse simultaneously appears at the clock input of flip-flop F2, this flip-flop responds to the signals appearing at its inputs before flip-flop Fl is reset. ~oth flip-flops have a zero hold time requirement for data appearing at the J
and K inputs with respect to a negative clock edge.
If the J2 input is connected to the Ql output the logic level 1 and 0 signals at the Ql and Ql outputs appear at the J2 and K2 inputs respectively.
When the neyative going edge o a R~F pulse subsequently appears at the clock input oE flip-flop F~, these logic level 1 and 0 signals are clocked into flip-flop F2 and a logic level 1 signal again appears at the Q2 output.
If the J2 input is connected to ground, logic level 0 signals appear at both the J2 and K2 inputs. With this arrangement, when the negative going edge of a RE~ pulse appears at the clock input of flip-flop F2, the logic level 1 signal at the Q2 output again remains unchanged, since flip-flop F2 does not switch when logic level 0 signals appear at its J2 and K2 inputs. Thus the absence of a failure condition is maintained since the -CLK FAIL signal remains at a logic level 1 as long as a negative going monitored CLK pulse edge occurs during the high time of the REF signal.
If the CLK pulse fails, flip flop Fl, after being reset by the RF.F pulse, remains reset with logic level 0 and 1 signals on its Ql and Ql outputs respec-tively.
If the J2 input is connected to the Ql output these logic level 0 and 1 signals appear at the J2 and K2 inputs respectivel~. When the negative going edge of a REF pulse subsequently appears at the clock input of flip-flop F2, it switches state and a logic level 0 signal appears a~ its Q2 output.
Thus the failure condition is detected since the -CLK
FAIL signal is at a logic level 0. In this conEig-uration, the failure condition can be cleared upon reappearance of a CLK pulse. If a CLK pulse does reappear logic level 1 and 0 signals appear at the 3~
Ql and Ql outputs respectively. Therefore, these signals also appear at the J2 and K2 inputs. Con-sequently, flip flop F2 switches out of ~he failure state and the -CLK FAIL signal returns to a logic level 1.
If the J2 input is connected to ground, logic level O and l signals still appear at the Ql and Ql outputs when a CLK pulse fails. However, only the K2 input responds to a signal from flip-flop Fl since a logic level O signal (ground) constantly appears at the J2 input. With this arrangement, when the negative going edge of a REF pulse appears at the clock input of flip-flop F2, it switches state and a logic level O signal appears at its Q2 output.
Thus the failure condition is again detected since the -CLK FAIL signal is again at a logic level 0.
However, in this configuration, the failure condition can only be cleared by a logic level O external clear signal -CLR FAIL applied to the preset input of flip-flop F2. Reappearance of a CLK pulse will not clearthe failure condition. It will cause flip-flop Fl to set, but this only results in logic level O signals being applied to the J2 and K2 inputs since J2 is connected to ground and a logic level O signal appears at K2 via Ql. Flip-flop F2 will not switch under such conditions and therefore the failure condition is not cleared~
Gate Gl provides a means for routining pulse monitor Ml since it allows for the simulation of a monitcred CLK pulse failure condition. This routining occurs when a logic level O (-FAI~ CLK~ signal appears at the first input of gate ~l. Similarly, gate Gl provides a means for routining pulse monitor M2 since it allows for the simulation of REF pulse failure condition.
The structure and operation of monitor M2 is identical to that of monitor Ml, except for the use of diferent clock and reference signals. There-fore the previous description of the operation of monitor Ml also applys to the operation of monitor M2.
The present invention thus discloses a highly reliable, minimum component, pulse monitor circuit which is not susceptible to race conditions, is capable of detecting failure o both the clock and reference signals, and can be reset by either an external clear signal or reappearance of the monitored clock or reference signals.
TITLE
PULSE MONITOR CIRCUIT
:
BACKGROUND OF_THE INVENTION
(1) Field of the Invention The present invention relates to digital s~itching systems and more particularly to a pulse monitor circuit for use in such systems.
(2~ Description of _he Prior Art:
Typical digital pulse monitor circuits require complex logic circuitry and often are unreliable and subject to race conditions. A recent advancement in the state of the art was disclosed by ~1. Ballentine in an article entitled "Clock-Activity Dete~tor Uses One DIP", Electronic Design News, January 5, 1980, page 156. However this circuit is subject to the following problems: potential race condi~ions for some circuit implementations due to insufficient clear pulse widths; any detected failure signal is cleared when the monitored pulse signal reappears; and it is unable to detect reference signal failures.
Accordingly it is the object of the present invention to provide a minimum component J highly reliable pulse monitor circuit, free of any potential race problems, resettable by either an external clear signal or reappearance of the monitored pulse, and capable of detecting failures of both the monitored and reference pulse signals.
--2~
~SUMMARY OF THE INVENTION
The present invention is a circuit which detects the occurrence of monitored clock pulses during time intervals defined by an external reference pulse train~ This circuit also detects failures of the reEerence pulse signals by monitoring the occur-rence of reference pulse signals during time intervals derived from the clock pulse signals. Thus, this circuit comprises two sections, namely, a clock pulse monitor section and a reference pulse monitor section.
In the clock pulse monitor section the external reference signal clocks a storage circuit, while a detection circuit is cLocked in response to monitored pulses. The detection circuit is also rese-t by the external reference signal.
The frequency of the reference clock pulses is less than half the frequency of the monitored clock pulses. This ratio guarantees that at least one monitored clock pulse edge occurs for each reference pulse.
If a monitored clock pulse edge occurs during the reference pulse the detection circuit switches to a set state. Its output signals are then transferred into the storage circuit when that circuit is clocked by the trailing edge oE the reference pulse. This storage circuit then provides a clock detected signal.
If the monitored pulse does not appear during the reference pulse, the detection circuit does not switch out of the reset state. Its output signals are then transferred to the storage circuit when that circuit is clocked by the trailing edge of the reference pulse. The storage circuit then provides a clock failure signal.
In one mode of operation, the clock failure condition is latched and the storage circuit thus provides a failure indication even i~ the monitored clock pulse signal reappears. Therefore, a failure 3~
condltion can only be reset by an external clear signal. In an alternate mode of operation the clock failure condition is not latched. Therefore an external clear signal is not required since the failure con-dition will be cleared when the monitored pulse re-appears.
Similarly, the reference pulse monitor section detects failure of the reference. This in-sures that the absence of a monitored pulse failure signal is not due to the absence of a reference signal.
The circuitry of this section is identical to that of the clock pulse monitor section. ~oweverl in this section the reference signal is applied to the clock input of -the de~ection circuit and the reference signal for this section is a frequency divided version of the monitored clock pulse signal. The Erequency of the frequency divided signal is less than half the frequency of the reference pulse signal and there-fore less than one-fourth the frequency of -the monitored clock pulse signal. This ratio guarantees that at least one reference pulse edge occurs for each frequency divided pulse.
DESCRIPTION OF TH_ DRAWING_ The single figure of the accompanying drawing is a logic diagram of a pulse monitor circuit in accordance with the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now to the accompanying drawing, the pulse monitor circuit of the present invention is sh~wn. This circuit includes pulse monitor Ml which operates to detect failures in the monitored clock pulse train (CLK), and pulse monitor M2 which operates to detect failures in the reference pulse train (REF). These pulse trains are provided ~y external pulse sources.
~ S)3~
If a failure is detected in the CLK pulse train a clock pulse failure (-CLK F~IL) s.ignal is generated by monitor Ml. Similarly, if a failure is detected in the REF pulse train, a reference pulse failure (-REF FAIL) signal is generated by monitor M2. ~y monitoring the reference REF pulse train, monitor M2 insures that an absence of a monitored clock pulse failure (-CLK FAIL) signal is not due to a failure of the REF signal.
For monitor M1, the frequency of the ref-erence pulse train REF is chosen to be less than half the frequency of the monitored clock pulse train CI.K.
This guarantees tha~ a least one negative CLK pulse edge occurs during the high time of the REF signal.
Similarly, the reference signal for monitor M2 must also have a frequency less than half the Erequency of its clock signal (REF), in order to guarantee that at least one REF pulse occurs during the high time of its reference signal. If the CLK signal is n times the fre~uency of the REF signal (n~ 2), dividing the CLK signal by something greater than 2n, results in the signal having a frequency less than half the frequency of the REF signal. Therefore, by applying the CLK signal to an appropriate frequency divider FD, this frequency divider provides monitor M2 with reference signal REF 2 of the desired frequency.
Referring now to the circuitry of pulse monitor Ml, the Ql output of flip-flop Fl is shown connected to the K2 input of flip-flop F2. Input J2 is shown connectable to either the Ql output of flip-flop Fl or to ground. The inputs, Jl and Kl of flip-flop Fl are shown connected to 5V and ground respectively. The clear input of flip-flop Fl and a negative edge triggered clock input of flip-flop F2 are shown connected to an external reference lREF) pulse source. The negative edge triggered clock input of flip-flop Fl is then connected to the moni~ored clock pulse (CLK) source via AND gate Gl. ThiS gate --5~
is also shown connected to an external clock failure (-FAIL CLK) routining control circuit. The preset input of flip-flop F2 is shown connected to an external clear signal (-CL~ FAIL) control circuit while the Q2 output of flip-flop F2 provides a clock failure (-CLK FAIL) signal.
The frequency of the REF pulse signal is chosen to be less than half the frequency of the monitored CLK signal. This ra~io guarantees that~
during normal operation, at least one negative going CLK pulse edge occurs during the high time of the REF signalO
To initialize this circuit a logic level 0 clear signal (-CLR FAIL) is applied to the preset input of storage flip-flop F2. This causes flip-flop F2 to clear the failure detected signal ( CLK F~IL) by driving i~s Q2 output to a logic level 1. During normal operations, the routining control signals (-FAIL CLK and -FAIL REF) are at a logic level 1.
Therefore, the monitored CLK pulse is normally applied by gate Gl to the clock input of flip-flop Fl, and frequency divider FD. Similarly, reference signal REF is normally applied to the clock input of flip-flops F2 and F3 and the clear input of flip-flop Fl.
When a negative going edge of a monitored CLK pulse appears at the clock input of flip-flop Fl the logic level 1 and 0 signals, at ~he Jl and Kl irputs, are transferred to the Ql and Ql outputs, respectively, of flip-flop Fl. When the negative going edge of a REF pulse subsequently appears at the clear input of flip-flop Fl it causes this flip-flop to reset.
However, since the REF pulse simultaneously appears at the clock input of flip-flop F2, this flip-flop responds to the signals appearing at its inputs before flip-flop Fl is reset. ~oth flip-flops have a zero hold time requirement for data appearing at the J
and K inputs with respect to a negative clock edge.
If the J2 input is connected to the Ql output the logic level 1 and 0 signals at the Ql and Ql outputs appear at the J2 and K2 inputs respectively.
When the neyative going edge o a R~F pulse subsequently appears at the clock input oE flip-flop F~, these logic level 1 and 0 signals are clocked into flip-flop F2 and a logic level 1 signal again appears at the Q2 output.
If the J2 input is connected to ground, logic level 0 signals appear at both the J2 and K2 inputs. With this arrangement, when the negative going edge of a RE~ pulse appears at the clock input of flip-flop F2, the logic level 1 signal at the Q2 output again remains unchanged, since flip-flop F2 does not switch when logic level 0 signals appear at its J2 and K2 inputs. Thus the absence of a failure condition is maintained since the -CLK FAIL signal remains at a logic level 1 as long as a negative going monitored CLK pulse edge occurs during the high time of the REF signal.
If the CLK pulse fails, flip flop Fl, after being reset by the RF.F pulse, remains reset with logic level 0 and 1 signals on its Ql and Ql outputs respec-tively.
If the J2 input is connected to the Ql output these logic level 0 and 1 signals appear at the J2 and K2 inputs respectivel~. When the negative going edge of a REF pulse subsequently appears at the clock input of flip-flop F2, it switches state and a logic level 0 signal appears a~ its Q2 output.
Thus the failure condition is detected since the -CLK
FAIL signal is at a logic level 0. In this conEig-uration, the failure condition can be cleared upon reappearance of a CLK pulse. If a CLK pulse does reappear logic level 1 and 0 signals appear at the 3~
Ql and Ql outputs respectively. Therefore, these signals also appear at the J2 and K2 inputs. Con-sequently, flip flop F2 switches out of ~he failure state and the -CLK FAIL signal returns to a logic level 1.
If the J2 input is connected to ground, logic level O and l signals still appear at the Ql and Ql outputs when a CLK pulse fails. However, only the K2 input responds to a signal from flip-flop Fl since a logic level O signal (ground) constantly appears at the J2 input. With this arrangement, when the negative going edge of a REF pulse appears at the clock input of flip-flop F2, it switches state and a logic level O signal appears at its Q2 output.
Thus the failure condition is again detected since the -CLK FAIL signal is again at a logic level 0.
However, in this configuration, the failure condition can only be cleared by a logic level O external clear signal -CLR FAIL applied to the preset input of flip-flop F2. Reappearance of a CLK pulse will not clearthe failure condition. It will cause flip-flop Fl to set, but this only results in logic level O signals being applied to the J2 and K2 inputs since J2 is connected to ground and a logic level O signal appears at K2 via Ql. Flip-flop F2 will not switch under such conditions and therefore the failure condition is not cleared~
Gate Gl provides a means for routining pulse monitor Ml since it allows for the simulation of a monitcred CLK pulse failure condition. This routining occurs when a logic level O (-FAI~ CLK~ signal appears at the first input of gate ~l. Similarly, gate Gl provides a means for routining pulse monitor M2 since it allows for the simulation of REF pulse failure condition.
The structure and operation of monitor M2 is identical to that of monitor Ml, except for the use of diferent clock and reference signals. There-fore the previous description of the operation of monitor Ml also applys to the operation of monitor M2.
The present invention thus discloses a highly reliable, minimum component, pulse monitor circuit which is not susceptible to race conditions, is capable of detecting failure o both the clock and reference signals, and can be reset by either an external clear signal or reappearance of the monitored clock or reference signals.
Claims (14)
1. A pulse monitor circuit for use in a switching system, including a reference signal source normally operated to provide reference signal pulses of first and second polarities and of a first frequency and abnormally operated to inhibit said reference signal pulses, and a clock signal source, normally operated to provide clock signal pulses of first and second polarities and of a first frequency and abnor-mally operated to inhibit said clock signal pulses, said pulse monitor circuit comprising:
clock monitor means connected to said clock signal source and said reference signal source, oper-ated in response to a reference signal pulse of said first polarity and an absence of a clock signal pulse to provide a clock failure signal;
frequency division means, connected to said clock signal source, operated to divide said first frequency of said clock signal pulses by a predeter-mined amount, whereby said frequency division means provides frequency divided clock signal pulses having first and second polarities and a second frequency less than said first frequency of said reference signal;
and reference monitor means, connected to said reference signal source and said frequency division means, operated in response to a frequency divided clock signal pulse of said first polarity and an absence of a reference signal pulse to provide a ref-erence failure signal.
clock monitor means connected to said clock signal source and said reference signal source, oper-ated in response to a reference signal pulse of said first polarity and an absence of a clock signal pulse to provide a clock failure signal;
frequency division means, connected to said clock signal source, operated to divide said first frequency of said clock signal pulses by a predeter-mined amount, whereby said frequency division means provides frequency divided clock signal pulses having first and second polarities and a second frequency less than said first frequency of said reference signal;
and reference monitor means, connected to said reference signal source and said frequency division means, operated in response to a frequency divided clock signal pulse of said first polarity and an absence of a reference signal pulse to provide a ref-erence failure signal.
2. A pulse monitor circuit as claimed in claim 1, wherein there is further included: a clear signal source, said clock monitor means and said ref-erence monitor means each further connected to said clear signal source and each further operated in response to said clear signal to clear said clock failure and reference failure signals, respectively.
3. A pulse monitor circuit as claimed in claim 1, wherein there is further included, a clock routining signal source, said pulse monitor circuit further comprising: gating means connected to said clock signal source and said clock routining signal source, operated in response to said clock routining signal to inhibit said clock signal.
4. A pulse monitor circuit as claimed in claim 1, wherein there is further included, a ref-erence routining signal source, said pulse monitor circuit further comprising: gating means connected to said reference signal source and said reference routining signal source, operated in response to said reference routining signal to inhibit said reference signal.
5. A pulse monitor circuit as claimed in claim 1, wherein said clock monitor means comprises:
detection means connected to said clock signal source and said reference signal source, operated in response to said reference signal pulse of said first polarity and an absence of said clock signal pulse to provide a clock failure detected signal;
said detection means further operated in response to said reference signal pulse of said second polarity to clear said clock failure detected signal;
and storage means connected to said detection means and said reference signal source, operated in response to said reference signal pulse of second polarity and said clock failure detected signal to provide said clock failure signal.
detection means connected to said clock signal source and said reference signal source, operated in response to said reference signal pulse of said first polarity and an absence of said clock signal pulse to provide a clock failure detected signal;
said detection means further operated in response to said reference signal pulse of said second polarity to clear said clock failure detected signal;
and storage means connected to said detection means and said reference signal source, operated in response to said reference signal pulse of second polarity and said clock failure detected signal to provide said clock failure signal.
6. A pulse monitor circuit as claimed in claim 1, wherein said reference monitor means comprises:
detection means connected to said reference signal source and said frequency division means, oper-ated in response to said frequency divided clock signal pulse of said first polarity and an absence of said reference signal pulse to provide a reference failure detected signal;
said detection means further operated in response to said frequency divided clock signal pulse of said second polarity to clear said reference fail-ure detected signal; and storage means connected to said detection means and said frequency division means, operated in response to said frequency divided clock signal pulse of second polarity and said reference failure detected signal to provide said reference failure signal.
detection means connected to said reference signal source and said frequency division means, oper-ated in response to said frequency divided clock signal pulse of said first polarity and an absence of said reference signal pulse to provide a reference failure detected signal;
said detection means further operated in response to said frequency divided clock signal pulse of said second polarity to clear said reference fail-ure detected signal; and storage means connected to said detection means and said frequency division means, operated in response to said frequency divided clock signal pulse of second polarity and said reference failure detected signal to provide said reference failure signal.
7. A pulse monitor circuit as claimed in claim 5, wherein: said storage means is further oper-ated in response to said reference signal pulse of second polarity and an absence of said clock failure detected signal to clear said clock failure signal.
8. A pulse monitor circuit as claimed in claim 6, wherein: said storage means is further oper-ated in response to said frequency divided clock signal pulse of second polarity and an absence of said ref-erence failure detected signal to clear said reference failure signal.
9. A pulse monitor circuit as claimed in claim 5, wherein said detection means comprises: a flip-flop having a clock input connected to said clock signal source and a clear input connected to said reference signal source.
10. A pulse monitor circuit as claimed in claim 6, wherein said detection means comprises: a flip-flop having a clock input connected to said ref-erence signal source and a clear input connected to said frequency division means.
11. A pulse monitor circuit as claimed in claim 5, wherein said storage means comprises: a flip-flop having a clock input connected to said ref-erence signal source, a first data input connected to ground and a second data input connected to said detec-tion means.
12. A pulse monitor circuit as claimed in claim 6, wherein said storage means comprises: a flip-flop having a clock input connected to said frequency division means and a first data input connected to ground and a second data input connected to said detec-tion means.
13. A pulse monitor circuit as claimed in claim 7, wherein said storage means comprises: a flip-flop having a clock input connected to said reference signal source and first and second data inputs con-nected to said detection means.
14. A pulse monitor circuit as claimed in claim 8, wherein said storage means comprises: a flip-flop having a clock input connected to said frequency division means and first and second data inputs con-nected to said detection means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/333,220 US4446437A (en) | 1981-12-21 | 1981-12-21 | Pulse monitor circuit |
| US333,220 | 1981-12-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1180396A true CA1180396A (en) | 1985-01-02 |
Family
ID=23301856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000416977A Expired CA1180396A (en) | 1981-12-21 | 1982-12-03 | Pulse monitor circuit |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4446437A (en) |
| CA (1) | CA1180396A (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4611295A (en) * | 1982-05-28 | 1986-09-09 | Robertshaw Controls Company | Supervisory control system for microprocessor based appliance controls |
| US4572966A (en) * | 1983-12-22 | 1986-02-25 | Rockwell International Corporation | Activity monitor, power-on clear circuit |
| AU572593B2 (en) * | 1983-12-22 | 1988-05-12 | Alcatel N.V. | Signal recognition system |
| US4628269A (en) * | 1984-05-23 | 1986-12-09 | Motorola, Inc. | Pulse detector for missing or extra pulses |
| JPH07104689B2 (en) * | 1986-11-07 | 1995-11-13 | フアナツク株式会社 | Pulse encoder |
| DE3704980A1 (en) * | 1987-02-17 | 1988-08-25 | Philips Patentverwaltung | CIRCUIT ARRANGEMENT FOR MONITORING A BINAER SIGNAL |
| EP0437425A1 (en) * | 1988-10-05 | 1991-07-24 | Siemens Aktiengesellschaft | Process and device for monitoring failures of timing signals |
| US5101127A (en) * | 1989-03-23 | 1992-03-31 | Texas Instruments Incorporated | Digital integrated frequency discriminator of external clock and internally generated signal backup |
| US5065047A (en) * | 1989-03-27 | 1991-11-12 | Nissan Motor Co., Ltd. | Digital circuit including fail-safe circuit |
| US5336939A (en) * | 1992-05-08 | 1994-08-09 | Cyrix Corporation | Stable internal clock generation for an integrated circuit |
| US5418481A (en) * | 1993-12-10 | 1995-05-23 | Cray Research, Inc. | Repetitive signal detector for preventing thermal runaway |
| DE4402124A1 (en) * | 1994-01-21 | 1995-07-27 | Siemens Ag | Circuit arrangement for monitoring digital periodic signals |
| JP4323782B2 (en) * | 2002-11-28 | 2009-09-02 | パナソニック株式会社 | Receiver circuit |
| US7454645B2 (en) * | 2005-03-31 | 2008-11-18 | Cypress Semiconductor Corp. | Circuit and method for monitoring the status of a clock signal |
| US10848140B1 (en) | 2020-07-20 | 2020-11-24 | Nxp Usa, Inc. | Method and system for detecting clock failure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE326321B (en) * | 1968-11-15 | 1970-07-20 | E Sjoequist | |
| US3795867A (en) * | 1973-04-02 | 1974-03-05 | Gte Automatic Electric Lab Inc | Pulse detection arrangement |
| US4342112A (en) * | 1980-09-08 | 1982-07-27 | Rockwell International Corporation | Error checking circuit |
-
1981
- 1981-12-21 US US06/333,220 patent/US4446437A/en not_active Expired - Fee Related
-
1982
- 1982-12-03 CA CA000416977A patent/CA1180396A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4446437A (en) | 1984-05-01 |
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