CA1186414A - Centralized hardware control of multi-system access to shared and non-shared subsystems - Google Patents

Centralized hardware control of multi-system access to shared and non-shared subsystems

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Publication number
CA1186414A
CA1186414A CA000424901A CA424901A CA1186414A CA 1186414 A CA1186414 A CA 1186414A CA 000424901 A CA000424901 A CA 000424901A CA 424901 A CA424901 A CA 424901A CA 1186414 A CA1186414 A CA 1186414A
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Canada
Prior art keywords
subsystem
ssp
interface
command
sau
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000424901A
Other languages
French (fr)
Inventor
John M. Quernemoen
Timothy R. Voltz
Joseph G. Kriscunas
Richard P. Campbell
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Sperry Corp
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Sperry Corp
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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/468Specific access rights for resources, e.g. using capability register

Abstract

ABSTRACT

A centralized control unit for use in a multisystem data processing configuration to provide dynamic access to shared and non-shared peripheral subsystems is disclosed. This unit, known herein as a subsystem access unit (SAU) is able to remotely control one or more system's accessibility to per-ipheral subsystem's from a central location. It is able to provide this control with the capability of either allowing a peripheral subsystem to be con-currently accessed by more than one system or forcibly ensuring that the peripheral subsystem is exclusively accessible by only a single system.

Description

A CENTlRALIZED HARD~VARE CONTROL Ol: MULTI-S STEM
~CCESS TO S~IARED AND NON-SHAl~ED SURSYSTEMS
_ __ _ ___ _ Background of the Invention _ A. Field of the Invention __ _ This invention relates generally to a centraliæed control apparatus for use in conjunction with a plurality of data processing systems and a plurality of shared and non-shared peripheral subsystems. In particular, a unit is provided which is able to control one or more system 's accessibility to one or more - peripheral subsystems from a central location. This unit has the capability of either allowing a peripheral subsystem to be concurrently accessed by more than one data proccssing system or ensuring that the peripheral subsystem is exclusively accessible to only one data processing system.

B. Prior Art In the past, as a customer's need fot data processing capability increased, the customer was required to either replace his existing system with a larger system or alternatively to add further systems to operate in conjunction with his existing one. Because of the numerous difficulties inherent in either solution, the customer often either delayed his decision until the last possiblemoment or he attempted to do without the expansion altogether. In other 21) words, there was little or no flexibility in his existing system.

Even with the advent of large scale multiprocessing systems or with the increasing use ol multiple similar systems, there was an increasing need for flexibility in the manner of use of each system component or set of system com ponents.
,~

It is o~ten advantageous to be able to separate a multiprocessor system into two or more electrically isolated and software independent entities. Each of these entities, of course, has the complete characteristics of a full operational system. One such entity might be required for maintenance purposes, while the other is used for work applicable to its site. Or there may exist the need for two user programs to be running concurrently, one performing scheduled production work while the other is dedicated to highly sensitive data processing that requires complete electrical isolation from the first for reasons of security.

The capability of forming electrically isolated and software independent entities in a given multiprocessor system from a central location has been achieved. Further, changing the composition of the independent entities within a system, by adding or removing components, without disrupting normal operarions has also been achieved. Although the peripher~l subsystems could be uniquely associated with a particular independent entity and electrically isolated from the others, the control of their association was either manual or via software functions associated with each independent entity. In the latter case, there was no dynamic hardware means to prevent the software of one independent entity from causing the removal of a subsystem from another entity and subsequently adding the subsystem to the first entity. In particular,dynamic hardware protection of mass storage files from a multiplicity of entities having a llardware means of communication with them was not available. Additionally, the capability of adding or removing a subsystem to or from entities was limited to entities within a single systern. ~or example, a péripheral subsystem such as a card reader may have limited use as a single subsystem, however, if R customer site had multiple systerns then the subsystemls utilizatian would be considerably increased if it could be used by each of the multiple systems. Naturally, the cost of any additional subsystems also could be spread over all of the systems using it and its increased utilization would likewise reduce its unit cost.

Most peripheral subsystems of present day data processing systems have interfaces capable of communication with more than one input/output processor.

~Iowever, in all of such known systems, these interfaces were ixed in a certain inflexible mode, either electrically or manually, upon determination of a particular system configuration. Thereafter they were only changed if the particular predetermined system configuration was modified and a change was S necessary to accommodate the modification.

It is the purpose of this invention to provide a peripheral subsystem access unit which possesses increased interface flexibility, in that it is not limited in its utilization to one system nor to one configuration.

Brief Descripti_of the Invention A. Objects of the Invention ____ ._ __ _ ~ccordingly, it is nn object of this invelltion to provide a unique and relatively simple mPan3 which dynamica]ly and switchably controls the acces-sibility of a plurality of data processing systerms to a plurality of shared and non-shared peripheral subsystems.

It is another object of this invention to extend the capability of present data processing systems, so that such peripheral subsystems may be shared between a plurality of entities each having charactcristics of a complete data processing system.

It is a further object of this invention to provide a central controlling unit 2n which, from a central location, dynamically enables and/or disables a plurality of subsystem interface interconnections to a set of data processing systems and a set of entities each having characteristics of a complete data processing system .

It is a still further object of this invention to provide a centrali~ed peripheral subsystem access unit which is capable of enforcing exclusive use of a particular subsystem by a particular entity of the plurality of entities within a multi-processing system or a set of data processing systems.

It is also an object of this invention to provide a centrali~ed peripheral subsystem access unit which is capable of enforcing this exclusive use during the 3~ period that non-sharing of this particular peripheral subsystem is desired.

B. Summary of the Invention A peripheral subsystem access unit is disclosed which allows complete flexibility of the use of a peripheral subsystcm by a plurality of entities within a multiprocessing system or a plurality of data processing systems. These entities are referred to in this description as applications and are hereinafterde~ined.

The access unit disclosed comprises a first interface means capable oî
being coupled to a plurality of command sources, a second interface means capable of being coupled to a plurality of peripheral subsystems and an internalstorage and logic means. The internal storage and logic means, under control of certain command sources, includes the resident data and the logic necessary to providc control and switching signals to the peripheral subsystems for switchably connecting particular peripheral subsystems to certain applications for shared use by these entities. Further, and equally important, the access unit is capable of preventing such shared use where exclusive use is desired.

Thus, via the interface to the command sources, the subsystem access unit accepts requests lo enable or disable a subsystem interface. This enabling or disabling of the data path to the peripheral subsystem allows a subsystem to be corlcurrently accessible to more than one application (i.e. shared) or to be exclusively used by one one such entity. The subsystem access unit is capable of enforcing this exclusive use upon all of the systems. That is, it can preventany I/O processor from having access to a subsystem even though the l/O
processor may desire such access.

_RIEF DESCRIPTION OF THF DR~WINGS

The foregoing objects and the summary will be more readily understood when read in conjunction with the accompanying drawings in which:

Fig. 1 is a blocl~ diagram of a data processing system illustrating a multiprocessing environment. It also illustrates an example of an application wherein the multiple processors share the same memory and executive software.

Fig. 2 is a block diagram of the multiprocessing system of E;ig. 1 which system is separated (partitioned) into two applications wherein the processor ofa given application has its own memory and executive software. The peripheral subsystems may or may not be shared.

Fig. 3 is a bloek diagram showing the multiproeessing system of Fig. L partitioned into two applications, the introduetion of the subsystem aeeess unit of the present invention into sueh a separated system, and an illustration of the swi~chable concepts of ~he peripheral subsystems.
Fig. 4 illustrates a flowehart of the use of resident information within the subsystem aecess unit to affect partitioning of the subsystems.
Fig. 5 is a more detailed block diagram of the sub-system aecess unit and its use in a system configuration.
Fig. 6 is a functional block diagram of the subsystem aeeess unit (SAU) of the present invention.
Fig. 7 ineludes Fig. 7A and Fig. 7B positioned as shown, and is a more detailed bloek diagram of the sub-system aeeess unit illustrating speeific suggested elements for each of the bloeks.
Fig. 8 is a timing diagram illustrating the eloek signal sequenee.
Fig. 9, Fig. 10, Fig. ll, Fig. 12, FigO 13 and Fig. 14 respeetively show the five eontrol sequences used in the subsystem aeeess unit~
Fig. 15 is a timing diayram showing the timing signals of the shared peripheral interface (SPI).
Fig. 16 is also a tirning diagram showing the timing signals of the byte ehannel transfer switch (BCTS) interface.
Fig. 17 illustrates the format of each entry register of the Subsystem Interface Table.
Fig. 18 shows the format of a register entry of the System Support Processor (SSP) Application Table~
FigO 19 i5 the format of a register entry of the Input/Output Processor State Table.

,~.

E;ig. 20 presents tlle format of a regisler entry in the SSP IIistory Table.

Fig. 21 is the register format of the four byte command word which controls the operations of the Subsystem Access Unit ~SAU).

Fig. 22 is the format of the Add Subsystem command.

Fig. 23 presents the format of the Remove Subsystem command.

Fig. 24 is the format of the Write Subsystem IOP Number command.

Fig. 25 is the format of each of the entries în the 160 locations of the Subsystem Interface Table when the command of Fig. 14 is given.

Fig. 26 is the format of the command to read the Subsystem lnterface - 10 Table.

Fig. 27 is the format of the five bytes of data which are returned to the -- SSP when the Read Subsystem Interface command of Fig. 27 is given.

Fig. 28 is the format of the Write IOP State command.

Fig. 29 shows the corresponding format of the Read IOP State command~

Fig. 30 is the command format of Write SSP Nun~ber.

Fig. 31 is the corresponding command format of Read SSP Number.

Fig. 32 is the format of the command to Write Control Store.

Fig. 33 is the corresponding command to Read ~ontrol Store.

Fig. 34 is the format of the command to Reserve SAU.

Fig. 35 is the command format for Release SAU.

Fig. 36 shows the command format for the Resetting of the SAU.

Fig. 37 is the format of the command to Read ID Word O.
Fig. 38 shows the format of the command to Read ID Word 1.
Fig. 39 presents the format of the command to Read SPI.
Fig. 40 is ~he command format for reading the BCTS
interface.
Fig. 41 is the oommand format for Set Test Mode.
Fig~ 42 is the format of the command to Clear Test Mode.
Fig. 43 shows the command format to Set the SAU Lock.
Fig. 44 illustrates the command format to Clear the SAU
lQ Lock.
Fig. 45 is the format of the command to Write SSP History.
Fig. 46 is the corresponding format of the command to ~ead SSP History.
Fig. 47 comprises Figs. 47A, 47B, 47C, 47D and 47E
positioned as shown, and taken together form a flow chart of the SAU microcode.
Fig. 48 is a memory map of the SAU.
DETAILED DESCRIPTION OF THE INVENTION
The following detailed description will be more easily
2~ comprehended when it is read with reference to the fore-going drawings in which like reference characters s~mbolize corresponding parts.
Definitions The ~ollowing terms are defined for use in the detailed description that follows:

....

System A SysteM is a set of components with interfaces between the components connected, i.e., the hardware means of communication between the components exists. Additionally, this set of components will at least support an executive 5 or host software and consists of the following:
(a) Processor com plexes (b) Memory (c) I/O com plexes -(d) Peripheral subsystems Enabled Interface The interface between two cornponents is enabled whenever the transfer of data and control information between the components is not prohibited by component or interface hardware, or by electrical isolation. One component is ~onsidered accessible ~o another compor ont if the interface betwecr tham is enabled.

Partitioning The process of enabling and disabling component interfaces.

Application An application is all or a subset of a systems components where:
(a) The set of components supports an executive or host software.
(b Interfaces between the components are enablcd.
(c) Any component with interfaces enabled to other cornponents in the application is considered a part of this application.
A mainframe component not in any particular application is said to be offline. A mainframe component cannot be in two applications sim ultaneously. A subsystem is in a particular application if it has an interface enabled to a channel of an Input/Output processor in this application~

hared Peripheral Subsystem A peripheral subsystem is shared if its contIol unit(s) has (have) interfaces enabled to different Input/Output complexes in different applications of the same or different systems.

~ - - 9 -Fxclusive Use An application is said to have exclusive use of a peripheral subsystem when:
(a) the peripheral subsystem's interfaces are enabled only to Input/Output channel(s) in that application;
(b) the peripheral subsystems interfaces to other Input/Output channel(s) in other applications are prevented from being enabled .

Fig. 1 is a block diagram of a data processing system illustrating a 1~ multiprocessing single application environmer t.

A pair of instruction processors 114, 122 share a common memory storage unit 116 which houses a single executive or host program. Similarly, a pair o~
input/output processors 112, 124 also share the same men~ory storage unit 116.
A single peripheral subsystem 110 may be used by either IOP, 112, or IOP 12~.
Although there exists a certain amount of concurrency in the multiprocessing system of Figure 1, in that IOP 112 and IOP 124~ may be concurrently operatin~
in conjunction with selected peripheral devices within the subsystem 110, this concurrency may exist only in a certain predetermined manner. Likewise, the instruction processors 114, 122 may also concurrently operate in a manner established by the single executive software. Similarly, the exclusive use of any given unit of the system or of any given peripheral device of the subsystem 110 is never enforced since no means exists to prevent any system unit from gaining access to any other system unit. In the present instance, this system may be partitioned into completely separate and independent applications.

Figure 2 illustrates this concept. In this case, a processor 114, a memory 116A and an input/output processor ]12 have interfaces enabled to each other~
Likewise, a second processor 122, a second memory ll6B and a second input/output processor 124 have interfaces enabled to each other. However, the interfaces between the differing sets cf components i.e., the cross-coupled interfaces as shown in Fig. 1, are disabled. Each application has its own memory and host software The following described system which illustrates a preferred environment in which the present invention can operate, can have up to four Instruction Processors, (IP's), Input/Output Processors (IOP's) and ~emory Storage Units - lo -(MSU's~. It supports centralized partitioning and power control at the IP, IOP, MSU, alld peripberal subsystem levels. Partitioning of the peripheral subsys-tems is performed by the Subsystem ~ccess Unit (SAU) which is the subject of this application. The S~U operates under commands from the System Support Processor (SSP), however, any source of command signals to the S~U may be utilized. Additionally, the SAU performs th~ subsystem partitioning function for a plurality o~ the above described systems.

Referring to Fig. 3, there is shown a first and a second separate application. Thus, the first application includes I~SU, 116A; IP, 114; and IOP
112, while the second application comprises MSU, 116B; IP, 122; and lOP, 124.
Thus, the multiprocessing system of ~ig. 1 has been partitioned into two separate applications.

Further, the IO~Is 112 and 12a~ share the peripher.ll subsystem 110, ~hich includes a byte channel interface 310, and a first 312 and a second 3l8 shared peripheral interface (SPI). It is believed readily apparent from the pictorial of Fig. 3 drawing that the SPI's are capable of providing concwrrent access through the plurality of separate switches of SPI, 312 and SPI, 318.
~lternately, the byte channel transfer switch 310 is pictorially illustrated as a single switch which allows only a single IOP to be coupled to the subsystem strings 330 at any given time.

The Subsystem Access Unit (SAU) 300 shown is capable of controlling the switch of the byte channel interface 310 and the multiple switches of the SPI's 31~, 318.

Subsystem partitioning consists of providing a means to connect a control unit or a subsystem string to one or more 1/~ channels. Three methods of connection are possible:
1.) The connection is direct, i.e., no switching mechanism exists between the control unit and I/O channel.

2.) If the control units and subsystem strings are adapted for use with a Shared Peripheral Interface (SPI) and Byte Channel Transfer Switch (BCTS), respectively, or with similar functioning entities, then suh-system partitioning may be accomplished by manually setting the SPI
or BCTS switches. Setting these switches causes the enabling or disabling of appropriate ports or channe~s on the SPIs and BCTSs.

(An S~l allows a control unit to interface with up to four I/O
channels; a BCTS allows a subsystem string to interf~ce with one of four I/O channels.)
3.) A means to remotely set the SP~ and BCTS switches is provided.

Note that the latter two methods make it possible to share a subsystem between applications. This invention provides a means to remotely set the SPI!s and the BCTS's with or without the presence of an operator.

~or the present system it was decided to develop a free-standing system component which would perform the remote subsystem partitioning function via commands from one or more command sources (herein SSP's) This component is called a Subsystem ~ccess IJnit (S~U).

Through the SAU, the present system supports an application's exclusive use of a subsystem and the sharing of subsystems between applications in the same or differellt systems. Because of this type of support, the SAU must perform subsystem partitioning for more than one system and/or application, i.e., if a subsystem can be shared by applications in more than one system, thenthe same SAU performs the subsystem partitioning for all the systems connected to that subsystem. In exercisingr this function there is no inherent requirementfor communications between applications either at the SSP or application level.

In the present embodirnent, the SAU can accept cornmands from a maximum of four SSP's, and it supports subsystem partitioning for a maximum of sixteen applications.

A maximum of four SAU's can be configured in a system or in systems having common peripheral equipment. ~ach SAU is physically and logically independent of the other SAU; thus, no communication between SAUs is required. Although an SSP treats the SAUs as separate ph~Tsical entities, it treats them logically as one; in particular, an SSP can have no more than one SAU request outstanding. Conversely, an SAU will neither queue nor honor a subsequent SSP request until it has completed service c~f the current one.

One SAU supports the partitioning for up to one hundIed twenty eight (128) SPI and four (~) BCTS interfaces. Thus, support is provided for a maximum of 512 SPI's arld 16 BCTS's in the maxirnum configuration.

- 12 ~

Having a single component (since the SAUs are functionally one component, they are hereafter referred to as one) perform partitioning functions for peripheral subsystems in different applications requires that this component also be able to prevent an application's unauthori~ed removal, and subsequent use, of5 a subsystem being used in other applications. The SAU meets this requirement by providing the following protection.

(a) It enforces an application's exclusive use of a subsystem.
(b) It accepts the SSP-generated subsystem partitioning change commands only when an SSP issuing a command is associated with the application 1~ affected or is permitted ~o issue the command on behalf of the application affected.

In order to provide this protection and to make subseq-lent decisions, the SAU relies or. infc rmation that s provided to it during its initialization.The SAV receives and maintains the following information: cabling information, 15 SSP/application designation, IOP/application status, partitioning status, and exclusive use status.

1. CABLING INFORMATION
The cabling information identifies which IOP is connected to each port of each SPI and each channel of each BCTS. It also identifies those control 20 units (i.c., SPI's) which are connected as multi-access subsystems. This data is written into the SAU via an SSP during the SAU's initiali~ation.

2. SSP/~PPLICATION DESIqNATION
An SSP requesting subsystem partitioning changes must be assigned to the same application(s) whose subsystem partitioning status is affected.
25 Associated with each application is a SAU resident location specifying which SSP is assigned to the application. The assignment of SSP to an application can be made by any SSP via a command to the SAU; additionally, any SSP
can assign another SSP to an application. SSP assignments can be made whenever certain locks are not set. These locks are described in subsequent 30 paragraphs.

The association between SSP and application is logical only from an SAU
point of view; it is not necessarily physical frorm an application or system point of view. Specifically, thc SSP which perforrns the partitioning, testing, and maintenance functions on the ullits in a given application is generally assigned5 to the application from a S~U point of view. Ilowever, another SSP not physically associated with the application is not precluded from being assigned to the application from a SAU point of view.

3. IOP STATUS
Associated with each IOP is a SAU resident location indicating the status LO of the IOP. From a SAU viewpoint, an IOP is in one of the following states:
(a) It is assigned to Application 0, 1, ...., or 15.
(b) It is offline, i.e., not assigned to an application.
(c) It has not been assigned to any of the above states.

The assignment of IOP's to applications or offline status within t-ne SAU is 15 made via SSP commands to the SAU.

Any SSP, via an SSP command to the SAU, can assign an IOP in "unassigned"
state to offline status. In order to assign an IOP to an application, the following conditions must be met:
(a) The SSP making the request must be in the same application as that to which the IOP is being assigned.
(b) The IOP must be in offline status.
(c) All subsystem interfaces that are to this IOP and are controlled by the S~U must be disabled.

~n IOP that is cuIrently assigned to an application (from a SAU viewpoint) 25 can be placed in offline status via an SSP command provided the following are met:
(a) The SSP making the request must be in the same application as that from which the IOP is being removed.
(b) All subsystem interfaces that are to this IOP and are controlled by the SAU must be disabled.
4. SUBSYSTEM PARTITION~ s r'~s Associaied with each SPI and each subsystem string of each BC~
is SAU resident d~ta that indicates SPI port or 13CTS channel enable/disable status. This information is updated with each subsystem partitioning change
5 requested by an SSP and effected by the SAU.

When the SAU powers on, the partitioning status table indicates that all SPI and BCTS interfaces are disabled. Once the SAU has been initialized, the partitioning status table indicates current status of each interface.

5. EXCLUSIVE USE STATUS
Associated with each SPI is information indicating whether or not the subsystem is currently dedicated to (i.e., is being exclusively used by) a particular application. Note that exclusive use is applied to the subsystem, not an SPI only. Thus, due consideration must be made to multi-access subsystems, i.e., subsystems controlled by more than one control unit via 15 an SPI per control unit.

Enabling/disabling exclusive use is a function that is implernented and enforced within the SAU. In particular, the subsystem 's control unit(s) is (are) not cognizant of exclusive use; rather, the control of which SPI ports are enabled or disabled according to application is within the scope of the 20 SAU's functions. The enabling or disabling of exclusive use is initiated by a command from an SSP.
Recall that all the data described above is supplied by SSP commands and is mod;fied RS R result of SSP commands. It is necessary to protect this information from modification due to a faulty SSP, operator error, 25 or lack of application integrity. As the same time an objective is to minimize and possibly eliminate manual intervention in the event of SAIJ faults and subsequent recovery. How these objectives are met and how the data is protected are described in the subsequent paragraphs.

SAU locks are used to protect the cabling information and the SSP/~pplication 30 assignments. These locks, internal to the SAU, are set via commands and, when set, provide the protection desired. The locks are cleared (i.e., data modification is made possible) via SSP commands, manual actions, or SAU
internal actions.

There is one lock for each possible application, i.e., 16 locks. Their meaning is as follows:
(a) The S~U will allow cabling information to be written only if all locks are cleared;
~b) The SSP/application assignment for a particular application can be written only when the lock associated with that application is cleared .

A lock is set by any SSP. The SAU locks are cleared according to the following:
1. A command from the SSP assigned to a given application causes the corresponding lock to be cleared. With one exception, no other SSP
can cause the SAU lock to be cleared. The exception is described below.
2. All the SAU iocks are cleared when the SA J powers ~p.
3. Located on the SAU are four push-button, momentary switches, each uniquely associated with an SSP interface. The activation of a given switch causes the clearing of those SAU locks corresponding to applications to which the SSP associated with the switch is assigned.
~. Located on the S~U are two two-state switches called SAU Lock Access Switches. One switch is associated with SSP interfaces 0, 1 and the other, with SSP interfaces 2, 3. If a system's SSP has a Unit Available Signal then associated with each SAU interface to an SSP is an SSP Unit Available Signal interface. The SAU interprets an inactive unit available signal to be the same as not having a unit available signal line connected to the SAU. The SAU's interpreta-tion of the status of the switches and the unit available signals is described in Table 1.

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c" ~ ~ ~ In n~ Q rl ~1 r-l rl R ~ ) U I
pl rl ~ ~ tn h t) o ~ u~ ~ o ~n P
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D
The S~U locks described above protect the cabling information and SSP/Application assignments. The IOP status, partitioning status and exclusive use status are protected via the checks specified in later paragraphs.
These checks are summarized as follows:
(a) IOP status is changed only via commands from the SSP assigned to subject application.
tb) A change in partitioning status (i.e;, enabling/disabling interfaces) is a direct result of changing the ei~try in the partitioning status table, an action taken only as a result of certain checks:
1.) match of application associated with SSP and subject inter-face(s), 2.) current enable/disable status (BCTS only);
3.) not violating implications of exclusive use, if currently in ef fect .
15 (c) Exclusive use status is cl~anged only when 1 ) requested by the appropriate SSP
2.) a single application has interfaces enabled to the subsystem.

Fig. 4 illustrates how the above information is used when a subsystem partitioning change request is made by an SSP. In particular, the SAU can 20 make the following determinations:
(a) Whicll application's partitioning status is being affected;
(b) Whether the SSP making the request is assigned to the application affected;
(c) Whether exclusive use is in effect for a given subsystem, and, ie SO, to which application the subsystem is given exclusive use.

Having made these determinations, the SAU will either reject the request or effect the subsystem partitioning change requested.

Note that it is inherently the SSP's responsibility to check for potential partitioning violations prior to making a subsystem partitioning change request 30 to the SA~1. Those checks effectively protect the application with which the SSP is associated. The SAU, on the other hand, protects applications from SSP's not associated with those application.

~eferring again to ~ig. ~, a plurality of SSP's request access via interface 410. Note here that four SSP interfaces are shown, however, this is just îor purposes of explanatioll and as shown by the presel-t embodiment. Also note that the SSP's here are really command sources, howevcr, they are called SSP's in the present prcferred system. The interface nurnber is passed along connectioll 412 to the cabling information table 414 contained in the Random Access Memory. This cabling in~ormation from that table provides the IOP
number at output terminal 416. This IOP number is then used to determine the application designation 418 to provide the num~er o~ the applicat;on affected at terminal 420. The System Support Processor application designated is provided at connection 424 to indicate the SSP interface number assigned to that application. It must then be determined whether the SSP interface number designated corresponds to the SSP interface number ass;gned to that applica-tiOll. This comparison is done in block 426. If the numbers do not corres-ponà, a rejection signal is activated at terminal 428. 1~ they do, this is indicated by a signal at terminal 430. Next, it must be determined i~ a change can be made. This AS accomplished in bloek 432 using partitioning stPtus and exclusive use status information. If the change cannot be effected, a rejection signal is indicated at terminal 434. If the change can be made,-a signal so indicating this is presented at terminal 436.

Fig. 5 is a block diagram of the Subsystem Access IJnit (SAU) of the present invention as it might be used in a system.

The SAU 300 is shown with a plurality of command sources 500.
Indicated as one of these so~lrces is an SSP 502. It is under the ()rder of these command sources 500 that the SAU is controlled. They are coupled into the SAU 300 via the 250K baud, unbalanced, half-duplex serial interface means 514.
Likewise, a plurality of s~stem panel controls 520 are coupled into the SAU 300 via the system panel interfaces 512. Only one of these panels S22 is shown.

- The peripheral subsystem interfaces are illustrated at the bottom of the SAU 300. They are shown as the shared peripheral inter~aces 540 and the BCT'S
interfaces 560. Coupled to one of the SPI interfaces 540, via coupling 542, is an SPI word control unit 552.

An Input/Output Processor unit 112 is shown having a Word Channel interface 544 and two Block Multiplexer Channel interfaces 546. The l~ord Channel interface 544 is connected to the word control unit 552 having an SPI
553. One Block Multiplexer Channel interface is connected via 548 to a BCTS
310 with a remote interface 564 and the other, via 54~ to a Byte Control Unit 55n havirlg an SPI, 551.

A plurality o~ Byte Channel TransfeI Switch interfaces 560 has one of its interfaces connectcd to a BCTS remote interface 564 of the BCTS interface Ullit.310. A Byte Subsystem String 331 is coupIed via connection 331 to the BCTS
rem ote unit 310 .

'I`he basic functions of the Subsystem Access Vnit 300 of Figure S are to:
(1) Accept commands from up to four command sources 500 execute these commands and report their status.
(2) Maintain configuration tables in its local memory which tables include information concerning:
10 (a) The association between input/output processors (IOP's) and applications.
(b) The association between command sources (SSP's) and appli-cat ions .
(c) The connections between shared peripheral interface (SPI) ports 540 byte channel transfer switch (BCTS) strings 560 and IOP's 112.
(3) Make partitioning checks according to information contained in the configuration tables of the local store.
(4) Enforce exclusive use within an application.

The maximum SAU interfaces per SAU are:
(1) Four 2501~ Baud interfaces, 500.
(2) One hundred twenty eigllt shared peripheral interface ports, 540.
(3) Four system panels, 520.
~4) Four Unit Available Signal interfaces, 212 (shown in ~igure 6).
25 (5 Four Bytc CnaIlnel Transfer Switches, 560.

A basic SAU is used to provide centralized control of peripheral subsystem partitioning. Control and Data Flow be~ween these interfaces may be accomplished by many well known microprocessing systems, however, the one "~ used in the present description is the Zilo~ zsn.

The term "microcomputer" has been used to describe virtually every type of small computing device designed within the last few years. This term has been applied to evcrything from simple '~microprogrammed'~ controllers construc-ted out of TTL MSI up to low end minicomputers with a portion of the CPU
'~ ,e~ k.

constructed out of ~'TL LSI "bit slices." Tlowever, the major impact of the LSI
technology within the last few years has been with MOS LSI. With this technology, it is possible to fabricate complete and very powerful computer systems with only a few ~OS LSI components.

The major reason for MOS I.SI domination of the microcornputer market is the low cost of these few LSI components. ~or example, MOS I,SI micro-compllters have already replaced TTL logic in such applications as terminal controllers, peripheral device controllers, traffic signal controllers, point of sale terminals, intelligent terminals and test systems. In fact the MOS ~SI
microcomputer is finding its way into almost every product that now uses electronics and it is even replacing many mechanical systems such as weight scales and automobile controls.

Microcomputcr systelns a.e e~tremely simple to c~ truct using wcll krown components. Any such system consists of three parts:

(1) Microprocessor (2) Memory (3) Interface Circuits to peripheral devices The microprocessor is the heart of the system. Its function is to obtain instructions from the memory and perform the desired operations. The memory is used to contain instructions and in most cases data that is to be processed.
~or example, a typical instruction sequence may be to read data from a specific peripheral device,'store it in a location in memory, check the parity and write it out to another peripheral device. Various general purpose I/O device controllers, and a wide range of memory devices may be used from any source.
Thus, all required components can be connecte~ together in a very simple manner with virtually no other external logic. The user's effort then becomes primarily one of software development. That is, the user can concentrate on describing his problem and translating it into a series o~ instructions that can be loaded into the microcomputer memory.

The components suggested for use herein are the Zilog Z-80 microprocessor (CPU), the Z-80 Serial Input/Output interfaces (510) and the Z-80 Para~lel Input/Output Interfaces (PIO). Other similar systems may be substituted hercin without departing from the spirit of this invention.

Next, consider Fig. 6, which illustrates a functional block diagram of the sut)system acccss unit.

Ba~ically, thcle are two separate data paths in the SI~U300. F:irst, there is the bidirectional data bus 620. This bus allows the m;croprocessor 610 to communicate with the SIO 624, the PIO 612, the memory 622 and the I/O Read Selector 614. The processor 610 generates a 16 bit address and five control signals to supervise control of the data bus.

l'he five control signals are:
(~ ) Instruction E:etch Cycle Signal 10 (2) Memory operation Signal ~'~; The Input/Output Operation Signal (4) The Read Signal (5) The Write Signal Using the 16 bit address and given a combination of the five control 15 signals, the microprocessor 610 is able to read its program instructions frommemory. Tt can then perform the following instructions under program control.

It may:
(1) Read from or write illtO each SIO device.
(2) Read from or write into each PIO device.
(3) Read from or write into the memol y.
(~) Read data from the I/O Read Selector.

In an SIO instruction, an SIO 624 translates a serial message from one of the 250K baud interfaces 514 into a series of eight bit bytes that can be read by the microprocessor 610. Alternately, it translates the eight bit bytes from 25 the microprocessor 624 into serial ~bit by bit) data for transmission out upon one of the interfaces 514.

The Interface Read Selector 614 allows the microprocessor to read a number of bytes of information from the parallel input/output device 612 by doing an input/output operation.

In a parallcl input/output instruction, the PIO 612, which houses a pair (2) of eiuht bit parallel I/O ports, is used as an input or an output means. These I/O ports are used to communicate with the SPI and the BCTS interface registers.

The second data path is between the SPl and the BCTS registers and the PIO device. The data lines from the PIO's are used to:
(a) generate an eight bit interface address. These eight bits are used to select an ;nterface register for a read or a write operation.
(b) generate write data for the interface registers.
(c? generate a write control signal for the interface registers.
(d) provide a read path for data from the registers. These registers are read only as data assurance means, that is, merely as a corroboration that the correct data was transm itted.

Their particular states are maintained in the Subsystem Interface Table, shown in Fig. 17, of the memory 622.

Using these signals, the microprocessor is able to read from or write into t5 the interface registers via the PIO devices. The interface registers are used to - drive the SPI and the BCTS interfaces.

From a functional standpoint, the SP~ and the ~3CTS interface registers are really the only registers in the subsystem access unit (SAU). All resident information (tables) are stored in the RAM memory contained in the local store 20 622.

Fig. 7 is a detailed schematic block diagram of the Subsystem Access Unit 30n.

The microprocessors in the lower left hand corner of Fig. 7 are the main microprocessor 610 and a redundant or support microprocessor 710. They both 25 util]~e an eight bit bidirectional data bus 620 and a sixteen bit address bus. The two microprocessors 610, '~10 are run simultaneously to provide error checking.
The address generated by each microprocessor is compared on each read or write cycle. Data from each microprocessor is compared on a write cycle only. The microprocessors share ~he data bus during a read cycle. A data or address 30 miscompare will set a flip flop (not shown) which will in turn suspend the operation of the microprocessor and a fault indicator will be activated. This condition will continue until a reset of the hardware is accomplished.

'l`he microprocessors are used for system control, addressing and eight bits of clata handling. Monitoring of the address and data busses and somc external control oï the microprocessors is possible through the maintenance inter~ace 726.

In general, s~lpport ~or the microprocessors consists o~ a system clock generator and drivers, timing logic, bus drivers and transceivers, seria]
input/output and parallel input/output integrated circuits. The circuits, or chips as they are known in the art, which are used in the present embodiment are eommercially ~<nown as the Z-80A family manufactured by the ZILOG Corpor-ation.

Sixteen Tri-State buffered address lines are provided as the internal address bus. External aecess to this address bus is provided through the maintenance interface 726. The address hus buffers are set to the Tri-State condition when the microprocessor is in BUS-ACK mode. With 16 bits, the microprocessor is capable of addressing 65,136 memory locations, however, only the lower byte is used for I/O operations providing a maximum of 256 device addresses.

In addition, an 8 bit internal bidirectional data bus is provided for the microprocessors 610, 710. This bus 620 is buffered with Tri-State transceiver circuits. Access to the data bus is also provided through the maintenance interface 726. As with the address bus, the data bus transceivers are set to theTri-State corldition during BUS-ACK mode.

Adclressing of the RAM 712 and EPROM 714 memories is expressed in hexadecimal notation.

2~, The RAM adclress range is 4000 to 6FFF ~COOO to EFFF). This repeats at address location COOO since address bit 0 is not used in the RAM selection bits.

The EPROM address range is OOOO to 2FFF (8000 to AFF). This also repeats at address 8000 since address bit 0 is not used in the EPROM selection bits Any atteMpt to read a memory location which is not included in the above specified ranges will produce an FE data byte and will log a single bit memory error in the SBE counter 72~. The Subsystem Access Unit contains 12,288 thirteen bit words in random access memory (RAM) 712. Bits 00 to 07 represent 5 data, and bits 08 to 12 are the error correction code (ECC) which activates ECC
logic 618. The entire ram array is built from 39 units, each similar to those known in the industry as type 2147. This type 2147 static chip is a 4096 word by one bit Random Access Memory integrated circuit. This monolithic memory uses N channel silicon gate MOS technology, is TTL compatible and requires no 1~ clocl<s nor refreshi~g cycles to operate. Data is read out non-destructively and has the same polarity as the input data. Separate pins are provided for input and output data with the outputs being three or tri-state: High, Low and High Im pedance .

The SAU also contains 10,240 sixteen bit words of EPROM memory. Bits 15 0û to 07 represent data, bits 08 to 12 are the Error Correclion Code previously mentioned, and bits 13 to 15 are not used. The EPROM array is built with 10 units similar to those known in the industry as type 2~16 or 2716-1. The type 2716 memory unit is an N-channel MOS, 16, 38~} bit, Erasable Programmable Read Only Memory (EPROM). This monolithic device has an organization of 20 20a~8 words, each 8 bits long. The inputs and outputs are TTL compatible and the outputs are three state; High, Low, and High Impedance. The memory is non-volative until erased ~mder ultraviolet light.

The Error Correction Code Logic 618 is a single bit correction, double bit detection crror correcting network which is incorporated in the memory. This 25 network operates on both RAM and EPROM space. A 5-bit ECC code CO - C~
is generated from the data as shown in Table 2 below. Even parity is maintained, i.e., a check bit is set whenever an odd number of the data inputs associated with that check bit are set.

EIGHT D~TA: BITS

Do D1 D2 D3 D4 D5 D6 D7 CO X X X X X X
_ . _ __ _ _ ~ Cl X X X X X X
,~
__ ~ C2 X X X X X X
C~
~ C3 ~ X X X

h C4 X X X X
-- _ _ .

Wherl a single bit error is detected, the memory address and syndrome bits are loaded into Trap Registers 720, 722. A 4-bit single bit error counter 724 is then incremented. These trap registers and the error counter are read through an I/O port 516.

-. - 26 -The s~ndrome bits for single bit errors are given in Table 3 below:

Syndrome Bits Failing Data ~it SO Sl S2 S3 -1 O 1 0 1 l O : 1 1 0 1 2 - 1 1 0 1 0 0,~

1 0 0 0 0 Check bit O
O 1 0 0 0 Check bi-t 1 lS . O O 1 0 0 Check bit 2 O O O 1 Check bit 3 When a multiple bit memory error (MBE) is detected, the MBE FF is set.
This FF drives the multiple bit memory error LED on the SAU panel. Operation 2û of the microprocessors is suspended using its wait control line. The micro-processors will remain in this condition until the hardware is reset.

The Input/Output (I/O) port acldresses are assigned and shown in Table 4 below. Note that an I/O read operation to an address outside of this map will resuit in an FF16 data byte.

- 27 ~

H X ADDRESS CONTENTS
80 . . . . . Memory Address Trap 00-07O
81 . . . . . Memory Address Trap 08-15.
82 . . . . . Syndrome Trap 00-04, 3 unused bits.
83. . . . . SBE Counter 00-03r 2 unused bits, access FF00, 02.
84 . . . O . SSP Unit Available 00-03, SSP Intexface Enable 00-03.
85 ~ . . . . SPI Feature 01-03, BCTS Feature 01-02, UTS 4000 Feature 01.
88 . . . . . PATC~ word 00 bits 00-07.
8~ . . . . . PATCH word 01 bits 00-07O
8A . . . o . PATCH word 02 bits 00-07.
8B ........... PATCH word 03 bits 00-07.
8C . . . . . PATCH word 04 bits 00-07.
8D . . . . . PATCH word 05 bits 00-07.
8E ........... PATCH word 06 bits 00-07.
BF . . . . . PATCH word 07 bits 00-07.
90 . . . . . PIO 0 Port A Da-ta word bits 00-07.
91 . . ~ . . PIO 0 Port B Data word bits 00-07.
92 . . . . . PIO 0 Port A control word bits 00-07~
93 . . . . . PIO 0 Port B control word bits 00-07.
A0 . . . . . P~O i. Port A Data word bits 00-07.
A1 . . . ~ . PIO 1 Port B Data word bits 00-07.
A2 . . . ~ . PIO l Port A control word bits 00-07.
A3 . . . . . PIO 1 Port B control word bits 00-07.
B0 . . . . . SIO 0 Port A Data word bits 00-07.
Bl . . . . . SIO 0 Port B Data word bits 00-07.
B2 ........... SIO 0 Port A control word bits 00-07.
B3 . . . . . SIO 0 Port B control word bits 00-07.
C0 . . . . . SIO 1 Port A Data word bits 00-07.
Cl . . . . . SIO 1 Port B Data word bits 00-07.
C2 . . . . . SIO 1 Port A con-trol word bits 00~07.
C3 . . . . . SIO 1 Port B control word bits 00-07.
D0 . . ~ . . SIO 2 Port A Data word bits 00-07.
Dl . . . . . SIO 2 Port B Data word bits 00-07.
C2 . . . . . SIO 2 Port A control word bits 00-07~
D3 . . . . . SIO 2 Port B control word bits 00-07.
E0 . . . . . SIO 3 Port A Data word bits 00-07.
El . . . . . SIO 3 Port B Data word bits 00-07.
E2 O . . . . SIO 3 Port A control word bi.ts 00-07.
4U E3 . . . . . SI~ 3 Port B control word bits 00-07.

~ABLE 4 The Parallel Input/Output Interface 612, includes a first 764 and h second 766 PIO device. Each device is a parallel input/output chip known in the industry asa Z-80 PIO. Each Z-80 parallel I/O (PIO) circuit is a programmable, two part device which provides a TTL compatible interface betweell peripheral devices and5 the central Z-80 microprocessor (CPU)~ The Z-80 PIO utilizes M channel silicongate depletion load technology and is packaged in a 40 pin dual inline package (DIP). Major features of the Z-80 PIO include:
(a) Two independent 8 bit bidirectional peripheral interface ports with "handshake" data transfer contro~.
(b) Interrupt driven "handshakel' for fast response.
(c) Any one of four distinct modes of operation may be selected for a port, including:
1.) Byte output - 2.) Byte Input 3.) Byte bidirectional bus (available on "A" port only) 4.) Bit Control mode (d) Daisy chain interrupt logic included to provide for automatic interrupt vectoring without external logic.
(e) Eight outputs capable of driving Darlington transistors.
~f) All inputs and outputs are fully TTI, compatible.
(g) A single 5 volt supply and a single phase clock are used.

The PIO's 764, 766 are primarily used to control, to read, and to write the interface registers and the locking flip flops of the SAII.

- 2 9 _ ~ D ~ d~ ~

The following Table 5 illustrates the Parallel Input/Output signal usage:
PIO O Port A
Bit 00 (output) MBE DSBL~ This signal will hold the MBE FF clear.
Bit 01 (output) UNUSE D~
Bit 02 (output) UNUSED~
Bit 03 (output) UNUSEDo Bit 04-07 (output) SPI BCTS WR DATA 00~03~ These signals provide write data for the SPI and BCTS interface registers.
PIO O Port B
Bit 00-03 (output) SAU Lock Ctrl. 00-03. The rising edge of this signal will toggle the associated SAU Lock FF.
Bit 04-07 (output) SAU Lock FF Rd. These signals represent the state of the SAU Lock FFs.
PIO 1 Port A
Bit 00-07 (output) SPI BCTS ADRS 00-07~ These signals are used to address an interface register for a read or write operation~
SPI interface registers 0-127 - ADRS 00-7Fl BCTS interface registers 0-32 = Adrs 8o-gFl Configuration Display Lines BCTS
0-32 = Adrs AO-~F16.
Bit 00 (output) SPI mainframe control~ This signal will disable the SPI and BCTS
interface pulses and will enable all SPI control lines regardless of the state of the interface registersO
Bit 01 (output) 5PI BCTS WR Ctrl. The addressed interface register will be loaded with wr data from PIO O Port A on the rising edge of this signalO

~ f .P~,, Table 5 ~ continued Bit 02 (output) Pulse All Ctrl. This signal will send an interface pulse on all SPI
and BCTS interfaces.
Bit 03 ~output) Clear ECC ERRORS. This signal will hold the SBE counter and trap registers clear. -Bit 04-07 (input) SPI BCTS rd DATA 00-03. These signals represent the state of the addressed interface register or set of BCTS configura-tion lines.

There are four SIO interface chips 770, 774, 778 and 782 shown in Fig. 7.
These are similar to commercial units known in the industry as Z-80 SlO's. Each is a dual channel multifunctioll peripheral component des;gned to satisfy a widevariety of serial data communications required in microprocessing systems. Its 5 basic function is a seriAl to parallel, parallel to serial converter/controller.

It is capable of handling asynchronous and synchronous byte-oriented pro-tocols such as the IBM SDLC. It can be used to handle most any other serial protocol for applications other than data communications, (for example 250K
baud). It is an N-channel silicon-gate depletion-load device, with a 40 pin DIP. It 10 uses a single 5V supply and a single phase clock. The S10 includes two fully duplexed, independent channels.

The SIO control line usage is as follows:
1.) TXDA (OUTPUT) Transmit Data 2.) RTSA (OUTPUT) Transmitter and its clock enabled (Receiver is always enabled) 3.) RXCA (~NPUT) Receive Data 4.) RXCA (INPUT) Extracted Receive clock 5.) TXCA (INPUT) 250 KHZ Transmit clock CLOCK GENERA'rION
Timing of the clock signals is shown in Fig. 8. The ~ MHz square wave 8lO
is used by the Z,-80 microprocessors, SIO and PIO chips. The 4 Ml-lz phase clocks 812, 814 are used by control sequences. The 20 Ml~Iz signal 816 is used tv decode arld to clock receive data on the 250K band interfaces.

4 Mllz signals 810 are derived from an 8 MHz oscillator. The 20 MHz signal 816 is generated independently from the 4 MHz si~nals 810.

_NTROI, SEQUENCES__ Figs. 9, 10, 11, 12, 13 and 14 illustrate the five control sequences used in theSubsystem Access Unit of the present invention.

A. Reset Sequence This sequence shown in Fig. 9 is used to generate a two microsecond pulse 910 on the Reset FF. It is started on the trailing edge of a reset signal initiated by the power control or a switch on the SAU panel. The reset sequence follows through on signals 912, 914, 916, 918 and 920.

B. Memory Wait Sequences 1. Microprocessor M1 eyele from EPROM
This sequence illustrated in the timing diagram of Fig. 10, is used to generate two wait states on the M1 eycle to the EPROM. This sequenee is initiated by the control signals RD 1010 and MREQ 1û12 on the control lines of the mieroproeessor. The two wait states are shown as G and D at the top of the figure. ~t point A of signal 1010, i.e., the falling edge, the address is loaded in the hold register and the address miseompare FF is cloeked. At point B the rising edge, of signal 1014, the address trap register is loaded and the Single Bit Error eounter is ineremented if it is an SBE operation. However, if it is an MBE
operation, then the MBE FF is set.

2 . M ieroproeessor Read Cyele from EPROM
This is the seeond memory wa;t sequenee and it is used to generate one wait s.~te on a rcad cycl_ to EPRO'~ and is illustrated in the timing diagram of Fig. 11.

At point ~ of signal 1110, the address hold register is loaded and the address miscompare flipflop is eloeked by the falling edge of this microprocessor read signal.

At point B of signal 1112, the Error Correction Code cloclc signal, the address and syndrome trap registers are loaded and the SBE counter is ineremented if it is an SBE operation. However, the MBE FF is set if the ME~E
is on the rising edge of the ECC Clock signal 111t).

Point C of signal 1114, the 4 Mllz elock, shows the wait eycle.

C. Interface Pulse Sequence This sequence, shown in Fig. 12, is used to generate a partitioning pulse for the SPI 1210 and BCTS 1212 interfaces. The sequence is initiated by the SPI
BCTS Write control (WR) or Pulse all eontrol lines from PIO 1.

D. Manchester Encode Sequence This sequence shown in Fig. 13, is used to generate a transmit elock 30 signal 1310 for the SIO ehip and to encode the transmit data signal 1312 for the 250K baud interface. The encode 1314 and transmit elock 1310 signals are generated from the 4 MIIz clock using a counter. The falling edge of transmit eloek signal 1310 is used for the SIO transmit elock signal 1316.

3 3 ~ ;1 D ~ S -E. I\~ nchester Decode Sequence This sequence shown in E;ig. 14 generates a clock signal used by the SIO chip to receive the encoded data on the 25ûI~ baud interface. The sequence is run on the 20 MHz clock l~l0. It is started by a Receive Data transition of signal l412 and generates a rising edge on the Receiver Clock signal 1414 three m icroseconds later.

DATA REGISTERS AND FLIP-~LOP CIRCUITS

A. Shared Peripheral Interface (SPI) Register E ~ch SPI has a 4 bit (00 to 03) register used to drive the channel disable lines for the hlterface. The register is addressed written into and read from using the address data and write control signals from the PIO chips previously described.
B. Byte Charmel Transfer Switch (BCTS) Registers Each BCTS interface contains eight ~-bit (00 to 03) registers used to drive the switch enable lines. These registers are maintained in the same manner as the SPI Registers.

C. Address IIold Register This 16 bit (00 to 15) regisier is used to hold the value of the address bus. It is loaded at the beginning of each microprocessor cycle by the falling edge of the RD or V~R microprocessor control lines.

D. Trap Address Register This 16 bit (00 to 15) register is used to trap the memory address where the last single bit error was encountered. It is loaded with data from the Address ~lold Register on the rising edge of the read control line if a single bit error is present .
.

E. Syndrome Trap Register This 5 bit (00 to 04) register is used to trap the syndrome bits of the last single bit error encountered. It is clocked with the same signal as the Address Trap Register above.

F. Single Bit Error Counter A 4 bit (00-03) used to log the number of single bit errors encountered.
The count is incremented using the same clock as the trap registers. Upon reaching the maximum value of 15 the counter will hold this value until cleared.

G. Multiple Bit Error Flip flop (MBE FE;) This FF is set when a multiple bit memory error is detected. It is clocked using the rising edge of the microprocessor read control. When sct the FF
will drive the memory error I.ED and will suspend operation of the microprocessors using the wait control signal.

. Data Miscompare Flip-flop This FF is set when a miscompare is detected between the two microprocessor data busses during a write cycle. It is clocked on the rising edge of the microprocessor write control. When the FF is set it will activate the microprocessor fault LED and will suspend operation of the microprocessors usingthe wait control signal.

1. Address Miscompare Flip-flop This FF is set when a miscompare is detected between the two microprocessor address busses during a ready or a write cycle. It is clocked on the falling edge of the microprocessor read or write control. Here again, the fault LED will be activated and the operation of the microprocessors will be suspendedusing a wait control signal.

J. Memory ~equest Flip-flop This FF is used to define a memory request cycle. The state of the - 20 microprocessor memory request signal is loaded on every phase Ol.

K. Read ~lip-flops (RDFF) RD~F used to detect the rising edge of the microprocessor RD control.
The state of the RD signal is loaded every phase 0~.

L. SAU Lock Flip-flops These are four flipflops 00 to 03. They are used to driYe the SAU lock LED's and to detect a lock clear from the SAU panel. The state of the FF's will toggle on the rising edge of the SAU Lock Control signal from PIO 0 and will be cleared using the CLEAR SAU lock switches.

M. Transmit Inhibit Flip flop This FF is used to disable the transmit enable signal from an SIO. It is set when an overload on the 250K baud interface is sensed by the transceiver circuit. It will be cleared when the SIO drops its transmit enable signal. Note here that registers, counters and flip-flops are well known devices in the art and arc not considered to need any further description.

_NTER~CES
A. Shared Peripheral Interface (SPI) An SPI is shown in Figs. 6 and 7 as 540. It consists of five signals sent to peripheral subsystems equipped to allow remote control of a multiple I/O
5 chamlel interface. Signals consist of four channel disable lines and a partitioning pulse line. This partitioning pulse indicates to the SPI that it shall partition its channel interfaces according to the state of the signal on the channel disable lines.

Each interface consists of a îour bit interface register (144, 7~8 of Fig. 7) and a partitioning pulse source for driving the control line drivers 746,750.

All channel disable lines are set to the enable condition after the system has been powered up or after a reset operation. Each SPI feature contains thirty-two(32) interfaces.

1. Signal Description (a) Disable channel The active (high) level of the signal 1510, shown in ~ig. 15 causes the SPI to disable its channel interface.
(b) Partitioning change Signal 1512, shown in Fig. 15, causes the SPI to partition its channel interfaces according to the state of the enable lines.

20 B. Byte Channel Transîer Switch (BCTS) Interface Interfaces for up to four byte channel transfer switches are available to the SAU. These are shown generally as 560 in E;ig. 6 and Fig. 7. Each BCTS
feature in the SA11 accommodates two four channel by eight bit string switches.
Connection to a BCTS is through its remote operator interface. Switch enable 25 signals are generated in eight 4 bit interface registers 752, 7f;2. These registers are maintained in the same manner as the SPI registers previously described.
1. Signal Description (a) Switch enable lines Thirty-two (32) of' these signals 1610 of ~ig. 16 are provided on each interface to control switching combinations for up to a four by eight (4x8) switch. l'hese signals are considered active when they are low.

- 3fi ~

~b) Manual override lines The signals on these lines are illustrated as 1612 of Fig. 16.
It provides a demand strobe for the switch enable lines causing the switching of the subsystem to be performed.
(c) Switch Configuration display lines Thirty-two (32) of these signals display the current parti-tioning status of the BCTS. The signals are considered in the active condition when they are low.

C. 25~1~ Baud Interface 1~ More completely defined, this is a 250K baud, unbalanced, half duplexed serial interface. It is used for communications between the S~U and the System Support Processor (SSP) or other command source. It is connected via the SSP's ~vstem Interface Adapter (Sl~). Universal Data Linlc Control tUDLC) protocol is used and the interface data is Manchester encoded.

Two SIO ports are used for each interface to provide error checking.
This is shown generally in Fig. 6 by reference numeral 624. ~ig. 7 is more specific -~ and illustrates the detail of this blocl< at 728 to 742, and at 770 to 782. During a receive operation both SIO ports of 770a, 770b are programmed as receivers andthe received data is compared by both 770a anà 770b ports. During transmission, 20 a master SIO 770b is programmed for transmit and a redundant SIO 770a is programmed for receivc. The master SIO port 770b sends serial data which is encoded by encoder portion of 728 and driven by the interface transceiver circuit 736. This sarne data is returned by the receiver section of the transceiver 736,decoded by decoder portion of 728 and received by the redundant SIO por~ 770a 25 for verification.

D. System Panel Interface Interfaces to four system panels are contained in the SAU. Alarm and environmental signals are handled by the SAU's power control unit. A total of eight select SSP signals are available (two from each o~ the four interfaces). A30 patch is used to select one signal for each 250K baud interface.

1. Signal Description (a) Select SSP
A high level on this signal will enable the selected 250K
band interface in the SAU. Interfaces will be enabled when no system panel cables are converted.

~ 37 ~

(b) Power/Environment Check ~Vhen a power or environment fault is detected in the SAU
a low level signal will be sent to all four system panels.
This signal is cleared by the fault reset switch on the SAU
power control panel.
tc) Alarm When a power or environment fault is detected in the SAU, a low level signal will be sent to all four system panels. An alarm reset signal from a system panel will clear the alarm ~ signal only for that panel interface.
(d) Alarm Reset A low active pulse from a system panel that will clear the alarm signal from the SAU to that panel.

E. Maintenance Interface This is an interface to the microprocessor 610 of Fig. 7 address, data and control busses. It is accomplished through a pair of forty (a~o) pin connectors.

1. Signal Description (a) Data bus signals This is an internal eight bit (00 to 07) bidirectional data bus which is used by the microprocessor 610 of Eiig. 7 for data handlin~. 'rhe bus is buffered with tri-state transceiver circuits.
(b) ~ddress Bus signals This is an internal sixteen bit (00 to 15) bus used by the microprocessor 610 to address the memory and the I/O ports.
The bus is driven by tri-sta-te drivers.
(c) BUSAK, M1, RD, WR, IORQ, RESII, MREQ signals These are control signals from the microprocessor S1û. They are driven by tri-state drivers.
30 (d) Clock signals This is a ~ MHZ square wave which is used by the microprocessor (CPU), SI~ and PIO chips. It is driven by a Schottky circuit.
(e) BUSRQ signal A low level on this signal will request the m icrcprocessor ~10 to go to the busy, acknowledge mode (BUS/ACK). It uses a Schottky receiver.

(f) Wait Signal low level on this signal will cause the microprocessor ~l0 to generate the wait signals previously described. A Schottky receiver is used.
(g) Error Inhibit signal A low level signal here will override the fatal fault condition of a multiple bit memory error (MBE) or a microprocessor 610, 710 miscompare.``
~h) A five vol~ signal provides the logic power to interface 1a through these lines.

F. Unit Available Interface The SAU contains an interface for receiving four SSP Unit Available signals. Implementation of these signals by an SSP is optional. This signal, when active, will prevent any other SSP from talcing over partitioning functions 15 regardless of the state of the SAU Lock Access Switches.

PROGRAMMING
.
A. Instruction Set A list of commands and their format utilized by the Subsystem Access Unit (S~U) will llOW be describe~.

Tn order to accomplish partitioning of any system, it is necessary to be aware, not only of what is available in a computer room, but also how the various computer components are configured.

The computer room configuration tables contain physical parameters associated with this interconnection of system components. The data consists of:
25 (a) The association between IOP and application.
(b) The identification of up to four SPIs that can control access to a multiple access subsystem.
(c) The designation of one of four SSPs which can make subsystem partitioning changes on behalf of up to sixteen applications.
30 (d) The connection between each SPI port and one of sixteen IOPs.
(e) The connection between each BCTS subsystem string and up to four of sixteen IOPs.
(f) Tlle enabled/disabled status of each SPI port.

- 39 ~ P~

~g) The enabled/disabled status of up to four IOP channels assigned to each BCTS subsystem string.
(h~ The indication that a subsystem is sharable between applications or is dedicated to a single application.
(i) The indication to ensure that subsystem partitioning is requested only by the SSP designated to do so on behalf of that application.

All SSP requests to the SAU undergo a series of checks against data housed in the computer room configuration tables. Based on the results of these checks, the request is either executed or rejected with a status indica-ting why the request was rejected. The following tables comprise the computer room configuration tables.

Subsystem Interface Table _ _ _ _ _ _ _ The Subsystem Interface Table contains 160 locations, one for each SPI
and BCTS subsystem string. Each SPI is assigned a table location in the range of 00 to 7F (hexadecimal). Each BCTS string is assigned a location in the range of 80 to 9~ (hexadecimal). The format of the table is shown in Fig. 17.

A Multiple Access Subsystem (MAS) represents one word subsystem (one word peripheral control unit) containing one or more four-channel Shared Peripheral Interfaces (SPI). Thc MAS bit identifies up to four SPIs controlling access of up to sixteen channels to a single multiple access subsystem. The following rules govern the use of multiple access subsystems.

(a~ The MAS bit is used only for those subsystems connected to SPIs. It has no meaning for subsystem springs connected to a BCTS and must be ~ero in all BCTS table locations.
(b) ~lhen set, the MAS bit indicates that the SPI is part of a multiple SPI subsystem.
(c) When clear, the MAS bit i ndicates that the SPI is the first of a set of multiple SPIs if the MAS bit in the next location is set. If the MAS bit in the next location is clear, the SPI
~0 is the only one configured on the subsystem.
(d) Multiple SPI subsystems must be configured such that their Subsystern Configuration Table locations are conti~uous.
(c) The maximum number of multiple SPls is four, i.e., one table location with the MAS bit clear followed by three consecutive locations with the MAS bit set.

- ~ 0 ~ D ' ~

Associated with each SPI and eaeh subsystem string of eaeh BCTS is SAU
resident data that indicates SPI port or BCTS channel cnable/disable status.
This information is updated with each subsystem partitioning change requested by an SSP and effected by the SAU.

When the SAU powers on, the partitioning status table indicates that all SPI and BCTS interfaees are disabled. Once the SAU has been initialized, the partitioning status table indicates current status of eaeh interface. The SAU
initialization process is described later in this specifica~ion.

This partitioning control flag field specifies the partitioning status of each SPI
or BCTS subsystem string.

Partitioning Control Flag_ CO - SPI Subsystems - The CO bit eontrols IOP access to port zero of the SPI. When set, it indicates that port zero of the SPI
is enabled to the ehannel to which it is connected. When clear, it indicates that port zero of the SPI is disabled from the channel to which it is connected.

- BC'IS Subsystem Strings - The CO bit eontrols BCTS channel A aecess to the subsystem string. When set, it indicates that BCTS channel A is connected to the subsystem string. When elear, it indicates that channel A is disconneeted from the subsystem string.

Cl _ SPI Subsystems - The C1 bit eontrols IOP access to port one of the SPI. When set, it indicates that port one of the SPl is enabled to the ehannel to whieh it is eonnected. When clear, it indicates that port one of the SPI is disabled from the-channel to which it is connected.

- BCTS Subsystem Strings - The C1 bit eontrols BCTS channel B
aeeess to the subsystem string. When set, it indieates that BCTS ehannel B is conneeted to the subsystem string. When elear, it indicates that ehannel B is disconnected from the subsystem string.

C2 - SPI Subsystems - 'I`he C2 bit controls IOP access to port two of the SPI. When set, it indicates that port two of the SPI is enabled to the channel to which it is connected. When clear, it indicates that port two of the SPI is disabled from the - 5 channel to which it is connected.

- BCTS Subsystem Strings - The C2 bit controlls BCTS channel C access to the subsystem string. When set, it i ndicates that BCTS channel C is connected to the subsystem string. When clear, it indicates that channel C is disconnected from the subsystem string.

(~,3 - SPI Subsyster,~s - The C3 bit controls IOP access to port three of the SPI. When set, it indicates that port tl)ree Oe the SPI
is enabled to the channel to which it is connected. When clear, it indicates that port three of the SPI is disabled from the channel to which it is connected.

- BC'I`S Subsystem Strings - The C3 bit controls BCTS channel Daccess to the subsystem string. When set, it indicates that BCTS channel D is connected to the subsystem string. When clear, it indicates that channel D is disconnected from the subsystem string.

EU - The Exclusive IJse bit controls subsystem availability to multiple applications. When set, it indicates that the sub-system is accessible to one application. When clear, it indicates that the subsystem is accessible to more than one application.

- The EU bit in the first location of a set of SPIs in a multiple~
access subsystem establishes Exclusive Use for all SPls connected to the subsystem. When E2cclusive Use is indicated, the SAU ensures that IOPs enabled to the subsystem all reside 3n in the same application.

- 42 ~ a.~

Tllis subsystem IOP number field specifies the IOP number associated with each of the four ports/channels of a SPI or BCTS. It also provides an indicationthat rnultiple SPls control access to the subsystem.
Sut.system 5 IOP Numb_ CO IOP Number- This field contains the number of the IOP connected to port zero of the SP~or channel A of the BCTS.

C1 IOP Number- The field contains the number of the IOP connected to port one of the SPI or channel B of the BCTS.

lU (:2 IOP Number- This field contains the number of the IOP connected to port two of the SPI or channel C of the BCTS.

C3 IOP Number- This field contains the number of the IOP connected to port three of the SPI or channel D of the BCTS.

- U Within each IOP number field is an Unassigned bit. This bit, when set, indicates that no IOP is connected to the SPI port or BCTS channel associated with this ficld.

SSP_pplication Table_ ____ - The SSP application table, one entry of which is shown in Fig. 18, contains 16 locations, one for each application. Each application must be assigned one SSP to make partitioning changes affecting the application. Only the SSP
designated to a particular application is allowed to change that application's partitioning. This designation can be altered by any SSP; however, the application whose SSP number is being changed must not be in SAU Lock Mode.

SSP's are assigned as follows:
L When set, the SAU Lock Mode bit prevents the Subsystem IOP
Number portion of the Subsystem Interface Table from being altered application. This bit can only be set by a command from the SSP whose number is present in bits 6-7. This bit can be cleared by a command from the SSP whose number is in 3~ bits 6~7; manually via the CLEAR SAU LOCiC 0,1,2,3 operator controls; and, in the event of a disabled SSP with redundancy specified, via a command from the redundant SSP. (A disabled - 43 ~ kJ~

SSP with reclundancy specified is defined as an SSP which has deactivated its Vnit Available signal and whose associated SAU LOCK ACCESS sl,vitch is in the DUAL position.

U When set, the Unassigned bit indicates that no SSP is assigned to make partitioning changes on behalf of the application. All partitioning requests affecting the application will be rejected.
The V bit is set by power-up initialization and an SAU Reset command. When the U bit is clear, bits two and three specify the SSP assigned to make partitioning changes in the applica-t oll.

SSP Number This value specifies the SSP number designated to make partitioning changes on behalf of the application. The possible values are:
00 Speci~ies that this SSP is connected to the SSP/SAU
interface 0 01 Specifies that this SSP is connected to the SSP/SAU
inl erface 10 Specifies that this SSP is connected to the SSP/SAU
interface 2 2û ll Specifies that this SSP is connected to the SSP/SAU
inlerface 3 IOP State Table ____ .

Associated with each IOP is a SAU resident location containing the information shown in Fig. 19 indicating the status of the IOP. From an SAU
viewpoint, an IOP is in one of the following states:
- (a) It is assigned to Application 0~ 1, ..., or 15.
~b) It is offline, i.e., not assigned to an application.
(c) It has not been assigned to any of the above states.

The assignment of IOPs to application or offline status within the SAU is made via SSP commands to the SAU. Note that assigning an IOP to an application at the IOP or system level is an action independent of assigning an IOP to an application at the SAU level. The first action causes the IOP to respond to the SSP assigned to the same application. The second action updates SAU-resident information used for SAU-internal checks~
, ~ Then the S~U powers up, the SAU considers an IOP to be neither in the offline state nor assigned to an application i.c., the IOP is in the unassigned state, defined above. After an IOP has been assigned to offline status or to an application, it is not re-assigned to the "unassigned" state without SAU re-5 initi~ lization.

Any SSP, via an SSP command t~ the SAU, can assign an IOP in "unassigned" state to offline status. In order to assfgn an IOP to an application, the following conditions must be met:
(l) The SSP making the request must be in the same application as that to which the IOP is being assigned.
(b) The IOP must be in offline status.
(c) All subsystem interfaces that are to this IOP and are controlled by the SAU must be disabl?d.

An IOP that is currently assigned to an application (from an SAU
viewpoint) can be placed in offline status via an SSP command under the following conditions:
(a) The SSP making the request must be in the same application as that from which the IOP is being removed.
(b) All subsystem interfaces that are to this IOP and are controllcd by the SAU rnust be disabled.

The IOP State Table an entry of which is shown in Fig. 19 contains 16 locations, one for each IOP. Each location contains a 5-bit value which reflectsthe partitioning status of an IOP. The following values are assigned:
State Value IOP Partitioning Status OOCOO Assigned to application zer~
00001 Assigned to application one 00010 Assigned to application two O(1LI11 Assigned to application three 00100 Assigned to application four 00101 Assigned to application five 00110 Assigned to application six OC111 Assigned to application seven 01000 Assigned to application eight State Value IOP Partitioning Status _ 01001 Assigned to application nine 010lO Assigned to application ten 01011 Assigned to application 11 01100 Assigned to application twelve 01101 Assigned to application thirteen 01110 Assigned to application fourteen 0~1ll Assigned to application fifteen 1 0000 Offline l~ltl01 to 11110 Reserved 11111 Never assigned to an application SSP History Table The informntion in the SSP ~Iistory Table, an ertry of which is shown in Fig. 2t~, is provided to aid in SAU initialization and recovery. The SSP
15 History Table has four entries, one for each SSP. Only the SSP assigned to anentry may write or read that entry. The bit assignments of the SSP ~Iistory flags are as îollows:

SAIJ Lock This bit is set by the SAU whenever the SSP for this table entry is assigned to an application whicl~
is in SAU Lock Mode.
Microcode This bit is set by the SSP which loads and Lo!~ded verifies the SAU control store. The setting of this bit by an SSP will cause it to be set for all table entries.
IOP Numbers This bit is set by the SSP which loads and Loaded verifies the IOP Number portion of the Subsystern Interface Table. The setting of this bit by an SSP
causes it to be set for all table entries.
SSP Nurnbers This bit is set by an SSP after it gains control Written of its applications by making assignments in the SSP Application Table.
Add/Remove This bit is set by an SSP after il: performs Subsystems the appropriate Add Subsystem and Remove Complete Subsystems commands in order to initialize the Subsystem Interface Table to a state which reflects the current partitioning of control units and subsystem strings within this SSR's control .

No SSP This bit is set by the SAU if it receives no Act;on Taken acknowledge to power-on status. The bit is set by an SSP in the event of an error or failure to initiate its responsibile areas within the SAU.

Associated with each SPI is information indicating whether or not the subsystem is currently dedicated to (i.e., is being exclusively used by) a particular application. Note that exclusive use is applied to the subsystem, notan SPI only. Thus, due consideration must be made to dual access subsystems, i.e., subsystems controlled by two control units via an SPI per control unit.

Enabling/disabling exclusive use is a function that is implemented and enforeed within the SAU. In particular, the subsystem's control unit(s3 is (are)not cognizant of exclusive use; rather, the control ol` which SPI ports are enabled or disabled according to application is within the scope of the SAU's functions .

The enabling or disabling of exclusive use is initiated by a command word from an SSP. This command is an integral part of an SPI port enable/disable command (referred to later as an add subsystem or remove subsystem c(;lr! m and).

SAU Operations __ Command Word SAU operations are controlled by a a~-byte command word in the format shown in Fig. 21.
Command - Contains the 8-bit code which identifies the operation.
Operand - Contains data necessary for the e2cecution of the command.
Address - Contains the address where the command will be executed.

The commands as sho~vn in Table No. 6 are executed by the SAU:
Command Code 0 1 2 3 'l 5 6 7 Add Subsystem 0 0 0 0 0 1 0 1 516 Remove Subsystem 0 0 0 1 0 1 0 1 1516 Write Subsystem IOP Number 0 0 0 0 1 0 0 1 916 Read Subsystem Interface Table 0 0 0 0 1 0 1 ~ ~16 Write IOP State 0 0 1 1 0 0 0 1 3116 Read IOP State 0 0 1 1 0 0 1 0 3216 10 Write SSP Number 0 0 1 0 0 0 0 1 2116 Read SSP Number 0 0 1 0 0 0 1 2216 Write Control Store 1 0 ~0 0 0 0 0 1 8116 :E~ead Control Store 1 0 0 0 0 0 1 0 8216 SAU Reserve 0 0 0 1 0 0 1 1 1316 15 SAU Release 0 0 1 0 0 0 1 1 231~
SAU Reset 1 1 1 1 1 1 1 1 FF16 - Read ID ~Vord O 0 0 0 0 1 1 1 0 OE16 Read ID lVord 1 0 0 0 1 0 0 1 0 1216 Read SPI 0 O 1 0 1 û 1 0 2A16 20 Read BCTS Interface 0 0 1 1 10 1 3A16 Set Test Mode 0 0 0 1 0 1 1 1 1716 Clear Test Mode 0 0 1 0 0 1 1 1 271~
Set SAU Lock 0 1 1 0 0 1 1 1 6716 Clear SAU Lock 1 0 0 0 0 1 1 1 8716 25 Write SSP llistory 1 0 0 1 0 0 ~ 9116 Read SSP History 1 0 0 1 0 0 1 0 9216 The SAU resident data is used by the SAU to cnsure SSE' and application integrity when partitioning status modifications are requested. These modifica-tions occur during the SAU's initialization and may also occur during a production period or between production periods. In particular, the changes are 5 initiated as a result of any of the following:

(a) The S~U is being initialized, and the partitioning status table and corresponding st~tus are being changed to indicate current status.

(b) A subsystem is to be added to and/or removed from an application.

(c) An application's mainframe composition (i.e., IPs, MSUs, IOPs) is being changed as a result of the beginning or end of a particular production period.

Three basic SSP commands are used to carry out the changes: add subsystem, remove subsystem, and change IOP status. Depending on the action (described above) initiated, one or a series of these commands are made.

The SAU checl~s made before effecting the changes requested are described below.

Add Subsystem The Add Subsystem command word is shown in E;ig. 22.
Command G516 Operand Specifies the SPI port, if any, or BCTS channel to be enabled and whether subsystem Exclusive Use is to be enabled.
Table Address Contains the 8~bit Subsystem lnterface Table address assigned to the subsystem.

The Add Subsystern command loads one-bits from positions 3-7 of the operand field into the partitioning control field of the addressed Subsystem Interface Table location. The subsystem is repartitioned as specified by the command. SPI ports and BCTS channels other than those specifies3 by one-bits from positions 3-7 of byte 1 are unaffected.

~ 9 _ ~ . t The followirig errors cause a Data Check status condition:
(a~ The E~clusve Use bit is already set in the table, and the subsystem is already enabled to IOPs that are in different applications.
(b) The subsystem is already enabled to an IOP that has never been partitioned to an application, assigned to a reserved state, or offline.

The follo~ing errors cause a Partitioning Checl~ status condition:
(a) The request specifies that more than one channel is to be enabled to a BCTS subsystem string.
(b) The IOP to which the subsystem is to be enabled has never been partitioned or is assigned to an offline state.
(c3 The requesting SSP is not authorized to make partitioning changes on behalf of the applications associated with the IOPs to which the subsystern is to be enabled.
(d) The command or table specifies Exclusive Use and the resulting partitioning state will cause the subsystem to be enabled to IOPs in different applications.
(e) The table address specifies a subsystem whose feature is not installed .

The command will be rejected if specified table address is out of range.

Re_ove _bsystem The Remove Subsystem command word is illustrated in Fig. 23.
Command l516 Operand Specifies the SPI port, if any, or BCTS channel to be disabled and whether s~lbsystem Exclusive Use is to be disabled.
Table ~Address Contains the 8-bit Subsystem Interface Table address assigned to the subsystem.

The Remove Subsystem command loads ~ero-bits frorn positions 3-7 of the 3n operand field into the partitioning control field of the addressed table location.
The subsystem is repartitioned as specified by the command. SPI ports and BC'IS channels other than those specified by zero-bits from positions 3-7 of byte 1 are unaifected.

5 0 ~ D ~

The following errors cause a Data Check status condition:
(a) The Exclusive Use bit is set and the subsystem is enabled to I9Ps in different applications.
(b) The subsystem is enabled to an IOP that has never been partitioned to an application, assigned to a reserved state, or is offline.

The following errors causes a Partitioning Check status condition:
(a) The requesting SSP is not authorized to make partitioning changes on behalf of the applications associated with the IOPs from which the subsystem is to be disabled.
(b) The table address specifies a subsystem whose feature is not installed.

The command will be rejected if the specified table address is out of range.

~Yrite System lOP number -~ 15 The Write System IOP number is shown in Fig. 24.
Cornmand 916 The Write Subsystem IOP Number command performs a block write of all t60 locations in the Subsystem Interface table starting at location zero.

Each table location requires five bytes of data as shown in the Fig. 25 20 format. The partitioningr control flags field is set to zero.

The command will be rejected if any of the 16 applications are in the SAU Lock Mode.

The following error causes a Data Check status condition:
(a) The MAS bit is set for the first location of the Subsystem Interface Table.
(b) ~s a result of the execution of the command, the MAS bit is set in more than three consecutive table locations.
~c) As a result of the execution of the command, the MAS bit is set for a BCTS subsystem string.

Read Subsystem Interface Table _ _ _ _ _ _ _ _ A Reaù Subsystem Interface table entry is shown in Fig. 26. The OA16 in Byte 0 is given in hexadecimal binary co~e.

Count This field contains the number of consecutive entries to return to the SSP, beginning with the entry specified in byte 2. The maximum allowable count is 2816-Table Address This field contains the starting address of a block of Subsystem Interface Table entries which will be returned to the requesting SSP.

The five bytes of data shown in Fig. 27 for each specified entry are returned to requesting 3SP. This comm~,ld will be iejected if it specifies a table address which is out of range.

Write IOP State This command is îllustrated in Fig. 28.

IOP State This field contains the partitioning state to be written into the IOP State Table location specified by the IOP number.
IOP Number This field contains the IOP number whose state is ~,0 changing.

The following errors cause a Partitioning Check status condition:
(clJ The requesting SSP is not authorized to make partitioning changes on behalf of the application currently assigned to the IOP.
(b) The requesting SSP is not authorized to make partitioning changes on behalf of the application specified in the IOP State field in the command.
(c) The addressed IOP is currently assigned to an application, and the command specifies an IOP state other than offline.
(d) The addressed IOP is currently assigned to offline, and the command specifies an IOP state other than an application.
(e) The addressed IOP is currently enabled to any SPI port or BCTS
subsystem string.

Read IOP State This command is shown in Fig. 29.
Commalld 3216 Count This field contains the number of consecutive lOP's whose states will be returned, beginning with IOP specified in Byte 2.
IC)P Number This field specifies first of a block of consecutive IOP numbers whose states will be returned to the requesting SSP.

~11rite SSP Number The Write SSP Number command is shown in Fig. 30.

Command 21 16 - SSP Number This field contains the number of the SSP to be assigned to make partitioning changes on behalf of the addressed application.
' 1`he SSP number assignments are shown below:
SSP Number SSP to be Asslgned Application This field specifies the application whose SSP
assignmen-t is changing.

U=0 Indicates that positions 6 and 7 of byte 1 spec-ify the SSP number to be assigned to make subsystem partitioning changes on behalf of the addressed application.
U=1 Indicates that the addressed application is to be unassigned to any SSP.

'f`he Write SSP Number cornmand will be rejected if the specified application is in SAU Lock mode.

- 53 ~ D~3 Read SSP ~Jumber The ~ead SSP Number command is shown in Fig. 31.

Command 2216 Count This field contains the number of consecutive applications whose SSP assignments will be returned, beginning with the application specified in byte 2.
Application This field specifies the first of a block of con-secutive applications whose SSP assignments will be returned to the requesting SSP.

For each specified application a byte of data is returned to the requesting SSP. This Byte 0 includes zeroes in bits 0-3. The SSP number in bits 6 and 7. An L (locked) in bit 4 and a U (unavailable) in bit 5. The command is rejected if the command specifies a table address which is out of range.
.
Write Control Store This command 8116 is illustrated in Fig. 32.

Count This field contains the number of control store locations to be written, beginning at the location specified by bytes 2 and 3.
Control Store These fields specify the first of a block of Address control store addresses to be written.

A write of control store is performed, beginning at the specified address. The number of bytes to be written is specified by the count field and is limited to 256 bytes per command.

The Load Control Storage command is rejected if any of the 16 applications are in SAU Lock Mode or if the command specified an address which is out of range.

Read Control Store This command 8216 is shown in Fig. 33.

Command 8116 Count This field contains the number of control store locations to be returned, beginning with the location speci~ied by bytes 2 and 3.
Control Store These fields speci~y the first of a block of Address control store addresses to be returned to the requesting SSP.
-A read of control store is performed, beginning at the specified address. Thenumber of bytes to be read is specified by the count field. A read of control 10 store is limited to 256 bytes per command.

The command is rejected if the command specifies a control store address which is out of range.

SAIJ Reserve The SAU Reserve command of Fig. 3~1 locks the SAU onto the SSP
interface that received the command. Other SSPs are denied access to the SAU until the r eserving SSP releases the interface or until an SAU Reset eommand is received from any SSP interface. A busy indication is returned for all commands (except SAU RESET) from other SSPs.

SAU Release ~0 The SAU Release cormmancl of F'ig. 35 unlocks the S~U from an SSP
interface. 1`he release command must be received froln the same SSP that caused the reserve condition. A reserve condition results from receipt of a Reserve command or the sending of Unit Check Status.

SAU Reset -~5 The SAU Reset command FF16 shovvn in Fig. 36 clears any lock condition, terminates all operations in progress and causes the SAU to perform a power-on confidence sequence. The command is always accepted, i.e., it cannot receive a busy response. The SAU E~eset command does not necessarily result in an orderly halt of operations in progress and clears all pending status 30 conditions. Reset is intended to recover the SAU from an abnormal state or operation. Its use should be limited to this function.

l~ead ID word 0 _ _ _ This command OE16 is shown in Fig. 37. In response to the Read ID
word 0 command, the SAU sends five bytes of data to the requesting SSP. The type number is in byte 0, byte 1 and four bits of byte 2. The revision level is in bits 4-7 of byte 2 and bits 0-3 of byte 3. Zeroes are contained in bits 4-7 of byte 3 as well as in all of byte 4. The type number is the binary value of the six digit SAU type number; while the revision level is the binary value of the SAU hardware revision level. The read ID word 0 command is accepted by the SAU regardless of whether or not Control Store is loaded or the tables are initializcd.

Read ID word I
The command 1216 is shown in Fig. 38. In response to this command, the S ~11 sends five 1 ytes (40 bits) cf data to the request;ng SSP. If a bit ispresent in bit 1 of byte 0, the installation of a temporary hardware change in the unit is indicated. The remaining 6 bits of byte 0, all 8 bits of byte 1 and bits 16 and 17 of byte 2 contain the binary value of the Unit Serial number.

The presence of a bit in bit location 18 of byte 2 indicates that the SAU
controls 64 SPI's. If a bit is also present in bit 19, then the SAU controls g6 SPI's. Finally, if a bit is also present in bit 20, theIl the SAU controls 128 SPI's. Similarly, a bit presence in bit 21 indicates that the SAU controls 16 subsystem strings while the further bit presence in bit 22 indicales control by the SAU o~ 32 subsystem strings. Bit presence at bit 24 indicates a system control interface expansion whcrein the SAU contains four SSP interfaces.
'~'he SSP number of the unit requesting this ID word is contained in the two bit field of bits 32 and 33, while bits 34 and 35 provide the field which contains the unit number of the SAU. Values 0,1,2 and 3 can be selected for this number. All other bit values of the 40 bits are ~ero.

_ad SPI
This command 2A16 is shown in Fig. 39.

Command This field contains the number of consecutive SAU
Partitioning Registers to be read, beginning with the SPI specified in byte 2.

Table Address This field specifies the first of a block of con-secutively numbered SPIs. The command performs a read of the specified SAU Partitioning Registers for the SPIs specified by bytes 1 and 2. One byte of data for each specified SPI i3 sent to the SSP
in the following manner.
Each byte includes a 4-bit field (bits 4-7) denoted an SPI port enable field. This field indicates the state of the SAU Partitioning Register for the addressed SPI. ~ Partitioning Check is generated if the Table Address specifies an SPI whose feature is not installed. The command is rejected if the command specified an SPI which is ou~side of the range of addresses assigned to SPIs.

20 Read BCTS In e face This command 3A16 is pictured in Fig. ~0.

Count This field contains the number of consecutive SAIl Partitioning Registers and receivers for BCTS
subsystem strings to be read beginning with the BCTS subsystem string specified in byte 2.

Table Address This field specifies the first of a block of cons-ecutively numbered BCTS subsystem strings.

This command performs a read of the specified SAU Partitioning Registers and receivers îor the BCTS subsystem strings specified by bytes 1 and 2. One byte of data for each specified 57~

BCTS is sent to the SSP in the followin~ format.
A four bit BCTS challnel connected field (bits 0-3) indicates BCTS confirmation of the connection between the addressed subsystem string and the channel selected by the BCTS Channel Enabled field. This latter field is also four bits (4-7) and indicates the state of the SAU Partitioning Register for the addressed BCTS subsystem string.

A Partitioning Check status condition is generated if neither of the BCTS expansion features are installed or if the command specifies a subsystem string connected to a BCTS whose feature is not installed. The command is rejected if it specifies a BCTS subsystem string which is outside of the range of addresses assigned to BCTS subsystem strings.

Set Test Mode This command 1716 is shown in Fig. 41. The Set Test mode command places all SPI port drivers in the enabled state and disables the partitioning change control line to each SPI and BCTS. The command is rejected if any application is in SAU Lock Mode.

Clear Test Mode Fig. 42 illustrates the Clear Test Mode command 2716. '~he Cle~r Test Mode command removes the enable to all SPI port drivers and partitions each SPI and BCTS subsystem string according to the current state of the partitioning registers. The command is rejected if any application is in the SAU Lock Mode.

Set SAU Lock This command 6716 is pictured in Fig. 43.
Application - This field specifies the application which is to be placed in SAU Lock Mode. This command will place the speeified application in SAU
Lock Mode. SAU Lock Mode prevents any SSP from changing the SSP
assignment for the associated application and prevents the Write Subsystem IOP Number command and Test Mode commands from being executed.
This command is rejected if the requesting SSP is not the same SSP assigned to the specified application or if the specified application is unassigned to any SSP.

- 58 ~ 3 ~

Clear_AU Lock This command 8716 is ilhlstrated in Fig. a4.
Application - This field specifies the application which is to be taken out of SAU Lock Mode. Th;s command is rejected if the specified application is 5 not assigned to any SSP or if the requesting SSP is not the same SSP assigned to the speci~ied application.

_rite SSP History This command 9116 is shown in Fi~g. 45.

History Flags Specifies which flags are to be set for the specified SSP History Table Entry. For a description of each of the flags; see Section 2 2.
Table Address Contains the number of the SSP History Table entry to be written into.

The Write SSP llistory command loads one-bits from byte 1 into the SSP
~listory Table location specified by byte 2.

The following errors cause the command to be rejected:
(a) An attempt to set the Control Store Loaded bit when the control store has not been fully written.
(b) An attempt to set the IOP Nllmbers Loaded bit when the IOP
Number portion of the Subsystem Interface Table has not been written.
(c) The specified table address is out of range.

Read SSP ~listory Fig. 46 illustrates commalld 9216-Table Address Contains the number of the SSP Histol y Table entry to be rehlrned to the request-ing SSP.

The Read SSP History command returns the SSP History Table entry as specified by byte 2. One byte of data is returned which indicates the binary value of the history flags. For a description of each of the flags~ see Fig. 2û.'~he command will be rejected if the specified table address is out of range.

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S'rATUS PRESENTATIONS

The subsystem access unit (SAU) presents status information to the System Support Processor (SSP) in the system portion of its message.
There are four possible status indications which the SAU can send to the SSP.
1. Data Assurance Clear - indicates successful completion of a specified command at the SAU.
2. Data Assurance Fail - indicates that the SAU deteeted an unusual condition that is detailed by information contained in the sense bytes. This indication of a programming or equipment error precludes execution of the command.
3. SUP Message Waiting - indicates the SAU has detected an unusual condition not related to a command received by an SSP. This ~condition is detailed by information contained in the sense bytes.
4. SUP Receive Not Ready - indicates the SAU is unable to accept a command due to the exis~ence of a reserve condition on one of the other SSP interfaces.

SENSE DATA

Sense data is transferred to the SSP, providing de-tailed information concernirlg unusual conditions detected by the SAU. There are seven sense 20 bytes which will now be dcscribed.

E'irst Se lse Byte The bits of the first sense byte as assigned as follows:
Sense Bit Dcscription 0 Command Reject 1 Not used 2 Not used 3 Equipment check 4 Data Check Not used
6 Length Check
7 Partitioning Check - 6 0 ~

Command Reject. - Command l~eject indicates that the SAU has detected a programming error. A command was received that the SAU was not designed to execute or could not execute due to the state of the S~U Lock indicators.

Equipment Check. Tlle Equipment Check sense bit indicates dctection of an internal error. This includes checks on register-to-register data transfer.
Detection of Equipment Check stops data transmission and terminates the operation prematurely. On write operations, this error may have caused invalid subsystem partition;ng or invalid entries in the Subsystem Interface Table. The second and third sense bytes identify the failing area.

~ata Check. Data Check indicates the detection of illegal state in the Subsystem Interface Table.

I,ength Check. The Length Checlc bit is returned if any of the following conditions are true: - A write command from an SSP has provided too little data or more data than is required.

Partitioning Check. - Partitioning Check indicates that the command attempted an operation that is currently protected by the SAU, e.g., the command requested exclusive use of a subsystem whose S!Pi ports were partitioned to IOPs in more than one application. The command is not executed.

Second Sense Byte _ _ _ _ _ ___ The second sense byte is an extension of the first. The foliowing Table 7 defines each bit which is dependent upon the condition specified by the first sense byte. (see page 61) Command Reject Table Address Out of Range - The command, received from the SSP~
specified an address which is beyond the maximum allowable address for the table.

SAU Lock Bit Set - The SAU is unable to execu-te the command due to an application in SAU Lock Mode.

First Sense Byte Specifies:
__ .. .
Bit Comnand Equipment Check Data Check Length Partitioning Check No. Reject Check _ _ . .......................... ... __ Table ~d- Correctable MAS Entries Write Subsystem Not O dress ~ut Memory Error Greater Than Error Configured of Range 4 _ . _ . ~
l SAU Lock Uncorxectable MAS Bit Set Read Undefined Bit Set Memory Error for BCTS Error . . _ .......... .. _ ,, ,_ 2 Unautho~ Registe~ MAS Bit Set Unde- Unauthorized SSP
rized SSP Error for First fined Table ~`ntry _ . _ .
3 Applica- PIO Error IOP State Unde- IOP State Error ~ion un- Error fined assigned to an SSP
. . .. _ . _ _ - _ . . . .
4 Control SIO Error BCTS Enabled Unde- BCTS Enabled to Store Not to More Than fined More Than One IOP
Loaded One IOP
~ ___ ~ _____ _ . .
5 Unrecog- Undefined Exclusive U~de- Exclusive Use nized Use Viola- fined Violation CoF~mand tion _ ___ ___ _ __ __ ..
6 IOP Undefined Ambiguous Unde- IOP CurrentlyNumbers Data fined Enabled to a Not Subsystem Loaded .
_ ~ . _ _ . __ . ___ 7 Unde- Undefined Undefined Unde- Undefined fined . fined _ _ _ . ~ _ . . . __ _ - 62 ~

Unauthorized SSP - The r equesting SSP does not have contr ol of the applicatiotl wllich would be affected by the execution of the command.

Application Unassigned to an SSP - The specified application has not been assigned to any SSP.

Control Store Not Loaded - Control store must be loaded in order to execute the command.

Unrecognized Command - The command received from the SSP is undeîined .

Equipment Check Correctable Memory Error - A single-bit memc,ry error nas been detected and corrected. The location of the error is identified by sense bytes 5 to 7.

Uncorrected Memory Error - A single-bit rrsemory error has been detected but was not able to be corrected. The location of the error is identified by sense bytes 5 to 7.

Register Error - An error has been detected on a SAU hardware register identified by sense bytes 5 to 6.

PIO Error - An error has been detected on a parallel input/o~stput device identified by sense bytes 5 anc; 6.

SIO Error - An error has been detected on a serial input/output device identified by sense bytes 5 and 6.

Data Check MAS Entries Greater Than ~ - After examination of the Subsystem Interface Table the SAU has detected the presence of four consecutive entries with the MAS bit sel.

~IAS Bit Set for BCTS - The SAU has detected the presence of an MAS
bit set for a BCTS entry in the Subsystem Interface Table.

`` - 63 ~

M~S Bit Set for I irst Table Entry - The SAU has detected the presence of a MAS bit set in the initial Subsystem Interface Table entry.

IOI' State Error - ~ subsystem is enabled to an IOP that has never been partitioned to an application, assigned to reserve state, or offline.

BCTS Enabled to More Than One IOP ~ ~ BCTS entry in the Subsystem Interface Table shows the subsystem- string enabled to more than one IOP.

Exclusive Use Violation - The ~:xclusive IJse bit is set for a subsystem, and that subsystem is already enabled to lOPs that are in different applications.

Ambiguous Data - The SAU has detected an undelined condition or s~ate of a register or memory location identified by sense bytes 5 and 6.

Length Check ~\lrite Error - The SSP has provided too little data or more data than is nccessary foI execution of the command.

Read E:rror - The SSP is requesting more data than the S~U can provide in a single-frame message.

Partitioning Check ,Subsystem Not Configures - The SSP is requesting partitioning changes for a subsystem whose feature is nol: installed.

Unauthorized SSP - The requesting SSP is not authorized to make partitioning changes for subsystems associated with IOPs in applications it does not control.

IOP State Error - The SSP requests that a subsystem be enabled to an IOP which is notassigned to an application or is offline; or the SSP
requests to assign the IOP to an illegal state.

- fi4 - ~ J~

BCTS Enabled to More Than One IOP - The SSP requests that a BCTS
subsystem string be enabled to more than one IOP; or the SSP reqnests a BC'I'S subsystem string be enabled to an IOP while it is currently enabled to another.

Exclusive Use Violation - The command or table specifies Exclusive Use and the resulting partitioning state will cause the subsystem to be enabled to IOPs in different applications.

IO~ Currently Enabled to a Subsystem - The SSP requests to change the state of an IOP which is enabled to a subsystem.

Third and ~ourth Sense Bytes Sense bytes 3 and 4 specify the program counter value at the ';i~e the error occurred. These bytes identify the S~U routines which detected the error. Sense bytes 3 and 4 will contain the least significant and most significant bytes of address, respectively.

E~ifth and Sixth Sense_Bytes Sense bytes 5 and 6 specify the memory location or hardware ID where an error has occurred. Sense byte 5 will contain the least significant byte of memory adclress or hardware ID. Sense byte 6 will contain the most significant memory address or hardwaI e ID.

Seventh Sense Byte _.~__ . .

Sense byte 7 contains five bits of syndrome information in the event of a single-bit error. Bits 3-7 identify the failing bit of microcode or ECC at the memory location identified by sense bytes 5 and 6. The syndrome information is defined in Table 8 as follows:

- - 65 ~ t~

Syndrome B s Failing Bit 0 1 2 3 ~ 5 6 7 O O O 1 1 0 0 1 Data 0 0 0 0 1 0 1 0 1 Data 1 0 0 0 0 1 1 0 1 Data 2 0 0 0 1 1 1 0 0 Data 3 0 0 0 1 1 0 1 0 Data 4 0 0 Q 1 0 1 1 0 Data 5 0 0 0 0 1 1 1 0 Data 6 0 0 0 1 1 1 1 1 Data 7 O O O 1 û O O O ECC 0 0 0 0 0 0 1 0 0 F.CC 2 o o n 0 0 0 1 0 ECC 3 ~5 0 0 0 0 0 0 0 1 ~CC 4 INITIALIZATION

Several tasks must be accomplished before the SAU can perform the initial or subsequent subsystem partitioning functions for one or several 20 applications. Tllese tasks, from SAIJ power-on ~hrough the initial subsystem partitioning for each of the active applications, will collectively be called SAU
initialization. Specifically, they include powering on, loading cont~ol store, writing cabling information, writing the SSP/application designators, writing for IOP status, and enabling/disabiing the subsystem interfaces.
25 Additionally, these tasks or functions must be carried out in the same order.
POWER ON/OFF
_ _ The SAU has a manually controlled AC breaker switch. It also has a local/remote switch which allows the SAU's DC power to be controlled either at the unit or remotely. Additionally, the SAU is able to detect environmental 3~ and voltage fault conditions, and subsequently power itself off.

~ 66 ~

~ lhen the SAU DC powers on, all registers and tables are set to a known state. Specifically:
~ a) Cabling information is cleared.
(b) The SSP/Application designators indicate no SSP is assigned to any application.
(c) Each IOP is in the "unassigned" state.
(d) SAU locks are cleared.
(e) r)ata describing partitioning status and exclusive use status for each of the SPIs and B(~TSs indicates that all SPI ports and BC1S
channels are disabled.

Once the SAU has powered up and has completed setting its registers and tables to a known state, it notifies the first available SSP of this action.The first available SSP is defined as the lowest numbered SSP interface number (at the SAU) ~Ivith interface enabled. If the SSP has not responded within a specified period of time, the SAU will attempt to notify the next available SSP. This process is repeated indefinitely until a response is received from an SSP.

The expected response from an SSP is first a reserve command which locks the SAU onto the SSP interface that received the command and second, a command to load control store. The set of commands accepted by the SAU
following its powering on is limited to these two plus two more:
a reset command which causes the SAU to reset its registers and tables, and a release command which counterrnands the reserve command.

1~ the power-on con~idence sequence has been successfully completed, the SAU will initialize all registers and storage elements to a known state.
The Subsystem Interface Table is cleared to ~eros. All 16 SSP application designators are set to unassigned. All 16 IOP state designators are set to never assigned. All SPIs are enabled; however, the partitioning change signals are not activated. All BCTS channel enable lines are deactivated and the Manual Override line is held inactive.- When this sequence is complete, the SAU will report to each SSP: SUP Message Waiting, SUP Error, and sense data indicating "power-on complete" status. After an SSP acknowledges the status, the SAU will continue with the next until all SSPs have been notified.

ln the event no acknowledge is received for the status, the SAU will set the NO SSP ~CTION TA~EN bit in the associated SSP History Table entry.

LOAD CONTROL STOR

An SSP command to load control store causes a blocl< write of the SAU's 5 microcode used to perform various required checks. These include the use of tables to determine SSP access rights, to enforce e:~clusive use, to maintain u~to-date partitioning status, and to report to the SSP any anomalous conditions as a result of a command. Writing this information is allowed by ~he S~U only if no SAU lock is set.

After reporting power-on complete status and prior to control Store initi~lization, the SAU will be able tc perform the following commands.

(a) Read Control Store (b) Write Control Store (c) SAU Reserve (d) SAU Release (e) SAU Reset (f) Write SSP History Table (g~) Read SSP History Table (h) Read ID Word 0 (i) Read lD Word 1 The normal sequence o~ events performed by an SSP in order to initialize the SAU control store following the receipt of power-on confidence status is as follows.

1.) The SSP reserves the SAU (SAU Reserve command).
2.) The SSP reads its SSP History Table entry (Read SSP Hislory~
command) in order to determine whether the SAIJ control store has already been initialized by another SSP. If the control store initialized bit is set, the SSP would begin initialization of its associated SAU Tables (see 2.6.3).
3a.) The SSP performs Write Control Store and Read Control Store commands in order to load and verify the SAU microcode.

- 68 ~

3b.) After the microcode is loaded, the SSP will set the Microcode Loaded bit (Write SSP ~Iistory command). (The state of this bit is reflected in each SSP ~listory Table entry.) If the microcode load is not successful, the SSP will set the NO SSP ACTION TAKEN bit in its associated SSP History Table entry.

4.) The SSP continues with the initialization of its associated SAU
tables.

LOAD CABLING INFO~MATION

The same SSP that loads the control store also would normally issue the command to load the cablin~ information. This information, also contained on SSP mass storage, identifies which of sixteen possible IOPs is connected to each SPI port or BCTS channel; it also identifies each group of SPI's that are in a multiaccess subsystem (note that the SPIs in a multiaccess subsystem can not be split between SAUs). As with the load control store command, the cabling information cannot be written into the SAU if any SAU lock is set.
.
CONDIT ONINC IN ERFACES AND STATUS TABLES

The end result of the SAU's initialization is the SAU's subsystem partitioning status table representing the current and desired status of each SPI and BC'I~ interface. Given the cabling information, the processes remaining to accomplish this are designating which SSP is assigned to each application, specifying each IOP's status, and enabling/disabling subsystem interfaces .

The SAU is designed so that no primary SSP is required to complete the initialization process. Rather, each SSP can carry out the last three stages of SAU initialization for each application with which it is associated.
In particular, the following sequence is effected by each SSP:
1. TJle applications with which the SSP is associated are specified.
2. The corresponding SAU locks are set.
3. IOP/Application assignments are written.
30 4. SPI and BCTS interfaccs cabled to lOPs in the SSP's applications are enabled/disabled and corresponding entries in the partitioning status table are updated.

SAU TA I.ES

After the SAU Control Store has been loaded, the IOP Number portion of the Subsystem Inter~ace Table must be initialized followed by the initialization of the SSP Application and IOP State Tables by each SSP.

The normal sequence of events performed by an SSP in order to initialize th~ SAU Tables is as follows. It is assumed that the SAU is reserved and the SSP History Table has been read from the control store initialization se~uences.

1.) Following the control store initialization sequences, the SSP
determines from the SSP History Table (IOP Numbers ~ritten bit) whether the Subsystem IOP Number portion of the Subsystem Interface Table has been written. If the IOP numbers have been written, then the SSP continues with step 3a.

2a) The SSP will perform a Write Subsystem IOP N~lmber command and a Read Subsystem Interface Table command in order to load and verify the IOP Number portion of the Subsystem Interface Table.

2b) The SSP sets the IOP Number Loaded bit (Write SSP History comrnand). (This bit is reflected in each SSP History Table entry.) 3a) The SSP writes its SSP nurnber (~rite SSP Number command) for the applications it controls.

3b) The SSP options sets the SAU loclc bit (Set SAU Lock Command) to prevent other SSP control of these applications.

3c) The SSP sets the SSP Numbers written bit in its associated SSP~
History Table entry (Write SSP History comrnand).

25 4) The SSP will write the appropriate IOP stat~s (Write IOP State command) for IOPs in its system:
a) IOP State Table entries representing IOPs which reside in an application are written to that state.

- 70 - ~

b) Entries which represent offline IOPs are temporarily set to an application controlled by the SSP.

5n) Tile SSP performs the appropriate Add Subsystem commands for subsystems in its system.
5b) The SSP performs the appropriate Remove Subsystem commands for subsystems in its system.
5c) The SSP rewrites to offline the IOP States Table entries (Write IOP
State command) for offline IOPs temporarily set to an application.
5d) The SSP sets the IOP States Written bit in its associated SSP
History Table entry (Write SSP History command).
5e) The SSP Sets the Add/Remove Subsystems Complete bit in its associated SSP History Table entry (Write SSP History command).
6) The SSP releases the SAIJ Reserve condition ~S~U Release com mand).

15 If any of the above sequences result in error, the SSP will set the NO SSP
ACTION bit in its associated SSP~ History Table entry.

B. Microcode A complete set of flow charts and their descriptions are included as an appendix to this specification for the sal~e of completeness. However, 20 a representative flow chart giving an overall view of the microcode structure will be described here with reference to Fig. 47.
I. Microcode Structul e The subsystem access unit (SAU) microcode is broken down into three areas.
They are:
a.l Power-on, Confidence and Initialization, 4710 b.) Idle Loop, 4750 c.) SAIJ Command Execution, 4720 1. Power-On, Confidence and Initialization (4710) Referring to Fig. 47, this area is noted as 4710. It contains a number of confidence tests 4714 status reporting procedures 4712 and initialization a~718. All of these steps are necessary prior to the execution of any commands from the command source (SSP). This area 4710 is entered whenever a reset command 4728 occurs. A reset is caused b~ a power-up , signal, a manual reset signal from the SAU panel, or a command signal from a command souce. The command source in this instance, is, of course, the system support processor (SSP). Reset from this command implies that the SAU is operating in the Idle I,oop 4750 and is capable of command execution. Power-on or a manual reset may be invoked at any time. The confidence tests, ~1714, are the first tests to be performed following a reset. These tests will now be described:

a.~ SAU Lock Test This test ensures the capability to set, clear and read the SAU locl< flip-flops.
b.) Register Test This test writes and reads a pattern to and from each of the one hundred and sixty (160) partitioning registers looking for errors.
c.) Programmable Read-Only Memory (PROM) Test This test reads eac:h location of the P~OM and looks for single bit errors (SBE).
d.) Random ~ccess Memory (R~M) Test This test writes and reads a pattern to and Erom each location of the RAM and looks for single or multiple bit errors (SE3E, MRE).
e.~ Error Correction Code (ECC) TEst This test reads eight (8) predetermined locations from the PROM, each containing a single bit error. The test will ensure proper bit correcting capability of the ECC
logic îor all eight bits of data. The tests also checks for proper capture of the failing address and syndrome information bits.

~hen any error is detected, a status reporting procedure is entered; and detailed error information is reported to all SSP's. ~fter reporting status, the testing resumes until completed. The contents of the status message have been previously described in conjunction with the description of the Sense Registers.

~ 72 ~ f~ ' ~ Yhen the confidence tests are completed, the initialization state, 4718, is activated. In this state, a number of tables and variables are initiali~ed to a predetermined state prior to the command execution. It is also necessary to relocate a resident microcode procedure to the RAM due to 5 timing restrictions. The number of configured SSP's is determined at this time and all SSP interfaces are set to the UDLC normal response mode.

2. ldle Loop (4750) The Idle Loop portion is shown in Fig. 47 at 4750. This loop performs four functions. They are:
n.) Look for pending microcode detected sense conditions 4752;
b.) Look for any manual changes involving SAU 1Ocks d~756;
c.) Look for any hardware detected memory errors 4760;
d.) Look for incoming SSP rec,uests ~"66.

Theidle loop, 4750, is entered following the initialization procedure 4710, via line 4719, during power on or reset, or whenever an abort is executed. The abort is involced whenever a command cannot be completed normally. The sense conditions which caused the abort are retained and reported during idle loop execution.

First, look for sense pending 4752. These procedures report any pending status conditions contained in the sense bytes previously described.
T}le status is reported to all configured SSP's. Sense data is always cleared to zero, after the information is presented to the SSP~s.

~tatus conditions found at this time are due, mainly, to hardware faults or errors which precluded normal cs)mpletion of a command. This includes conditions which invoked the abort operation.

Next, we look for operator control changes, 4756. These procedures detect any manual clearing of the S~U Iock flip-flops from the SAU operator panel. A detected manual clear causes the microcode to clear the associated S~U lock indicators stored in that table in the RAM. l~ach time the microcode looks for changes, the state of the lock flip-flops is stored. This stored information is used to de-termine manual clearing of the locks the next time these procedures are executed.

- 7 3 ~ t ~

Memory errors, ~60 are looked for next. These procedures are useà for detection of any single bit errors (S13E? which may have occurred since the last look for such memory errors. If lhe SBE counter has been incremented, status information is formed and reported to all configured 5 SS~'s. The content of this message has also been previously described in conjunction with the Sense Registers.

I,ook for requests, 4766 procedures perforrn the following tasks:
a.) look for incoming frames from all configured SSP's;
b.) prioritize the requests;
c.) read in the entire frame from one SSP;
d.) perform a number of checks involving both transmission faults and protocol violations, e.) assemble more than one transmission into a multiple frame message, and report any protocol errors to th~ associ-- ted SSP.

This look for requests also handles UDLC protocol s~ommunication which includes mode setting commands.

3. SAU Command E~ecution (4720~
When an assembled message contains a SAU command, 4720, the following tasks are performed:
a.) The microcode determines whether the command can be executed, a~726 (i.e. microcode loaded);
b.) The command procedures are executed, ~722;
c.) A status message is returned indicating successful completion of the command 4723, or a reason given as to why the command cannot be performed. Data is returned with the status information when the command is a read operation, whereas data is sent in the command message for write type commands 4729. The SAU instruction set has been previously described and illustrated in Table 6 and will not be repeated here.
Similarly, the tables and buffers stored in the R~M as they appear in the SAU microcode have also been previously described under the 7nstruction Set portion of the programming portion in the immediately preceding - 74 ~ 3~ ~

section. 17Or example, the SSP application table is illus-trated in Fig. 18 and the IC)P state table is set forth in ~ig. 19, etc. The Frame Buffer, however, has not been previously described and deser~es a brieî mention. It is a storage device which is 256 bytes deep by 8 bytes across, which is used to store outgoing/incoming frames to/from the SSP. Each frame is composed of four parts. They are:
1. UDLC command 2. System Session 3. Status 4. ~ead Data ~or outgoing messages, the UDCL command and the system session portion of the fram e is generated an placed in the frame buffer. The data and status are thereafter obtained from the Input/Output buffer and sense register respectively and placed in the frame buffer. The entire frame is then sent to an SSP.

For incoming messages, the entire frame is stored in the frame buffeI. The UDI~C command and system session is then checked and stripped off. The remainder of the frame which is composed of the SAU command and the write data, is stored in the Input/Output buffer.
This process is repeated for multiple frame messages until the entire message has been assembled in the Input/Output buffer.

The Input/Output buffer is a lK by 8 bit buffer used by the SAU command rnicrocode. It contains a data, length, command word, and read/write data. The data length is 16 bits long. It is the number of data bytes received in a SSP message or the number of data bytes to send to the SSP in an SAU message. The command word is 4 bytes long. It is for incoming messages only and contains the SAU command, one byte of operand and two address bytes. If more than one byte of operand is required, all operand bytes will be obtained from the data buffer.

- 75 ~

The data buffer is 994 bytes long. It contains the data necessary for the execution of an SAII command or; for OUtgOillg messages, it contains the read data requested by a previous SAU command.

The sense registers have been previously described in detail and will not be repeated here~ They are - described under Status Presentations and include Table 7.

Memory Map The SAU memory shown in Fig. 48 consists of 22K bytes of PROM and RAM. It is broken down into four sections.
They are:
1. ~esident control store code, 4~10.
2. Resident 2501~ baud interface code, 4812.
3. Loadable eontrol store code, 4814.
4. SAU tables area, 4818.

The resident control store contains microcode capable of performing the necessary power on and initialization tasks.
These inelude:
20 1. Confidence tests 2. Table initialization 3. 250K Baud interface protocol 4. Execution of the following commands a.) Read Control Store b.) Write Control Store c.) SAU Reserve d.) SAU release e.) SAU Reset f.) Write SSP History g.) Read SSP History h.) Read ID Word O
i.) Read ID word I

The resident 250~ baud interface eode handles incoming SSP
re~uests, and data transfers between the frame buffer and the SIO's. It is necessary for this code to be resideni in the SAU as well as execute fast enough to keep up with the -- 7 6 -- ~ ~ ~d~

interface data transfer rate. This requires the 250K baud code to be stored in PRO[VI and transferred to R~M during initialization. The code is executed out of RAM which has a faster access time than PROM.

Loadable control store contains the balance of the S~U
command set not included in the resident control store. This code is loaded by the SSP during the SSP's S~U initialization sequences. ~ special sentinel character occupies the last location OI loadable control store. This sentinel character is ~Q used by the S~J in determining whether this control store is loaded and thus, capflble of being executed.

The S~U tables area contains all tables and variables used by the microcode. In addition, a stack, used to pass parameters and return addresses between procedures is contained in this area.

Code Assembly N~SI - SCHNEIDERMANN flowcharts are provided in the appendix of this application.
.

Summarizing thc SAU can be tho-lght of as consisting of three parts:
1. Interfaces to command sources.
2. Interfaces to peripheral subsystems.
3. Internal resident data and logic used to control status of subsystem interfaces to I/O complexes.

Yia the interface to a command source, the S~U can accept requests to enable or disable subsystem interfaces and to make a subsystem accessible to only one application or to all the applications ~i.e., shared subsystems) whose I/O complexes have interfaces to the subsystem. These interfaces can also be used as a means to initialize the SAU, i.e., load the SAU with its control logicand resident data.

The S~U's interfaces to subsystems provide the means to electrically enable or disable the subsystem 's interfaces to l/O com plexes.

- 77 ~ f.(~

The SAU's control logic and resident data are used to service the requests made by the command source(s). Also, certain checks are made for each request in order to ensure the following:
1. If a subsystem's inlerface to an l/O comple~ is to be enabled or disabled, the command source making the request must be as-soc;ated with the same application that is associated with the subsystem interface.
2. If a subsystem interface is to ~e enabled, and exclusive use is in effect for that subsystem, then the interface to be enabled must be associated with the same application that has exclusive use of the subsystem.

3. 1~ exclusive use is to be put into effect or be discontinued for a particular subsystem, then the request to do so must be from the command source associated with the same application that is associated with the currently enabled subsystern interface(s).

4. If exclusive use is to be put into effect for a particular subsystem, then that subsystem's interfaces that are already enabled must all be in the same application.

The association between command source and application is logical only from an SAW point of view; it is not necessarily physical from an application point of view. In particular, the command source may be a suppor~ processor which performs partitionirlg, testing, and maintenance functions on the units in a given application; normally this support processor would also be associatedwith the application from an SAU point of view. However~ another command source not physically associated with the application is not precluded from requesting changes in subsystem interface status for interfaces associated with the application.

The association between application and command source is made via a command to the SAU from any command source. An SAU internal lock associated with t~le application can be set to prevent any other command source frorn making this association while one command source is so assoc-iated. This lock can be set by any command source. A lock is cleared when any of the following occurs:

`' 1. The S~U powers up.
2. The associated command source causes the lock to be cleared.
3. Manual action at the S~U causes all locks associated with a given command source to be cleared.
4. The S~U can optionally be set in either of two modes:
The only command source that can cause the lock to be cleared is the one so associated.
~ny of a pre-specified group of command sources can cause the loc~ to be cleared.
Setting of mode is a manual action ~t the S~U; specification of command source group is hard-wired.

In addition to locks, the SAU uses certain information to make its checlcs to ensure command source integrity; it also maintains a current status of each subsystem interface. Any command source provides the SA~J with ~he 15 association between each subsystem interface and I/O complex, indicating the connections that are made durin~ configuration. Any of the above locks set prevents modification of this information. Also provided is the association between each I/O complex and application. A ground rule is that only the command source associated with a ~iven application can make this 20 association/ deassociation. Thus, the followin~ composite mapping exists:

Subsystem intcrface --~ I/O complex -~ pplication This allows the unit to determine if the subsystern interface affected is associatcd with the same application as the command source, i.e., Subsystem interface ---' I/O Complex ~ pplication Command ---~ Application Source If the above applications correspond one ~o another, there is a match;
otherwise a mismatch is indicated.

This information is also used to determine if a sllt)system interface can 30 be enabled or disabled reiative to any exclusive use o~ subsystem. Suppose subsystem interface A is to be enabled and exclusive use is already set for thissubsystern; then a check is to determine if all other enabled interfaces for this subsystem are associated with the same application:

~ _ ~9 _ L~
Subsystem interface ~ I/O Complex --~ Application Subsystem interface B --~ I/O Complex -~ Application If the applications correspond one to anothcr, there is a match; otherwise a mismatch is indicated.

If exclusive use is to be set, then the same comparison is made, i.e., ensuring that all enabled interfaces are associated with the same application.
Having more than one command source allows more hardware independence of systems and applications, i.e., communication between applications is not required, and a command source can uniguely represent an application's subsystem partitioning needs. In the latter case, the number of applications that will be accessing a common set of subsystems determine the number of command sources required.

The combination of locks and checking herein described provides the SAU with the capability to allow or disallow concurrent accessibility to a subsystem by more than one application. Additionally, this capability provides - for ensuring application and command source integrity in the use of common subsystems.

It will be understood from the foregoing description that various modifications and changes may be made in the preferred embodiment of the present invention without departing from its true spirit. It is intended that this description is for purposes of illustration only and sho-lld not be construed in a limiting sense. The scope of this invention should be limited only by the language of the claims which follow the attached appendix of flowcharts.

What is claimed is:

.

~N D I X

Ml~ F~E

L~ 1~ Q F C Q~l. T E N T S
Fi~ures Fi~ure 0-1. Flowchart of ABORT 1-2 Figure ~2. Flowchart of ADD_IOP _ ENABLE_COUNTlenables) 1-2 ~igure ~3. Flowchart oF ADD SUBSYSTEM (part 1 of 21 1-3 Figure 0-4. Flowchart of ADD SUBSYSTEM (part 2 of 2) 11-4 Figure ~5. Elowchart of ASSEME~LE MESSA(;E 1-5 Figure 0-6. Flowchart of AlJT~lORIZED _ SSP_CHECK 1-6 Fi~ur~ ~7. Fiowchart of BCTS _ CONFIGURATION 1-6 Figure ~$. Flowchart of BCTS_ENABLE_CHECK - 1-7 Figur~ ~3. Flowcharl~ OF BLOCK 'TFlANSFER(readreg,writereg) 1 Figure ~10. Flowchart of BUtLD SYSTEM SESSION 1-9 Fi~ure ~11. Flowchar~ of CLEAR LED(ssp number) 1-10 Fi~ure O-t2. Flowchart of CLEAR_SAU _ LOCK 1-~1 Figure 0-13. Flowchart of CLEAR_TEST_ MODE 1-12 Fi~ure ~14. Flowchart o~ COMMAND RECEIVED 1-13 Fi~ure ~15. flo~Nchar~ of CORRECTABLE MEMORY ERROR 1-14 Figure ~16. Flowchart of CORRECT ECCImemory addr~ss) 1-15 Figure t)-17. Flowchar~ of E~C TEST 1~16 Figure 0-18. flowrjhart of ECC TEST ~part 2 of 31@ 1-17 Fi~ure 0-19. flowqhart of ECC TE5T lpart 3 of 33@ 11-18 Fi~ure 0-20. flowchart of ECC TEST ERROR 1-19 Figllre 0-21. Flowchart of EU_CHECK 1-20 Fi~ure 0-22. Flowchart of EXECUTE _ COMMAND ~part 1 of 2) 1-21 Fi~ure U-23. Flowchart of EXECUTE _ COMMANI:) (part 2 of 2) 1-22 Fi~ure 0-24. Flowchart of EXECUTE DISCONNECT C:OMMAND 1-23 Figuro ~25. Flowchart of EXECUTE SET NORMAL RESPONSE MODE 7-23 COMMAND
Figure 0-26. Flowchart of iEXECUTE TEST COMMAND î-23 Figure $:~-27. Flowchar~ of EXECUTE EXCHANGE ID COMMAND 1-23 Fi0ur~ 0-28. Flowchart of FAULT DETECT î-24 Figure 0-29. Flowchart of FRAME CHEOKS 1-25 Flgure ~30. Flo~chart of FR~ME REJECT CHECKS ~par~ 1 of 2) 1-26 Fi~LIrs 1) 31. Flowchar~ of FRAME REJECT CHECKS !palt 2 of 2) 1-27 Fi~ure () 32. Flowcart of GENERATE FRAME REJECT RESPONSE 1-27 Fi~ure ~33. Flowchart of GENERATE SYSTEM SES~ION POINTERS 1-28 Figure ~34. Flowchars of HARDWARE _ COMMAND(si~r~al,signal_output _ port) 1-2g Fi~ure 1:~35. Flowchan of IDLE 1-30 Fi~ure ~36. Flowcllan o7 INFORMATION FI~LD CHECKS 1-31 Fi~urs ~37. Flowchart of II`JITIALIZ BCTS SPI I~JTERFACE 1-32 Fi~u~e ~38. Flowchsrt of INlTiALlZE PlO(porl,i/o control) 1-~2 F;gure 0-39. Flowchart of INiTlALlZE_Sl(~ _ RECEIVE 1-33 Figure 0-40. Flowchart of INITIALIZE SlO TRA!~ISMIT 1-34 Figure 0-41. Flowchart of INPUT - 1-34 Figure 0-42. Flowchart of IOP _ APPLICATION _ CHECK 1-35 Fiyure 0-43. Flowchart of LOOK FOR ACKNOWLEDGE(interface number) 1-36 Figure 0-44. Flowchart cf LOOK FOR OPERATOR CONTROL CHANGES 1-37 Figure 0-45. Flowchart of LOOK FOR POLLIinterface number) 1-38 Figure 0-46. Flowchar~ of LOOK _ FOR _ REQUESTludlc number,timout value) 1-39 Figure 0-47. Flowchart of LOOK FOI~ SENSE PENDIN(i 1-40 Figure 0-48. Flowchart of MANUAL CLEAR SAU LOCKS(SSP NUMBER) 1-40 Figure 0-49. Flowchart of MODE CHECKS 1-41 Figure 0-50. Flowchart of OUTPUT~data,port) 1-42 Figure 0-51. Flowchart of OUTPUT_AND_VERlFY~data,portl 1-42 Figure ~52. Flowchart of PC _ ADDRESS 1-42 Figure 0-53. Flowchart of POLL_READ_CHARACTER_AVAILABLE_STATUS 1-43 Figure 0-54. Flowchart of PRESENTATION CHECKS - 1-44 Figure 0-55. Flowchart of PROM TEST 1-45 Figure 0-56. F10wchart of RAM TEST 1-46 Figure 0-57. FLOWCHART OF READ _ BCTS (PART 1 OF 2) 1-47 Figure 0-58. Flowchart af READ _ CONTROL _ STORE 1-~18 Figure 0-59. Flowchart of READ _ FF;AME ~part 1 of 2) 1-49 Figure 0-60. Flowchart of READ_FRAME ~part 2 of 2) 1-50 Figure 0-61. Flowchart of READ _ ID_WORD _ O 1-51 Figure 0-62. Flowchart of READ _ ID_WORD _ 1 1-52 Figure (:)-63. Flowchart of READ_IOP _ STATE 1-53 Figure 0-64. Flowchart of READ SSP HISTORY 1-54 Figure 0-65. Flowchart of READ SSP NUMBER 1-55 Figure 0-66. Flowchart of READ _ SPI 1-56 Figure 0-67. Flowchart of READ SUBSYS-rEM INTERFACE TABLE 1-57 Figure 0-68. Flowchart of REGISTER TEST (part 1 of 2) 1-58 Figure 0-69. Flowchart of REGISTER TEST (part 2 of 2) 1-59 Figure 0-70. Flowchart of REMOVE_ SUBS`tSTEM (par~ 1 of 2) 1-~0 Figure 0-71. Flowchart of REMOVE_SUBSYSTEM (part 2 of 2~ 1-61 Figure 0-72. Flowchart of SAU IIARDWARE INITIALIZATION AND TEST 1-62 Figure 0-73. Flowchart of SAU_INITIALIZATION 1-fi3 Figure 0-74. Flowchart of S~U LOCK CHECKS(ssp numb0r) 1-64 Figure 0 75. Flowchart of SAlJ LOCK TEST 1-65 Figure 0-76. Flowchart of SAU RELEASE 1--6B
Figure 0-77. Flowcllar~ of SAU RESERVE 1-66 Figure 0-78. FLOWCHART OF SAU_RESET 1-66 Figure 0-79. Flowchart of SEND ATTENTION 1-67 Figure 0-80. Flowchart of SEND COMMAND END 1-~
Figure 0-81. Flowchart of SEND DISCONNECT MODE 1-69 Figure 0-82. Flowchart of SEND _ FRAME(udlc number,count) (part 1 of 33 1-69 Figure 0-83. Flowchart of SEND_FRAME(u~:llc number,count~ Ipart 2 of 3) 1 70 Figure 0-84. Flowchart of SEND_FRAME(udlc number,oount) ~part 3 of 3~ 1-71 Figure 0-85. Flowchart ~f SEND FRAME REJECT 1-72 Figure 0-86. Flowchart of SEND RECEIVE NOT REAI)Y 1-73 Figure 0-87. Flowchart of SEND RECEIVE READY 1-74 Figure 0-88. Flowchart of SEND UNNUMBERED ACKNOWLEDGE 1-74 T:iyure 0-89. Flowchart of SET LED(ssp number) 1-75 Figure 0-90. Flowchar~ of SET _ SAU _ LOCK 1-76 Figure 0-91. Flowcllart of SET _ TEST _ MODE 1-77 Figure 0~92. Flowchart of SlO TEST 1-78 Figure 0-93. Flowchar~ of SPI_CONFIGUFIATION 1-79 Figure 0-94. Flowchar~ of SUBTRACT _ IOP _ ENABLE _ COUNT(enables) 1-80 Figure 0-95. Flowchart of SYSTEM SESSION CHECKS (part 1 of 2)@ 1-81 Figure 0-96. Flowchart of SYSTEM SESSION CHECKS (part 2 of 2)@ 1-82 Figure 0-97. Flowchart of UDLC CODE TRANSPi~NT 1-83 Figure 0-98. flowchart of UNCORRECTABLE MEMORY ERROR 1-84 Figure 0-99. Flvwchart of VERlFYisignal,signal_ou~put_port) 1-84 Figure t) 100. Flowchar~ of WRITE _ CONTROL_STORE 1-85 Figure ~101. Flowchar~ of WRITE _ IOP _ STATE - 1-86 Figure ~102. Flowchart of WRITE _ PARTiTlONlNG_REGISTER 1-81 Figure ~103. Flowchart of WRITE SSP HISTORY - 1-88 Figure 1) 104. Flowchart of WRITE _ SSP _ NUMBER 1-89 Figure 0-105. Flowchart of WRITE SUBSYSTEM IOP NUMBERlPart 1 of 2) 1-90 Figure (t-106. Flowchart of WRITE SUBSYSTEM IOP NUMBER(Part 2 of 2) 1-91 ~iguro ~1. t1owch~rt of ABOflT
_. _ INlTlALtZE STACK POINTER TO 3000 HEX

UNCONDITIONAI. JUNlP TO IDLE (See Figure ~35) _ fi~ure ~2 Flowohart of ADD_IOP_ENABLE_CO~JNT(en~h/esJ
.
DO FOR 1:= O TO 3 _~_______________________________________________________________________ SHIFT enables ONE BIT POSITION TO LEFT

IF enables(3) = 1 .
ItlEN ___ _ _ _ _ _ _ _ _ __ __ _ _ __ _ _ _ _ _ _ _ __ _ _ _ _ __ _ _ __ _ __ _ _ __ _ _ __ _ _ _ _ _ ~SE_ .._ _ _ ___ IOP_ENABLE _ COUNT(SIT_IOP_NUMBER(TABLE_ADDRESS,I)) --IOP_ENABLE_COUNTISIT_IOP_NUMBER(TABLE_ADDRESS,I)) + 1 _ _ ~
~ETURN

~ ~ }~ ~ .i F~

Figuro ~3. F/owchs~7 o~ADD SUBSYSrEbJ/p~ o/Z
TABLE ADDRESS := COMMAND WORD~2) .
_ COMMAND PARTITIONING CONTROL FLA(~S := COMMAND WORD~1) .
......................... ~ .......................... .............., ......... -SPI CONFIGURATION ~See Figure ~93) BCTS CONFIGURATION (See Figure 0-7) ......................................... _.
IF TAE;LE ADDRESS GT MAX SPI ADDRESS
T~ __________ __ __ _ _ __ ____________ ____ ~ _______ __ ______ ~__ IF ~TABLE ADDRESS LT 128) OR flABLE ADDRESS GT MAX BCTS ADDRES
T~________ _ _______________ __ ______ _ _________ ___ _ ___ L~__ IF TABLE ADDRESS GT 159 - . ..
I~E~ _____________ __________ _ L~E______ ________ ____________ . .
SEN~SE REGISTER(O)--COMMAND SENSE REGISTER~O) = PARTlrlONlNG . .
REJECT SENSE- C:HECK SENSE - . .
:
TABLE ADDRESS OUT OF RANGE = SUBSYSTEM NOT CONFIGURED = .
TRUE TRUE
~ .
.- UNIT CHECK = TRUE . .
_ _ .
CODE ADDRESS = PC ADDRESS (See Figure ~52j .
. .
RETURN .
IOP APPLICATION CHECK ~See FiDure 0-423 _ ..... ..

T-H-EN- _ ~L~ E_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . EU CHECK ~See Figure 0-21) . BCTS ENABLE CHECK ~Ser~ Fi~ur0 ~B~
SENSE REGISTER~1) NE O
THN ~ _ _____________ _ __________________ _ ______ LSE __ ____ SENSE REGISTER~O)--DATA CHECK SENSE
_ _ UNIT CHECK = TRUE . .
CODE ADDRESS = PC ADDRESS ~See Fi~ur2 ~52~
. .
RETURN
. _ ~*** flow~hart continued on fi~ure 0 4 , ~,~ ,, f~

~igur~ ~4. Flowchan of ADD SU95YSTf M ~p~rt 2 of 2J
TEMPORARY REGISTER~1) = SIT PARTITIONING CONTROL FLAGS(TABLE ADDRESS) -SIT PARTITIONING CONTROL FLAGS(TABLE ADDRESS) = SIT PARTITIONING CONTROL
FLAGSfrABLE ADDRESS) LOR COMMAND PARTITIONING CONTROL FLAGS
................... - -....... ;
, AUTHORIZED SSP CHFCK ~See Figure ~6;
' IOP APPLICATION CHECK (See Figure 0-42) :.................. ............................................
IF TAi3LE ADDRESS LE 127 I~N____ _, __ __ _ ___ ____ ______ _________ __ ~L~E________ _______ __ __ ____ __________ ', EU CHECK (See Fi~ure 0-21) . . E~CTS ENABLE Ci-lECK (See F;gure 0 S) :.................. ........: :
SENSE REGISTER(1) NE O
ItlEt L _ _ . . _ _ _ _ _ _ _ _ _, . _ _ L~iE _ _ _ _ - - - - - - - - - - - - - ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
SENSE REGISTERIO) = OUTPUT DATA = TABLE ADDRESS
PARTITIONING CHECK SENSE
OUTPUT AND VERiFY~OUTPUT DATA,PARTITIONING REGISTER
UNIT CHECK = TRUE . ADDRESS POF;T~
(See Figure 0-51) CODE ADDRESS = PC
ADDRESS (See Figure 0-52~ IF HARDWARE ERROR
It~E~I _ _ _._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ELS E_ _ _ _ _ __ _ _ _ __ _ _ _ _ _ _ ___ _ . SIT PARTITIONING C(:)NTROL EOUlPiVlENT CHECK SENSE TE,iMPORARY REGlSTi-R 1 LXOR
FLAGSSIT PARTITIONING CONTROL
= TEMPORARY REGISTER 1 PlO ERROR = TRUE FlAGS~rABLE ADDRFSS~
:ADD IOP ENABI E COUNT ~Se~, .SENSE REGISTER(2,3) = PCFigure 0-2) ADDRESS (See Figure ~62) :_. ....... .............. :
. ~ I TEMPORARY REGISTER 1 -MEMORY ADDRESS ~ INPUT~PARTITIQNING
PARTITIONING REGISTERREGIS1ER READ P05'1T) ADDRESS PORT
................................ ;... TEMPORARY REGISTER 1 =
: : TEMPORARY REGISTER 1 LOP
ABORT (See Figure (}1~ SIT PARTITIONING CONTROL
. . FLAGS[TABLE ADDRESSH2 ts~
: 5~
. . , WRI1~E PARTiTioNiN(i , . . REGISTERlTABLE ADDRESS, .
. . '.TEMPORARY REGISTEFl 1)~Sea : . . Fi~ure ~-102) _ :............... ...........................
RETURN

ro 0-5. F/owch~rt of ASS~MBLE MESSAGE
. _ _ _ __ _ IF FRAME BUFFER~SEG HIC POINTER)17) = FIRST .
I~ENL_________ ___________________----- ELS~_______ _______ ____ _____________ . I_O BUFFER POINTER = 2FRAME BUFFER PblNTER = SUP END HIC
PC)INTER ~ 1 _ DATA LENGTH = PARAMETER LENGTH - 5 : , .
FRAME BUFFEFI POINTER = SUP END IIIC
POINTER ~ 5 . .
.
IF FRAME BUFFERISEG HIC POINTER)18~ = t Asr I~_____________ _ __ ______ ____ ~L~ ________ _____ ______ _____ _____ SEGMENT LENGTH = MESSAGE COUNT SEGMENT LENGTH--MAX SEGMENT
LENGTH

MESSAGE COUNT = MESSAGE COUNT-SEGMENT LENGTH
'~'. . .........................................................
. . SEND RECEIVE READY
. ~See Figur~87~
___ :......................... :

______________________..______________________ _________~____ ..___________ I_O EIUFFERII_O BUFFER POINTER) = FRAME BUFFERIfRAME BUFFR POINTER~ .
, ___ _~ ___ - FRAME BUFFER POINTER = FRAME BUFFRE POIIJTER ~ 1 . _ _ I_O BUFFER POINTER = I_O BUFFER POINTER ~ 1 ._ .
RETURN

~Q~,,?

f;gur~ ~6. fJ~wchort oJAUrllORlZ~D_SSP CH~CI~ -FLA(iS--COMMAND_PARTITIONING_CONTROi'_FLAGS

DO FOR I = O TO 3 _____________________ .____ _____________________________________________ SitlFl' FLAGS ONE BIT POSITION TO THE LEFT FOR TEST
_ IF FI~GS[3) IS SET
IHE~J_ _ _ _ _ _ _ __ __ _ __ _ __ __ _ __ _ _ _ _ _ ___ __ _ _ ___ _ _____ ____ _ ___ _ _____ EL~iE____ STATE _ COi~APARE =
IOP_STATE_TABLElSIT_ IOP_NUMBER~TABLE_ADDRESS,J)) .
.
IF STATE_COMPARE SPECIFIES AN APPLICATION .
I~ , L~E____ IF llEQUESTiNG_SSP_NUMBER NE , .
SSP_APPLICATION_TABLE~STATE_COMPARE) .
ItlE~I_ __ _ _ __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___ _ _ _ _ _ _ __ _ _ _ __ _ _ _ __ LS~_ __ _ .
UNAUTHORIZED_SSP := TRUE . .

RETURN
_ __ - ___ __~ ~_ ~
RETURN
.~

fii~uro ~7. Flov~chort of ~CTS_CON~IGL/~,4TION
_ _ .
HARDWARE_READ_SELECTOR = INPUT(PATCH_WORD_PORr~
__._ _~
IF B(:TS_FEATURE_2 IS SET
1~ ___ ___ __ _____ _ ,~E ________________________________ __ _ __ ____ MAX_BCTS_ADDRESS = IF BCTS_FEATURE_1 IS SEr 1~9 TtlE~__ _ _ _ ___ __ _ __- -- -- ~LS~__ __ _ _ _ __ __ _ __ _ _ __ _ _ __ MAX_i3CTS_ADDRESS-- MAX_BCTS_ADDRESS = I) t43 _ _ .
FlETURN .
_ ~iguru 0-8. flowchdrf of BCJS_fNABLE_CHECI~

~iF SIT_PARTITIONING_CONTROL_FLAGS~TABLE ADDRESS) SET GT 1 I~IE~I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .. _ _ _ _ _ LSE_ __ _ _ __ _ BCTS_ENABLE_tiT_1 := TRUE
- . ' .
_ ,.
RETURN
. ~

Figure tJ 9. flowchor~ OF BLOCK_ JRANs~ff~fro3dre~wr;rero9J
POP RETURN ADDRESS AND STORE IN SAVEHL

. POP INPUT REGISTER ADDRESS AND STORE IN REGISTEFI PAIR DE

POP OUTPUT REGISTER ADDRESS AND STORE IN REGISTER PAIR HL

. . - - CLEAR REGISTER B
_ ._ LOAD ACCIIMULATOR WITH B~E COUNT

MOVE B`fTE COUNT TO REGISTEF( C
. _ . _ . TRANSFER CONTENTS OF REGISTER PAIR HL TO LOCATtON ADDRESSED BY REGISTER
PAIR DE
_ _ .
HL = HL ~ 1 DE = DE ~ 1 . BC--E~C- 1 ______ ___________ _____________________________________________________.
REPEAT WHILE BC NE O
___ _____ __ _ HL REGISTER PAIR = SAVEHL lRETURN ADDRESS OF CALLING ROLJTINE) _ _~___ LOAD PROGRAM COUNTER REGISTER WITH REGISTER PAIR IIL

RETURN
_ F;our~ o-ro. FlowchDlt of BUILD SKSTEM SESSION
UDLS COMMAND = INFORMATION RESPONSE CODE
UDLC: COMMAND[2 TO 4) = OUTPUT SEND VARIABLEIREQUESTING SSP NUMBER) UDLC COMMAND12) :=: UDLC CGMMAND14) . OUTPl)T SEND VARIABLEIREQUFSTING SSP NUMBER) = OUTPIJT SEND
VARIABLE(REQUESTING SSP NUMBER~ ~ 1 _ .
UDLC COMMANDlfi TO 8) = OUTPUT RECEIVE VARIABLEIREOUESTING SSP NUMBER~
. ~ , UDLC COMMAND~6) :=: UDLC COMMAND(8) .-SYSTEM SESS!ON HIC = 1 t . _ _ SYSTEM SESSION ID = Ol . .
FRAME BUFFER~3)(1 TO 4) = AU HIC
_ . FRAME BUFFER(3)(5 TO 8) = ASSURANCE UNIT.` . _ _ FRAME BUFFER(4~ = AU LENGTH
_ . _ _ FFAME BUFFER15) = AU LABEL
_ . , FRAIVIE BUFFER(6) - SUP MESSAGE WAITING/BUSY HIC
____ _ _ _ IF UNIT CHECK
~H~-___________________~,._____ __. .______ ~i~_____~________ _______________ FRAME BUFFER(7~ = ERR HICFRAME BUFFER(7) = SUP END Hl~:
. .
FRAME BUFFER~8~ = SS ERRMESSAGE COUNT = 8 DO FOR I = 9 TO 15 _______________________________________ FRAME BUFFER(I) = SENS REGISTER(1-9) FRAME BUFFERtl6) = SUP END HIC .
. MESSAGE ~:OUNT-- 17 _ RETURN

~;17Uro 0-1 r. Fl~wchor~ of CLEAR LED~ssp nl~m~r~
. SAU LOCKS = INPUT(SAU LOCK PORT) .
SAU LOCK ERROR = FALSE
SSP NUMBER =
.___________________ _________________ __________________ __________________ _ IF SAU LOCKS(5) = O IF SAU LOCKS16) = 0 IF SAU LOCKS(71 = IF SAU LOCKS(8) = O
l ~EN_____E ~E______~ ~ E .SE_____~ ~L ___E SE_____~ tl~N_ ___E ~E______ ERROR-- MASTER SAU LOC.Y MASTER SAU LOCK MASTER ERROR-- MASTER
TRUE BIT LOCK TRUE BFIFT LOC~ TRUE BFIFT--020K TRUE BFIFT L010 RETURN RETURN REIURN _ RETURN
. ....... .. --..... .............. ............. ............... ............ - .. --.... .............
HARDWARE COMMAND ( MASTER BIT LOCK FF, SAU LOCK PORT ~ -(Se~ Figur~ ~34~ -:...................................... ...............................
IF HARDWARE ERROR
l -J~N______________ _____________________________________________~ .~i~________ SENSE REGISTER~O) = EQUIPMENT CHECK SENSE
P10 ERROR--TRUE . .
.. ___ CODE ADDRESS = PC ADDRESS
_ MEMORY ADDRESS = SAIJ LOCK PORT
_ -RETURN .
_~ ~
SAU LOCKS = INPUT~SAU LOCK PORT) _ _ , .
IF SAU LOCKS~5 to 8) ~LAND~ MASTER BIT LOCK FFIî to 4~ NE O
l ~EN __ _ __ __ _ _ _ _ _ _ __ ___ ___________ __ __________________________ __~E SE_ _ ___ _ SENSE REGISTER~O) = E~UIPMENT CHECK SENSE
_ REGISTER ERROR = TPIUE
CODE ADDRESS = PC ADDRESS
_ _ _ F~ETURI`I

O

~i~uru O- t2. Fto~churt of CLMfJ_SAU_LOCK
. HARDWARE READ SELECTOR = INPUT~HARDWARE READ SELECTOR POFIT(4 _ _ TABLE_ADDRESS = COMMAND_WORI:)11) _ _ IF TABLE ADDRESS >-`15 T~E _________ ____ ______ _____ _______ . TABLE_Al)DRESS_OUT_OF_RANGE = TRUE
_ -- .
IF SSP_APPLICATION TABEL(TABLE _ADDRESS)(UNASSIGNED_BIT) NE O
I~ ___________ __ _ ____ ___ ______ ______ _ . APPLICATION_UNASSIGNED_TO_SSP = TRUE
__ .
. IF SENSE_REGISTER11) > O
ItlE~I ______ __ ~S~__ ___ UNIT_ CHECK = TRUE .
. I
CODE__ADDRESS--PC_ADDRESS
SENSE_REG1STER(O)--COMMAND_REJECT_SENSE
. RETURN
_ _ ~
IF (REQUESTING_SSP_NUMBER = SSP_APPLICATION_TABLE (TABLE_ADDRESS)I3 to 4)) SAU LOCK _ DUAL _ ACCESS _ 01 AND ~RE~UESTING_SSP_NUMBER = O OR
REOUESTING_SSP_NUMBER = 1)) OR .
SAU _ LOCK_DUAL_ACCE5S_23 AND (REaUESTlNG_SSP_NUM8ER = 2 OR
FIEQUESlING_SSP_NU ~,~1 = 3)) ___________ ItlE~I____ ___ __ _ __ _ _ _ __ __ __ _ _ ___ _ __ __ _ _ _ _ ~ _ ._ . _ __ _ _ SSP APPLICATION TABLE~TABLE ADDRESS)ISAUUNlr_CHECK = TRUE
LOCK BIT) = O _~_ ;................................ UNAUTHORI7ED_SSP = TRUE
SAU LOCK CHECKS(ssp application ~able(tab1a _ address~3to4)) . CODE_ADDFIESS--PC_ADDRESS ~Ser~
:......................... .... _ SENSE REGISTER(O) NE O
I~L _____ __ ___ _______________ _ EL~E__SENSE_REGISTERlo) =
ABOPIT . COMMAND_REJECT_SENSE
_ ~
RETURN

tiyure ~13. flou~ch~;t of CLE~ ST MODE
DO FOR 1:_ O TO 15 . ______________~.__________________________________________________________ IF ANY SAU Ll:)CK OF SSP APPLICATION TAELE IS SET
I~E~ __ ________ __ __________ __ _ _ __ ___ _____ ___ ELSE ___ ___ SENSE_REGISTERIO) := COMMAND_REJECT_SENSE

UNIT_CHK = TRUE .

CODE_ADDRESS = PC_ADDRESS (See Figure 0-52) .

SAU_LOCK_BIT_SET = TRUE

RETURN
,.. ....................................... ,.. ,... ,.. ,................ ............... ~
OUTPUT(ZERO_BYTE,PARTITIONING_REGISTER_CONTROL_PORT) .(See Figure 0-50) HARDWARE_COMMANDlPULSE_ALL_COMMAND, PA~lTlTlONlNG_REGISTER_CONTROL_PORT) .(See Figure 0-34) :.. ,.,,.. ,.. _.,.. _............................. ,........ :
IF HAFIDWARE_ERROR
I~~ ___ __ _ ______ _ _ __ __ _ _------ LS~
SEN5E_ REGISTERI01 = EOUlPMENr._CHECK_SENSE
_ . _~ , PlO_ERROR = TRUE
~ _ CODE_ADDRESS = PC_A[)DRESS (See Figure 0-523 . .
MEMORY_ADDRESS = PARTlrlONlNG_REGISTEFI_CONTROL_PORT .
..... ~ ... : ................ ,, ... , AEIORT (See Figure ~1) .

RETURN

~ q~

fiiyvr:~ O- 14. ~7owchd rr of COAfMA~17 RECI~IKED
_ .
I)DLC COMMAND SPECIFIES:
___________________ _______________~___ __________________ _________________ CI~SSONNECT EXCHANGE ID RECEIVE READY OR TEST RECEIVE NOT READY
............................. ............................. ........ -......... ...........................
EXECUTE DISCONNECT EXECUTE EXCHANGE 1~ SEND RECEIVE READY . EXECUTE TEST
COMMAND ~See Figure COMMAND ~See Finure (See Figure ~87~ : COMMAND ~See.
1) 24) . ~27) . . Figure ~26) UDLC COMMAND SPECIFIES:
_________________________ ____ _______________ ___ _______ _________________ NFORMATION SET NORMAL FIESPONSE OTHER
MODE
........................ ----SEND RECEIVE READY ~See EXECUTE SET NORMAL . SENSE REGISTER(O) = DATA
Figure 0-87) . RESPONSE MODE COMMAND CHECK
...................................... ~See Fi~ure ~25) .'.~ ...................................... , . .
. EXECUTE COMMAND ~See . AMBIGUOUS DATA = TRUE
Figure O-Z2) . .
: :
. . . . C:ODE ADDRESS = Pl::
. . . ADDRESS
. . ... ;.. ~
. . . . ABORT (Se0 Figure ~1) ,,,,,___ .. :................ : :.. _. ............ :
RETUFIN
__ __ figure~t~i. tio~chdrtofCOMECrABLEMEMORrER~OR
SENSE REGISTER10) = EQUIPMENT CHECK SENSE

CORRECTA~LE MEMORY ERROP~ = TRUE

CODE ADDRESS = PC ADDRESS .
.
MEMORY ADDRESS = ADDRESS POINTER

.SYNDROME = O
. --. C-R SBE COUNTER
............. -LOOK FOR SENSE PENDING ISee Figure~47) . .... .............................................
RETURN
_ ' -Fi3uro ~16. rrowchart o~ cOMEcr Ecc/memorJ~ oddrossJ
___ READ DATA AT MEMORY ADDRESS
_ REWRITE DATA AT MEMORY ADDRESS
. . _ , CLR ECC SBE COIJNTER

READ DATA AT P~EMORY ADDRESS
' - IF READ DATA NE WRITE DATA
I~E~L_________ ___ _ ____ ___________ __ _______ __ _ __ ____ _ lSE________ UNCORRE(`.TAB~F MEMORY E~ROR = TRUE
.
CLR ECC SBE C:OUNTER . . . .
, . .
RETURN
' . , -- . `~
. IF ECC SBE COUNTER NE O
~I~E~L_________ ___ _ ___ _ -_ ------------------------------ El~ E_ __ _ _ _ _ CORRECTABLE MEMORY ERROR = TRUE .
_ .
CLR ECC SBE COUNTER
_ _ _ ~ .
RETURN

. `

~q~ ..

FiglJr~ ~ J J. Ftowch~rt of ECC TEST
CLEAR SBE COUNTER
. ECC ADDRESS = 27F8 .
READ ECC ADDRESS
.. _, .
IF SBE COUNTER NE O
It~E~_~ ________ .L~____________________ IF SYNDROME TRAP Et:~ 64 ECC TEST ERROR
I~EN ______ __ ________ L~E __________________ . (See FigureO-20) ADDRESS TRAP EQ 27F8 ECC TEST ERROF; .
ItlEN_ ~SE _______ __ __ ____ ~See FigureO-20~ : :
: : ECC TEST ERROR : . .
. (See FigureO-20~ .
~_ :................ .. . ... .
CLR SBE COUNTER
__ __ ECC ADDRESS = 27F9 _ .
- READ ECC ADDRESS
IF SBE COUNTER NE O
- TtlE~I _ _ __ _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ __ _ _ _ _ _ _ _ _ __ _ __ _ _ _ ____ _ __ _ ~S__ _ _ _ __ _ _ _ _ _ __ __ _ __ _ ItlE~ _____ _ _-_------------- ELSE _____ ~See FigureO-20) ADDRESS TRAP ECI 27F9 ECC TEST ERROR .
..... -.... -.. -.... - : ~See Figuret) 20) : : .
. l ECC TEST ERROR . . . .
l: lSee Fi9ureo-2o) : : . .
CLR SBE COUNTER
. ECC ADDRESS = 27FA
___ _____ READ ECC ADDRESS
___ IF SBE COUNTER NE O
1~~_______ __ __ __ _ ___ __________ __ _________ ~_____ ___ _________ SYNDROMF TRAF EQ 34 E(:C TEST ERROI~
I~L_______ ______________ ~L~E ___________________ - lSee Fi9ureo-23 ~DDRESS TRAP EQ 27FA ECC TEST ERROR , .
I~E~J ECC TESr ERROR ~See Figure~20~ . .
: : ~Sea Fi~3ureO-20) : : . .
:............... : :......... _. , .........

* ~ flowchart continued on fi~ureO-1B**

,~' ;' '7 - Fi~ur~ O-t8. 170wchJrt of ECC r~ST~p~rt 2 Of 3/_-r _ .
CLR SBE COUNTER
_ _ ECC ADDRESS = 27FB
READ ECC ADDRESS
IF SBE COUNTER NE O
T~E~_______ __ ___ _ ________ _ _ EL~E ____ _- ...... -I~E~____________ ___ _______ ~SE_ _ _----_---------- ISee FigureO-20) ADDRESS TRAP EQ 27FB ¦. ECC TEST ERROR .
ItlE~J ELSE_______ _.. .___ .-- 1. lSee Figure~20) : .
. : ECC TEST ERROP . .
. ISeo FigureO-20~ : : : : .
~, :.. ,............. :............... : _............... .
CLR SBE COUNTER
_ _ _ ECC ADDRESS = 27FC
READ ECC ADDRESS
. _ IF SBE COUNTER NE O
I~E~_______ __ ______________________________________ ~L~E____________________ SYNDROME TRAP EQ 68 . ECC TEST ERROR
I~E~_______ _ ___ _________ ,LSE _________ ___ __ (See FigureO-20) ADDRESS TRAP EQ 27FC ECC TEST ERROR . .
I~E~_ ECC TEST ERROR . ~See FigureO-20) . (See Figure~20) . . . . .
:.............. : :.............. ...... .... -.. -:
CLR SBE COUNTER
___ . _ ECC ADDRESS = 27FD
. ~
READ ECC ADDRESS `
IF SBE COUNTER NE O
I~E~_______ _ __ ___________________________________ LSE _________ 1~~__ _ ___ ________ ___ LSE_____ ___ ............. .. - ISee FigureO-20) ADDRESS TRAP EQ 27FD . ECC TEST ERROR . .
ltlEI~I EL~_ .. - -.. -.... tSee Fi9ure~2o) ECC TEST ERROR : : : :
. ISee FigureO-20) . .
~ :............... :.... _ ......... :............... .
** flowchart continuad on ~i~ure~l9~
, , .

~ ~g ~

Figuro (t- 19. nowch~rt of ECC JEST ~p~rt ~ of 3J' CLR S~E COUNTEP~
.
SBE COUNTER CLR = O
_ ECC ADDRESS = 27FE

READ ECC ADDRESS
.
IF SBE COUNTER NE O
ltlEN_______ _____ ___ __ __ __ ______ ________ _______ ~EL~E_ ___ ______________ SYNDROME TRAP EQ 3~ ECC TEST E9ROR .
Itl~J_ ~S~ . . (See FigureO-20~ .
__ _____________________ ................................... , . I
ADDRESS TRAP EO 27FE ECC TEST ERROR . . .
ItlE~_ EL~E____ _(See FigureO-20) :
. ECC TEST ERROR . . . .
. (See Figure~20) . . .

CLR SBE COUNTER
' ._ ECC ADDRESS = 27FF

READ ECC ADDRESS
_ __ IF SE;E COUNTER NE O
I~E~__ _______ __ _ ________ ______ _____ _________ EL~E_ _ _ SYNDROME TF;AP EQ 7C ECC TEST ERROR
~J ~ E . ~See Figure~20) T~, _______ ___ __ _____ __ ~........... -.-.. -.. -... -.. -.- .
ADDRESS TRAP EQ 27FF . ECC TEST ERROR . .
I~E~ ~ ~See FigureO-20) .
:._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . . .
.ECC TEST ERROR . . .
. (See Fi~ureO-20) . . . .
~, :............... : :.. ,............ ..................................
RETUFIN

., ~igur~ ~20. f70wch~r~ of ECC rEsT ERflOR
_ , .
SENSE REGISTER(O) =. EQUIPMENT CHECK SENSE
. , _ __ . .
ECC ERROR = TRUE
_ CODE ADDRESS = PC AD;)RESS
_ . . .
MEMORY ADDRESS = ECC ADDRESS .
. '-SYNDROME = SYNDROME TRAP
-.. ;....... :
: LOOK FOR SENSE PENDING
~See FigureO-47) :.. ~............................. :
RETURN

~1~ ' ' ' ' `i~
vr~ ~2 ~. Flowch~rt of ElJ_ CW~CK
.. ~"~ _ . -' ENTRY _ PU;!`ITER = .
TABLE_ADI)RESS - Slr_MAS_ENTRY_NUMBER(TAEILE-_ADDRESS) _ _ _ IF THE
SiT_PARTITIONING_CONTROL_FLAGSlENTRY_POINTER)(EU_BIT~= O
.It!~l __ _ _ _____ _ _____________________________________________ ~LSE ______ RETURN .
_ - _ _ FIRST = TRUE
- .
DO FOR I = O TO 3 ________________. __ _____________________ ___________________ ___________ FLAGS = .
SiT_PARTITIONING_CONROL_FLAGS~ENTRY_POlNTER~i3 ____ DO FOR J = O TO 3 _______________________________________________ _._____________.____ SHIFT FLAGS ONE BIT POSITION TO THE LEFT FOR TEST
. .
IF FLAGS(3) IS SET
I~EN _ _ _ __ _ _ _ _ _ _ _ __ _ _ _ _ ____ _ __ _ ___ _ _ _________ _ ___ ___ _ ____ __ EL~;E_ _____ IF FIRST = TRUE
ItiEN_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - - - - - - - - - - - - - - L~iE_ _ _ __ _ .
STATE_COMPARE = . .
IOP_STATE_TABLE~SIT_IOP _NUMBEI~ENTRY_POINTER+I, .
_ :
FIRST = FLASE _Y_ IF STATE _ COMPARE IS NOT EQUAI TO
IOP_STATE_TABLElSlT_IOP_NUMBER(ENTRY_POI~ ~L~ ÉJ)3 EXCI.USIVE_USE_ERROR := TRUE .
. _ _ .
RETURN
_ . Y ~
IF SIT_PARTITIONING=CONTROL_FLAGS(ENTRY_POlNTER~i+1)~MAS_1)--O
RETtJRN
_ ~
MAS_ENTRIES_GT_4 = TRlJE

RETURN

.... .

~igur~ O-ZZ. Flowchdrt of EX~CUTE_COMMAND fip~rt 1 of 2 COMl\fiAND END PENDING = TRUE
IF COMMAND_WORD~O) SPECIFIES: .
_ _ _ _ _ _ _ _ _ _ _ ~ _ _ _ _ _ _ _ _ _ _ _ . _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .COMMAND COMMAND SAU RESERVE COMMAND
WRITE CONTF;O STORE READ CoNTRoi STORi-. SAU RESERVE
See Figure ~lO~) ~See Figure ~-58? (Se Figure ~77) . . .
RETURN
~ _ IF COMMAND_WORD~O) SPECIFIES:
_________________________ _________________________ _________________________ SAU RELEASE COMMAND WRITE SSP HISTORY READ SSP HISTORY
SAU RELEASE . WRiTE SSP HISTORY . Ri-AD SSP HiS roRY
~See Figure 0-76) . ~See F;~ure ~1n~) . (See IFigure 0-64 ................................ ..........
RETURN
_ _ .
IF COMMAND_WORDlO) SPECIFIES:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .. _ _ _ _ _ _ _ _ _ _ _ _ _ _ .. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ... READ ID WVRD O COMMAND READ ID WORD 1 COMMAND SAU RESET COMMAND
REAb ID WORD O READ Ib WORD j gAu REsEr ¦ -~See Figure ~61) ISe~ Figure ~62) . . (See Figur~ ~7S) ................. _ .................................
RETURN
IF NOr MICROCODE LOADED
IHE~I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~. _ _ El.SE_ _ _ _ _ _ CONTROL STORE NOT LOADED. = TRUE
___ ._ _ __ CODE ADDRESS = PC ADDRESS
____ IF SIT_IOP_NUMBER)159 3) = X FF I.SE_ T~N___ _ _ . ----------------------- _ IOP NUMBERS NOT LOADED := TRUE .
. .
CODE ADDRESS = PC ADDRESS .
~, IF SENSE REGISTER(1) = û
It~E~ __ __ _ _ _ _ LSE_ _ . SENSE REGISTER(O) = COMMAND REJECT SENSE
. UNIT CHECK = TRUE
. __ _. _ : RETURN
_ -** flowchart continued on ~ Jro 0-23 ~

Fi~ut~ O-Z3. Flo~vch~rt of EXECUrE_ COMMAMD ~ In 2 o~ y _ ' _ IF COMMAND_WORD(O) SPECIFIE5:
_ ________~________ ~__________________ _~________________ . ________________ . ADD SUBSYSTEM PIEMOVE SUBSYSTEM IOP NUMBEFi INTERFACE TAEtLE
COMMAND COMMANI:) COMMAND COMMAND
............................. ,....... :.... :WRITE SUBSYSTEM . READ SUBSYSTEi~i .
ADD SUBSYSTEM REMOVE SUBSYSTEM I IOP NUMBER INTERFACE TABLE
. (Ser~ Figure ~3j . ISee Figure 0-70) ¦. lSee Figure (See Figure . . . . I- 0-1051 . 0-67 - IF COMMAND_WORD(O~ SPECIFIES:
_______ ___________ ________________ __ ______ _______ ___ _________________ WP~ITE IOP STATE READ IOP STATE WRITE SSP NUMBER READ SSP NUMBER
COMMAND . COMMAND COMMAND COMMAND
............................. ............................... ............................ ...........................
- WRITE IOP STATE READ IOP STATE . (See Figure . ~tEAD SSPFjNU~ -~See Figure ~}101) ~See Figure ~631 . 0-104~ . 0-65) IF COMMAND_WORD(O) SPEC!FIES:
___________________ ________~_____ ____ ___________ ______ _________________ READ BCTS INTERFACE SET TEST MODE CLEAR TEST MODE
. .READ SPI COMMAND COMIUAND COMMAND COMMAND
..... -...... - ............. ............................ ............................
......... . READ BCTS INTERFACE. SET TEST MODE CLEAR TEST MODE .
~Se~ Fi~ure 0-66) (See Figure ~91) . - ISee Figure .
_ .
IF COMMAND_WORDlO) SPECIFIES:
_________________________ __________ _____________ _________________________ l SET SAU l.OCK COMMAND CLEAR SAU LOCK COMMAND OTHER
SF.T SAU LOCK Cl.EAR SAU LOCK UNIT CHECK = 7RUE
(See F;gur~: 0-90). . (See Figure ~12) .
. . . .SENSE REGISTER(O~ =
. . . .COMMAND REJECT SENSE
. . . . . ., . . . .UNRECOGNIZED COMMAND
. . .=TRUE
. . . .
. . . .CODE ADDRESS = P{: .
. . .ADDRESS
:................. :
FtETURN
__ _ _ Fi~9urLl ~Z4. F/owchDr~ of EXECLJrE DlSCONNECT COMMAND
MODEIREQUESTING SSP NUMBER) = DISCONNCT MODE
...................... ,.. ,.... ,,,.. ,.,.. ,.. ,.. ,,,.. ,............... ~
SEND UNNUMBERED ACKNOWLEDGE ISee Figure ~88) ' :............ ... ..... ..... ..... ... ... ..... ................ ...... .
RETURN

Fi~uro ~25. Flowch~n af EXECUTE SE7 llOIqMAL f1FSPONSE MODE COMMAND
.
OU I PUl- r~ECElVE VARIABLE = O

OUTPUT SEND VARIABLE = O
_ _ MODE(REQUES~ING SSP NUMBER) = NORMAL RESPONSE MODE
.. .......................................................................................................................
. SEND UNNUMBERED ACKNOWLEDGE ~See Figure 0-88) : .... .............. .
RETURN

riOur0 ~26 Flowchort of EX~CurE TES~ COMMAf/D
.. , .. , .. : .. --..... , .... , .. , .... , .... , .. , ............ ;
SEND RECEIVE READY (See Figure ~87) :..... ,...................... :
RE~URN

FiDuro ~Z7. Flow~,h~tt of ~ECUJ~ EXCHANGE ID COMMAND
. - .. - .. , ...... ..- .. - ....... : ................ - .. I
SEND RECEiY READY (See Figure {) 87 F .................................
RETURN

~ < .

Figuro ~2~. FlowchDrt of F,41JL r DETECT
__ _ SBE COUNTER = INPLITISBE COUNTER PO~

IF SBE COUNTER NE O
1~~__________ _____ _ ________ _________ _____________________ _ ____ L~E__ SYNDROME~4 to 8) = INPUT(SYNDROMIE PORT)11 to 5~
. .
MEMORY ADDRESS ~1 to 8~ = INPUT(ADDRESS TRAP PORT i\ASB) . ~ , --.
MEMORY ADDRESS l9 to 16) = INPUTIADDRESS TRAP PORT LSB) .
_, . , .
SENSE REGtSTER[O) = ECIUIPMENT OHECK SENSE .

IF MEMORY ADDRESS GE RAM START ADDRESS .
lt!E~I _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ELSE_ _ _ _ _ _ _ _ _ _ _ _ - - - - ~ - - - - - - - - - -............... -.-........................ .
CORRECT ECC(MEMORY ADDRESS)(See UNCORRECTABLE MEMORY EF;ROR = TFIUE
. . Figure 0-16) . . .

LOOK FOR SENSE PENDING ~See Figure ~47) :.................................. ........... .......
RETURN
. _ _ __ _ Figure ~Z9. ~iowch~r~ of FMME CIIECI~S
.IF POLL BiT IS NOT SET
I~E~__________ __ ____ _ _____ __ _ L~E________ REQUEST RECEIVED = FALSE
RETURN
_ . W
IF II`ITERFACE STATUS =i MISCOMPAP~E
ItlEU__ ___ _____ __ ______ ____ _ ELSE_______ ¦
. REQUEST RECEIVED = FALSE .
~ _ . . .
RETURN , . . ~
IF INTERFACE STATUS = RECEIV OVERRUN ERROR
I~E~ _ ____ _ _____ ______ ____ ____________________ _______ ELSE_______ REQUEST RECEIVED = FALSE
. '. . -RETU RN

IF INTERFACE STATUS = CRCJFRAMING ERROR
I~EU ____________ ------------------------------------------------ ELSE___ ____ REQUEST RECEIVED = FALSE . .
_ _ _ .
RETURN

IF INTERFACE STATUS = NU END FLAG RECEIVED
ItlE~J ___ _ _ _ ..__ _ _ ____ __ - - -- - - - - - - - - --- -- - - --- - - - -- ----- --------- - ~L~iE____ ____ REQUEST RECEIVED = FALSE
, ; PIETLIRN
_ . ~ .

Four~ ~n Flowcha~ o~ Fff~4ME ~fJ~CT CH~C~S /p~rs J ~If 2) FFlAME F;EJECT l~ESPONSE(REQUE~TING SSP NUMBER,3) = O
IF IJDLC COMAND = INFORMATION or RECEIVE READY or RECEiVE NQT READY or SET
NO MAL RESPONSE MODE or DISCONNECT or EXCHANGE ID or TEST
I~E~_________ ~S~___________ ___ __ __________ ______ _ ___________ _________ . FRAME REJECT RESPONSE(REOUESTING SSP NUMBER ,3) - CONTROL FiELD
. ERROR
. .. ................ ,.. -. . GENERATE FRAME REJECT RESPONSE ISee Flgure 0-32) . . SEND FRAME REJECT ~See Figurs 0-35~ .
. :............... ....., .RETURN .
. ~ _ . .
IF UDLC FORMAT = INFORMATION OR SUPERVISORY
~H~L_____________ _____ _______________________________________ _ LSE______ VARIA8LE REVERSED = UDLC COMMAND ~6 TO 3~
VARIABLE REVERSED(1) :=: VARIABLE REVERSED[3) .
, _ IF VARIABLE REVERSED IS NOT EQUAL TO OUTPUT SEND
. . VARIABLEIREQUESTING SSP NUMBER) LSE
::: I~E~_________ ____ ____ __ _ _ _ _________ ________ _ ___ - FRAME REJECT RESPONSE(REQUESTING SSP NUMBER,~) = receive . . . .
variable error . :
,.............. ,.. ,.,,,,.,,.. ,,,.,,.. ,.. ,.. ,....... .
GENERATE FRAME REJECT RESPONSE ~See Fi~ure ~32) .
. SEND FRAME REJECT ~See Fi~ure 0-85) .
:.............. .......... .
RETURN .
_ _ =
IF UDLC FORMAT IS NOT EQVAL TO INFC)RMATION
ItiE~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~L~iE_ _ __ _ _ IF RECEIVED B~E COUNT IS GREATER THAN 3 I~E~L_________ ________________ ___ _ __ _____ ____ __ ~SE____ _ FRAME REJECT RESPONSE~REQUESTING SSP NUMBER,3) = .
INFORMATION FIELD ERROP~ .
.......................................... ,.. ,,,.. ,,,,,,,.. ,,.. ,,,.. ,.. ,....... :
~iENERATE FRAME REJECT RESPONSE lSee Fi~ure 0-32) .
SEND FRAME REJECT (See Fi~ure 0-85~ .
:............. ,.. ,.. ,,.,,., ,................... .., RETURN .
. ~ w **** flowchar~ con~inued on figure 0-31 ****
,."

. . .

Figurr~ ~31. ~/owch~t of MAME ffEJECT C/tEC~S /pDrt 2 of y _ _ .
IF IN1'ERFACE STATUS = QVERFLOW ERROR
T~E~_______________ ___ _ _ LSE________ FRAME REJECT RESPONSE(requesting ssp number,3~ = overfl~w error . .. --.............. ,.. ,.,.. ,,,,,,;.. ,,,,,.,,.. ,............. , . ' . GENERATE FRAME REJECT RESPONSE ~See Figure (~32) .

SEND FRAME REJECT lSee Figure ~85) , , . .
.. , ............................... ....~, I
' RETURN
. - - ,- . . . .' Fgrw~ ~32. F~OWCDrt of GENEM TE FPAME PEJ~C J A/ESPONSE

FRAME REJECT RESPONSElREUUESTlNG SSP NUMBER,1~ = UDLC COMMAND
...
FRA~E REJECT RESPONSE(RE(:~UESTING SSP NUMBER,2)11 ~O 4) = OUTPUT SEND
VARIABLE~REQUESTING SSP NllMBER~
_ _ . __ FRAME REJECT RESPONSEInEQUESTING SSP NUMBER,2~6 TO 8~ = OUTPUT RECEIVE
VARIABLEIREQUESTING SSP NUMBER~

RETU RN

Fi~ur~ 0 33. tlowchi~r~ of GENER4rE SYST~M SESSION POINTE~S
ERROR FLAG = FALSE, SYSTEM SESSION POINTER = 3, HICS FOUND = O
_ _ _ DO WHiLE SYSTEM SESSION POINTER LElFRAME BUFFER POINTER- 12) ________~_________________________________ _______________________________ FRAME BUFFERlSYSTEM SESSION POINTER~Il TO 4) SPECI,'IES:
_____________________________ _____________________________ ______________ ASSURANCE UNIT HiC SEGMENT HIC OTHER
IF AU HIC FOUND IF SEG HIC FOUND ERROR FLAG =
. ~I~L _ _ _ _ _ _ _ _ ~t~ _ ___ _ _ _ _ _ _ _ H~N _ _ _ _ _ _ _ _ _ _ .1,~ _ _ _ _ _ _ _ _ _ _ TRU E
ERROR FLAG = AU HIC FOUND = ERROR FLAG = SE(i HIC FOlJND
TRUE TRI)E ' TRUE = TRUE CODE ADDRESS
CODE ADDRESS AU HIC POINTER CODE ADDRESS SEG HIC POINTER
= PC ADDRESS . = SYSTEM = PC ADDRESS --SYSTEM RETURN
` SESSIOI`I _ SESSION `
.RETURN POINTERRETURN POINTER
SYSTEM SESSION POINTER _ SYSTEM SESSION POlNT'n =
SYSTEM SESSION POINTER ~ 3 SYSTEM SESSION POINTER + t FRAME BUFFER~SYSTEM SESSION POINTER)~1 TO 4) SPECIFIES:~CASE CONTtt`~UED) ___________________________________ ______________________________________ . , , SUP HIC
... , . IF FRAME BUFFER~SYSTEM SESSION POINTER)(5T081 _ END HIC
. .~N__ _ _ _ _ _ ~SE _ _ - - - ----- --- -SUP END HIC POINTER--SYSTEM SESSION IF FRAME BUFFER(SYSTEM SESSION POINTER ~ POINTER)~5TO ~PAD HIC
_~NL___ _ _ _ __ _ __________.
'~ItL L~ IF AU HIC FOUND TRUE SYSTEM SESSION
. _ ____________________________ POINTER =
. ERROR FLAG = TRUE CODE ADDRESS = SYSTEM SESSION
. CODE ADDFIESS = PC ADDRESS PC ADDRESS POlNrER ~ 1 :
. , RETURNRETURN
~ _.
IF NOT SEG HIC FOUND
~I~L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . _ _ 3 ' ~r IF FRAME BUFFER(AU HIC POINTER)15T08) '~F~N_ I`tE ~SE_______ ~ROF~ FLAG = TRUE SEG HtC POINTER = .

CODE ADDRESS = PC AU HIC POINTER
ADDRESS
RETURN
_ . _ _ ERROR FLAG = TRUE, CODE ADDRESS--PC ADDRESS
RETURN
__ .
., .
.

~igllro ~34. }lowchDr~ of ~fARDWARE_COMMAND/s;gn~l,si~nDI OL~tpU~ portJ
ERROR RETRY := O
, HARDWARE_ERROR = TRUE
_ _ ERROR_RETRY := ERROR_RETRY ~ 1 .
OUTPUT_DATA := INPUT[siynal_output_ poTt) OR~ signal ........................................................................................... ~
OUTPUTIOUTPUT_DATA signal_output_port) ~See Figure 0-50~ ~
:..............................................................................................................
......... -..... :.:.................................... , VERIFY(OUTPUT_DATA signal_output_port) (See Figure 0-99) .
~ ... _ ............ ~ ...................... , .. _ REPEAT WHILE HARDWARE_ERROR AND~ ERROR_RETRY IS LESS THAN 3 IF HARDWARE_ERROR
IHE~J_____________________________________________________________ I ~E________ . . - RETURN
. _ __ , ERROR RETRY := O

HARDWARE ERROR = TRUE
._ __ __ ERROR_RETRY := ERROR_RETRY -t 1 ___ . ' .
OUTPUT_DATA := OUTPUT_DATA XOR signal .................................................................................................................. , OUTPUT~OUTPUT_DATA signal_oulput_port) ~See Figure ~50) .
.:::-:::::::::::::::: :
YERIFYIOUTPUT_i:)ATA signal_output_port~ ISee F;gure ~99) .. . . _ . . . . . . .. ._ . . . .. .. . .. . . ._ . . . . .. . . . . .... . . .. . .... . ...
REPEAT WHII.E HARDWARE_ERROR ~AND~ ERP(OP_RETRY IS LESS THAN 3 F~ETURN

G,~.^ ' f~L~r~ 0-35. Fl~wch~rt of lDLE
REPEAT
____________________________________________ ___________________________ LOOK-FOR SENSE PENDING ~See Figure 0-47) :.......... ; , ::::::::::::::::::::::::::'::' . FAULT DETECT ~See Figure 0-28) .
:.......... ..... ...
LOOK FOR OPERATOR CONTROL CHANGES ~See Figure 0-44) ~EaUEST RECEIVED _ TRUE; MESSAGE COMPLETE--FALSE, MULTliLE FRAME
MESSAGE = FALSE, READ DATA AVAILABLE = FALSE, SENSE REGISTER(0-6) = O, UN!T
CHECK = FALSE
LOdK FOR REQijESTiCONFlGURED UDi hUMBERS;UDLC TiMEoUT iSëe Figure;
:............................ .............................................
I~ IF REQUEST RECEIVED __ ______________ L~
............................................................. . , __ : FRAME CHECKS (S8e Figure ~29) - .
:.................................. ............................................... :
. IF REaUEST RECEIVED .
'rtl~L___, ., ,_. ,_, ,_,.,,_, ,.. ,_. ,-,, . ,, ,-, .,, .,, .,, .. -.. -.. -.. -.- .. -.-..... r-l,SE__ .
MODE CHECKS (See FIGURE ~49). , ........................................................................................ : :
IF REQUEST RECEIVED .
Tt!E~J_ _ _ __ _ ___ _ _ ___ _ __ _ _ _ _ __ __ _ _ _ __ _ _ _ __ ________ ____ EL~iE _ .
: FRAME REJECT CHECKS (See Figure ~30) . .
' -- - -' - - - ' - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - -- -- - - - - - - - -- --- - - -- - - - -- -1: : :
, IF REOUST RECEIVED ~ .
ltlE~ __ ___ _ __ ____-_----- - ------ ------------- E __ : :
l~~ IF UDLC COMMAND--INFORMATION L~iE__ . . . .
, lI;l~ORMArl~ F~ELD CHECK~ (Sëe F~bu;e : . . . .
0,.-36.) ,. ,, .,, ,, . ,. . . '.' . . .
I~U IF REQUEST RECEIVED_____ L~E . .. .
~51 . F
.. ... _ .. .. ... . ...... .... ~__ ~__ ~___ ~__ ~__ ~__ DO IF NOT MESSA(~E COMPLETE AND REQUEST RECEIVF.D
. ___ IF REQUEST RECEIVED LSE
I~ENL_______ _ _ __ ___ _ COMMAIYD END PENDING = FALSE .
-.................................. .. --' COMMANC) RECEIYED (See Figure 0-14~
G ...............................................................................
IF COMMAND END PENDING J.~E
ltl.~N_______ _ ____ ______ ______________________ _____ __ E __ IF tJNIT CHECK :
I~EkL______________ ___ ______~_ __________________ __ __ . .
ASSURANCE UNIT = FAIL ¦ ASSURANCE UNIT--CLEAR .
................................................. ~ .................... :
SEND COMMAND END ~See Figure 0 80) . .

SEN5E REGISTER~6) = O
_ _ , ~.--f Figur~ ~3f,. Flc~wchon Df JNFOf~!M JlON FIEI D CHf C~S
_ . _ VARIABLE REVERSED = UDLC COMMAND~ TO 4~
VARIA8LE REVERSED(l) :=: VARIABLE REVERSED13) _ _ IF VARIABEE REVERSED = OUTPUT RECEIVE VARIABLE(REQUESTING SSP NUMBER) I!~EN_ __ _ _ ___ __ __ ____ ___ __ __-- - __----- ~LS~_ --_- ---_ _- - ----- _-- ---_--- _ _-- -OUTPUT RECEIVE VARIABLE(REQUESTING SSP REQUEST RECEIVED = FALSE
NUMBER~ = OUTPUT RECEIVE _ VARIABLE5REQUESTING SSP NUMBER) ~ 1 RETURN
_ ERROR Fi AG--FALSE
,.................. --............ ;................... -SYSTEM SESSION Ci-lECKS ~See Figure ~95) . .
................ ...........................................................
IF ERROR FIACi Tt~EL~I_ _______ _ _ -- --------- -.SE_ __ ______ ___ _ _ _ . _. .. _ .. - .- .. ..- .....
TRUE PRESENTA;rlON CNECKS (See Figure 0-54 IF ERROR FLAG
. I~E~I__ ____ __ _______ L~E______________--~
PRESENTATION ERROR = IREQUESTING SSP NUt~BER =
.TRUE RESERVED SSP NUMBER) or 5COMMAND WORD(O~--SAU
It!EN. ~L.S~ RESET~
. SEND RFCEIVE NOT
.0-8 6) . ~REQUEST RECEIVED =

. RETURN
~ _ _ _ _ _ ASSURANCE UNIT = FAIL
_ ;
. UNIT Ci IECK = TRUE
.............................................................................................. ;
SEND RECEIVE READY tSee Figure Q-û7) . SEND COMMAND END (See Fi~ure ~80) :
:........... ................................................................. ,........... :
REQUEST RECE!VFD = FALSE
RETURN
. _ F;~uro ~37. Flowchnr~ of INITIALIZE 8CTS SPI INTEflFACE
.~
DO FOR I = O TO 127 .
. _________________________________________ _______________________________ R (iISTER ADDRESS--I .
............................................... ;.. -...... ....~
OUTPLlT ~REGISTER ADDRESS, . .
.PARTITIONING REGISTER ADDR~SS PORT) ~See Figure ~-51) . .

OUTPUT ~1 IEX OF
P~P~TITIONING REGISTER ADDRESS PORT) (See Figure 0-51) ' ' ' ' ! ............ .................
DO FOR I = 128 ro 159 _ _ _ . _ _ _ _ _ . _ _ _ _ _ _ _. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ REGISTER ADDRESS = I
,.................................................................................................................
. : OUTPUT ~REGISTER ADDRESS, PARTITIONING REGISTER ADDRESS PORT) tSee Figure 0-5 I) . ''.' .:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::'.. .
_ . .OUTPUT ~HEX 00 PARTITIONIN~ REGISTER ADDRESS PORT) ~See Figure 0-51) CLEAR TEST MODE ~See Figure ~13~ .

RETURN

FipL/to O 38, Flowch~r~ of /NtJl~LlZE Pl~port,i/o control~
.................... ,.. ,.. ,......... ,.,.. ,.... ,,.. ,.... --OUTPUT~PIO INTERRUPT VECTOR,por~)(See Figure ~50) .::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::i::::::::::::::::::::::::::::::::::-OUTPUT(PIO MODE,port)lSee Figure ~59) , .................. ...............................................................................................
................... :::::::............................. ................................;
,OUTPUT~i/o contr~I,por~)(See Figure ~50) OUTPUT(PIO INTERRUPT CONTROL,pott)ISee Figure ~50) ,-, . . :....... ................................................................. ....
., RETURN
.' . _ f;~ur~ ~39. fJowcl1ort of IHlrMLlZE ~;10_~ECEIVE
_ WRITE_REGISTER_O = CHANNEL_RESET

WRITE_REGISTER_4 = CLOCK MULTIPLIER,SDLC MODE,SYNC MODE ENABLE
,. I
VVRITE_REGiSTER_7 = UDLC FLAG (01111110) _ . .
WRITE_REGISTER 6 = UDLC ADDRESS
- - , .WRITE_REGISTER_1 = INTERRUPTS DISABLED

WRITE_REGiSTER_ 5 = TRANSMIT 8 BITS/BYTE,TRANSMIT DISABLED,SDLC SELECT
_ _ .
. WRITE_REGtSTER_3 = RECEIVE S BITS/BYTE,RECEIVE CRC ENABLE,RECEIVE ENABLE

WRITE_REGISTER_O = RESET RECEIVE CRC CHECKEFI

RETURN
_ _ .If;3uro ~a Flowth~rt of INlrL4LlZF S10 TFANSMIT

SEND AND RECEIVE SlO REGISTER O = CHANNEL RESET

SEND AND RECEIVE SlO RE~ISTER 4 = CLOCK MULTIPLIER,SDLC MODE,SYNC MODE ENABLE
. , - _ SEND AND RECEIVE SlO REGISTER 7 = UDLC FLAG ~01111110~
_. _ SEND AND RECEIVE SlO REGISTER 6 a UDLC ADDRESS
SEND S10 REGISTER 5 = TRANSMIT 8 BITSJCHARACTER,TRANSMIT ENABLE,REt~UEST TO
SEND,SDLC SELECT,TRANSMIT CRC ENABLE .

RECEIVE SlO REGISTER 5 = TRANSMIT 8 BITS/CHARACTER,TRANSMIT DISABLE,SDLC
S ELECT
_ _ _.
SEND SlO WRITE REGlSTEFl O =RESET TR~NSMIT CRC GENEFIATOR

RECEIVE SlO WRITE REGISTER 3 = RECEIVE 8 BlTStCHARACTER,RECElVE CRC ENAEILE, RECEIVE ENABLE
. - .
RECEIVE SlO WRITE REGIS1ER O--RESET RECEIVE CRC CHECKER
_ _ RETIJRN
_ . _ .

Fgur~ 0 4 r. Flowch~rt of INPUT
POP RETURN ADDRESS INTO H REG

POP l/O ADDRESS INTO B REG

MOVE l/O ADDRESS INTO C REG

INPUT INTO A REG FROM ADDRESS IN C llE~i . JUMP Tl:l RETURN ADDFIESS
_ Figvro ~42. Flowch~t of IOP _APPLrCArlOh~_ CHEC~
ENTRY_POINTER =T~BLE_ADDRESS - Sl J-_MAS_ENTRY_I`IUMBER(TAE LE_ADDRESS) _ , _ DO FOR I = O TO 3 _____________.________________________________,__________________________ FLAGS = SIT_PARTlTlONiNG_CONTROL_FLAGS~ENTRY_POINTER~I) . DO FOR J = O TO 3 __________. ___________________ ______________________________________ I

_ . IF FLAGS~3) IS SET LS~
T~~ _ ____ __ ______ ___________ _____________________ _ ~. __ _ IF THE IOP _ STATE_TABLE~SiT IOP_NUMBER~ENTRY_POINTER+I,J)) SPECIFIES: RESEF;VED, OFFLINE OR NEVER ASSIGNED
ItiE~ F . I
IOP_STATE_EFIROR := TRUE . . .
~ .
RETURN
__ _ ~ ~_ IF SIT_PARTITIONING_C:ONTROL_FLAGS~ENTRY_POINTER~ MAS~ O
1~ _ _ ___ _ ____ __ ___ ___ _______ .________ __ _______ l 5~ETURN

MAS_ENTRIES_GT_~1 = TRUE

RETURN

Fgurs (~43. Frowchor~ of LOOf~ FOR ACKNOWL~DGE~nror~c~ nurnb~r~
........................................................................................................................
. LOOK FOP REQUEST(;nter~ac~ numb~r,ack tim~out) ~S~e Fiyur~ 0-46) F
IF REQUEST RECEIVED
T~E~______________ _______ __ _____ _____ ____ _________ ____ __ ~LSE____ FRAME CHECKS ~See Figure ~29) :....................... ........... ..... _ -- IF REQUESr RECEIVED .
I~E~___________________________ ____________ ____________ LSE______ VARIABLE REVERSED := UDLC COMMAND[5 to 8) .
. . ..
\JARIABLE REVERSLLJ~ =: VARIABLE REV~ SED~3) .
_ . . .
IF YARIABLE REVERSED = OUTPUT SEND VARlABLElREaUESTlNG SSP .
NUMBERt ~ 1 .
ltiE~I_________ ____________________________________ ~L~iE______ .
. ~ . OUTPUT SEND VARlABLElREQUESTlNG SSP NUMBER) = . . .
OUTPUT SEND YARIABLE[REQUESTING SSP NUMBER) ~ 1 .
. .
ACKNOWLEDGE RECEIVED = TRUE . . .
_ _ _ __ . .
RETLIRN .
--_ _ ~
ACKNDWLEDGE RECEIVED = FALSE
_~ _ RETURN
_ __ .- . .
.. .

F/~ur~ O 44. F~owchort o/ L OOI~ f 0~7 OP~RA rOR CONTROL C/~ANG~S
.................................................. ;... .:... ,..... -SAU LOCKS = INPUT(SAU LOCK PORT) :.:....................... ..... ...... .............. :
IF SAU LC)CKS~5)= O AND PREYIOUS SAU LOCKS~5~ = 1 I~I ______________________ ____.___ _____________ _____________ EL~________ OPERATOR CHANGE = O
.....................................................................................................
MANUAL CEEAR SAU LOCK~OPEFATOR-CHANGE)tSee Figure 0-48) .. ...... :........ ............. :
IF SAU LOCKS~6)= O AND PREVIOUS SAU LQCKS16~
I~E~ _ ___ _ __ __ _ __ _ ________ _ ________________ __ LSE___ ____ OPERATOR Clt~NGE = 1 ................... ;.............. ' . MANUAL CLEAR SAU LOCK(OPERATOR CHANGE)lSee Figure ~4~) :...................... ..... ........ : _ _ IF SAU LOCKS~7~= O AND PREVIOUS SAU LOCKS~7) = 1 .
,-.ltlE~I ____________________________________________________________ LSE________ OPERATOR CHANliE = 2 -...................................................................................................
MANUAL CLEAR SAU LOCK~OPERATOR CHANGE)(See Figure ~8) .
..... .... .................. '.
IF SAU LOCKS~P)= O AND PREVJOUS SAU LOCKSI~) = 1 T~JU _ _ _ _ _____ __ __ ___ __ _ _____ __ LS~ _______ OPERATOR CHANGE = 3 .................................... :
MANUAL CLEAR SAU LOCK~OPERATOR CHANGE)~See Figure 0-4S~
:...... ,............................. ....................., '. ~
PREVIOUS SAU LOCKS = SAU LOCKS
-RETURN
.

F/Ru~ ;. FlowchDr~ of LOOI< FO~ POLL~int~r~co numbrr) ~
........... ,.,.. ,.. ,.,.. ,.. ,,,..... ,,.,,,....................... , . LOOK FOR REQUEST(interface n~mber,poll time~ut) (See Figure ~46) IF REQUEST RECEIVED
It!E.~.. . ____ . .. _ .. _. __ . .. .. . ... .. -__ . . _..-.-..-.. --- ---L~____ _ FRAME CHECKS (See Fi~ure 0-29) . . .
IF REIIUEST RECEIVED .
ItlE~I___.. ~ .. ....... _ _ _ .. _ . . . - - .. -.. - .. LSE______ FRAME REJECT CHECKS (See Figure 0-30) I .
.............................................. ;... _ ~ ~
RETURN
_ . _ ~ - . . .

~iguro ~}46. f lowch~rt o~ ~ 00~_FOf~_ ~EaVESr~ud/c number, rim~ur v~luDJ
.......................................................................................................................
INITIALIZE_S10_RECEIVE ~See F;gure 0-39) .. :........................................................................................................................
REQUEST TIMEOUT = timeout valu~
..
INTERFACE STATUS--O
--..........................................................................................................
- POLL_READ_~:HARACTER_AVAILABLE_STATUS (See Figure ~}53) :............. ....................................
REQUEST_READY = READ_CHARACTER AVAllABLE STATUS AND- udlc number _ REQUEST TIMEOUT = REQUEST TIMEOUT ~ 1 ________ _ ___________ _ __ __________ ______________________________ ___ DO WHiLE NOT REQUEST_READY AND REQUEST TIMEOUT NOT EQUAL TO O
. - .
. IF REQUEST TIMEOUT = O
Itl E~I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~I~S~_ __ _ _ _ _ _ REaUEST RECEIVED = FALSE
._ RETURN

. READ_FRAME ~See Figute ~59) ............................. ,.......... ... ,.. _ RETURN
__ __ -Fi~uro 0-47. Flowch Irt of L OOK f OR S~NSE Pf NDlNG
IF SENSE REGISTER~O) NE O
__________________________________ DO FOR l := O TO MAX SSP NUMBER
__________.______________________________________________ _____ REQUESTiNG UDLC NUMBER := UDLC NUMBER ARRAYfl) .

REQUESTING SSP NUMBER := I
........ ~ .......... , . SEND ArrENTlON ~See Figure ~79) .
_ .... :.. ............... .
_ : _ ___ SENSE REGISTERIO) = O ~ .

. RETURN

. . .
. ~ .
FiDI~r~ ~4U. flowchort of MANVAL CLf~R SAU LOCI~S/SSP ~JUMBEf~
__ DO FOR I = O TO 15 ____________________ ____________________________________________________ IF SSP APPLICATION TABLE~ 7 to 81= SSP NUMBER
IL~E~l _ _ _ - _ _ - - - - - - - - - - - - - - - - - - - - -- - - - - - - -- - - -- - - - - - -- ~LSE_ ___ . _ IF SSP APPI.ICATION TA~LE~ 51 = 1 It!EN_ _ __________ _______ _____ ___ ____ _________ .,I.S___ __ SSP APPLICATION TABLE (i~5~ = O .
_ ~ ~
RETURN
_ ~ , _ Fgur~ 9. ~lowch~rt of MOD~ CHECltS
IF MODElREQUESTlNG SSP NUMBER)--DISCONNECT MODE
ltlE~ ___ _ _ _ _ _ _ _ __ _ _ _ _ _ _ _ __ _._ _ __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - - - - - - - - - - - -- -- - -- - - I,~ E_ _ IF UDLC COMMAND = EXCHANGE ID OR SET NORMAL RESPONSE MODE
1~1_ _ _ _ _ _ _ _ _ _ __ __ _ __ _ _ _ _ _ _ _ _ _ _ __ _ El.~;E __ _ _`_ _ _ _ __ - - . - - .-.. ....
REQUEST RECEIVED = TRUE SEND DISCONNECT MODE ISee Figure .
. :........................ .
. . REQUEST RECEtVED = FALSE .
.
RETURN
, . ~ I
IF MODE(REQUESTING SSP NUMBER) = FRAME REJECT MODE
T~EU _ ___ __ _ ____ _ __ __ _ _ ------------------ ~L~E__ IF UDI.C COMMAND = SET NORMAL RESPONSE MODE OR DISCONNECT .
I~E~J _ _ ____ _ _ _ _ _ __ _ _ _ _ _ ______ __ ___ FLsE---- _ ___ _ __ ___ ____ _ _~_____ _ ~ _ I .
REQUEST RECEIVED = TRUE SEND FRAME REJECr (See Figure REQUEST RECEIVED = FALSE .
. RETURN
_ _ IF MODE(REQUESTING SSP NUMBER) = NORMAL RESPONSE MODE
. TtlE~ _____ __ ___________ ___ ____ ___ __ ___.__------------------ EL~E
IF SSP RESERVE
TtlE~ __ ELS~ ._ ---------------- .
IF REQUESTING SSP NUMBER = RESERVED SSP NUMBER R E EIVED TRUE
or UDLC COMMAND = INFORMATION EQUEST R C =
It!E~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ELSE_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ REQUEST RECEIVED = TRUESEND RECEIVE NOT READY . .
... ,..... .. .....
: REQUEST RECEIVED = .
... .. .... FALSE
RETURN .
_ ~
SENSE REGiSTER(O) = DATA CHECK
AMBIGUOUS 5~ATA = TRU
_ . _ REQUEST RECEIVED = FALSE
_ _ CODE ADDRESS = PC ADDRESS
,............... ,,,.. ,.,.. ,,,,,,........... -............ ., .
ABORT ~Se~ Figur~
:............... ,.,... ,,................................ _ ... . .

J

i$

~i~uro ~50. Flowch~rt of OUTPUJ(doto,por~
POP RETURN ADDRESS OFF STACK AND STORE IN REGlSrER PAIR HL
_ .
. POP porl OFF STACK AND STORE IN REGISTER PAIR DE

POP data OFF STACK AND STORE IN REGISTER PAIR BC
. , - .
MOVE DATA FROM B TO C

OUTPUT DATA IN REGISTER C TO PORT IN REGISTER D
__ _ __ _ figuro ~51. Flowchort of ouJpur AiJD_VEFlFY(rfot~,portJ
DO FOR 1:= 1 TO 3 .,.- . _________________________________________________________________________ .
. . . OUTPUT(data,port) ISee FiDure 0-50) .
... ..
........................................................................................................ ~
VERlFYldata,port) ISee Fi~ur~ ~39) ................................... ............................... .... ..........
IF NOT HARDWARE_ERROFl Itl~l_ __ ___ __________ ___ ___ ____________ __________ EL~iE________ RETURN .
__ _ _. . .
RETURN

Fi~uro ~52 Flowch~rt of f C_ADDRESS
POP TOP OF STACI( ~RETURN ADDRESS~ TO HL REGISTERS

LOAD PC REGISTER WITH HL ~RETURN ADDRESS) ... . .

~ O,ro ~53. tlowch3r~ of POLL~ C~Aa4CTfl'~_AVAILA6LE STATUS
READ_CIIARACTER_AVAILALE_STATUS = INPUT~SIO_OA_STATUS) MASIC FOR READ_CHARACTER_AVALABLE_STATUS
_ _ .
ROlATE LEFl- 1 BIT POSITION
SAVE_REGISTER--READ_CHARACTER_AVAILABLE_STATUS
- READ_CHARACTER_AVAILALE_STATUS = INPUT~SIO_1A_STATUS) MASK FOR READ CHARACTER_AVALABLE_STATUS
READ_CHARACTR_AVAiLABL.E_STATUS = READ_CHARACTER AVAILABLE_STATUS OR
SAVE
_ `
ROTATE LEFl: 1 BIT POSITION
SAVE REGISTER = READ_CHARACTER_AVAllABLE_STATUS
READ_CHARACTER_AVAILALE_STATUS--INPUT(SIO_2A_STATUS~ .
_ . .
MASK FOR READ_CHARACTER_AVALABLE_SrATUS
_~
RLAD_CHARACTER_AVAILAEILE_STArUS = READ_CHAFIACTER_AVAILABLE_STATUS OFI
SAVE .
___ _ -F1OTATE LEFr 1 BIT POSITION
_ _ SAYE_REGISTER = READ_CHARACTER_AVAILABLE_STATUS
READ_CHARACTER_AVAILALE_STATUS = INPUT~SIO_3A STATUS) MASK FOR FIEAD_CHARACTER_AVALABLF_STATUS
READ_CHARACTER_AVAILABLE_STATUS = REAI~ CHARACTER_AVAILABLE_STATUS OR
SAVE
RETURN
.

Fi~uro 0-54. flowchDrt of PRESENJANON CHECKS
iF FRAME BUFFER~SEG HIC POINTER~17) SPECIFIES FIRST
I~E~_______ __ _________ ____ ____ ___ _____ _______ __ ______ __ L~
. IF FRAME BUFFERISUP END HIC P~INTER ~ 1] = OUTPUT HIC OR IIJP~ HIC
1~~______ EL~E_ ______ _______---------------------------------------- .
. ERROR FLAS = TRl)E . .
. . ~ .
. CODE ADDRESS ~ PC ADDRESS .

_ RETURN .
_ ~ _~
- IF PARAMETER LENGTH LE 400~hex) T~E~ ____ ____ E~E________------------------------ .
MESSAGE COUNT = PARAMETER LENGTH ERROR FLAG = TRUE .
,. ' , .CODE ADDRESS = PC ADDRESS .
. ' . . _ . RETURN . .
_ _ __, ~
IF FRAME BUFFERISEG HIC POINTER~(8~ SPECIFIES LAST
It!E~J___ __ _ _ _ ._____ ______________ .__ _______________________________ L~iE_____ .
IF FRAME BUFFER~SUP END HIC POINTER + MESSAGE COUNT ~ ~4 * SEG HIC
FIRST FLAG~) = END FLAG
IHE~J______ El ~E____________ ---------------------------------------. ERROFI FI~G = TRUE

. CODE ADDRESS--PC ADDRESS
. _ .I~ETURN
. ~, _ ~
RETUFIN
.

~, .

~ ~*C~

ur~ 0-55. FJowch3rt of PPOM T~r CLEAR SBE COUNTFR
_ __ _ _ _ __ ________________________________________________________________ ___ _ READ WORD AT ADDRESS POINTER
_ IF ECC COUNTER NE O
.1~1___________ __ _____ __ _ _____ ______________ ______ EL~E________ UNCORRECTABLE MEMORY ERROR ~Se~ Figur~ ~98) .............................. ........................................
CLEAR SBE COUNTER
- . w . RETURN
_ ~ ~*~ ~

fi~uro ~56 Fiowchorlo~M M TEsr SET IUBE ERROR DISABLE
, .
DATA PATTERN = AA .

DO FOR POINTER = 4000 TO 6FFF .

¦ MEMORY~POINTER~ = DATA PATTERN

~ DO FOR POINTER = 4000 TO 6FFF
____________________________ ____________________________________________ . RD PATTERN = MEMORY~POINTER) _ IF Rl: PATTERN NE DATA PATTERN -1~____________________________ ~L~
UNCORRECTAE~LE MEMORY ERROR ISee IF SBE COUNTER NE O
Fi~ureO-98~ I~L _ ________ ____ _ ____ ___ ~ E__ . . CORRECTABLE MEMORY ERROR lSee . . Figure0-15~
__ ......................... ' . ~_ RETURN

~0 ~-~s~

~ c..~s~co~F~G~R~no~Nfl~seeBFi~ ~ ~1 0F2~
TABLE ADDRESS = COMMAND WORD12 BYTE _ COUNT = COMMAND WORD~l~
IH N IF BYTE `~T > (MAX _ BCTS_ADDRESS- 127) ~EI~SE ~ 0~-- lF~L~-~tE~;5-L~178 ~TA~L~--he:~REss-f----LENGTH CHECK SENSE E~3: BYTE C0UNTDD1REss___________ ELC r READ ERROR = TRUE ltl UNIT _ CIIECK--TRUE
COt)E ADl~RtSS--F~l~ CODE_ADDRESS = PC_ADDRESS (See Figùre 0-52) - _IF lA~Lt AD~E~LI 1Z~ OR
UNIT CHECK = TRUE . Sl~sE~CK
TABLE ADDFIESS OUT OF SUBSY~:ltM NOI
RANGE = TRUE CONFIGURED = TRUE
I~E~__________________--- 1~ SENSE RFGISTER(0) - O ~E' ~E_ . . DATA LENGTH = () -_ _ DO FOR I: _ TABLE ADDRESS TO TABLE ADDRESS + BYTE_COUN T - 1 ____________________________ __________________.._________________ OUTPUT _ DATA = I
~ffll=~E~~ ~E~T~
~See Figure ~51) .. . IF HARDWARE ERROR -LSE_ I~EN __ __ _ _ _ _______ __ - _ ____ _ ____ . __ __ . .......... SENSE _ REG~0) = EQUIPMEMT_CHECK_SENSE
PIC)_ERROR = TRUE . .
CODE_AI)DRESS =- PC_ADDRESS ISe0 Figure ~52) .
MEMORY ADDRESS = PARTITIONING REGISTER ADDRESS PORT .
:ia BC~RT (See Fi~ure 5 ~AT~ tlFFE Ri C~A~E-i~TF~-- ~ _ INPlJTlPARTlTlONlNG REGISTER READ_P9RT
OUTPUT _ DATA = I + 32 0~,_-~E~tt~tO~P~h~ t~ ~-SS
lSee Figure ~51) .
It:!ElY IF HARDWARE_ERROR -~iE _____ .
SENSE _ REG~0) = EQUIPMEMT CHECK_SENSE .
PIO_ERROR--TRUE .
CODE_ADDRESS--PC_ADDRESS (See Figure 9-52) .
MEMORY ADDRESS = PARTITIONING REGISTER ADDRESS PORT .
'- - -~BORT (See Fi~ure 0:1) - - - - - ~ : .
LJAIA ~u~t~(vAlA L~Nl,;HNrT~--INPUT~PARTITIONING FlEGlSTER RFAD _ PORT) DATA_LENGTH = DATA_LENGTH ~ 1 = READ_DATA_AVAILABLE = TRUE w RETURN

Fi~ro ~58. Flowchort of f~EAD_CONJPIOL_SJORE
SYTE_COUNT = CC)MMAND_WORD~13 REL_CONTROL_STORE_ADDRESS~1 TO 8)--COMMAND_WORD~2) REL_CONTROL_ST()RE_ADDRESSl9 TO 16~ = COMMAND_WORD~3j _ . .
ABS_CONTROL_STORE_ADDRESS = REL_CO~lTROL_ STORE_ADDRESS ~ HEX 4000 . . ..
IF BYTE_COUNT = O
I~E~_______________ __________ ___ ____ _____________ __------ ~_ ______ RETIJRN .
. _ IF BYTE_COUNT > 241 ~roo MUCH DATA FOR ONE FRAME) IHE~_____ ___ ____ _________ __ ______ _ LSE________ ____________ ____ _ _ ____ SENSE_REGISTER(O) = LENGTH CHECK IF ABS_CONTflOL_STORE_ADDRESS < HEX
SENSE 4000 OR ABS_CONTROL_STORE_At)DRESS
_ 1 8YTE COUNT- 1 >HEX 6FFF
READ ERROR - TRUE I~E~L__ ______ _______ ___ __ ___ .LSE__ _ TABLE_ADDRESS_OUT_OF_RANGE = .
CODE _ ADDRESS--PC_ADDRESS tS~e :
Fi~ur~ 0-52) _ _ _ .
__ SENSE_REGISTERIO~ _ COMMAND_REJECT SENSE
UNIT CHECK = TRUE
. . CODE_ADDRESS _ PC_ADDRESS ISe~ .
FiElure ~52~
. ' . _ .
UNIT_CHECK = TRUE
. _ ~., IF NO ERRORS ABOVE
I~EJ!J_ _ _ _ _ _ _ _ _ _ _ __ _ _ _ __ __ _ _ __ _ ___ _ _ _ _ _ _ _ - __ -_ - -- - ___ - -- - - --- - -- - - ~l ~iE__ ___ __ BLICTRAN (REQUESTED CONTROL STORE ADDRESS, ADDRESS_OF_DATA_BUFFERIO)) (S~r~ Fi~re ~9~
........... :
FIEAD DATA AVAILABLE--TRU .

_ . RETURN

figur/~ ~59. ~lo~ch~rt of READ_FfrAMF~p~r~ t of 2J
DETERMINE REQUESTING UDLC INTERFACE NUMBER, REQUESTING SSP NUMBER, AND
OUTSTANDING REQUESTS
' FRAME 8UFFEFI POINTER = O

` BYTE COUNT = FFlhex)`~
__ TIMEOUT COUNT = READ CHARACTER TIMEOUT

. DETERMINE REQUESTING UDLC NUMBER - -FRAME BUFFER(FRAME BUFFER POINTER) = INPUT(READ CllARACTERlPRlMARY S10)) DECREMENT BYTE COUNT
_ _ IF INPUT(READ CHARACTER(REDUNDANT S10)) IS NOT EClUAL TO FRAME BUFFER(FRAME
BUFFER POINTER) It!EN__ _ _ l~iE___ ________________________~____ INTERFACE STATUS = MISCOMPARE INCREMENr FRAME BUFFER POINTER
. _ _ RETURN _ =--_ _ = __ ___ _ RECEIVE STATUS = INPUT~RECEIVE CONDITIONS~REIDUNDANT S10)) _____.____________ ______________________________________________________ DO UNTIL TIMEOUT = O OR BYTE COUNT = O
_ **** ~lowchart continued on figure 0-60 *~**

F;~uro ~0. Flowch~r~ of ~EAD_~MME /p~rt 2 of 2~
_ --IF BYTE COUNT = O
T~E~ ____ _ __ _ _ _-- --------------------------- ,LS~____ RAD C~IARACTER AVAILABLE = INPUTlREAD CHARACTER AVAILABLE .
. STATUSIPRIMARY S10~) -`` _ IF READ CHAFIACIER AVAILABLE .
1~ Y_____________ _________________________________________ ~S~___ __ INPUT ~END OF FRAME STATUSIPRIMARY S10)) _____________________ _________________________________ :
REPEAT UNTIL END OF FRAME RECEIVED . .
_ .
DETERMINE REQUESTING UDLC AND SSP NUMBER .
: . . .
INTERFACE STATUS = OVERFLOW ERROR - :
. .
RETURN :
_~
-iNPUT iEND OF FRAME STATUSlPRlMARY S10)) IF END OF FRAME RECEIVED
Tt!E~ _ _ _ _ _ _ _ _ EL~;E _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - - - - - - - - - - - - - - - - - - - - - - - - - - - -. INTERFACE STATUS = NO END FLAG
, _ DETERMINE RE(:lUESTlNG UDLC AND SSP NUMBER
: _ _ . RETURN
IF CRC/FRAMING ERROR
I~E~L_______________________.._____________________________~______ LSE. _____ INTERFACE STATUS = CRC/FRAMING ERROR
_ _ DETERMINE REQUESTING UDLC AND SSP NUMBER
__ _ _ _ .
RETURN .
.
IF RECEIVE OVERRUN
TtlE~_~ __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ _ - _ - - --- -- - - - - - - - - - - - - L~iE_ __ _ _ _ _ _ INTERFACE STATUS = RECEIVE OVERRUN
__ DETERMINE REQUESTING UDLC A!`ID SSP NUMBEfl _ ~ .
RETURN .
_ .
INTERFACE STATUS = NO ERROR5 . _ DETERMINE REQUESTING UDLC AN[) SSP NUMBER
_ _ .
~ RETURN

Fif~vto~61. Fhwch~rtorF~AD ID_WORD_O
_ __ _ _ DATA_BUFFER(O) = TrPE_NUMBER~ MSBj DATA_EtUFFR~ TYPL_I~IUMBER~2)~LSB) HARDWARE_READ_SELECTOR = INPUT5PATCII_WORD_PORT(3))(S~N OF TYPE NUMBER~
DATA_BUFFER~2)~1 TO 4) = TYPE_NUMBER~3)(1 TO 4) LOR
HARDWARE_READ SELECTORI1) .
HARDWARE_READ_SELECTOR = INPUT~PATCH_WORD_PORT~2))(REVISION) . .
DATA_E~UFFER~2)~5 TO 8) = HARDWARE_READ_SELECTOR(l TO 4~ -DATA_BUFFR[3)(1 TO '1) = HARDWARE_READ_SELECTOR(5 TO 8) . ..
. . DATA_BUFFERI3) = DATA_BUFFER(3j LAND HEX FO .

DATA BUFFER(4) = ZERO_BYTE
. ~
. DATA_LEN(iTH = 5 . READ DATA_AVAILABl.F. = TRUE
_ _ _ RETIJRN

~ ~3~

~`
Fi~ure ~ô2. ~lowcl~or~ of ~I~AD_ID_ WOf~D_ 1 HARDWARE_READ_SELECTOR =INPUT(PATCH_WORD PORT~3)(FIRST BYI-E OF SERIAL
NUMBER~
t)ATA_BUFFrR(O~ = IIARDWARE_READ_SELECTOR
HARDWARE_READ_SELECTQR =INPUll(PATCH_WORD_PORT(4)~2ND 8YTE OF SERIAL
NUMBER) -. _.
DATA_BUFFER( 1 ) _ HARDWARE_REAI:)_SELECTOR
HARDWARE_READ_SELECTOR =INPUT~PATCH_WORD_PORT(5)(LAST 2 BITS OF S/N) __ .
DATA_BUFFERl23(1 TO 2) = HARDWARE READ_SELECl'C)RIl TO 23 HARDWARE READ_SELECTOR =INPUT~PATCH_WORD_PORT(13(SPI, BCTS EXP 81TS) DATA_BUFFER[2~(3 TO 73 = HARDWARE_READ_SELECTORIl TCi 5) . . DATA_BUFFERI2) = DATA_BUFFERI2) lAND HEX DE
.
HARDWARE_READ_SELECTOF; =INPUT(PATCH_WORD_PORTI5)~SYSTEM CONSOLE EXP
BIT) ' DATA_BlJFFER(3)(1) = HARDWARF_READ_SELECTOR(3) . DATA_BUFFERI3) = DATA BUFFErl(3~ LAND HEX 80 _~

DATA_BUFFERI43(3 TO 4) = HARDWARE_READ_SELECTOR(4 TO 5) -- . _ DATA_BUFFERI4) = DATA_B'JFFEF'((4) LAND HEX FO
DATA_LENGTH = 5 __ READ_DATA_AVAil ABLE = TRU
RETURN

~ ~3 ~

Fii3uri~ ~63. Flowch~rt of RfAD_IOP_STArE
' _ .
TABLE_ADDRESS = COMMAND_WORDl2~
_ . ' , - BYTE_COUNT = COMMAND_WORD(l) _ .
IF BYTE_COUNT > 18 IH~______________ _____ ___ ______ EL~E____ ____ ______ ___________________ SENSE_RE(;ISTER(O) = LENGTH CHECK IF TABLE_ADDRESS + BYTE_COUNT ~ 16 SENSEIt!E~I__ _ ___________________________ El.S
__ UNIT_CHECK = ~RUE
READ ERROR = TRUE .
CODE ADDRESS = PC_ADDRESS ~S~e CODE ADDRESS = PC ADDRESS (See Figur~ ~52) Figure ~52~ . .
_ .
SENSE_REGISTER~O~ = .
.~ UNIT CHECK = TRUE COMI\AAND_REJECT_SENSE

.TABLE_ADDRESS_OUT_OF_RhNGE =
~, IF SENSE REGISTER~O) = O
IHE~I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ELsE- _ _ _ _ DATA_LENGTH = O
. _ , .
DO FOF; i = TABLE_ADDRESS TO TABLE_ADDRESS + . .
E~rFE_COUNT- l .
___________.._______________________________ __________ ________ DATA_BUFFER(DATiA_LENGTH) = IS)P_STATE_TABLEII) .
DATA_LENGTIl = DATiA_LEN(iTH ~ 1 REhD_DATA_AYAIIA~LE--TRUE .
. . -~
RETURN
_. .

, O .~

Fiou~o ~64. ROwch~rt of ~EAD SSP Ji/SrOflY
. _ IF COM MAND_ WORD(2) > 3 :
I~E~L_________ __ __ _ EL~E__ ___----------------------------SENSE _ REGISTER~O) = COMMAND REJECT- DATA_BUFFER~O) =
SENSESSP_HISTORY_TABLE(COMMAND WORD~) , . _ TABLE ADDRESS OUI OF RANGE = TRUEREAD DATA AYAILABLE _ TRUE
., CODE ADDRESS = PC ADDRESS - DATA LEN{;TH = 1 IJNIT CHECK = TRUE .
__ _ _ RETURN
.' ~ ' , . :
. . .

~3S ~

Fir~ur~ ~66 Flowchort of R~AD SSP NVMeER
__ TABLE_ADDRESS = COMMAND_WORD~23 ~_ --BYTE_COUNT = COMMAND_W0RDt1) . IEi3YTE_COUNT > 16 liHE~ __ __ ___ ____ ____ _ Ei.~E ___ _ __ ___________ _ _ _ _____ SENSE REGISTER(O)--LENGTH CHECK IF TABLE_ADDRESS + BYTE_COUNT GT 16 - SEIYSE ltl~N__ __ ________ ____ _______ _ ~ SE_ SENSE_REGISTER(O) = .
READ ERROR _ TRUE COMMAND_REJFCT_SENSE .
. ' .
CODE ADDRESS = PC ADDRESS ~See UNIT_CHECK = TRUE
Fi~ure 0-523 ~
_ TABLE_ADDRESS_OUT_OF_RANGE =
UNiT CHECK = TRUE TRUE
-' .
. CODE ADDRESS--PC_ADDRESS (See .
Fi~ure (~52) __ _ ~
IF SENSE REGiSTER~O) = O .
Ii~E~________ _________ ______ _ L~E_____ DATA LENGTH = O .
_ ___ _ _ _ DO FOR I:--TABLE_ADDRESS TO ~TABLE_ADDRESS t BYIE_COUNT~ 1) _______________________________________________________________ .
. DAT5~_BUFFER(DATA_LENGTH3--SSP_APPLICATION_TABLE(I) _ _ .
DATA_LENGTH = DATA_LENGTII + 1 _ READ_DA~A_AVAILABLE = TRUE
_ ~_ RETUF/N

.
.

~3~

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .~. . . . . . . . . . . . . . . , . , . . . . . . . . . . . . . . . . . -. . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . _ . . , SPI CONFIGURATION (Ser~ Figure (~93) _.................................................. ....
TABLE ADDRESS = COMMAND WORD~2) _ 'BYTE_COUNT = COMMAND WORD~1 _ _ IE BYTE COUNT ~ (MAX_SPI_ADDRESS + 1) SENSE REGlSTERlO)-- IF ~TABLE_ADDRESS +` BYTE_COUNT =1) GT
LENGTII C!IECK-SENSE Itl~ MAX SPI_ADDRESS EL' E
P~EAD ERROR = TRUE UNIT_CHECK := TRUE
_ CODE AaDRESS = PC CODE_ADDRESS := PC_ADDRESS ~See Figure ~52~
ADDRESS lSee Figure 0-52~ :
.T~I iF ~TABLE_ADDRESS + BLY~T~E_COUNT) GT 128 UNIT CHECK = TRUE-SENSE REGlSfER[O)-- SENSE REGIS1'ER(O)--(~OMMAND F:EJ'CT PARTlTlnr~'lNG CHECK
SENSE . SNSE :
.TABLE ADDRESS OUT OFSl IBsysTEM_NOT_CONFIGUR .
RANGE := TRUE := TRUE :
,~, IF SENSE FEGISTER~O) = O ELSE
ItlE~J________---------------------------------------------------- ~~ ~~~ ___ DATA_LENGTH := O .
_ ~ .
DO FOR l := TABLE_ADDRESS TO (TABLE_ADDRESS -~ BYTE_COUNT- 1~
________________________________________________________________ OUTPUT_DATA = I ~
OUTPVT_AND ~IFYlOUTPUT DATA,PARTITIONING REGISTER ADDRESS
~See Figure ~51) .
IF HARDWARE_ERROR I~SE_ .
I~E~L__ _. __ __ __ _-__ ___ _ _ _____ _____ __ _____ SENSE_REGISTER~O)--EQUIPMENT_CHECK_SENSE .
___ .:
PlO ERROR = TRUE .
_,. --~ _ :
CODE_ADDRESS = PC_ADDRESS ~See Figure ()-52) :
MEMORY ADDRESS = PARTITIONING REGISTER ADDRESS PORT .
,.. ,........................... , ...... :
ABORT ~See Fi~ure 0-1~ ' . .
:.. _. ,............................. _ ~o.
DATA BUFFERlDATA_LENGTH)--- INPUTlPARTlTlONlNG RE(iISTER READ PORT) .
. ~
DATA_t ENGTH = DATA_LENGTH ~ 1 _ _ READ_DATA_AVAILABLE = TRUE
RETUP~N
_ ~

~gur~ 0-67. Flowchi~rr of ~AD SU6JSYST~M INrEf~FACE TA8LE
BYTE_C0UNT = COMMAND_WORD~l) _ .
TABLE ADDRESS = COMMAND_WORD(2) _ _ I
IF BYTE _ COUNT > 4(3 ' H~I _____________________ _______ ELSE________----------'-------------------SENSE _ REGISTER~0) = LENGTH CHECK !F TABLE _ADDRESS + BYTE_COUNT GT 160 SENSE OR

. _ c, T~ _~___________________ ____ .READ ERROR = TRUESENSE_REGISTER~0) =
_ C0MMAND REJECT SENSE
CODE ADDRESS = PC ADDRESS ISee , __ ~
Figure ~52) UNIT_CHK =- TRUE :
.
UNIT CHECK = TRUETABLE_ADDRESS_ ou-r_ OF_RANGE = .
. TRUE
. . .
. (::ODE_ADDRESS = PC ADDRESS jSee .
. Fi~ure ()-52~
. _. ,. ~
IF SENSE REGISTER(0) = 0 ' I~E~________________________.______________ _________________________ E~SE_ _ INITIALI~E DATA_LENGTtl TO O
,~ _ DO FOR l := TABLE_ADDFESS TO (TABLE_hDDRESS ~ BYTE_COUNT- 1) .._.__________________________________________ ____________~__.___ DATA_ BUFFER(DATA_LENG7'H) = ,'SIT_PARTITIONING_CONTP~OL_FLA~iSIl) _ __ __ --DO FOR J := 0 TO 2 BY 2 ____________.________________________________________________ DATA _BUFFER~DATA_LENGTH tJ+ 1) = SIT_IOF~ NUMBEF,(I,J) __ _ DATA_BUFFER(DATA_LENGTH~J+2) = SIT_IOF'_NUMBER~I,J~13 _ _ _ DATP~_LENGtH = DATA_LENGTH ~ 5 _ . _ READ_DATA_AYAILABLE _ TRUE .

RETURN
, .

g,.6~

Fi~ufo 0 6~. FlowchDn o~EGlSTEr~ TESr~pDrl 1 c~f 2) .......................... -...... , .. ----.,,, .. , ., .. -SET_TEST_MODE~ISee Figure ~91~
..........................................................
DO FOR I = O TO 159 ________________________ ______________ _______ __________ _____________.
REGISTER ADDRESS ~
........................................... -........... ,.. :............ ~
OUTPIJT AND VERlFY[REGlSTER ADDRESS, .
. . PAF~TITIONING REGISTER ADDRESS PORT) ~See Figure ~51) . :.................................. , IF HARDWARE ERROR .
. Itl~___________ _ _________ ____ .._______ _________ _______ LSE__ _____ SENSE REGISTER(O) = EQUiPMENT CHECK SENSE .
. . . .
PlO ERROR = TRUE
~ --. CQDE ADDRESS = PC A~DRESS (See Figure 0-52) MEMORY ADDRESS = PARTITIONING REGISTER ADDRESS PORT
............................................................................................... , .. . INITIALIZE ~CTS SPI INTERFACES ~See Figure 0-37) .
. . :........................ ,......... , . ' RETUR~J
.................................................. ,,..... ,............ ........ ~
OUTPUT (HEX OA, .
PARTITIONING REGISTER WRITE POR~7 ~See Fi~urs :.................. .............................................. .................
IF INPUTlPARTlTlONlNG REGISTEPI READ PORT) NE HEX 0~ L~E .
It~l__________., _____________________________ _______________ ________ SENSE REGISTER~O) = EQUIPMENT CHECK SENSE
. _ REGISTER ERROR = TRUE .
_ CODE ADDRESS = PC ADDRESS ~See Figure ~52) .
_ MEMORY ADDRESS = REGISTE~ AD~RESS ; .
............................................................................................... , INITIALIZE BCTS SPI INTERFA~ES ISe~ Figure ~37) :...............................................................................................
RETUP~N
**** flowchart continusd on figur0 0-69 **~*
_ - .

, ,.. i . . ~

Figvro 0 69. Flowchort of f7EGlSrER ~sr/p~" 2 of 2) ,.. ,.,,,,,.. ,.,.. ,,,,,.,.,,,,,,.,,,,,,,,,.,,,,,.. ,,,.. ,., (lUTPUT (HEX 05, ' PAR~ITIONING REGISTER WRITE PORT~ ~See Figure 0-51) T~E~I IF INPUTIPARTITIONING REGISTER READ PORT~ NE HEX 05 1.~ _ ______________________________________________ SENSE REGISTER(O) = EQUIPMENT CHECK SENSE
REGISTER ERROR = TRUE
__ _ CODE ADDRESS. = PC ~DDRESS (See F;gure 0-52~
. . :
MEMORY ADDRESS = REGISTER ADDRESS .
, _ .................................. ,.. ,.. ,.,,.. ,.. ,.................. .
. INITIALI2E BCTS SPI INTERFACES (See Figure ~37) .
:........... ,.. :
. . RETURN , . . . .
. . ~
IF REGISTER ADDRESS < 128 '' ''' ''''''' ''OUT'PU '~HE'X'05 OUTFUT (HEX 00;
PARTITIONING REGISTER WRITE PORT) (See . PARTITIONING REGISTER WF;ITE PORT) Figure,~.5,1!,,,,,,, .......... (See Fig,u,re, ,0. ,5,1,), .. , IF INPUT(PARTITIONING RGISTER READ IF INPUT(PARTITIONING REGISTER READ
ltlE~ PORTI NE HEX OF EI.~__ PORT) NE H'EX 00 rL~i3~__ CODE ADDRESS = PC ADDRESS ISee . CODE ADDRESS = PC ADDRES5 Figu~e Q-52) .lSee Fi9ure () 52~
ERROR FLAG = TRUE _i~ERROR FLA(; = TRUE
.
IF ERROR FLAG
.T~E~ __._. ___ ______ _------------------------------------- LSL___ ___ SENSE REGISTER~O~ = E~IUIPMENT CHECK SENSE .
_ MLMORY ADDRESS--RE(iISTER ADDRESS .
REGISTER ERROR--TffUE
....... ,.. ,.. ,.. ,......... ,.,.. ,.. ,.. ,, INITIALIZE BCTS SPI IN~ERFACES (S~e Figure ~:~71 :.,.. ,... ,.. ,.,.. ,... ,............... . .
RETURN
__ ________________ ________________ ________________________ ___ ~ _____ DO UNTIL I = 1~9 .
,......................... ,.... ,... ~.. ;;.... ;
CLEAR TEST MODE ISee Figure ~3) ..............................................................................................................

RETURI~
_ - _ . .

~i~ur~ 0-7a F/owchf~t orPf~hlOVE_SUBSYS~M(p~r~ r of 2) ~ABLE_ADDRESS := COMMAND_WORD~2) -_ `
COMMAND_PARTITIONING_CONTROL_FLAGS := COMMAND_WORD~1) ... -................................................... , - SPI_CONFIGURATION ISee Figure ~93) .............................................................................................................
. BCTS_CONFIGURATION tSee Figure ~7) :........................................................................................................................
IF TABLE_ADDRESS GT MAX_SPI ADDRESS
T~E~3____________________-----------------------------------------------iF (TABLE_ADDRESS LT 128) OR ITABLE_ADDRESS GT MAX_BCTS_ADDRESS) .
T~__ _______ ___ ____ _______ __ _______ ____ _________ ___ LSE__ IF TABLE _ ADDRESS GT 159 :
I~EU____ ___ _______ ____..______ ~LS~____ _._____________________ .
SENSE_ REGISTER~O) = SENSE_REGlSTEh(O) =
COMMAND_REJECT_SENSE PARTITIONING_CHECK_SENSE . .
:
TABLE_ADDRESS_OUT_OF_RANGE = SUBSYSTEM_NOT_CONFIGURED = .
TRU E TRUE .
__ _ . : :
:: UNIT_CHK = TRUE .
.... CODE_ADDRESS = PC_ADDRESS (See Figure 0-52) .__ . _ . .
RETURN .
IOP_APPLiCATlON_CHECK (See ~i~ure ~423 :.......... ....... ..
IF TABLE ADDRESS LE 127 .
I~E~____ __ _ _._ ___ _ _ ______ E!L~E_______ _____~_____ __ _____ ___ __ EU_CHECK (Sce Fit3ure 0-21) BCTS_ENABLE_CHECK ~Sec Fi~3ure _ ............ ...........................
SENSE_REGISTER(l) I`;E C L~E________ SENS'_REGISTER(O) = DATA_CH'CK_SENSE .
-UNiT CHK = TRUE .
CODE_ADDRESS = PC_ADDRESS lSea Fi~ure 1~2) RETURN
_ - __ ~*** flowchart continucd ~n fiaur~3 1) 71 ~***
_ _ ... .

FlourtJ 0-71. F7QwchDn of t~EMOV~_SUBSYSrE/~J /p~rt 2 of 2J
TEMPORARY_REGISTR_1 = SIT_PARTITIONING_CONTROL_FLAGSlTABLE ADDRESS~
. .. _ ._. .. . .
SIT PARTITIC)NING_CONTROL_FLAGSrTABLE ADDRESS)12 to 6) =
SIT_PARTITIONING_CONTROL_FLAGSITABLE ADDRESS)12 to 6) LAND
COMMAND PAF~TlTlO.~ G_CONTROL_FLAGS(l to 5) _ ~
COMPLEMENT COMMAND_PARTITIONING_CONTROL_FLAGS
.......................................................................................................................
. ' AUTHORIZED_SSP_CHECK ISee Figure ~6) .
F
SENSE_REGISTER~l) NE O ' . ' .- I~E~ EL~
SENSE _ REGISTERlO) = OUTPUT _ DATA = TABLE_ADDRESS
PARTITIONING, _CI IECK _SENS ~ ' ___ , .
. OUTPUT_AND_VERIFY~OUTPUT DATA,PARTITIONING
UNIT_CHK _ TRUE REGISTER ADDRESS PORT) . ~S~e Figure ~51) CODE_ADDRESS =
. ' PC _ ADDRESS (See Ei~ure IF HARDWARE _ ERROR
~52) - I~E~i_ _ _ ________ _____ _ ____ LS~_____ ______ _ _ _ _______ . ~ SENSE _ REGlSrER~O)--TEMPORARY REGISTER 1 =
-. SIT _PARTITIDNING_CONTROL_FL ,~lJIPMENT_CHECK_SENSE SIT PARTITIONING CONTROL
= TEMPORARY_REGISTER_1 PlO_ERROR = TRUE ~TABLE ADDRESS) ................................... , CODE_ADDRESS = SUBTRACT IOP ENABLE
. PC _ ADDRESS [See Fi~ure . COUNT
. ~2~ : (TEMPORARY REGISTER 11 .
, ~See Figure ~94 . ME,MOR-' ADDRESS = ...............................
. PARTITIONING REGISTER TEMPORARY REGISTER 2 =
. . ADDRESS PORT INPUT(PARTITIONINl;
,..... .......................... ................................ , REGISTER READ PORT) ABORT ~See Fi~ure 0-1) . TEMPORARY REGISTER 1 = ¦
. . TEMPORARY REGISTER 1(2 to . . . . 5) LXOR TEMPORAR)' . . REGISTEPI 2 . . WRITE iARTiTiONlNG
. . . RE~ISTER~TABLE_ADDRESS, .
. I . TEMPORARY REGISTER 1)(See.
i . . Figure ~102~
....................................
RETURN
.
.
~ .

.. . .

Figuro 0-72. Ftowch~r~o~SAUHARDWAR~lNlTlAUZA710NAND tfST

INITIALIZE PIO(PIO CONTROL PORT(I),PIO 10 CONTROL(I)~ ~See Figure ~3~
.--.. , .. .. .....
ECC TEST (See Figure 0-17~ -.PROM TEST ISee Figure ~55) ':::::::::::::::::.::::::-.' '::::::::::::::::::::::: :::: ::: ::
RAM TEST ~See Figure 0-56) .
:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::~ '::'..:::::::::::::::::..::.::
REGISTER TEST (See Figure ~6~i~
. :::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: ::::::::::::::.'.::::
.LOOK FOR SENSE PENDiN~; ~See Figure 0~7) ::::::::'--::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::':::::::::::::::::::':::' S10 TEST ~Sce Figure ~92) F .......................................................................................................................
: . .......................................................................................................................
LOOK FOR SENSE PENDING ISea Figure ~47) SAU LOCK TEST ~See Figure ~75) .

LOOK FOR Si--NSE PENDING ISee Fi~ure ~47) lUi~LC CODE TRANSPLANT ~See Fi~ure 0-97~
I . ......................................................................................... '.
.. ', .,,,:::,::::::::::::::.:.. --..................... : SAU INITIALIZATION ISee Figute 0-73) ::::::::::::-:.,:.-:-'-:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
A80RT (See Figure ~1~

.

Figur~ ~73., Ftr~wch~rJ ~f SAU_INITIALIZATIC)P~
_ _ HARDWARE_READ_SELECTOR = PATGH WORD PORT(l) __ _ IF UDLC FEATURE-lt~l!l___ __________---------_----------- ~LSE________ ______________________ __ MA~S SSP NUMBER = HEX 03 MAX SSP NUI\ABER = IIEX Ol . ~ _ CONFIGURED UDLC NUMBERS = HEX OF CONFIGURED UDLC NUMBERS = HEX 03 - . _ FOR I = O TO 159 DO
______________ ________ __________ ___ __________________________ _______ . SIT IDP NUMBER~I,O) = HEX FF .
. ' ' .
SIT IOP NUMBER(I,l) = HEX FF.

. SIT ll)P NUMBER~1,2) = HEX FF
.. . , '.
SIT IOP NUM8ER(1,3) = HEX FF

RETURN

FiDur~ ~74. FJowchdrt cf SAU LOCK CHECKS~ssp numbdr~
_ .
~ DO FOR I = S:) TO 15 ______________________________________ _____________ ____________________ . IF SSP APPLICATION TABLE(I)~BT04) = SSP NUMBER
I~E~ _________ _________________ _ L~E_ __ _ IF SSP APPLICATION TABLE~1)(1) = 1 . I~EN ___ ___ __ _______ ____________________________~LSE______ . RETURN . .
... ;.. ...... '............ ,.................... ..... ~.... ..... ~... , '. CLEAR LEDlSSP NUMBER) tsee Figure (~113 :.............. ......................................................................................
SENSE REGISTER~O) NE O
II~EN _ _ _ _ _ _ _ __ _ _ _ __ __ ___ _ _ ___ _ _ __ _ _ _ _ _ _ .LS E_ _ _ _ _ _ _ _ __ _ _ _ _ _ - .- - -- - - - - - - - -- - -- - -ABORT PREVIOUS SAU LOCKS = SAU LOCKS

RETURN
.~ -~.'' _ . .

.

, ; ,. . .

F;~uro 0-75. flowchJr~ of SAV L~C~ J~ST
SAULOCtCS = INPUT(SAU LOCK POFT3 - - - ' .
TEMPORARY REGISTER l(lT04~ = SAULOCKS15to8) xor f ....... ;.... ~................... ,.,,.. ,.. ,, OUTPUT 5TEMPORY flEGlSTER 1, SAU LOCK PORT) ~See Figure~50~ .
., ... ~.......... ....... ....... ,.. ,.. ,.. ,.,.. ,,.. ,,.,.. ,.. , SAULOCI<S = INPUT (SAU LOCK PORT) _ __ _ IF SAULOCKS~5 to 8) = f I~E~________________------------------- ELSE _______________________ _________ SAU LOCK ERROR = FALSE SAU LOCK ERROR = TRUE
_ . ~
SAULOCKS C FF .
.......................................................................................................................
OUTPUT ~SAULOCKS, SAU LOCK PORn (See Figure()~50) ..................................................... ,,.. ,.. ,.. ,.... ,... ,,.... , SAULOCKS = INPUTISAU Ll:~CI< PORT) IF SAULOCKS15to8) = O
I~ ____ ___ E~___ _ ____ ____ ___---------------------------------------. SAU LOCI( ERROR = TRUE
_ IF SAU LOCK ERROR = TRUE
I~E~________ _______ _ ..___ _______ ___ _ ______._ _______ _ __ LSE______~
SENSE REGIST~RIO) = EQUIPMENT CHECK SENSE
___ . REGISTER EFIROR = TRUE
. .
CODE ADDRESS = PC ADDRESS
- _ _ _ MEMORY ADDRESS = t60 .
_ SAU LOCK ERROR c FALSE
. , . ~
RFrl)RII
_ .

. , ~.. . .

~ *
F;Duro 0-76. F/owcharl of SAV RtLEASE

SSP RESERVE = FALSE

. RETURN
. . .

, Fi~uro 0-77. Flowchar~ o~ SAU REStflVE
__ , .
RESERVED SSP NUMBER =REQUESTING SSP NUMBER

SSP RESERVE = TRUE .

RETURN

, Fi~uro 0-7~. FLOWcHARr OF SAU _RESEr ......................... ~.,... ,,,,,.. ,~, SAV_HARDWARE_INITIALIZATION_AND _TEST(See Fi~ure 0-72) ..................... . .......... , .. , .. .,.... ,.. ,................. :
.:.. :....... ::.::::.. ,.,.. ,...... ,... ,... ,,.,.. --ABORT~See Figure 0~

Figur~ ~79. Ftowcl~rf of SEWD AT7ENnON
. AU HIC VALlJE--8 _ .
ASSURANCE UNIT = F
.
AU LABEL = 8F
__ AU LENGTH = ~F
. .
UNIT CHECK = TRUE
.

SUR ~AESSAGE WAITING/BUSY HIC = ~E
' .......................... --BUILD SYSTEM SESSION ~See Fi~ure ~10) .
:............. ..............................................................................
FRAME BUFFER~MESSAGE COUNT) = END
. . .. ~ ...................................... -..... -LOOK FOK POLL(REQUESTING UDLC NIJME;ER) ~See Fi~ure 0-45) , :................................................................................................................
IF REQUEST RECEIVED
I~ _ __________ _____________________ _ _ _ ________________ ~L~
SEND FRAME(F1EQUESTING UDLC NUMBER,~MESSAGE COUNT)) (See Figure .
..........................................................................................
' LOOK FOR /~CKNOWLEDGEIREQUESrlNG UDLC NUMBER) (Se~ Figure .
:............................ ....... ......... .
IF ACKNOWLEDGE RECEIYED .
ItlE~_ _____ _____________ _ ~L~i~______ RETURN .
_______.___________________________ ______ _________ __~c____. __ ~___ _ RETR~ 3 TIMES

RETURN
-- --- , ~y~

tSIuro 0-8Q flowch~ of S~/D COMMAND END
SUP MESSAGE WAITING/BUSY HIC = BF
,.........................................................................................................................
: BUILD SYSTEM SESSION ~See Figure 0-10) ~
IF READ DATA AVAILABLE L~E_ ~____ .______________________________.. ___________________________ _____ FRAME BUFf:ER(MESSAGE COUNT) = INPUT HIC
FRAMB BUFFER~MESSAGE COUNT ~ 1) = TEXT HIC . .
. DATA LENGTH.= DATA LENGTH + 1 . . : . .
.: .FR~ME BUFFERIMESSAGE COUNT ~ 2)--I/O BUFFER10) _ , FRAME BUFFERIMESSAGE COUNT + 3) = I/O BUFFER(1) .
MESSAf`,E COUNT = MESSAGE C~)UNT ~ ~ . .
.
DATA LENGTH = DATA LENGTH - 1 .
DATA BUFFER POINTER = O -.
DQ F3R I = MESSAGE COUNT TO MESSAGE COUNT + DATA LENGTH - 11) .
_______________________________________________________________ ~ FRAME BUFFERII) = DATA BUFFERIDATA BUFFER POINTER) .. ., ... DATA BUFFER POINTER = DATA BUFFER POINTER + 1 . _ ~AESSAGE COUNT - MESSAGE COUNT + DATA LENGTH .
_ .
FRAME BUFFER(MESSAGE COUNT) = END
..................................................................................................................
: LOOK FOR POLLIREQUESTING UDLC NUMBER) (Sce Figure 0-45) .......................................
. IF REQUEST RECEIVED
SEND FRA~E~RE UESTING UDLC NUMBE!R,MESgAG CO NT ¦S~e 'gure EL~E______ :...................... , ..... ,......... ..........
IF SENSE REGISTERIO) NE O
I~E~ _ _ _ __ _ _ __ _ _ __ __ ~SE_ __ ABORT(See Fi~ur~ O-l) :1 :
. LOOK F~ ~CKNOWLEDGEiREQUESTlN6 UDiC NUMBER) lSee igùrë .
...............................................................................................
IF ACKNOYVLEDGE RETURNED
I~E~________________________________________ ________ ~E______ RETURN .
_______________ _______________ __________ __________ , _~_____ __~;c_____ RETURN
_ , . .
~ . .
.

Figure O 81. ~lowc17~r~ of SEND DISCONNECT MOD~

UDLC COMMAND = DISCONNECT MODE RESPONSE CODE
........................................................................................................................
. . SEND FRAMEIREQUESTING UDLC NUMBER,l) (See Figur~ 82 IF SENSE_REGISTER10~ NE O
T~__ _ _ _______ _ ______ ____ ____________ __________ _______ L~E________ - ABORT ~See Figure ~1) :................................................ ~
. RETURN .

Fi~uro ~fJ2. flo~ch~r~ of SEND F~AM~(udlc nurrlb~r,count) rp~rt 1 of 3J
l)ETERMINE SSP NUMBER

INITIALI~E S10 TRANSMIT~REQUESTING SSP NUMEIER~ ISee Figure ~40) ............................................................................... , GENERATE SEND AND RECEIVE TIMEOUT COUNTS

TRANSMIT BUFFER EMPTY = FALSE
~ _ _ GENERATE SEND AND RECEIVE B~E COUNTS
___ __ . _ __ GENERATE SEND AND RECEIVE FRAME B(IFFER POINTERS

OUTPI)T(FRAME BUFFER~SEND FRAME BUFFER POINTER~) INCREMENT SEND FRAME BUFFEFI POINTER
_ ._ DECREMENT SEND BYTE COi)NT
_ SEND WFIITE REGISTER O = RESET TRANSMIT U~IDERRIJN LATCH

- * x*~ flowchart continued Drl fi~ure ~83 *~**

,.~7.,~j .

Figur~ 0-83. Fl~wch~rt of SEND_FRAME~udlc numb~r,count~ ~port Z r~f 3~
_ TRANSMIT BUFFER EMPTY = INPUT~TRANSMIT STATUS~SEND S10~) ~ .
IF NOT TRANSMIT BUFFER EMPTY .
. It~N _ _____ _ ___ __ ___ _____________ _______ ~______ . SEND TIMEOUT = SEND TIMEOUT- 1 IF SEND TIMEOUT = O LS}~
. 1~!~______ _ _ _______ _ __ _ __ __ __ _ INTERFACE STATUS--SEND TlMEOlJT .
. . _ . . : . .
CODE ADDRESS = PC ADDRESS .
: :
. SENSE REGISTER10) = EQUIPMENT CHECK SENSE .
_ : .:
S10 ERROR = TRUE
~ .
MEMOFlY ADDRESS = PRIMARY S10 . .
___ I :
RETURN : .
.___ _ _ _ __ _ _ _ ___ __ _ __ __ _ _ _ _ _ _ _ _ _ _ __ _ _ _ __ __ _ _ __ _ _ _ _ ~__ __ L__~;C_ __ __ DO WHILE NOT TRANSMIT BUFFER EMPTY
.
OUTPUT~FR4ME BUFFERISEND FR~ME BUFFER POINTER)~
INCREMENT SEND BUFFER POINTER AND DECREMENT SEND BYTE COUNT
READ CHARACTER AVAILABLE = INPUTIREAD CHARACTER AVAILABLE STA~USlRECElVE
,. ~ S10"
IF NOT READ CHARACTER AVAILABLE
Tt!E~I----- ___________ _____ ____ COMPARE FRAME BUFFERlRECEIVE FRAME
RECEIVE TIMEOUT _Bt)FFER POINTER) WiTHlNPUT READ
RECEIVE TIMEOVT- 1CHARACTER~RECEIVE S10) __ INCREMENT RECEIVE ~UFFER POINTER AND
DECREMENT RECEiVE BYTE COUNT
_ .
. IF COMPARE WAS SUCCESSFlJL
IL~ _ E~E __ _ ___ ______ ____ _____ . .INTERFACE STATUS--MISCOMPARE
. .CODE ADDRESS = PC ADDRESS
. .SENSE REGISTER(O) = EQUIPMENT
:CHECK SENSE
. . _ _ .S10 ERROR = TRUE
: .MEMORY ADDRESS = PRIMARY Sll:) . .RETURN

________________________________ __ ~___ ______ _____ ______________ _=
DO WHILE SEND BYTE COUNT NOT EQUAL TO O
_ . _ **~* flowchart continued on figur~ ~û4 ****

~ . , .~ . .

~0~

Figur~ 0-84. Flo~chDlt of SEND fMME~udtc numb~r,count) ~p~rr 3 of 3J
. ~ _ IF RECEIVE BYTE COUNT = O
Tt!E~I _ _ _ _ _ _ __ _ _ _ _ __ _ _ _ _ _ __ _ - - - - -- - - - - - - - - ~ --- -- - - - - -- - - - - -- - - ELSE_ __ _ __ _ F~ESET TRANSMIT S10 _ . _ RETURN .
~., READ CHARACTER AVAILABLE = INPUT~READ CHARACTER AVAILABLE S-l ATUS(RECEIVE
S10~) .
IF NOT READ CHARACTER AVAILABLE
Itl~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ E~E_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - - - - - - - - - - - - - - - - - -. COMPARE FRAME BUFFER~RECEIVE FRAME
RECEIVE TIMEOUT = RECEIVE TIMEOUT BUFFER POINTER) WITH INPUT READ
-1 CHAFI~CTERIRE(,'EIVE S10) . .
. . INCREMENT RECEIVE FRAME BUFFER POINTER
DECREMENT RECEIVE BYTE COUNT
IF COMPARE WAS SUCCESSFUL
.ltlE~I_ _ _ E~SE_ __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . INTERFACE STATUS = MISCOMPARE
.CODE ADDRESS = PC ADDRESS
. .SENSE REGISTER(O) = EQUIPMENT
.CHECK SENSE
. ~ .S10 ERROR = TRUE
. .MEMORY ADDRESS = PRIMAR~ S10 .RETURN
_________________________________ __ ~___ ____________________ =____ __ DO WHILE PECEIVE TIMEOUT NOT EQUAL TO O
INTERFACE STATUS = RECEIVE TIMEOUT
CODE ADDRESS = PC: ADDRESS
_ _ .
SEI`JSE REGISTER~O) = EOUIPMENT CHECK SENSE
S10 ERR(:)R = TRUE
RETURN
_ _ , .... ..

F~ure ~85. Flowch~n r~f S~ND f RAME REJ~Cr ~_ UDLC COMM~ND = FRAME REJECT RESPONSE CODE
.

DO FOR I-- l TO ~

ERAME BUFFERlI+~) = FRAME REJECT RESPONSEtREQUESTlNG SSP NUMBER,I) .... !.............................. , . SEND FRAI\11EIREQUESTING UDLC NUMBER,~) ISee Figure ~82) . ...................................................... ,...... .,.. :
IF SENSE_REGlSTERlO) NE O . .
I~EN_________ _______ _____ __ _______________________________~__ EL~E________ ABORT ~See Figure ~1) .
................................................. : ~ .
RETURN

.

., ~1~3 Figur~ 0-86. Flowchart of SENO RECEJV~ N~r P~ Y
AU tlIC VALUE = 8 ASSURANCE UNIT = F

AU LABEL = 8F

AU LENGTH = 8F

UNIT CHECK ~ FALSE

SUP MESSAGE WAITING~BUSY HIC = 83 .......................................................................................................................
BUILD SYSTEM SESSION (See Figure ~10) ................................................................................
-- . FRAME BUFFER(MESSAGE COUNT) = END
....................................... , ........... ; .................. --.
SEND FRAME(REQUESTING UDLC NUMBER,(MESSAGE COUNT~) tSee Figure 0-82) . ................................
IF SENSE_REGISTER(O) NE O
-[H~I_ _ ___ ___ _ _ __ _ _ _ _____ __ _ __ _ _ ___ _ ___ _ __ __ _____ __ _ ____ _____ __ _ __ El~E___ ___~_ . ABORT ~See Figure O-1~ .

. LOOK FOFI ACKNOWLEt~GE(REQUESTING UDLC NUMBER) ISee Fi~ure 0-~13) .. ,. _... ................... _..... .
IF ACKNOWLEDGE RECEIVED

RETURN
__________ __________________________________________________ ____ ~ _____ Figur~ ~87. Flowchort of SEND RECEIV~ READY
_ UDEC COMMAND = RR RESPONSE CODE
_ _ _ UDLC ~:OMMAND[6 TO 8) = OUTPUT RECEIVE VARIABLE~REQUESTING SSP NUMBER) .................................................................................................................... .
SEND FRAME~REQUESTING UDEC NUMBER,1) (See Figure 0-82) ;............................................ ........ ... ....... ..
. IF SENSE_REGISTER(O) NE O
T~E~I______ _ ____________________ ______ _______ ________________ ___ El.S~________ . ABORT (See Figure 0-1) . . .
:............................................ :
RETURN
_ - _ . . F~gur~ 0 88. Ftcv~ch~rt of SEAID UNNUM8E~ED ACl~NOWLEDGE
_ _ . UDLC COMMAND = UNNUMBERED ACKNOWLEDGE RESPONSE CODE
.........................................................................................................................
. SEND FRAME(REQUESTING UDLC NUMBER,1) (See Figure 0-82) ................ _. ....... :
IF SENSE_REGISTER~O) NE O
TI~E~_______ I~E_ __ __ ABORT ~See Fi~ur~ ~1) _................ ....,.... .......... ~ I
RETURN
._ - _ S' ~igu~ 0~9. ~towchort of 5~ L~D~ssp nvmb~r) _ SAU LOCKS = INPUTISAU LOCK PORT~
SAU LOCK ERROR = FALSE
SSP NUMBER = .
___________________ _____ ____________ __________________ _________________ . ~ ....................... , .
IF SAU LOCKS(5)-- 1 IF SAU LOCKS(6) = 1 IF SAU LO ::KSp) = 1 IF SAU LOCKS(8) = 1l ~N_____E SE_ ____~ L~L___ E SE ____-~ tl~N_ __E SE_____3 tlEN- ___E .~iE______ ERROR-- MASTER SAl) LOCK MASTER SAU LOCK MASTER ERROR-- MASTER
TRUE ~FIF--8 K TRUE BFIFT _OCoK TRUE PFIFT 20 TRUE BFIFT _OCK
RETURN RETU~N . RET','RN . RETURN _ ............... ~ ..... ............... ........... '.. ............... ............. .............. ..............
. . HARDWARE COMMAND I MASTER BIT LOCK FF, SAU LOCK PORT ) lSee Figure 0-34) :...... .............................................
IF HARDWARE ERROR
1 :JEN_____________________________________ _ __ ___ _ _____ ____~ ~iE________ SENSE REGISTERIO)--EQUIPMENT CHECK SEIJSE . .
. _ . PlO ERROR = TRUE
_ CODE ADDRESS = PC ADDRESS
MEMORY ADDRESS = SAU LOCK PORT .
.
RETURN
_ --_ -_ -- _ _. _ ~
SAU LOCKS--INPUT(SAU LOCK PORT) IF SAU LOCKS(5 ~o 8 ) LAND MASTER BIT LOCK FF~1 to 4~ = O
__________________________.. _________________________________ __ _ _____ SENSE REGISTER(O) = EQUlPMENt CHECK SENSE
REGISTER ERROR = TRUE
. _ _ CODE ADDRESS--PC ADDRESS
_ ._ MEMORY ADDRESS = l 60 _ ~ , RETl)RN

Fivur~ ~90. Fl~wch~r~ of SEr SAV LOC~
~' TABLE_ADDRESS = COMMAND_W()RD~1) IF SAT ADDRESS >- 15 I~IEI!I~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - _ -- - - - - - - - - - - - - - - - - - - - - - - - - - - - L~j~_ __ _ ~ _ __ TABLE_ADDRESS_OUT_OF_RANGE = TRUE

IF REQUESTED APPLICATION IS UNASSIGNED
ltlE~I _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . _ _ _ _ _ _ _ _ _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - rLS __ _ _ _ _ _ APPLICATION_UNASSIGNED_TO_SSP = TRUE
.
IF REQUESTING SSP NE SSP IN SSP_APPL_TABLE .
ItlE~I!I _ _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ __ - - - - - - --- - - --- -- - - - - - -- - --- - - L~;~_ ___ `_ _ _ UNAUTHORIZED_SSP = TRUE
. ~ _ IF SENSE _ REGiSTER[1J NE O
- T~ ____ __ __ _ ____ ___ ,L~___ _ ___ ___ _ _____ _ _ _ _ _____ UNIT_CHECK = TRUESSP APPI.ICATIO\I TABLEITABLE ADDRESS)(SAU
LOCK BIT) = 1 CODE_ADDRESS = PC~ADDRESS jSee .............................................. -~
Figure 0-52)SET_LED(ssp numberJ ~See Figure ~89) SENSE _ REGISTERIO) =IF SENSE REGISTER~O) NE O
COMMAND_~EJECT_SENSE T~EN _ ___ _____ ~ L~E__ . ABOllT
_ _ ~
RETURN

o~

Fiour~ ~9 r. Flo.YchO,t of sEr rFsr MODE
~ .
DO FOR I := O TO t5 _________________________________________________________________________ IF ANY SAU LOCK OF SSP APPLICATION TABLE IS SET -Itl~eJ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - EL~ - - ~
SENSE_R~GISTER(O~ := COMMAND_REJECT_SENSE .
. _ . .
UNIT_CHK := TRUE
, ' . .
CODE_ADDRESS = PC_ADDRESS (See Figure ~52) ~ . .

SAU_LOCK_EIT_SET = TRUE
. .
:
RETURN .
..... ............................................... ,..................... ........ ~
. OUTPUT(SET_MAINT_MODE,PARTITIONING_REGISTER_CONTROL_PORT) .
(See Fiyure 0-50~
.: ............................ :
RETURN

Figur~ ~92 F~owch~tt of S10 TEST
_~ .
INITIALIZE ALL SIDS FOR SEND AND RECEIVE

DO FOR I := t) TO MAX SSP NUMBR .
___________________________________________ ______ _______ _________ ____ SEND TEST Cl IARACTER TO S10 (1) . , P~ESET TRANSMIT UNDERRUN LATCH FOR S10~13 ' ' , . ' . ~
. DO FORI:= 8 TO 1 r-----------------------_-_______________ WAIT FOR READ CHARACTER AVAILABLE S10(1) . READ IN CHARACTER S10~1) IF TIMEOUT OR READ CHARACTER NE TEST CHARACTER
`. IHEel_ _ _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ _ - - - _ - - - - - - - - - -- - - - - - - - - - - - --- - - -- - - _ - I.~;E____ _ _ __ S10 ERROR = TRUE
. ' -- ~ .
CODE ADDRESS = PC ADDRESS
_ _ _ SENSE ~lEGlSTEFI~O~ ~ E(~UIPMENT CHECK SENS~
___ . . _ MEMORY ADDRESS = S10~1) .~
RETURN
_ __ RETURN
_ i; . .
.

Figuro t) 93. Flowch;ut of SPI OONFt~;~ttM770N
HARDWARE_READ_ SEEECTOR = INPUT(PATCH_ WORD_PORT(l~) , IF SPI_FEATURE3 1~ ~Y _ _ _ _ _ _ _ _ _-- . -.I..S~- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . MAX_SPI_ADDRESS = IFSPI_FEATURE2 127 I~E~_______________. ~S~__ __________________ __________ . MAX_SPI_ADDRESS = IFSPI_F~ATURE1 . . lli~ __ _ _ _ _ _ _ _ ~ _ _ __ _ _ _ _ _ _ _ _ . . . MAX_SPI~ADDRESS Mt~X_SPl_ADDRESS

_ _ __ _ _ __ I
. RETURN
_ , .

, - , ~0~ ~

Fi~ur~ ~94. ffowchJN of SVBrR4Cr lOf' ENA~LE_COUNrt~n~olssJ
DO FOR I := O TO 3 .
___________________________________________________ ___.__ ______________ SHIFT enables ONE BIT POSITION TO LEFT

. IEenable~3) = 1 I~E~_____._._ _ ____ _ _ ____ _____ _ _______ __ ___ _ E~SE______ IF IS~P_ENABLE_COUNT~SIT_IOP_NUMBERITABLE_ADDRESS,I)) = O .
I ~Y ______ ___ _______________________ ________ ___ ~___ _ . SENSE_REGiSTER(O)--I~ATA_CHECK_SENSE . .
, . ' . .
. AMBIGUOUS_DATA = TRUE . :-UNIT_CHECK = TRUE .
. : . .

. - . RETUR~I .

. IOP_ENABLE_COUNT(SIT_IQP_NUMBER~TABLE_ADDRESS,I)) =IOP_ENABLE_COUNT~SIT_IOP_NUMBER(TABLF._ADDRESS,I))- 1 _ . _ . RETURN

fi~ure ~95. Flowchort o~ SYSrEM SESSION C~JECKS ~p~rt r of ~)' _ IF SYSTEM SESSION HIC = 11 - 1~ ______ _ ELSE __ _____ _______ ____ ____________ _____ _ _ ____ _ __ . ERROR FLA~ = TRUE .
.
. CODE ADGRESS = PC ADDRESS
. _ .
. RETURN
~_ _ - __ _ IF SYSTEM SESSION I[) = 01 Itl~N___ ELS~_ _________ __----------------------------------------------- .
EilROrt FLAG = TRUE
. . _ _ . SYSTEIYI SESSION NUMBER ERROR = TRUE
.
. .CODE ADDRESS = PC ADDRESS . .
.
. RETURN

(iENERATE SYSTEM SESSION POlNTERS (See Fi~ure ~33 ) :...... ,......... .................... ,............. :
IF ERROR FLAG
THEN.________________ __----------------------------------------- ELS~___..____ RETURN

IF FRAME BUFFER~AU HIC POINTER)~5 TO 8) =FRAME BUFFER~SEG HIC POlNTER~I5 TO ~)AND
FRAME BUFFER~AU HIC POINTEFI ~ 1)--Ol IHE~____________________----------------------------------------- EL~_______ CODE ADI:)F;ESS = PC ADDRESS
_ ., ERROR FLAG = TRUE
.
RETURN
_ ~
**** flowcharI ~ontinued on fi~ure ~96 ****
_ ~

Fi3uro 0-96. ~wchD~ o~ S YS rEM SESS/ON CHECKS ~r~ i of 2)' . _ . _ , . _ ,_ ,,... .._ .. _ _ IF FRAME BUFFER~SEG HIC POINTERN7) = FIRST
lEI!I__ _______ ____ _______________~ ~S~_______________________________________ AU LENGTH = FRAM BUFFERlAU HIC IF AU LABEL = FRAME BUFFER(AU HIC POINTER .
POINTR + 1 ) . - ~ 2 ) _ . JlEJY__E L,SE_____ __- --- ~~~~~~~~~~~~~~~~~~~~~
AU LABEL a FRAME BUFFER(AU HIC . CODE ADDRESS = PC ADDRESS
POINTER ~2 ) . .. _ ._ _ . ERROR FLAG--TRUE .
ASSUF1ANCE U~IT HIC = C . _ _ . ~ . - RETURN .
._. ~ `- ... ~ _ ._ ... _ -.
PARAh1ETER LSB = FRAME E~UFFER[SUP END HIC POINTER ~ 3) ... _ . . _ . ......... .. __ ._ .
PARAMETER MSB = FRAME BUFFER~SUP END HIC POINTER ~ 4~
_ , ,, . _ .
. . AX SEGMENT LENGTH := 256 - FRAME CHECK SEQUENCE - ~SUP END HIC POINTER * 1~ -~4 * SEG HIC FIRST FLAG) . ._ ... . ._ _ ....... _ _._ . .
FRAME BUFFER~SEG HIC POINTERJ~7 TO 8~ SPECIFIES.
___ ________________ _ ___________________ _____________________ _______ ___ FIRST/LAST FIRST LAST NTERMEDIAT
_ .__ .... .. ... _ ~ ............... ... .... . _ F NOT MULTIPLE FRAME IF NOT MULTIPLE FRAME IF MULTiPLE FRAMF IF ~ULTIPLE
ESSAGE AND TEXTL HIC MESSAGE AND TEXTL HIC MESSAGE AND MESSAGE FRAME
PRESENT AND PRESENT AND COUNT LE MAX SEGMENT ~ESSAGE
PARAMETER LENGTH LE PARAMETER LENGTII GT LEN TH AND
HEI!I______ E NT LENGTH HE~I ______~ ~iE_______ HEIY______ E SE ______ MESSAGE
MESSAGE COC~E MULTIPLE CODE FRAME ADDRESS = SE
COMPLETE ADDRESS--FRAME ADDRESS = MESSAGE = C ADDRESS GMENT
--TRUE PC ADDRESS MESSAGE = PC ADDRESS FALSE ._ J:E ~GT.51 ._ TRUE ERROR FLAG . CODE
ERROR FLAG ERROR FLAG MESSAGE = TRUE . ADDRESS
_ TRUE = TRUE COMF'LET . = PC
= TRUE ADDRESS
. .ERROR
.FLARG E--_ _ .... __ _ ._ ~ ~
RETURN

figuro 0-97. F/owchdrt o~ UDLC COD~C TfL4NSPLANJ
__ . POP RETURN ADDRESSINTO HLREGISTERS .
.
STORE HLIN SAVEHL -BC = 6FFHEX BY~TES TO TRANSFER .
_ . HL = 2000 HEXlSTART ADDRESS OF ASMUDLCIN PROM) . .
DE = 6000 HEX~START ADDRESS OF ASMUDLCIN RAM) _, .
DE _ HL
. , - _.
HL = HL + 1 DE = DE ~ 1 BC = BC-l ____________ ______________..______________.______________________________ REPEAT UNTILBC = O

LOAD HL WITH SAVEHL~RETURN ADDRESS) . _~
PROGRAM COIJNTER REGISTER - HLREGlSTERStRETURN).

Figuro (~B. flowchort of UNCOflrl~CTA8LF M~MOflY EflflO~
_ _ SENSE REGlSTERlO) = EQUIPMENT CHECK SENSE
_ .
MEMORY ADDRESS = ADDRESS POINTER
.
UNCORRECTABLE MEMORY ERROR = TRUE

SYNDROME[4T08; = SYNDROME TRAP~lT05) .
..................................... -. LOOK FOR SENSE PENDlNGlSee Figure ~47~
............... ..............................................................
RETURN
-- Fi~Juro ~5/~. flowchort of VfhUFY~si!Jnol,sigo~l_ou~put portJ
_ _ _ TEMP(:IRARY_REGISTEF;_2 := INPUT(signal_output_port) IF TEMPORARY_REGISTER_2 ---si~nal T~~_____________ _ __ _____ -_-------- LS_____~ _.______-------------------HARDWARE_ERROR := FALSE HARDWARE_ERROR:--TRUE
. ~
RETURN

.. ... .. , - - . .. . :

Fpur~ OO. ~lowcho~t o~ W~ITE_CONTROL_STORE
BYTE_COUNT_ COMMAND_WORDI1) _ .
CONTROL_STORE_ADDF;ESSI1 TO S) = CGMMAND_WORDl2) CONTROL_ STORE ~ADDRESS~9 TO 1~) = COMMAND_WORD~3;

CONTROL_ STORE_ADDRESS = CONTROL_STORE ADDRESS + HEX 40QO

tF BYTE_COUNT = O
I~EU__ ______________ _ ______~_____________ ____ ____ ________ E~SE_______ RETUR~ . .
. ~
IF CONTROL _ STORE_ADDRESS ~ HEX 4000 OR CONTROL_ STORE_ADDRESS
BYTE_COUNT- 1 >HEX ~;FFF
I~E~ ___ ___ ____________________~_____ ____ ____________________ .L~E________ TABLE_ADDRESS OUT_OF_RANGE = TRUE
_ _ ~
1)0 FOR I = O TO 15 ____ ___________________________~_______________________________________ . IF ANY SAU LOCK BIT IS SET OF SSP_ APPLICATION_TABLE
I~ENL_____________ _________________ E~E______._ SAU_LOCK_ BIT_SET = TRUE ~
__ . - _ _ IFANYERRORS OCCURRED
I~E~ _ -__ ________ __ . L~E;_ _ __ l SENSE_REGISTER~O) -.BLKTRAN IADDRESS_ OF_DATA_BUFFERlO),- .
COMMAND_REJECT_SENSEREQUESTED CONTROL STORE ADDRESS) ~Ses Figure Q-~ :
: - :
CODE_~DDRESS = PC_ADDRESS (See Fi~ure 0~52) ..
. : :
UNIT_CHECK = TI~UE _ ~ ... ,.
F~ETURN
_ Fi3ur~ 0-10~. F~owch~r~ of WR/rE_IOP_STArE
IOP_NUMBER := IOP NUMBER lî3 COMMAND WORD
_ IOP_STATE := IOP STATE IN COMI~lAND WORD
_ .
IF IOP _ STATE DOES NOT SPECIFY AN APPLICATION OR OFFLINE
~l~i~_ _ _ _ _ _ _ _ ` _ _ _ _ _ _ _ ___ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ELSE__ _ _ _ _ _ lOi_STATE_ERROR := TRUE
. ~
IOP_STATE SPECIFIES AN APPLICATION AND IOP_STATE_TABLE(IOP_NUMBER) DOES NOT
SPECIFY AN OFFLINE
li~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ _ __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ELSE__ _ _ _ _ _ IOP_STATE_ERROR := TRUE
~ _ IF IOP _ STATE SPECIFIES OFFLINE AND IOP _ STATE _ TABLEIIOP_NUMBER) DOES NOT
SPECIEY AN APPLlCATln~l OR UNASSIGNED
liHEU_______________ ____ _ ______-------------------------------- ELS_______ IOP_STATE_ERROR := TRUE
.
IF lOi_STATE SPECIFIES OFFLINE
I~E~ ____ LS_ __ _____ _____ _________ __--------------------------------:IF REQUESTING _ SSP _ NUMBER IS SSP ASSIGNED TO IOP_STA~i .Tt! E~_ _ _ _ _ _ _ ELS__ _ _ _ _ _ __ _ _ _ _ _ __ _ _ _ _ _ _ -- - - - - - - - - - - - - - - - - - - -- - ---- -.-. UNAUTHORIZED~SSP := TRUE
~,.. ' v ~
IF IOP_STATE_TABLE(IOP_NUMBER) IS OFFLINE OR UNASSIGNED
TtlE~J____ ___ E!~SE_ __ _ __ _ ___ ___ _ ______ _ _____ ____ ___ __ _ __ _ _ _ __ ____ ____ __ _ . IF REQUESTING _ SSP _ NUMBi R = SSP ASSIGNED TO APPLICATION
. SPE:CIFIED B~ IOP_STATE_TABLE~IOP_NUMBER) :Tt!E~L _ ___ _ EJ.S _ _ _ _ _ __ _ _ __ __ _ _ _ _ _ _ _ __ _ _ - _ - - - - - - - - - - - -- - - - - - - - - - --.. UNAUTHORlZEi~_SSP := TRUE
v IF IOP _ NUMBER IS ENABLED TO ANY SUBSYSTEM
liYEN _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ELS~_ _ _ _ __ _ _ IOP_CURPENTLY_ENABLED: _ TRUE
____ _ ___ IF SENSE _ RElilSTER(1)--O
T~EN__________ _____________ _-------- LSE____ ____ _________---------------IOP _ STATE TABLE(IOP _ NUMBER) := UNIT_CHECK := TRUE
I r~ n s ~-~ A -r~
v~ _O . . . SENSE _ REGISTER[O) :c . PARTITIONING_Cl IECK
.
. SENSE _ RESiSTERI2 ~ - PC _ADDRESS
. ISe~ Fi~ura ~52) _. _ Rf ETURN
, -- -~ .

~DO~ ~ -_ ~ ?
.
Firure? ~102. Flowchart ~ WPlITE PAf'~rlJlONtNG P~EGISTER
r A~D VEF~IFYITA'8LE 'AOURE~S,P~RTITI~)N~I~G R'~ i'TER' ' 'ADt)RE~;S - P~RT~
, .. , ., .,,, ., ., .. ~Se,e, .F,ig,u,re. ~51).. , .................. :
IF HARDWAR_ERROR l,SE
~?E~_____________________________________________________________ ________ SENSE_REGISTER~O) = EQlJlPMENT_CHECK_SENSE
_ :
P10_ERP~OR = TRU
C:ODE ADDRESS = PC_ADDRESS (See Figure 0-52j .
li~EMORY_ADDRESS = PARTITIONING_REGISTER_ACDRESS PORT .
....................................................................................................
: ABORT (See Figure 0-1) , .
~ 9i~iT'Ui _ ?ANV_~t~liYt~i-r PARiiilUNiNi~ CCiN'ii~Ui ~ L~_Al ~5 : . PARTlTiONlNG _ REGISTER_ WRITE_POF~) , IF HARDWARE_ERROR ~ E
I~E~L_____________________ _____________________________________ .~ _ ____ . SENSE_.REGlSTERtO) = EQUIPMENT_Cl IECK_SENSE
__ _ _ P10 ERROR = TRUE
_ CODE_ADDRESS = PC_ADDRESS (See Figure t~52) _ . .
MEMORY_ADDRESS = PARTITIONING_REGISTER_WRITE_PORT .
..................................................................................................... , .. :ABORT ISee Figure ~1~ : .
:................................................ v_. I
. IF Fi AGS NE INPUT~PARTITIONING_REGISTER_WRITE_POP~T) L~E
I~E~L___ _________ __ ___-------------------------------------- ________ SENS~_REGISTER(O) = EQUIPMENT_CRECK_SENSE
REGISTEF._ERROR = TRUE
_ _ CODE ADDRESS = PC_ADDRESS ~See Figure 0-52) _-- _ _ __ MEMORY_ADDRESS--PARTITIONING_RE(~ISTER_WRITE_POPlT
............................................. ,.................... ..........:
' ABt:)RT ~See Figure ~ .
_ RaL- PORT)--.
ISee Fi~ure 0-34) _ ................................................ , ........... ..............
IF HARDWARE_ERROR LSE
T~E~L __ _ __ _ __ ~ _____ __ SENSE_REGISTEFI~O~ = EQUIPMENT_CHECK_SENSE
_ P10 ERROR = TRUE
_ .
CODE_ADDRESS = PC_ADDRESS (See Figure ~52 MEMORY ADDF/ESS = PARTITIONING_REGISTER,_CONTROL_POR~
.................... ................................................................................
: ABORT ISee Figure 0-1) :................. .............................................................. ~ .
RETURN
_ - _ ',' . ' ' ' .

ur~ 03. F!owch~rtof Wf~IrESSP ~Is~o~r ., ~
IF COMMAND _ WORDl2) ~ 3 I~E~_____________ _____________ __ ___________________ __________ L~E________ . . TABLE ADDRESS OUT OF RANGE = TRUE .

CODE ADDRESS := PC ADDRESS
. _ IF COMMAND _ WORD(l~ SPECIFIES 'MICROCODE LOADED~
T~________________ _ ______ _ _______ __ ________________ ___ ELSE______ IF CONTROL STORE SENTINEL = 76~hex) .
.~1~_______ LSE__________ _________ _____ ___ _ _____ ___________ .
.CONTROL STORE NOT LOADED = TRUE . .
. _ .CODE ADDRESS := PC ADDRESS .
~ .
IF COMMAND_WORD(l) SPECIFIES ~IOP NUMBERS LOADED~
.I~EU_________________ _ _________ ________ ___-------------------- EL~E______ .. If SIT_IOP NUMBER~159,3~ = X~FF- -; I~________________ ____________________________________ ~5~______ IOP NUMBERS NOT LOADED = TRUE .

CODE ADDRESS := PC ADDRESS

. IF SENSE _ REGISTER~l) = O
.I~EN-- ___ ________ _ ~ ___ ___ ____L~E______ _______. _ __ ________ SSP_HISTORY_TABLED~COMMAND_WORD~2)) :=SENSE _ RE(ilSTER~O) := COMMAND
SSP_HlSTORY_ TABLElCOMMAND_WORD~2)) LORREJECT SENSE
COMMAND_WORD 11) UNIT CHECK := TRUE
DO FOR 1:= O TO 3 ___________________________________.____ SSP _ HISTOR`f _ TABLE(1)(3 TO 4) :=
SSP _ HISTORY _ TABLE(1)(3 TO 4) LOR
. COMMAND_WORDIlN3 TS~ 4) _ . -I
. RETURN
_ ___ ., ~. . . .. .

F;~ur~ 0-10~. ~JowchDrt of WPflTE_SSP_ NUlUBEf~
. _ _ IF COMMAND_WORDI2~ ~ 15 1~~_______________~__________________________ _______ __ ______ L~E___ ___ TAaLE_ADDREss_ouT_oF RANGE``= TRUE
_ . _ ~
IF SAU LOCK SET FOR REQUESTED APPLiCATlON
I~E~______________________________ _ __ ________________________ ~S_______ I .
SAU_LOCK_BIT_SEr _ TRUE .
_ _ ~
. IF SENSE_REGISTER~l) = O
I~E~___ .______ _____ _______ ___ ____ ELSL ___ _____ _____ ____ WRITE SSP NUMEIER FOR REQUESTEI~ SENSE_REGISTER~0) =
APPLICATION COMMAND_REJECT SENSE

CODE_ADDRESS = PC_ADDRESS(See . Figure ~52~

UNIT_CHECK _ TRUE

RETURN
__ .,. J
Fi~uro ~105. FJow~hort of W~/~ SUBSYSTEM IOP NVM~ERp~rt J of y ERROR F~AG = FALSE
. , , .
IF DATA _ LFNGTH NE 804 I ~I!L___ __ _______ ______________ ________________________ ____ L~E___ SENSE_REGISTER[0) = LENGTH_CHECK_SENSE
DATA_LENGTH_ERROR = TRUE
_ .
CODE_ADDRESS = PC_ADDRESS (See Figure ~52) . ~:
UNIT_CHK--TRUE .
_ :
RETURN -DO FCR I - 0 Tt) 15 __________________________________________________________________ ______ IF ANY SAU LOCK BIT OF SSP APPLICATION TABLE IS SET
I~E~ _ ____ _ _ __ _ _ _ ELSE __ _ SENSE REGISTER~0) = C0MM~ND REJECT SENSE
SAU LOCK BIT SET = TRUE ; .
UNIT CHECK = TRUE . .
. .CODE ADDRESS = PC ADDRESS ~See Figure ~52) .
RETURN
_ . _ ~, MASCOUNT = 0 -DATA_LENGTH = O
IF FIRST MAS Bll IS SET
I~EN________ _ : _ _- -------- ~S __ __ SENSE REGISTERl0) = DATA_CHECK_SENSE
IRST_MAS_BIT_ SET = TFlUE
.
CODE_ADDRESS = PC_ADI)RESS ~ee Figure ~52) .
_ UNIT_CHECK = TRUE .
RETURN
_ -** flowehart cont~nued on fi0uro ~106 , Fiyur~ ~tO6. Flo~chort of WRITE SUBSYST~M IOP N~JM~JER~Po~l 2 of 2J
DO FOR J = O TO 159 _________~_________..______________________________________________________ SIT PARTITIONING CONTROL FLAGS(J)lMAS _ 1j = DATA
BUFFER~DATA_LEN5TH)iMAS_3~
. . , .

IF SPI TA8LE ENTRY AND MAS BIT = 1 r~u~L ~L~i~________ _______ ________________________ MASCOUNT = MASCOUNT + î IF SPI TABLE ENTRY, MAS BIT = O
r~L .~i~
IF MASCOUNT > 3 SIT MAS ENTRY IF BCTS TABLE ENTRY, MAS BIT =
~N__ _. J L~E____ _ __ NUMBERIJ) = O O
SENSE NUMBER~J) = REINITIALIZE r~N - L~E

SENSE MASCOUNT MASCOUNT TO O NUMBER(J) = O DATA CHECK
MAS ENTRIES GT
4 = TRUE . . --TFtUE
.,. 1 .
; UNIT CHECK =
TRUE VNIT CHECK =
_ TFIUE
CODE ADDRESS _ .
= PC ADDRESS CODE ADDRESS
~See Figure = PC ADDRESS
~52) tS0e Fi~ure . . 0-52) RETURN
RETURN
_ __ _ _ _, DO FOR K = O TO 2 BY 2 SIT IOP NUMBER~J,KI _ DATA BUFFER(DATA_LENGTH+iC~1) SIT IOP NUMBER~J,K+1j = DATA BUFFER~DATA_LENGTH+IC~2) _ INCREMENT INDEX TO D~TA_BUFFEP~
RETURN
_ -,.
~..

~J~ _

Claims (34)

Claims:
1. A central controlling unit, for use with a plurality of data processing systems, none, some, or all of which are capable of being partitioned into a further plurality of separate entities, having the characteristics of a complete data processing system and a plurality of subsystem interface connections, said central controlling unit comprising:
enabling/disabling connection means connected to said plurality of subsystem interface connections for dynamically enabling/disabling, from a central location, said plurality of subsystem interface connections to selected entities and/or systems; and means coupled to said enabling/disabling connection means for maintaining these enabled/disabled inter-connections for as long as desired from undesired appropriation; and storage means commonly connected to said enabling/
disabling connection means and to said means for maintaining these interconnections, said storage means having residual information stored therein to cause various subsystem interconnections in response to corresponding system command signals.
2. A subsystem access unit which supports subsystem partitioning for multisystems and/or for multiprocessing systems comprising:
enabling/disabling connection means coupled to the interfaces of said subsystems for enabling/disabling said interfaces;
means coupled for receiving one or more command source signals associated with said multisystems and/or said multiprocessing systems to activate said enabling/disabling connection means; and storage means commonly coupled to said enabling/
disabling connection means and for receiving said command source signals, said storage means having stored therein resident information to cause various combinations of enabling/disabling interface connections and to enforce the integrity of said command source signals by preventing undesired misappropriation of said subsystems by preventing erroneous enabling/disabling of said subsystem interfaces.
3. A plurality of data processing systems, none, some, or all of which are capable of being partitioned into a plurality of separate system entities, each data processing system and/or each entity comprising at least one central processor unit, at least one I/O processor, and at least one memory, at least one peripheral subsystem commonly connected to said plurality of data processing systems and/or said plurality of separate system entities, and a subsystem access unit commonly connected to said plurality of data processing system and/or separate system entities and to said at least one peripheral subsystem to enable/
disable communication between the I/O processor of each of said pluralities of data processing systems and/or entities and said peripheral subsystem and to monitor and maintain accessibility/inaccessibility between the I/O processors and said peripheral subsystem.
4. The data processing system as set forth in claim 3 wherein said peripheral subsystem includes switching control means under the control of said subsystem access unit whereby portions of said switching means may be selectively activated/inactivated by said subsystem access unit to thereby provide selective communication between said I/O processors and said peripheral subsystem wherein said peripheral subsystem may be operated on a shared/non-shared basis by said I/O processors.
5. The invention as set forth in claim 4 wherein said system access unit comprises:
(a) a first interface means coupled to said plurality of data processing systems and adapted to receive commands from one or more command sources;
(b) a second interface means connected to the switching control means of the peripheral subsystem; and (c) a microprocessing control system connected between said first and second interface means whereby certain commands received by the command interface provides selected switching control signals at said second interface to activate/deactivate selected switching portions of said switching control means thereby allowing communication between certain I/O processors and selected portions of said peripheral subsystem.
6. The invention as set forth in claim 5 wherein said microprocessing control system includes a plurality of microprocessors, a plurality of serial input/output means and a plurality of parallel input/output means.
7. The invention as set forth in claim 6 wherein said plurality of microprocessors includes a main and a redundant microprocessor which are operated constantly in phase while performing identical operations.
8. The invention as set forth in claim 7 wherein said microprocessing control system further includes a comparing means connected between said main and redundant micro-processors which constantly monitors the output signals of both microprocessors and indicates a miscompare signal whenever said main and redundant microprocessors provide different output signals.
9. The invention as set forth in claim 6 wherein said microprocessing control system includes a pair of serial input/output means associated with each of a plurality of channels.
10. A subsystem access unit for use in conjunction with a, partitionable multisystem and/or a multiprocessing system, wherein each of said multiprocessing systems is capable of being partitioned into a plurality of separate entities, each entity having at least one instruction processor, at least one memory storage unit and at least one input/output processor, at least one peripheral subsystem, wherein said subsystem access unit is coupled to the data processing systems of said multisystem and/or to the entities of said multiprocessing system and includes means for enabling/disabling communication between input/output processors and said common peripheral subsystem, and enforcing exclusive use thereof once the communication link is enabled.
11. The invention as set forth in claim 10 wherein said centralized peripheral subsystem access means comprises:
(a) a plurality of command source interface means coupled to said data processing systems for receiving commands therefrom;
(b) a plurality of enabling/disabling means connected between said input/output means and said peripheral sub-system for providing selective intercommunication therebetween; and (c) a control means coupled to said plurality of command source interfaces and connected to said plurality of enabling/disabling means for monitoring of the status of said enabling/disabling means by providing access to said enabling/disabling means when it is indicated, and for forcibly preventing such access when that is desired.
12. In a plurality of data processing systems, none, some, or all of which are capable of being partitioned into one or more separate entities, said data processing system having more than one instruction processing means, more than one memory means, more than one input/output processing means and at least one peripheral subsystem, a centralized control system comprising:
(a) dynamically enabling/disabling means coupled between the peripheral subsystem means and the remainder of the means of the data processing systems to provide or prevent intercommunication therebetween;
(b) policing and enforcing means further coupled to said peripheral subsystem means to determine, monitor and maintain the accessibility or inaccessibility of said peripheral subsystem to one or more of said systems or partitionable portions; and (c) central control means commonly connected to said data processing system and said peripheral subsystem to provide control for the dynamic enabling/disabling means and for the policing and enforcing means, via external, intelligent message protocols.
13. A centralized controlling system for use with a plurality of data processing systems each of the plurality of data processing systems capable of isolated performance, a peripheral subsystem coupled to said plurality of data processing systems for either shared or non-shared use by the separate ones of said data processing systems, said centralized controlling system comprising:
enabling/disabling means for dynamically enabling/
disabling hardware communication links between the plurality of data processing systems and the peripheral subsystem;
further means coupled to said enabling/disabling means for policing and enforcing accessibility/inaccessibility of the peripheral subsystem once the enabling/disabling decision has been accomplished; and controlling means commonly connected to said enabling/
disabling means and said further means for providing this control via external, intelligent message protocols.
14. A subsystem access unit (SAU) for use in a partitionable multiprocessing system, said SAU comprising:
(a) means for the interface coupling of said SAU to one or more command sources;
(b) means for the interface coupling of said SAU to one or more shared peripheral interfaces;
(c) means for the interface coupling of said SAU to one or more serial channel transfer switch interfaces;
(d) means interconnected to (a), (b) and (c) for receiving information from said command sources, processing same, and therefrom providing switching information via said shared peripheral interfaces and said channel transfer switch interfaces which switching information is capable of not only enabling/disabling communication paths between a plurality of processing systems and a plurality of peripheral devices, but policing and enforcing said enabling/disabling decisions to allow exclusive use of a certain peripheral device by a certain system.
15. A method of dynamically disconnecting and/or exclusively connecting data processing systems and/or partitions/applications of partitionable multiprocessing systems to a peripheral subsystem through the use of the resident information of a subsystem access unit comprising the steps of:
(a) sending a first identifying request signal from a command source to said subsystem access unit;
(b) accessing a cabling information table within the resident information stored in said access unit;
(c) providing the identification of an input/output processor from said cabling information table;
(d) supplying the application number affected by this identified input/output processor from the input/output processor/application designation table within said stored resident information;
(e) supplying from a command source/application designation table of said resident information, the inter-face number assigned to that application;
(f) comparing the assigned command source interface number with the requesting command source interface number;
(g) if a mixmatch exists, rejecting the request;
(h) if a match exists, determining if change can be made, using the partitioning status information status and the exclusive use status information;
(i) if change cannot be made, rejecting the request;
(j) if change can be made, effecting the change.
16. A method of dynamically changing the application assignments of peripheral units of a shared peripheral subsystem to other application assignments within a multi-processor system and/or a multisystem by remotely controlling a switching peripheral control unit from a subsystem access unit comprising the steps of:
(a) sending a command request to said subsystem access unit requesting a particular interface;
(b) from a cabling information table within said sub-system access unit providing the identification number of the I/O processor making the request;
(c) using the input/output processor identification number, determine from the I/O processor/application designation table of the resident information which application is affected;
(d) using the application number, determine from the command source/application designation table of the resident information, the command source interface number assigned to that application number;
(e) compare this assigned command source interface number with the requesting interface number;
(f) if a mixmatch exists, reject the request;
(g) if a match exists, determine if a change can be made using the resident information on partitioning and exclusive use status;
(h) is the change cannot be made, reject the request;
(i) if the change can be made affect the change.
17. A peripheral subsystem access unit for use in centrally controlling multisystem or multiprocessing system access to shared and non-shared peripheral sub-systems comprising:
a microprocessing means;
a plurality of serial input/output circuits commonly coupled to said microprocessing means;
a plurality of parallel input/output circuits also commonly coupled to said microprocessing means;
a memory means coupled to said microprocessing means;

an input/output read selector connected to said plurality of serial and parallel input/output circuits;
a bidirectional data bus interconnected between said microprocessing means, said pluralities of serial and parallel input/output circuits, said memory means and said input/output read selector to provide a communication path therebetween;
a plurality of shared peripheral interface registers;
a plurality of byte channel transfer switch interface registers; and another data bus interconnected between said pluralities of shared peripheral interface registers and said byte channel transfer switch interface registers and the plurality of parallel input/output circuits to provide a data path therebetween.
18. The peripheral subsystem access unit as set forth in claim 17 wherein the microprocessor includes means for generating a plurality of address signals and a plurality of control signals to supervise control of the signals along the bidirectional data bus.
19. The peripheral subsystem access unit as set forth in claim 18 wherein said plurality of address signals com-prise a sixteen (16) bit address signal and said plurality of control signals comprise five (5) control signals.
20. The peripheral subsystem access unit as set forth in claim 19 wherein said five (5) control signals comprise an:
(a) Instruction fetch cycle signal; a (b) Memory operation signal; an (c) Input/output operation signal; a (d) Read signal and a (e) Write signal.
21. The peripheral subsystem access unit as set forth in claim 20 wherein the microprocessor further includes means, using the address and control signals, for reading its program instructions from said memory and further means enabling it to perform the following operations under program control to:
(a) Read or write each serial input/output register; to (b) Read or write each parallel input/output register;
to (c) Read or write into the memory; and to (d) Read data from the input/output read selector.
22. The peripheral subsystem access unit as set forth in claim 17 wherein each serial input/output circuit includes further means enabling it to translate a serial message from a 250K baud interface means into a series of eight bit bytes that can be read by the microprocessor or to translate bytes from the microprocessor into serial data for transmission on the 250K baud interface means.
23. The peripheral subsystem access unit as set forth in claim 17 wherein the interface read selector includes means for allowing the microprocessor to read a plurality of information bytes by doing an input/output operation.
24. The peripheral subsystem access unit as set forth in claim 17 wherein each of said parallel input/output circuits includes two eight (8) bit parallel input/output ports that can be used as input or output means, which ports are used to communicate with the shared peripheral interface registers and the byte channel transfer switching interface registers.
25. The peripheral subsystem access unit as set forth in claim 17 wherein the data bus interconnecting the shared peripheral interface registers, the byte channel switch interface registers and the plurality of parallel input/
output circuits further includes:
(a) means for generating an interface address;
(b) means for generating write data for the interface registers;

(c) means for generating a write signal for the inter-face registers; and (d) means to provide a read path for the data from the interface registers.
26. The peripheral subsystem access unit as set forth in claim 25 wherein the generated interface address comprises an eight bit signal capable of selecting an interface register for a read or write operation.
27. The peripheral subsystem access unit as set forth in claim 26 wherein the registers associated with the read path means capable of carrying the data from the interface are read only registers used as data assurance means whose bit status is maintained as an entry in a subsystem inter-face table in the memory means enabling the microprocessor to use these signals to read or write into the interface registers through the parallel input/output circuits.
28. The peripheral subsystem access unit as set forth in claim 27, wherein the contents of each of these inter-face registers are used to drive the shared peripheral interfaces and the byte channel transfer switch interfaces.
29. The peripheral subsystem access unit as set forth in claim 17 wherein said microprocessing means includes a further memory means.
30. The peripheral subsystem access unit as set forth in claim 17 wherein the memory means includes an error correction means.
31. The peripheral subsystem access unit as set forth in claim 30 wherein the memory error correction means is accomplished by means capable of error correction whenever reference is made to the information resident therein.
32. The peripheral subsystem access unit as set forth in claim 17 wherein further means are included for reading information from the byte channel transfer switch interface registers which indicates the enable/disable status of the interface channel.
33. The peripheral subsystem as set forth in claim 17 wherein further means are included for reading information from the shared peripheral interface registers which indicates the enable/disable status of that interface.
34. The peripheral device as set forth in claim 9 wherein the pair of serial input/output means associated with each of a plurality of channels are interconnected in a manner to provide a redundant path for comparison by the microprocessor on incoming messages and to further provide a turnaround path for comparison by the microprocessor on outgoing messages and thereby accomplish an error checking function.
CA000424901A 1982-07-07 1983-03-30 Centralized hardware control of multi-system access to shared and non-shared subsystems Expired CA1186414A (en)

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