CA1190615A - Switched capacitor n-path filter - Google Patents
Switched capacitor n-path filterInfo
- Publication number
- CA1190615A CA1190615A CA000411583A CA411583A CA1190615A CA 1190615 A CA1190615 A CA 1190615A CA 000411583 A CA000411583 A CA 000411583A CA 411583 A CA411583 A CA 411583A CA 1190615 A CA1190615 A CA 1190615A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 106
- 238000000034 method Methods 0.000 claims description 10
- 238000010276 construction Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 2
- FHNINJWBTRXEBC-UHFFFAOYSA-N Sudan III Chemical compound OC1=CC=C2C=CC=CC2=C1N=NC(C=C1)=CC=C1N=NC1=CC=CC=C1 FHNINJWBTRXEBC-UHFFFAOYSA-N 0.000 description 1
- 102220414579 c.213T>C Human genes 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035772 mutation Effects 0.000 description 1
- 102220109507 rs2230906 Human genes 0.000 description 1
- 102220042260 rs34160178 Human genes 0.000 description 1
- 102220213184 rs370284124 Human genes 0.000 description 1
- 102220062291 rs761825242 Human genes 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H19/00—Networks using time-varying elements, e.g. N-path filters
- H03H19/002—N-path filters
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
- G06G7/18—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals
- G06G7/184—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals using capacitive elements
- G06G7/186—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals using capacitive elements using an operational amplifier comprising a capacitor or a resistor in the feedback loop
- G06G7/1865—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals using capacitive elements using an operational amplifier comprising a capacitor or a resistor in the feedback loop with initial condition setting
Abstract
SWITCHED CAPACITOR N-PATH FILTER
By Chieh Chang and Man Shek Lee ABSTRACT OF DISCLOSURE
A switched capacitor N-path filter in which all capacitors that introduce delay in the paths, in that they have memory and are characterized such that the new charge flow into each such capacitor during each commutation cycle depends on the old charge on it from the previous commutation cycle, are replaced with an associated plurality of N-commutating capacitors.
By Chieh Chang and Man Shek Lee ABSTRACT OF DISCLOSURE
A switched capacitor N-path filter in which all capacitors that introduce delay in the paths, in that they have memory and are characterized such that the new charge flow into each such capacitor during each commutation cycle depends on the old charge on it from the previous commutation cycle, are replaced with an associated plurality of N-commutating capacitors.
Description
s 3Thls invention relates to switched capacltor N-path 4 fllters and to an ~mproved method of syntheslzing switched capacitor N-path filters.
6 A monolithic N-path filter lmplPmPnted wlth r~os sampled 7 data techniques is described ln the artlcle, "A Switched Capacitor 8 N-Path Filter" by D. J. Allstot and K. S. Tan, IEEE International 9 Symposiun on Circuits and Systems, rkay 1980, pp. 313-316.
The idea there is to develop a 11 switched capacitor active-ladder equivalent of a prototype ladder 12 fllter with the energy storage or integrating capacitor Or each 13 integrator being replaced by N ldentical commutating capacitors and 14 MOSFET switches which share a co~mon active element. Although this technique gives additional freedom in designing filters wlth 16 trans~er functions having co~rle~ poles and zeros and provides fullD
17 integrated N-path filters, it has been found that the 18 characteristlcs of the resultant network only approximates 19 those of the co~ onding prototype ladder filter, i.e.~ the ripple and loss in the prototype and resultant filters may not be the same 21 magnitudes nor that predlcted by N~path filter theory 22 An ob~ect of thls lnvention is the provislon of an 23 improved switched capacltor N~path filter.
24 SUM~URY CF ~rVENTION
In accordance wlth this invention, a commutating switched 26 capacitor integrator circuit in a N-path rllter comprises: an active 27 element having a ~irst input termlnal and an output terminal; a 28 first plurality o~ N capacltors, each having the s~ne value of 29 capacitance; first switch means selectively~sequentially connecting, at a oommutating rate, indivldual ones of the flrst plurality of 31 capacltors a~ integrating capacitors between th~ active elements7 32 flrst lnput and output terrninals only durlng associated palr9 of
6 A monolithic N-path filter lmplPmPnted wlth r~os sampled 7 data techniques is described ln the artlcle, "A Switched Capacitor 8 N-Path Filter" by D. J. Allstot and K. S. Tan, IEEE International 9 Symposiun on Circuits and Systems, rkay 1980, pp. 313-316.
The idea there is to develop a 11 switched capacitor active-ladder equivalent of a prototype ladder 12 fllter with the energy storage or integrating capacitor Or each 13 integrator being replaced by N ldentical commutating capacitors and 14 MOSFET switches which share a co~mon active element. Although this technique gives additional freedom in designing filters wlth 16 trans~er functions having co~rle~ poles and zeros and provides fullD
17 integrated N-path filters, it has been found that the 18 characteristlcs of the resultant network only approximates 19 those of the co~ onding prototype ladder filter, i.e.~ the ripple and loss in the prototype and resultant filters may not be the same 21 magnitudes nor that predlcted by N~path filter theory 22 An ob~ect of thls lnvention is the provislon of an 23 improved switched capacltor N~path filter.
24 SUM~URY CF ~rVENTION
In accordance wlth this invention, a commutating switched 26 capacitor integrator circuit in a N-path rllter comprises: an active 27 element having a ~irst input termlnal and an output terminal; a 28 first plurality o~ N capacltors, each having the s~ne value of 29 capacitance; first switch means selectively~sequentially connecting, at a oommutating rate, indivldual ones of the flrst plurality of 31 capacltors a~ integrating capacitors between th~ active elements7 32 flrst lnput and output terrninals only durlng associated palr9 of
-2 1 ad~acent time slots for storing charge; and connecting means for 2 selectively-sequentially connecting one of: (1) one and other sides
3 of indivldual ones of a second plurality of N capacitors, each
4 having the same value of capacltance at the commutatlng rate fc~
between the first input terminal and a second input terminal, 6 respectively, only during associated pairs of adjacent time slots 7 for selectively storing charge for an input voltage on the second 8 input terminal; and (2) one and other sides of individual ones of a 9 third plurality of capacitors, each having the same value of capacitance, during associated pairs of adjacent t~me slots in a 11 manner so as to alternately connect, at the commutating rate and 12 during first and second time s]ots of each pair thereof, one and 13 other sides of an individual one of the third plurality of 14 capacitors to the first input terminal and a ground reference potential, respectively, and to ground and a third input terminal, 16 respectively, for alternately transferring charge between associated 17 ones of the third and first plurality of capacitors and storing 18 charge on the associated one of the third plurality of capacitors 19 for an input voltage on the third input terminal, respectively.
In accordance with another aspect of this invention, a method of 21 transforming a prototype switched capacitor integrator-filter 22 net~ork into a switched capacitor N-path filter comprises the steps 23 of replacing the integrating capacitor with a plurality of N
24 identical co~mutation capacitors, identifying other capacitors in the prototype that introduce delay in paths, and replacing all such 26 identified capacitors with an associated plurality of N-commutating 27 capacitors.
29 FIG. 1 is a schematic circuit diagram of a switched capacitor integrator circuit 7 which may be an element of a 31 mu]ti-stage switched capacitor filter.
32 FIG. 2 is a schematic circuit diagram of the corresponding ~g~6gs D-23,860 l N-path switched capacltor integrator 17 for the lntegrator circuit 2 in FIG. l, ~here N=3.
3 FIG. 3 is a schematlc circuit diagram of a m~ltl-stage 4 third order low pass switched capacitor filter including connected capacitors of the three types shown in FIG. 1.
6 FIG. 4 is a schematic circuit diagram of the corresponding 7 N-path switched capacitor fllter ~or the rilter network in Fig. 3, 8 where N=4.
9 v~ ON CF ~K~KKL~ EMBODIMENTS
Embodiments of this lnventlon are described in the paper, 11 "Exact Synthesls Or N-Path Swltched Capacltor Fllters" by Man Shek 12 Lee and Chieh Chang, presented at the International Sy~poslum on 13 Circuits and Systems, Chicag~, Illinois, May 1981.
Re~erring now to Fig. 1, a stray insensltive switched 16 capacitor integrator circuit 7 that ls lmrlpmpnted in integrated 17 circuit form comprises a differentlal input operational amplifler A0 18 that is associated with an integrated fee~h~k capacltor CO, and a 19 plurality of integrated capacltors Cl-C3 that are assoclated with the inverting input of AO. Since the non-inverting lnput termdnal 21 of AO is connected to ground for impressing a vlrtual ground 22 potential on lts invertin3 lnput terminal 8 and the amplifler 23 operates as a voltage source, thé clrcuit 7 is lnsensltlve to 24 parasitlc capacltance erfects associated wlth both the top and bottom plates Or CO. And in a multl-stage ~ilter netw~rk comprising 26 a plurallty of integrator circults 7, the lines 11 13 are connected 27 to output terminals o~ vDltage sources or ~round. Thus, the clrcuit 28 7 requires that plates of lntegrat~d capacitors C1-C3 be connected 29 to the output Or a v~l~age source, ground or a vlrtual ground potentl~l; be swltched between the output terminal o~ a vDltage 31 source and ground, or be swltched be~ . ground and a vlrtual gFound 32 potentlal. The clrcuit 7 is therefore also insensltive to l~Q~
1 parasitic capacitance effects associated with both the top and 2 bottom plates of Cl-C3.
3 'Ihe capacitors C1-C3 and any associated switches in Fig. 1 4 represent the three basic types of capacitor circuits that are employed in parasitic :insensitive switched capacitor filters. 'rhe 6 switches S1 and S2, that are associated with C2, are each 7 :implemented in Fig. 1 with series connected MOSFEr transistors. The 8 gate electrodes of these transistors are driven by different ones of 9 a pair of non-overlapping timing signals 0A and ~B that are produced by a two-phase timing signal source 16. The common 11 terminals of the transistor pairs are connected to associated plates 12 of C2. 'I~he timing signals 0A and 0B are 180 out of phase ,~nd 13 pre~erably have a duty cycle of slightly less than 50%. The upper 14 transistors QlA and Q2A conduct only when 0A is high for connecting C2 between the source voltage V2(z) and the inverting 16 input of A0, during a first time slot between t:lmes tO and -tl. The 17 lower transistors QlB and Q2B conduct only when 0B is high for 18 connecting both sides of C2 to ground for resetting the charge on it 19 to zero during a second time slot between times tl and t2. All of the transistors of S1 and S2 are non-conducting when 0A and ~B
21 are both low. The switches S1 and S2 are shown in schematic form in 22 Fig. 2. The transistors of S3 and S4 in Fig. 1 are responsive 'co 23 0A and 0B for al-ternately connecting C3 between ground and line 24 8, and between the source voltage V3(z) and ground, so as to alternately transfer charge from C3 to C0 and update charge on C3, 26 respectively.
27 Considering ~hat the source voltages V1-V3 in Fig. 1 are 28 periodically sampled and stored for presentation on lines 11-13, 29 they are characterized in Fig. 1 by their z-transforms, where z is the operator in the z-domain and V(z) is a discrete time voltage.
31 The charge voltage relationships for operation of capacitors Cl C3 32 and associated switches in the z-domain are then representable as ~5--~ 9~s 1 QQ~z) = C~ z )v(z~ (1) 2 aQ(z) = c2v(z) (2) 3 ~Q(z) = -C3(z l)v(z) 4 where ~Q(z) is the dlfferential charge on the capacltors between ad~acent time slots. Re~erence to equations (1) and (3) reveals 6 that unit delays o~ z-l are introduced by the storage of 7 information on Cl and C3. More specifically, Cl and C3 have a 8 m~mory in that the charge on them is updated during each clock cycle 9 in 0A and 0B (e.g., time tO-t2)9 whereas the charge on C2 is reset to zero. The capacitor C0 also introduces a unit delay.
11 In accordance with thls invention, the lntegrator 7 is 12 tran~formed to an assoclated N-path circult 17 in Flg. 2 by 13 repl~1ng all of the afo~ loned unit delay producing elements 14 with commutatlon structure introducing N units o~ delay. That is, C0, Cl and C3 are each replaced with an associated plurality of N
16 oommutatlng capacitors for storing N pieces o~ information, where N=3 17 in Flg. 2. The capacltor C0 ls replaced here by the capacltors C01, 18 C02 and C03 (all having the same capacitance C0) and associated 19 switches 51, 52 and 53. Slmllarly, Cl ls replaced by capacltors Cll, C12 and C13, of the same values, and assoclated switches 61, 62 21 and 63. The commutating switches 51-53 and 61-63 are ~he same types 22 as Sl-S4, although some of them are shown in schematlc form in Flg.
23 2 ~or convenience of illustratlon. Associated ones of switches 24 51-53 and 61-63 are driven by timing As~rAlA5 01+02, 03+04, and 05+~6, respectlvely, in assoclated pairs of AJd~acent time 26 slots. These capacitors C01-C03 and C11-C13 store a charge when the 27 associated timlng signals are low, with the charge thereon beir~
28 updated every N-2 time slots. The charge-voltage relationshi~ for 2~ these t~ pluralltle~ o~ capacitors are therefore of the ~orm ~Q(Z) = C (l-z N~ V[z) (4) ~ ? ~
~ ~9(~6~5 1 The swltched capacitor C3 is also replaced with N
2 capacltors C31, C32 and C33 Or the same values and associated palrs 3 of switches. The translstors of switches 31 and 41 are re~o~lve 4 to tim ~ slgnals 01 and 02 for connecting C31 between ground and A0 in only the ~lrst time slot and connecting lt between the 6 source voltage V3(Z) and ground (for updating charge on C31) in 7 only the second time slot. AIl of the transistors o~ switches 31 8 and 41 are non-conducting when ~1 and 02 are hoth low ~or 9 storing charge on C31 until 01 sl~hsequPntly goes high in the sevenU- time slot here. Switches 32 and 42 connect C32 in a similar 11 manner during the fourth and fifth tlme slots, i.e., when 04 and 12 05 are hi~h. The switches 33 and 43, which are shown ln schematic 13 ~orm in Flg. 2, are responsive to ~5 and 06 ~or connecting C33 14 in a similar manner in the flfth and slxth time slots~ Opposlte sides of C2 are oonnected to associated lines 8 and 12 durlng 16 odd-numbered time slots, and ~oth t~ ground during even-numb~red 17 tlme slots. m e charge~oltage relatlonship for this plurallty of 18 capacitors C3N is therefore of the form 19 ~Q(z) - -c3~z ) v(z) Consldering conservatlon of charge at the inverting input 21 terminal 8 o~ A0 ln Fig. 2, the charge-voltage relatlonship there is 22 CO (l-z )VO (z) +Cl (l-z ~Vl (2) 23 c2v2(z) - c3(z )V3 ~z) = O (6) 24 This operatlon i~ repeated in sl~hsequ~nt time slots. In summary, C01, Cll and C31 are operatively connected in clrcult 17 durin3 the 26 first and second time slots; C02, C12 ~nd C32 are oonnected ln the 27 integrator during the third and ~our~h t~e slots; etc., wlth both 28 sldes of C2 being connected to ground durin~ alternate tlme slots.
29 A glven low pass prototype swltched capaclt3r rilter 27 ln Fig. 3 comprises three switched capacib~r ~lL~yLd~L~ each 31 ~ncl~~A1ne an assoclated one o~ the actlYe elements Al-~3. Th~s 32 filter 27 includes pluralitles of the three types of ~apacitor :, 6~
1 circuits illustrated in ~ig. 1. The capacitors 71-73 are 2 integrating capacitors, whereas the capacitors 74-76 are similar to 3 Cl. The capacitors 82 and 83 are essentially switched capacitors, 4 whereas capacitors 77-81 are similar to C2. The filter 27 is designed to meet specifications of: sampling frequency = 4kHz; pass-6 band edge = lOOHz; pass-band ripple = 0.269db and stop-band 7 re~ection = 40db. In this filter 27, the normalized capacitances of 8 integrating and feedback capacitors are: C71=C73=8.122; C72=6.793;
9 and C75=C76=0.541. The capacitors 77-83, inclusive, have normalized unit capacitances, whereas the capacitance of capacitor 74 is half 11 that value.
12 In accordance with this invention, the filter 27 is 13 transformed to the corresponding switched capacitor N-path filter 14 27' (where N=4) in Fig. 4. Ihe pluralities of capacitors replacing capacitors 71-76 and 82-83 are designated by primed reference 16 characters in Fig. 4. The switches associated with the pluralities 17 of capacitors 71' and 75' and capacitors 73' and 76' are combined 18 into the pluralities of co~mutating switches 101 and 103, 19 respectively. The pluralities of capacitors 82' and 83' also share ones of the pluralities of switches 106 i~ Fig. 4. Referring now to 21 the inverting input of A3, the voltages on lines 111, 112, and 113 22 correspond to the source voltages Vl(z), V2(z) and V3(z) in Fig. 1.
23 The various ones of the 2N=8 timing signals required for driving the ?4 various switches in Fig. 4 are designated by the numerals ad~acent thereto. By way of example, various ones of the plurality of 26 switches 104 associated with capacitors 74' are driven by timing 27 signals 01~02; 03+04; etc. The attenuation characteristics, 28 i.e., pass-band ripple and stop-band loss, for an N-path filter 27' 29 tha~ was built and operated satisfactorily were substantially identical to those predicted by theory of N-path filters.
31 Although this invention is described in relation to 32 preferred embodiments thereof~ variations and modifications will 1~L9(~6~S
D~23860 1 occur to those skilled in the art. ~y way of example, the switches 2 may be implemented with CMOS transfer gates. Also, the timing 3 signal source may periodically generate the timing signals that 4 drive the switches. Additionally, the filters may be reallzed with integrated circuit technologies other than MOS, in other than fully 6 integrated circuit rorm, and fu]ly or partially implemented with 7 discrete components. Also, the switch means may comprise other 8 types of switching elements such as discrete transistors, 9 electromechanical switches or relays, and other types of integrated switches. rlhe scope of this invention is therefore to be 11 determined from the attached claims rather than from the 12 a~orementioned detailed descriptions of preferred embodiments 13 thereof.
3o _g_
between the first input terminal and a second input terminal, 6 respectively, only during associated pairs of adjacent time slots 7 for selectively storing charge for an input voltage on the second 8 input terminal; and (2) one and other sides of individual ones of a 9 third plurality of capacitors, each having the same value of capacitance, during associated pairs of adjacent t~me slots in a 11 manner so as to alternately connect, at the commutating rate and 12 during first and second time s]ots of each pair thereof, one and 13 other sides of an individual one of the third plurality of 14 capacitors to the first input terminal and a ground reference potential, respectively, and to ground and a third input terminal, 16 respectively, for alternately transferring charge between associated 17 ones of the third and first plurality of capacitors and storing 18 charge on the associated one of the third plurality of capacitors 19 for an input voltage on the third input terminal, respectively.
In accordance with another aspect of this invention, a method of 21 transforming a prototype switched capacitor integrator-filter 22 net~ork into a switched capacitor N-path filter comprises the steps 23 of replacing the integrating capacitor with a plurality of N
24 identical co~mutation capacitors, identifying other capacitors in the prototype that introduce delay in paths, and replacing all such 26 identified capacitors with an associated plurality of N-commutating 27 capacitors.
29 FIG. 1 is a schematic circuit diagram of a switched capacitor integrator circuit 7 which may be an element of a 31 mu]ti-stage switched capacitor filter.
32 FIG. 2 is a schematic circuit diagram of the corresponding ~g~6gs D-23,860 l N-path switched capacltor integrator 17 for the lntegrator circuit 2 in FIG. l, ~here N=3.
3 FIG. 3 is a schematlc circuit diagram of a m~ltl-stage 4 third order low pass switched capacitor filter including connected capacitors of the three types shown in FIG. 1.
6 FIG. 4 is a schematic circuit diagram of the corresponding 7 N-path switched capacitor fllter ~or the rilter network in Fig. 3, 8 where N=4.
9 v~ ON CF ~K~KKL~ EMBODIMENTS
Embodiments of this lnventlon are described in the paper, 11 "Exact Synthesls Or N-Path Swltched Capacltor Fllters" by Man Shek 12 Lee and Chieh Chang, presented at the International Sy~poslum on 13 Circuits and Systems, Chicag~, Illinois, May 1981.
Re~erring now to Fig. 1, a stray insensltive switched 16 capacitor integrator circuit 7 that ls lmrlpmpnted in integrated 17 circuit form comprises a differentlal input operational amplifler A0 18 that is associated with an integrated fee~h~k capacltor CO, and a 19 plurality of integrated capacltors Cl-C3 that are assoclated with the inverting input of AO. Since the non-inverting lnput termdnal 21 of AO is connected to ground for impressing a vlrtual ground 22 potential on lts invertin3 lnput terminal 8 and the amplifler 23 operates as a voltage source, thé clrcuit 7 is lnsensltlve to 24 parasitlc capacltance erfects associated wlth both the top and bottom plates Or CO. And in a multl-stage ~ilter netw~rk comprising 26 a plurallty of integrator circults 7, the lines 11 13 are connected 27 to output terminals o~ vDltage sources or ~round. Thus, the clrcuit 28 7 requires that plates of lntegrat~d capacitors C1-C3 be connected 29 to the output Or a v~l~age source, ground or a vlrtual ground potentl~l; be swltched between the output terminal o~ a vDltage 31 source and ground, or be swltched be~ . ground and a vlrtual gFound 32 potentlal. The clrcuit 7 is therefore also insensltive to l~Q~
1 parasitic capacitance effects associated with both the top and 2 bottom plates of Cl-C3.
3 'Ihe capacitors C1-C3 and any associated switches in Fig. 1 4 represent the three basic types of capacitor circuits that are employed in parasitic :insensitive switched capacitor filters. 'rhe 6 switches S1 and S2, that are associated with C2, are each 7 :implemented in Fig. 1 with series connected MOSFEr transistors. The 8 gate electrodes of these transistors are driven by different ones of 9 a pair of non-overlapping timing signals 0A and ~B that are produced by a two-phase timing signal source 16. The common 11 terminals of the transistor pairs are connected to associated plates 12 of C2. 'I~he timing signals 0A and 0B are 180 out of phase ,~nd 13 pre~erably have a duty cycle of slightly less than 50%. The upper 14 transistors QlA and Q2A conduct only when 0A is high for connecting C2 between the source voltage V2(z) and the inverting 16 input of A0, during a first time slot between t:lmes tO and -tl. The 17 lower transistors QlB and Q2B conduct only when 0B is high for 18 connecting both sides of C2 to ground for resetting the charge on it 19 to zero during a second time slot between times tl and t2. All of the transistors of S1 and S2 are non-conducting when 0A and ~B
21 are both low. The switches S1 and S2 are shown in schematic form in 22 Fig. 2. The transistors of S3 and S4 in Fig. 1 are responsive 'co 23 0A and 0B for al-ternately connecting C3 between ground and line 24 8, and between the source voltage V3(z) and ground, so as to alternately transfer charge from C3 to C0 and update charge on C3, 26 respectively.
27 Considering ~hat the source voltages V1-V3 in Fig. 1 are 28 periodically sampled and stored for presentation on lines 11-13, 29 they are characterized in Fig. 1 by their z-transforms, where z is the operator in the z-domain and V(z) is a discrete time voltage.
31 The charge voltage relationships for operation of capacitors Cl C3 32 and associated switches in the z-domain are then representable as ~5--~ 9~s 1 QQ~z) = C~ z )v(z~ (1) 2 aQ(z) = c2v(z) (2) 3 ~Q(z) = -C3(z l)v(z) 4 where ~Q(z) is the dlfferential charge on the capacltors between ad~acent time slots. Re~erence to equations (1) and (3) reveals 6 that unit delays o~ z-l are introduced by the storage of 7 information on Cl and C3. More specifically, Cl and C3 have a 8 m~mory in that the charge on them is updated during each clock cycle 9 in 0A and 0B (e.g., time tO-t2)9 whereas the charge on C2 is reset to zero. The capacitor C0 also introduces a unit delay.
11 In accordance with thls invention, the lntegrator 7 is 12 tran~formed to an assoclated N-path circult 17 in Flg. 2 by 13 repl~1ng all of the afo~ loned unit delay producing elements 14 with commutatlon structure introducing N units o~ delay. That is, C0, Cl and C3 are each replaced with an associated plurality of N
16 oommutatlng capacitors for storing N pieces o~ information, where N=3 17 in Flg. 2. The capacltor C0 ls replaced here by the capacltors C01, 18 C02 and C03 (all having the same capacitance C0) and associated 19 switches 51, 52 and 53. Slmllarly, Cl ls replaced by capacltors Cll, C12 and C13, of the same values, and assoclated switches 61, 62 21 and 63. The commutating switches 51-53 and 61-63 are ~he same types 22 as Sl-S4, although some of them are shown in schematlc form in Flg.
23 2 ~or convenience of illustratlon. Associated ones of switches 24 51-53 and 61-63 are driven by timing As~rAlA5 01+02, 03+04, and 05+~6, respectlvely, in assoclated pairs of AJd~acent time 26 slots. These capacitors C01-C03 and C11-C13 store a charge when the 27 associated timlng signals are low, with the charge thereon beir~
28 updated every N-2 time slots. The charge-voltage relationshi~ for 2~ these t~ pluralltle~ o~ capacitors are therefore of the ~orm ~Q(Z) = C (l-z N~ V[z) (4) ~ ? ~
~ ~9(~6~5 1 The swltched capacitor C3 is also replaced with N
2 capacltors C31, C32 and C33 Or the same values and associated palrs 3 of switches. The translstors of switches 31 and 41 are re~o~lve 4 to tim ~ slgnals 01 and 02 for connecting C31 between ground and A0 in only the ~lrst time slot and connecting lt between the 6 source voltage V3(Z) and ground (for updating charge on C31) in 7 only the second time slot. AIl of the transistors o~ switches 31 8 and 41 are non-conducting when ~1 and 02 are hoth low ~or 9 storing charge on C31 until 01 sl~hsequPntly goes high in the sevenU- time slot here. Switches 32 and 42 connect C32 in a similar 11 manner during the fourth and fifth tlme slots, i.e., when 04 and 12 05 are hi~h. The switches 33 and 43, which are shown ln schematic 13 ~orm in Flg. 2, are responsive to ~5 and 06 ~or connecting C33 14 in a similar manner in the flfth and slxth time slots~ Opposlte sides of C2 are oonnected to associated lines 8 and 12 durlng 16 odd-numbered time slots, and ~oth t~ ground during even-numb~red 17 tlme slots. m e charge~oltage relatlonship for this plurallty of 18 capacitors C3N is therefore of the form 19 ~Q(z) - -c3~z ) v(z) Consldering conservatlon of charge at the inverting input 21 terminal 8 o~ A0 ln Fig. 2, the charge-voltage relatlonship there is 22 CO (l-z )VO (z) +Cl (l-z ~Vl (2) 23 c2v2(z) - c3(z )V3 ~z) = O (6) 24 This operatlon i~ repeated in sl~hsequ~nt time slots. In summary, C01, Cll and C31 are operatively connected in clrcult 17 durin3 the 26 first and second time slots; C02, C12 ~nd C32 are oonnected ln the 27 integrator during the third and ~our~h t~e slots; etc., wlth both 28 sldes of C2 being connected to ground durin~ alternate tlme slots.
29 A glven low pass prototype swltched capaclt3r rilter 27 ln Fig. 3 comprises three switched capacib~r ~lL~yLd~L~ each 31 ~ncl~~A1ne an assoclated one o~ the actlYe elements Al-~3. Th~s 32 filter 27 includes pluralitles of the three types of ~apacitor :, 6~
1 circuits illustrated in ~ig. 1. The capacitors 71-73 are 2 integrating capacitors, whereas the capacitors 74-76 are similar to 3 Cl. The capacitors 82 and 83 are essentially switched capacitors, 4 whereas capacitors 77-81 are similar to C2. The filter 27 is designed to meet specifications of: sampling frequency = 4kHz; pass-6 band edge = lOOHz; pass-band ripple = 0.269db and stop-band 7 re~ection = 40db. In this filter 27, the normalized capacitances of 8 integrating and feedback capacitors are: C71=C73=8.122; C72=6.793;
9 and C75=C76=0.541. The capacitors 77-83, inclusive, have normalized unit capacitances, whereas the capacitance of capacitor 74 is half 11 that value.
12 In accordance with this invention, the filter 27 is 13 transformed to the corresponding switched capacitor N-path filter 14 27' (where N=4) in Fig. 4. Ihe pluralities of capacitors replacing capacitors 71-76 and 82-83 are designated by primed reference 16 characters in Fig. 4. The switches associated with the pluralities 17 of capacitors 71' and 75' and capacitors 73' and 76' are combined 18 into the pluralities of co~mutating switches 101 and 103, 19 respectively. The pluralities of capacitors 82' and 83' also share ones of the pluralities of switches 106 i~ Fig. 4. Referring now to 21 the inverting input of A3, the voltages on lines 111, 112, and 113 22 correspond to the source voltages Vl(z), V2(z) and V3(z) in Fig. 1.
23 The various ones of the 2N=8 timing signals required for driving the ?4 various switches in Fig. 4 are designated by the numerals ad~acent thereto. By way of example, various ones of the plurality of 26 switches 104 associated with capacitors 74' are driven by timing 27 signals 01~02; 03+04; etc. The attenuation characteristics, 28 i.e., pass-band ripple and stop-band loss, for an N-path filter 27' 29 tha~ was built and operated satisfactorily were substantially identical to those predicted by theory of N-path filters.
31 Although this invention is described in relation to 32 preferred embodiments thereof~ variations and modifications will 1~L9(~6~S
D~23860 1 occur to those skilled in the art. ~y way of example, the switches 2 may be implemented with CMOS transfer gates. Also, the timing 3 signal source may periodically generate the timing signals that 4 drive the switches. Additionally, the filters may be reallzed with integrated circuit technologies other than MOS, in other than fully 6 integrated circuit rorm, and fu]ly or partially implemented with 7 discrete components. Also, the switch means may comprise other 8 types of switching elements such as discrete transistors, 9 electromechanical switches or relays, and other types of integrated switches. rlhe scope of this invention is therefore to be 11 determined from the attached claims rather than from the 12 a~orementioned detailed descriptions of preferred embodiments 13 thereof.
3o _g_
Claims (11)
1. In an N-path filter, a commutating switched capacitor integrator circuit comprising:
an active element having a first input terminal and an output terminal;
a first plurality of N capacitors each having the same value of capacitance;
first switch means selectively-sequentially connecting, at a commutating rate, individual ones of said first plurality of capacitors as integrating capacitors between said active elements' first input and output terminals only during associated pairs of adjacent time slots for storing charge; and connecting means for selectively-sequentially connecting one of: (1) one and other sides of individual ones of a second plurality of N-capacitors each having the same values of capacitance, at the commutating rate, between said first input terminal and a second input terminal, respectively, only during associated pairs of adjacent time slots for selectively storing charge for an input voltage on said second input terminal; and (2) one and other sides of individual ones of a third plurality of capacitors of the same value of capacitance during associated pairs of adjacent time slots in a manner so as to alternately connect, at the commutating rate and during first and second time slots of each pair thereof, one and other sides of an individual one of said third plurality of capacitors to said first input terminal and a ground reference potential, respectively, and to ground and a third input terminal, respectively, for alternately transferring charge between associated ones of said first and third pluralities of capacitors and storing charge on the associated one of said third plurality of capacitors for an input voltage on said third input terminal, respectively.
an active element having a first input terminal and an output terminal;
a first plurality of N capacitors each having the same value of capacitance;
first switch means selectively-sequentially connecting, at a commutating rate, individual ones of said first plurality of capacitors as integrating capacitors between said active elements' first input and output terminals only during associated pairs of adjacent time slots for storing charge; and connecting means for selectively-sequentially connecting one of: (1) one and other sides of individual ones of a second plurality of N-capacitors each having the same values of capacitance, at the commutating rate, between said first input terminal and a second input terminal, respectively, only during associated pairs of adjacent time slots for selectively storing charge for an input voltage on said second input terminal; and (2) one and other sides of individual ones of a third plurality of capacitors of the same value of capacitance during associated pairs of adjacent time slots in a manner so as to alternately connect, at the commutating rate and during first and second time slots of each pair thereof, one and other sides of an individual one of said third plurality of capacitors to said first input terminal and a ground reference potential, respectively, and to ground and a third input terminal, respectively, for alternately transferring charge between associated ones of said first and third pluralities of capacitors and storing charge on the associated one of said third plurality of capacitors for an input voltage on said third input terminal, respectively.
2. The circuit according to claim 1 wherein said connecting means connects said third plurality of capacitors in the circuit in the prescribed manner.
3. The circuit according to claim 1 wherein said connecting means is operative for selectively-simultaneously connecting opposite sides of associated capacitors of both said second and third pluralities of capacitors as recited at (1) and (2) above.
4. The circuit according to claim 3 wherein said first input terminal of said active element has a virtual ground potential impressed on it.
5. The circuit according to claim 4 wherein said active element comprises a differential input operational amplifier having its non-inverting input terminal electrically connected to ground for impressing a virtual ground potential on its inverting input terminal which is said first input terminal.
6. The circuit according to claim 2 or 3 further comprising a first capacitor and second switch means for alternately connecting, at the commutating rate and during first and second time slots of each pair thereof, one and other sides of said first capacitor to said first input terminal and a fourth input terminal that is adapted for receiving an input voltage, respectively, and both sides of said first capacitor to ground.
7. A method of deriving construction parameters for a switched capacitor N-path filter from a switched capacitor network, where the network comprises a first capacitor connected as an integrating capacitor between a first input terminal and an output terminal of an active element; a second capacitor, which is a switched capacitor, having one and other sides thereof; and first switch means for alternately connecting one and other sides of the second capacitor between the first input terminal and a ground reference potential for updating charge on the first-integrating capacitor, and between ground and a second input terminal for updating charge on the second capacitor with an input voltage on the second input terminal; the method comprising:
replacing the first capacitor with a first plurality of N
capacitors, each having the same capacitance value, and second switch means selectively-sequentially connecting, at a commutating rate, individual ones of the first plurality of capacitors as integrating capacitors across the active element only during associated pairs of adjacent time slots for sequentially storing charge on them, while others of the first plurality of capacitors are disconnected from the active element; and replacing the second capacitor and first switch means with a second plurality of N capacitors, each having the same capacitance value, and third switch means, respectively, the latter alternately connecting, at the commutating rate, one and other sides of individual ones of the second plurality of capacitors as prescribed above for the second capacitor and first switch means during first and second time slots of associated pairs thereof for alternately transferring charge to an associated integrating capacitor of said first plurality thereof and updating stored charge for an input voltage on the second input terminal.
replacing the first capacitor with a first plurality of N
capacitors, each having the same capacitance value, and second switch means selectively-sequentially connecting, at a commutating rate, individual ones of the first plurality of capacitors as integrating capacitors across the active element only during associated pairs of adjacent time slots for sequentially storing charge on them, while others of the first plurality of capacitors are disconnected from the active element; and replacing the second capacitor and first switch means with a second plurality of N capacitors, each having the same capacitance value, and third switch means, respectively, the latter alternately connecting, at the commutating rate, one and other sides of individual ones of the second plurality of capacitors as prescribed above for the second capacitor and first switch means during first and second time slots of associated pairs thereof for alternately transferring charge to an associated integrating capacitor of said first plurality thereof and updating stored charge for an input voltage on the second input terminal.
8. The method according to claim 7 wherein the active element is an operational amplifier having a non-inverting input terminal electrically connected to ground for impressing a virtual ground potential on the inverting input terminal thereof which is the first input terminal.
9. The method according to claim 8 wherein the switched capacitor equivalent network further comprises a third capacitor electrically connected between the first input terminal and a third input terminal which is adapted for receiving an input voltage, and further comprising the step of replacing the third capacitor with a third plurality of N capacitors, all having the same capacitance value, and fourth switch means alternately connecting, at the commutating rate and during associated pairs of time slots, individual ones of the third plurality of capacitors between the third input terminal and the first input terminal for selectively updating charge on them at the commutating rate, others of the third plurality of capacitors being disconnected from the amplifier for storing charge during other than associated pairs of time slots.
10. In a commutated switched capacitor integrator circuit of an N-path filter, the method of deriving construction parameters comprising the steps of: identifying capacitors that introduce delay in the paths; and replacing each capacitor that causes delay in the paths with an associated plurality of N
commutating capacitors.
commutating capacitors.
11. The method of deriving construction parameters for a commutated switched capacitor integrator circuit of an N-path filter comprising the step of replacing each capacitor that has a memory, in that the new charge flow into each such capacitor during each commutation cycle depends on the old charge on it from the previous commutation cycle, with a plurality of N commutating capacitors.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US314,827 | 1981-10-26 | ||
| US06/314,827 US4446438A (en) | 1981-10-26 | 1981-10-26 | Switched capacitor n-path filter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1190615A true CA1190615A (en) | 1985-07-16 |
Family
ID=23221624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000411583A Expired CA1190615A (en) | 1981-10-26 | 1982-09-16 | Switched capacitor n-path filter |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4446438A (en) |
| CA (1) | CA1190615A (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| US4446438A (en) | 1984-05-01 |
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