CA1193023A - Programmable controller with expandable i/o interface circuitry - Google Patents
Programmable controller with expandable i/o interface circuitryInfo
- Publication number
- CA1193023A CA1193023A CA000435127A CA435127A CA1193023A CA 1193023 A CA1193023 A CA 1193023A CA 000435127 A CA000435127 A CA 000435127A CA 435127 A CA435127 A CA 435127A CA 1193023 A CA1193023 A CA 1193023A
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- CA
- Canada
- Prior art keywords
- address
- module
- bus
- buses
- rack
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/054—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/10—Plc systems
- G05B2219/11—Plc I-O input output
- G05B2219/1107—Hardware expansion of function of plc, programmable, connected in output line
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Programmable Controllers (AREA)
Abstract
PROGRAMMABLE CONTROLLER WITH EXPANDABLE
I/O INTERFACE CIRCUITRY
Abstract of the Disclosure A programmable controller has eight I/O buses which will support a corresponding number of I/O modules. The I/O capacity of the programmable controller may be increased by replacing four of the I/O modules with an I/O address module and three I/O
interface modules that drive I/O expansion buses. Up to eight I/O racks, each containing three I/O modules and one adaptor circuit, can be connected to the I/O expansion buses.
I/O INTERFACE CIRCUITRY
Abstract of the Disclosure A programmable controller has eight I/O buses which will support a corresponding number of I/O modules. The I/O capacity of the programmable controller may be increased by replacing four of the I/O modules with an I/O address module and three I/O
interface modules that drive I/O expansion buses. Up to eight I/O racks, each containing three I/O modules and one adaptor circuit, can be connected to the I/O expansion buses.
Description
'3 The field of the invention is programmable controllers such as those disclosed in U. S. Patent Nos. 4,165,534; ~,266,281; and 4,291,38~.
Programmable controllers are employed in many lndustrial and commercial applications to corltrol the operation of various types of machines. Programmable controllers are characterized by the repeated execution of a stored control program which contains instructions that direct the controller to examine the status of various sensing devices on the controlled machine and to operate various output devices on the controlled machine~
The size, or capacity, of a programmable controller should be compatible with the size of the machine or process being controlled. Si~e is typically measured by the number of I/O
points the controller can support without degrading its response time. In many applications this goal is met with a relatively small capacity programmable controller, but in some applicatlons additional I/O points are required which may exceed the capacity of a small programmable controller.
One solution to this problem is disclosed in U. S. Patent No. 4,250,563 where the processor in a low capacity programmable controller may be easily replaced with a more powerful processor which will support additional I~O points. Another solution which is applicable to some installations is disclosed in U. S. Patent No. 4,~19,338 entitled "Industrial Communications Network". The industrial communications network enables programmable control-lersi to be connected together throuqh a high speed data link.
Although this network has very effectively enabled programmable controllers to communicate with each other, and has thereby facilitated the addition of controllers as the control task grows, the hardwdre requ~Lect Lor such comlrlllnications networKs is relatively expensive.
In some applications -the sensing devices and opera-ting devices on the machine or process being controlled are distributed over a wide area, and it is desirable to ermploy a plurality of small programmable controllers which are dis-tri-buted throughout the facility rather than a single large pro-grammable controller. A system suitab]e for such applications is disclosed in copending Canadian patent application Serial No. 419,100 which was filed on January 1, 1983, and is en-titled "Communications Network for Programmable Controllers".
The present invention relates -to a programmable controller haviny an I/O bus structure for supporting direct]y a selec-ted number of I/O modules ancl a mul-tiplexing system ~or expanding the number of I/O modules supported by the I/O
bus structure This is accomplished by an I/O address module and a set of I/O interface modules which couple the I/O bus s-tructure to I/O expansion buses that connect -to a plurali-ty of I/O racks. Each I/O rack contains an adapter circuit which enables the I/O rack when its rack address is genera-ted by the I/O address module, and each I/O rack mounts a set oF I/O
modules which communicate with the [/o interFclce modules.
More specifically, the present invention provides in a programmable con-troller having a processor which repea-tedly executeS a user con-trol program and an I/O scan program, and having a fixed number of I/O buses for interfacing the processor with a corresponding number of I/O modules, the improvemen-t therein comprising: an I/O address module connected to one of -the I/O buses for receiving data from the processor and generating a rack address on a firs-t I/O expansion bus said I/O address module including rneans for signaling the ~3~ 23 processor that the I/O address module is connected to said one I/O bus; a set of I/O interface modules connected to a set o-f other ones of the I/O buses and to a corresponding se-t of additional I/O expansion buses, each I/O interface module being operable to couple data between one of said other I/O
buses and one of said additional YO expansion buses; an I/O
rack which includes: (a) an adaptor circuit connected -to the first I/O expansion bus for receiving the rack addresses gener-ated thereon and producing an enabling signal when its presel-ec-ted rack address is received thereon; and (b) a se-t of I/O
modules each coupled to one of the addi-tional I/O expansion buses to couple data between devices on a machine being con-tro~L-led and its associated additional I/O expansion bus when the enabling signal is produced; wherein the processor is respon-sive to the signal from the I/O address module to al-ter the I/O scan sequence which is performed in response to -the execu-tion of the I/O scan program.
The invention will enable one to expand the I/O capa-city of a programmable controller having a fixed I/O bus struc--ture. The I/O data is multiplexed -through the I/O in-terface modules to addressed I/O racks. A portion of -the I/O bus s-truc-ture is employed by -the I/O address module to enable the proper I/O rack.
The invention will also enable the :[/O racks to be located remotely from the processor. This is accomplished in part by the I/O interface modules which are designed to connect to one end of -the I/O expansion buses and in part by interface circuits located -2a--~93~ 3 in the I/O racks which couple the I~O modules to the other end of the I/O expansion buses.
In drawings whi~h illustrate the embodiments of the inven-ti on, ~ig. 1 is a block diagram of the programmable controller configured with the maximum number of I/O modules which can be directly supported;
Fig. 2 is a block diagram of the programmable controller configured with the multiplexer which expands the number of I/O
modules that can be supported;
Fig. 3 is an electrical schematic diagram of t~e processor which forms part of the system of Figs. 1 and 2;
Fig. 4 is an electrical schematic diagram of an output channel which forms part of the system of Fig. 2;
Fig. 5 is an electrical schematic diagram of an input channel which forms part of the system of Fig. 2; and Fig. 6 is a :Elow chart of the programs executed by the microprocessor shown in Fig. 3.
Referring particularly to Fig. 1, the programmable controller system includes a processor 1 which executes a stored control program to operate machinery connected to eight I/O modules 2A-5A
and 2B-5B. The control program is enterred into the processor 1 using a hand-held programming terminal 6 which connects to the processor 1 through a serial data line 7.
Each I/O module 2-5 includes either four input circuits or four output circuits which connect to the processor 1 through respective 4-bit I/O buses 8A-llA and 8B-llB. In addition, each I/O module 2-5 connects to an ID bus 12A or 12B which contains two leads for each module 2-5. Each output circuit may be separately controlled to operate a device such as a motor starter, solenoid or lamp, and each input sircuit monitors the state of a device such as a switch. When configured as shown in Fig. 1, the programmable controller can thus support up to 32 I/0 points.
Referring particularly to Fig. 2, the programmable control-ler can be configured to support up to ninety si~ I/0 points by connecting an I/0 address module 20A and three I/0 interface modules 2~A-23~ to the respective I/0 buses 8A-llA. The modules 20A-23A in turn connect to I/0 expansion buses 25A-28A which connect to a series of I/~ racks. Up to eight I/0 racks may be supported by the I/0 expansion buses 25A-28A and two of these are indicated in Fig. 2 at 29 and 30.
Each I/0 rack 29 and 30 includes an adaptor circuit 31 which connects to the I/0 expansion bus 25A and three interface circuits 32-3~ which connect to the I/0 expansion buses 26A-28A. As will be explained in more detail below, the I/0 address module 20A
generates a rack address on the expansion bus 25A and the adaptor circuits 31 in each I/0 rack 29 and 30 compare this address with their own preset I/0 rack number. When identity is detected, the I/0 rack is enabled to both receive output data from the I/0 expansion buses 26A-28A and send input data back to the I/0 interface modules 21A-23A through the buses 26A-28A. The processor 1 may thus exchange I/0 data with a selected I/0 rack 29 or 30 by writing the corresponding rack number to the I/0 address module 20A.
Referring still to Fig. 2, each I/0 rack 29 and 30 includes up to three I/0 modules 35-37 which may be identical in construc-tion to the I/0 modules 2-5 employed in the conventionally con-figured system of Fig. 1. These I/0 modules 35-37 may be any of a variety of modules. However, the direction of data flow, and hence the choice of input or output module, is determined by the choice of I/0 interface modules 21A-23A. For example, if the I/0 interface module 21A is a four channel output circuit, then the ~5a36~23 I~0 module 35 in each I/0 rack is an output module and its cor-responding interface circuit 32 receives output data from the I/O
expansion bus 26A. If the I/O interface module 22A on the o_her hand, is a four channel input circuit, then the I/O ~odule ~6 in each I/0 rack is an input module. In other words, either our input channels or four output channels are formed by each I/0 interface module 21A-23A, and the choice will determine the nature of the corresponding I/0 module 35-37 in each I/0 rack attached to the I/O expansion buses 26A-28A.
A detailed description of an input channel and an output channel will be described below with reference to Figs. 4 and 5.
But first, a detailed description of the processor 1 will be made with reference to Fig. 3.
Referring particularly to Fig. 3, the processor 1 is struc-tured around an 8-bit microprocessor 40 which drives an 8-bit data bus 41 and a 16-bit address bus 42. A model 8051 micro-processor manufactured by Intel Corporation is employed and it is driven by a 7 MHz clock 43. A read or write operation is per-formed by first outputting through 8-bit microprocessor port P0 the least significant address byte to an octal latch 44 and then generating the most significant address byte directly on the address ~us 42 through an 8-bit microprocessor port P2. An ~-bit byte of data is either input or output through port P0 when this 16-bit address is generated. A third 8-bit microprocessor port P1 is employed for a number of control functions, including the operation of four light-emitting diodes 45-48 which indicate the operating mode of the programmable controller.
The microprocessor 40 includes a full duplex universal asynchronous receiver/transmitter which outputs serial data at a TXD terminal ~9 and which receives serial data at an RXD terminal 50. The TXD terminal 49 connects to the input of a line driver 51 which couples to the serial data link 7 and the RXD input 50 ~3~3 connects to a line receiver 52. The inputs to the line receiver 52 are driven by the serial data link 7 through a voltage limit-ing circuit 53. Communications with the hand held terminal 6 is thus established directly with the microprocessor 40.
The microprocessor 40 also contains a 4~ x 8 read-only memory which stores programs that direct the operation of the microprocessor 40. In addi~ion, a 4K x 8 CMOS random access memory (RAM) 54 is connected to the data bus 41 and address bus 42 along with an additional 4K x 8 read-only memory (ROM) 55.
The memories 54 and 55 along with other elements in the processor 1 are enabled by a BCD-to-ten-bit decoder circuit 56 which con-nects to leads A12-A15 in the address bus 42. Three outputs S0-S2 of the decoder 56 connect to an AND gate 57 which drives a chip enable terminal (CE) on the RO~I 55, and decoder outputs S6 and S7 connect to chip enable terminals on the RAM 54. Program instructions and constants may be read from the ROM 55 when it is addressed and a program store enable line (PSEN) is driven low by the microprocessor 40. Data may be read from or written to the RAM 54 when it is addressed and an enable line (E) is driven low by an AND gate 58. A ~-rite control line ~WR) driven by the microprocessor 40 determines if a write operation is to be per-formed and a read control line (RD) is driven low during read operations.
The microprocessor 40 is coupled to the I/O buses 8-11 by a pair of peripheral interface adapters (PIA) 60 and 61. The PIAs 60 and 61 each include two 8-bit ports which may be separately configured as input or output points by commands received throu~h the data bus 41 Each of these 8-bit ports is divided to form two of the I/O buses 8-11 and data is input from these or output to them when the decoder output S3 is enabled. Address bus ieads A0-A~ connect to the control terminals on the PIAs 60 and 61 and the operation of the PIAs is thus completely controlled by the ~3~23 microprocessor 40 under the ~irec~ion of stored programs. Table A is a memory map which indicates the functions performed by th~
PIAs 60 and 61 when read or write ope~ati.ons are performed on the indicated addresses.
TABLE A
HEX ADDR DESCRIPTION
3010 (WRITE TO THE DATA DIRECTION REGISTER FOR BUS 08A
SET 09A AS INPUT OR OUTPUT) OR (WRITE TO G8A AND
TO 09A) 3011 (WRITE TO THE DATA DIRECTION REGISTER FOR BUS 10A
AND BUS llA TO SET 10A AS INPUT OR OUTPUT AND TO
SET llA AS INPUT OR OUTPUT) OR (WRITE TO 10A AND
TO llA) 3012 (WRITE TO THE DATA DiRECTION REGISTER FOR BUS 08B
SET O9B AS INPUT OR OUTPUT) OR ~WRITE TO 08B AND
TO 09B) 3013 (WRITE TO THE 3ATA DIRECTION REGISTER FOR BUS 10B
~ND BUS llB TO SET 10B AS INPUT OR OUTPUT AND TO
SET llB AS INPUT OR OUTPUT) OR (WRITE TO 10B AND
TO llB) 3015 READ BUS 10A AND BUS llA
30'.6 READ BUS 08B AND BUS 09B
3017 READ BUS lOB AND BUS llB
SET~UP CONDITIONS FOR BUS 10A AND BUS llA
~33~23 301B WRITE TO THE CONTR~ REGISTER TO PREPARF FOR
SET-UP CONDITIONS FOR BUS lOB AND BUS llB
As indicated above, the PIA ports may be separately con-fiqured as input or output points. This configuration is per-formed during initialization of the system after power-up. To determine whether a particular I/O bus 8-11 is an input or output channel a pair of 8-bit data selectors 63 and 64 are connected to the respective data bus leads DO and D1. The eight inputs on each data selector 63 and 64 connect to leads in the ID buses 12A
and 12B and the three select terminals connect to address bus leads AO-A2 Two leads in the ID bus 12 connect to each I/O
module 2-5, in a conventionally configured system (Fig. 1), or to an I/O interface module 20-23, in an expanded configuration (Fig.
Programmable controllers are employed in many lndustrial and commercial applications to corltrol the operation of various types of machines. Programmable controllers are characterized by the repeated execution of a stored control program which contains instructions that direct the controller to examine the status of various sensing devices on the controlled machine and to operate various output devices on the controlled machine~
The size, or capacity, of a programmable controller should be compatible with the size of the machine or process being controlled. Si~e is typically measured by the number of I/O
points the controller can support without degrading its response time. In many applications this goal is met with a relatively small capacity programmable controller, but in some applicatlons additional I/O points are required which may exceed the capacity of a small programmable controller.
One solution to this problem is disclosed in U. S. Patent No. 4,250,563 where the processor in a low capacity programmable controller may be easily replaced with a more powerful processor which will support additional I~O points. Another solution which is applicable to some installations is disclosed in U. S. Patent No. 4,~19,338 entitled "Industrial Communications Network". The industrial communications network enables programmable control-lersi to be connected together throuqh a high speed data link.
Although this network has very effectively enabled programmable controllers to communicate with each other, and has thereby facilitated the addition of controllers as the control task grows, the hardwdre requ~Lect Lor such comlrlllnications networKs is relatively expensive.
In some applications -the sensing devices and opera-ting devices on the machine or process being controlled are distributed over a wide area, and it is desirable to ermploy a plurality of small programmable controllers which are dis-tri-buted throughout the facility rather than a single large pro-grammable controller. A system suitab]e for such applications is disclosed in copending Canadian patent application Serial No. 419,100 which was filed on January 1, 1983, and is en-titled "Communications Network for Programmable Controllers".
The present invention relates -to a programmable controller haviny an I/O bus structure for supporting direct]y a selec-ted number of I/O modules ancl a mul-tiplexing system ~or expanding the number of I/O modules supported by the I/O
bus structure This is accomplished by an I/O address module and a set of I/O interface modules which couple the I/O bus s-tructure to I/O expansion buses that connect -to a plurali-ty of I/O racks. Each I/O rack contains an adapter circuit which enables the I/O rack when its rack address is genera-ted by the I/O address module, and each I/O rack mounts a set oF I/O
modules which communicate with the [/o interFclce modules.
More specifically, the present invention provides in a programmable con-troller having a processor which repea-tedly executeS a user con-trol program and an I/O scan program, and having a fixed number of I/O buses for interfacing the processor with a corresponding number of I/O modules, the improvemen-t therein comprising: an I/O address module connected to one of -the I/O buses for receiving data from the processor and generating a rack address on a firs-t I/O expansion bus said I/O address module including rneans for signaling the ~3~ 23 processor that the I/O address module is connected to said one I/O bus; a set of I/O interface modules connected to a set o-f other ones of the I/O buses and to a corresponding se-t of additional I/O expansion buses, each I/O interface module being operable to couple data between one of said other I/O
buses and one of said additional YO expansion buses; an I/O
rack which includes: (a) an adaptor circuit connected -to the first I/O expansion bus for receiving the rack addresses gener-ated thereon and producing an enabling signal when its presel-ec-ted rack address is received thereon; and (b) a se-t of I/O
modules each coupled to one of the addi-tional I/O expansion buses to couple data between devices on a machine being con-tro~L-led and its associated additional I/O expansion bus when the enabling signal is produced; wherein the processor is respon-sive to the signal from the I/O address module to al-ter the I/O scan sequence which is performed in response to -the execu-tion of the I/O scan program.
The invention will enable one to expand the I/O capa-city of a programmable controller having a fixed I/O bus struc--ture. The I/O data is multiplexed -through the I/O in-terface modules to addressed I/O racks. A portion of -the I/O bus s-truc-ture is employed by -the I/O address module to enable the proper I/O rack.
The invention will also enable the :[/O racks to be located remotely from the processor. This is accomplished in part by the I/O interface modules which are designed to connect to one end of -the I/O expansion buses and in part by interface circuits located -2a--~93~ 3 in the I/O racks which couple the I~O modules to the other end of the I/O expansion buses.
In drawings whi~h illustrate the embodiments of the inven-ti on, ~ig. 1 is a block diagram of the programmable controller configured with the maximum number of I/O modules which can be directly supported;
Fig. 2 is a block diagram of the programmable controller configured with the multiplexer which expands the number of I/O
modules that can be supported;
Fig. 3 is an electrical schematic diagram of t~e processor which forms part of the system of Figs. 1 and 2;
Fig. 4 is an electrical schematic diagram of an output channel which forms part of the system of Fig. 2;
Fig. 5 is an electrical schematic diagram of an input channel which forms part of the system of Fig. 2; and Fig. 6 is a :Elow chart of the programs executed by the microprocessor shown in Fig. 3.
Referring particularly to Fig. 1, the programmable controller system includes a processor 1 which executes a stored control program to operate machinery connected to eight I/O modules 2A-5A
and 2B-5B. The control program is enterred into the processor 1 using a hand-held programming terminal 6 which connects to the processor 1 through a serial data line 7.
Each I/O module 2-5 includes either four input circuits or four output circuits which connect to the processor 1 through respective 4-bit I/O buses 8A-llA and 8B-llB. In addition, each I/O module 2-5 connects to an ID bus 12A or 12B which contains two leads for each module 2-5. Each output circuit may be separately controlled to operate a device such as a motor starter, solenoid or lamp, and each input sircuit monitors the state of a device such as a switch. When configured as shown in Fig. 1, the programmable controller can thus support up to 32 I/0 points.
Referring particularly to Fig. 2, the programmable control-ler can be configured to support up to ninety si~ I/0 points by connecting an I/0 address module 20A and three I/0 interface modules 2~A-23~ to the respective I/0 buses 8A-llA. The modules 20A-23A in turn connect to I/0 expansion buses 25A-28A which connect to a series of I/~ racks. Up to eight I/0 racks may be supported by the I/0 expansion buses 25A-28A and two of these are indicated in Fig. 2 at 29 and 30.
Each I/0 rack 29 and 30 includes an adaptor circuit 31 which connects to the I/0 expansion bus 25A and three interface circuits 32-3~ which connect to the I/0 expansion buses 26A-28A. As will be explained in more detail below, the I/0 address module 20A
generates a rack address on the expansion bus 25A and the adaptor circuits 31 in each I/0 rack 29 and 30 compare this address with their own preset I/0 rack number. When identity is detected, the I/0 rack is enabled to both receive output data from the I/0 expansion buses 26A-28A and send input data back to the I/0 interface modules 21A-23A through the buses 26A-28A. The processor 1 may thus exchange I/0 data with a selected I/0 rack 29 or 30 by writing the corresponding rack number to the I/0 address module 20A.
Referring still to Fig. 2, each I/0 rack 29 and 30 includes up to three I/0 modules 35-37 which may be identical in construc-tion to the I/0 modules 2-5 employed in the conventionally con-figured system of Fig. 1. These I/0 modules 35-37 may be any of a variety of modules. However, the direction of data flow, and hence the choice of input or output module, is determined by the choice of I/0 interface modules 21A-23A. For example, if the I/0 interface module 21A is a four channel output circuit, then the ~5a36~23 I~0 module 35 in each I/0 rack is an output module and its cor-responding interface circuit 32 receives output data from the I/O
expansion bus 26A. If the I/O interface module 22A on the o_her hand, is a four channel input circuit, then the I/O ~odule ~6 in each I/0 rack is an input module. In other words, either our input channels or four output channels are formed by each I/0 interface module 21A-23A, and the choice will determine the nature of the corresponding I/0 module 35-37 in each I/0 rack attached to the I/O expansion buses 26A-28A.
A detailed description of an input channel and an output channel will be described below with reference to Figs. 4 and 5.
But first, a detailed description of the processor 1 will be made with reference to Fig. 3.
Referring particularly to Fig. 3, the processor 1 is struc-tured around an 8-bit microprocessor 40 which drives an 8-bit data bus 41 and a 16-bit address bus 42. A model 8051 micro-processor manufactured by Intel Corporation is employed and it is driven by a 7 MHz clock 43. A read or write operation is per-formed by first outputting through 8-bit microprocessor port P0 the least significant address byte to an octal latch 44 and then generating the most significant address byte directly on the address ~us 42 through an 8-bit microprocessor port P2. An ~-bit byte of data is either input or output through port P0 when this 16-bit address is generated. A third 8-bit microprocessor port P1 is employed for a number of control functions, including the operation of four light-emitting diodes 45-48 which indicate the operating mode of the programmable controller.
The microprocessor 40 includes a full duplex universal asynchronous receiver/transmitter which outputs serial data at a TXD terminal ~9 and which receives serial data at an RXD terminal 50. The TXD terminal 49 connects to the input of a line driver 51 which couples to the serial data link 7 and the RXD input 50 ~3~3 connects to a line receiver 52. The inputs to the line receiver 52 are driven by the serial data link 7 through a voltage limit-ing circuit 53. Communications with the hand held terminal 6 is thus established directly with the microprocessor 40.
The microprocessor 40 also contains a 4~ x 8 read-only memory which stores programs that direct the operation of the microprocessor 40. In addi~ion, a 4K x 8 CMOS random access memory (RAM) 54 is connected to the data bus 41 and address bus 42 along with an additional 4K x 8 read-only memory (ROM) 55.
The memories 54 and 55 along with other elements in the processor 1 are enabled by a BCD-to-ten-bit decoder circuit 56 which con-nects to leads A12-A15 in the address bus 42. Three outputs S0-S2 of the decoder 56 connect to an AND gate 57 which drives a chip enable terminal (CE) on the RO~I 55, and decoder outputs S6 and S7 connect to chip enable terminals on the RAM 54. Program instructions and constants may be read from the ROM 55 when it is addressed and a program store enable line (PSEN) is driven low by the microprocessor 40. Data may be read from or written to the RAM 54 when it is addressed and an enable line (E) is driven low by an AND gate 58. A ~-rite control line ~WR) driven by the microprocessor 40 determines if a write operation is to be per-formed and a read control line (RD) is driven low during read operations.
The microprocessor 40 is coupled to the I/O buses 8-11 by a pair of peripheral interface adapters (PIA) 60 and 61. The PIAs 60 and 61 each include two 8-bit ports which may be separately configured as input or output points by commands received throu~h the data bus 41 Each of these 8-bit ports is divided to form two of the I/O buses 8-11 and data is input from these or output to them when the decoder output S3 is enabled. Address bus ieads A0-A~ connect to the control terminals on the PIAs 60 and 61 and the operation of the PIAs is thus completely controlled by the ~3~23 microprocessor 40 under the ~irec~ion of stored programs. Table A is a memory map which indicates the functions performed by th~
PIAs 60 and 61 when read or write ope~ati.ons are performed on the indicated addresses.
TABLE A
HEX ADDR DESCRIPTION
3010 (WRITE TO THE DATA DIRECTION REGISTER FOR BUS 08A
SET 09A AS INPUT OR OUTPUT) OR (WRITE TO G8A AND
TO 09A) 3011 (WRITE TO THE DATA DIRECTION REGISTER FOR BUS 10A
AND BUS llA TO SET 10A AS INPUT OR OUTPUT AND TO
SET llA AS INPUT OR OUTPUT) OR (WRITE TO 10A AND
TO llA) 3012 (WRITE TO THE DATA DiRECTION REGISTER FOR BUS 08B
SET O9B AS INPUT OR OUTPUT) OR ~WRITE TO 08B AND
TO 09B) 3013 (WRITE TO THE 3ATA DIRECTION REGISTER FOR BUS 10B
~ND BUS llB TO SET 10B AS INPUT OR OUTPUT AND TO
SET llB AS INPUT OR OUTPUT) OR (WRITE TO 10B AND
TO llB) 3015 READ BUS 10A AND BUS llA
30'.6 READ BUS 08B AND BUS 09B
3017 READ BUS lOB AND BUS llB
SET~UP CONDITIONS FOR BUS 10A AND BUS llA
~33~23 301B WRITE TO THE CONTR~ REGISTER TO PREPARF FOR
SET-UP CONDITIONS FOR BUS lOB AND BUS llB
As indicated above, the PIA ports may be separately con-fiqured as input or output points. This configuration is per-formed during initialization of the system after power-up. To determine whether a particular I/O bus 8-11 is an input or output channel a pair of 8-bit data selectors 63 and 64 are connected to the respective data bus leads DO and D1. The eight inputs on each data selector 63 and 64 connect to leads in the ID buses 12A
and 12B and the three select terminals connect to address bus leads AO-A2 Two leads in the ID bus 12 connect to each I/O
module 2-5, in a conventionally configured system (Fig. 1), or to an I/O interface module 20-23, in an expanded configuration (Fig.
2). As will be described in more detail below, when one of these two leads is active an output channel is indicated, and when the other lead is active, an input channel is indicated. By address-ing the data selectors 63 and 64 during initializati.on, the microprocessor 40 reads the status of each I/O channel to deter-mine whether it is active, and if so, whether it is an input or output channel.
At the same time the data selectors 63 and 64 are addressed, a third data selector 65 is addressed. The output of the data selector 65 connects to data bus lead D2 and its select terminals connect to address bus leads AO-A2. Four inputs to the data selector 65 connect to the four poles of a switch 66 and the remaining four inputs connect to an optional memory module 67.
The poles switch 66 are manually set to provide data that describes the program memory configuration and one of the four inputs from the memory module 67 is connected to circuit ground
At the same time the data selectors 63 and 64 are addressed, a third data selector 65 is addressed. The output of the data selector 65 connects to data bus lead D2 and its select terminals connect to address bus leads AO-A2. Four inputs to the data selector 65 connect to the four poles of a switch 66 and the remaining four inputs connect to an optional memory module 67.
The poles switch 66 are manually set to provide data that describes the program memory configuration and one of the four inputs from the memory module 67 is connected to circuit ground
3~ to indicate the type of memory module used. Table B is a memory map of the addresses which enable tbe data selectors 63-65 and the functions which are performed.
~3~323 TABLE B
HEX ADDR DESCRIPTION
400C-4002 Read program memory configuration.
4003-4007 Read memory module type.
4000-4007 Read the type of I/O module (input, output, address, neither) employed in the eight I/O slots.
The memory module 67 is formed on a separate circuit board which is inserted into a connector on the processor's main cir-cuit board. One of four devices may be employed as the memory 68 in the optional memory module 67. These devices include a 2K x 8, 4K x 8 or 8K x 8 UVPROM device, or a 2~ x 8 electrically erasable PRO~. The type of memory module used is indicated by grounding one of four inputs to the data selector 65 with a jumper wire soldered to selector pads 69 which are formed on the module's circuit board. Address bus leads AO-All are coupled to the memory module 67 by bus driver gates 70, and the eight leads in the data bus 41 are coupled to the module 67 by bus transceiver gates 71. The transceiver gates 71 are enabled when an OR gate 72 is operated by control lines E and S5, and the direction of data flow is determined by the state of lead 5 of the micro-processor port Pl. The memory device 68 in the memory module 67 is enabled by an OR gate 73 which is driven by the decoder output S5 and lead 6 of the microprocessor port Pl. An inverter gate 74 drives an output enable terminal OE on the memory device 68 when a read operation is performed.
As indicated above, when the programmable controller is configured with expanded I/O capability, a set of input channels are formed for inputting machine status data into the processor 1 and a set of output channels are formed for outputting status data to the machine being controlled. Referring particularly to Figs. 2 and 4, each output channel includes four output points which are drlven by one of the I/O interface modules 21A-23A
~3~3 through one of the expansion buses 26A-28A. In Fig. 4, the I/O
interface module 21A is shown as an output channel which drives four output circuits in the output module 35. The I/O interface module 21A in this case is comprised of four bus driver circuits 5 80 which have their inputs connected to the four leads in the I/O
bus 9A. Their output terminals connect to the four leads in the I/O expansion bus 26A which in turn connects to the interface circuit 32 of each I/O rack 29 and 30.
The interface circuit 32 of this output channel incluc3es four line receivers 81 which connect to the respective leads in the I/O expansion bus 26A. The line receivers 81 connect to the data input terminals of a quad latch 82, and when the latch 82 is clocked by an output enable line 83, the state of the bus 26A is stored in the latch 82. The four outpu~ terminals Q1-04 of the latch 82 drive the inputs to four a.c. output circuits contained in the I/O module 35. One of these four output circuits is shown in Fig. 4 and it includes a trigger circuit 84 which generates trigger pulses to a triac 85 when its input is at a logic low voltage. When thus triggered into its conductive state, the 20 triac 85 conducts a.c. power to a load attached to output termi-nals 86. ~lhen the trigger circuit 84 is disabled, the triac 85 becomes non-conductive and the attached load is deenergized.
Referring particularly to Fig. 4, the output enable line 83 is driven by the adaptor circuit 31 and extends to each interface 25 circuit in the I/O rack. The adaptor circuit 31 includes a 4-bit comparator circuit 90 which has its A inputs connected to the four leads in the I/O expansion bus 25A. Its B inputs are con-nected to the poles of a 4-bit DIP switch 91 which is manually preset to indicate a unique I/O rack number. When this I/O racX
30 number is generated on the I/O expansion bus 25A, a logic high voltage appears at an output terminal 92. The output 92 connects to a line driver gate 93 which controls an input enable line 94, 3~23 and it connects through an R C delay circuit 95 to the input of a monostable multivibrator 96. The monostable multivibrator 96 generates a 20 microsecond pulse on the output enable line 83 five microseconds after the comparator 90 detects the I/0 rack address on the I/0 expansion bus 25A. This delay allows output data on the I/0 expansion bus 26A time to settle before it is clocked into the latch 82.
The input channels operate in a very similar manner to the output channels, but data flow is in the opposite direction.
Referring particularly to Figs. 2 and 5, an input module 36 is employed with an input interface circuit 33 and an input inter-face module 22A to couple four bits of input data to the proces-sor l. Numerous types of input modules may be employed and the module 36 shown in Fig. 5 includes four a.c. input circuits which detect the presence of a 110 volt alternating current applied to their input terminals 100-103. Each input circuit includes a bridge rectifier 104 and filter circuit 105 which convert the a.c. input to a d.c. voltage, and each includes a zener diode 106 which reduces this d.c. voltage to a value which produces a ten milliampere current flow through the diode in an optical coupler 107.
The logic level signal generated by the optical coupler 107 in each input circuit is applied to the inputs of a 4-bit line driver circuit 108. When a logic low signal is generated on the input enable line 94 by the adaptor circuit 31, the state of the four input circuits is gated onto the I/0 expansion bus 27A.
These four digital signals are thus applied to the inputs of four identical interface circuits in the interface module 22A.
Each interface circuit in the module 22A includes diodes 110 and zener diodes 111 which protect the circuit from excessive voltage spikes and electric noise which may be induced onto the - I/0 expansion bus 27A. The input signals are applied to the base ~3~3 o~ a transistor 112 which amplifies the signal to drive both a light emitting diode 113 and a lead in the I/0 bus lOA. The state of each input point 100~103 is thus continuously applied to the respective leads in the I/0 bus lOA as four logic le~el signals.
It should be apparent that a number of variations can be made in the above described I/0 circuitry. In the preferred embodiment the input modules and output modules may be used either in the conventional con iquration of Fig. 1 or the ex-panded configuration of Fig. 2. While this reduces the number ofdifferent txpes of I/0 module constructions that are required, it does require that interfaced circuits 32-3~ be provided on each I/0 rack to connect these standard I/0 modules 35-37 to the I/0 expansion buses 26~-28A. An alternative design might include the interface circuits 32-34 as part of the I/0 module or as part of the adaptor circuit 31.
The microprocessor 40 executes program instructions stored in the ROM 55 to perform programmable controller functions. In general terms these functions include inputting the state o all sensing devices connected to input modules, executing a user control program comprised of programmable controller instruc-tions, and outputting state signals to operating devices con-nected to each output module. These functions are performed continuously and repeatedly when the controller is in the RUN
mode.
Referring particularly to Figs. 3 and 6, when the program-mable controller is powered-up it executes a number of instruc-tions indicated by process block 125 which initialize the hard-ware elements and the system data structures. Among these data structures is a 16-bit configure register which stores the I/0 configuration data which is input from the bus 12 through the data selectors 63 and 64. If an I/0 address module is connected ~L~93~3 (i.e. a pair of leads 12A or 12~ are both grounded), the I/O
expansion feature is indicated. This is tested at decision block 126, and if I/O expansion is indicatedl an expand flag is set at process block 1~7. A loop indicated generally by the arrow 128 is then entered.
The loop 128 is repeatedly executed while the controller is in the RUN mode. It in~ludes instructions indicated by decision block 129 which check the expand flag. If this flag is not set, an input scan subroutine is executed at process block 130 to update an image table 131 in the RAM 54 with the status of all sensing device.s connected to the controller input modules. In either case the user control program is then executed as indi-cated by process block 132. The user control program is executed by sequentially reading user instructions from the RAM 54 and interpreting them in a manner indicated in U.S. patent Nos.
~3~323 TABLE B
HEX ADDR DESCRIPTION
400C-4002 Read program memory configuration.
4003-4007 Read memory module type.
4000-4007 Read the type of I/O module (input, output, address, neither) employed in the eight I/O slots.
The memory module 67 is formed on a separate circuit board which is inserted into a connector on the processor's main cir-cuit board. One of four devices may be employed as the memory 68 in the optional memory module 67. These devices include a 2K x 8, 4K x 8 or 8K x 8 UVPROM device, or a 2~ x 8 electrically erasable PRO~. The type of memory module used is indicated by grounding one of four inputs to the data selector 65 with a jumper wire soldered to selector pads 69 which are formed on the module's circuit board. Address bus leads AO-All are coupled to the memory module 67 by bus driver gates 70, and the eight leads in the data bus 41 are coupled to the module 67 by bus transceiver gates 71. The transceiver gates 71 are enabled when an OR gate 72 is operated by control lines E and S5, and the direction of data flow is determined by the state of lead 5 of the micro-processor port Pl. The memory device 68 in the memory module 67 is enabled by an OR gate 73 which is driven by the decoder output S5 and lead 6 of the microprocessor port Pl. An inverter gate 74 drives an output enable terminal OE on the memory device 68 when a read operation is performed.
As indicated above, when the programmable controller is configured with expanded I/O capability, a set of input channels are formed for inputting machine status data into the processor 1 and a set of output channels are formed for outputting status data to the machine being controlled. Referring particularly to Figs. 2 and 4, each output channel includes four output points which are drlven by one of the I/O interface modules 21A-23A
~3~3 through one of the expansion buses 26A-28A. In Fig. 4, the I/O
interface module 21A is shown as an output channel which drives four output circuits in the output module 35. The I/O interface module 21A in this case is comprised of four bus driver circuits 5 80 which have their inputs connected to the four leads in the I/O
bus 9A. Their output terminals connect to the four leads in the I/O expansion bus 26A which in turn connects to the interface circuit 32 of each I/O rack 29 and 30.
The interface circuit 32 of this output channel incluc3es four line receivers 81 which connect to the respective leads in the I/O expansion bus 26A. The line receivers 81 connect to the data input terminals of a quad latch 82, and when the latch 82 is clocked by an output enable line 83, the state of the bus 26A is stored in the latch 82. The four outpu~ terminals Q1-04 of the latch 82 drive the inputs to four a.c. output circuits contained in the I/O module 35. One of these four output circuits is shown in Fig. 4 and it includes a trigger circuit 84 which generates trigger pulses to a triac 85 when its input is at a logic low voltage. When thus triggered into its conductive state, the 20 triac 85 conducts a.c. power to a load attached to output termi-nals 86. ~lhen the trigger circuit 84 is disabled, the triac 85 becomes non-conductive and the attached load is deenergized.
Referring particularly to Fig. 4, the output enable line 83 is driven by the adaptor circuit 31 and extends to each interface 25 circuit in the I/O rack. The adaptor circuit 31 includes a 4-bit comparator circuit 90 which has its A inputs connected to the four leads in the I/O expansion bus 25A. Its B inputs are con-nected to the poles of a 4-bit DIP switch 91 which is manually preset to indicate a unique I/O rack number. When this I/O racX
30 number is generated on the I/O expansion bus 25A, a logic high voltage appears at an output terminal 92. The output 92 connects to a line driver gate 93 which controls an input enable line 94, 3~23 and it connects through an R C delay circuit 95 to the input of a monostable multivibrator 96. The monostable multivibrator 96 generates a 20 microsecond pulse on the output enable line 83 five microseconds after the comparator 90 detects the I/0 rack address on the I/0 expansion bus 25A. This delay allows output data on the I/0 expansion bus 26A time to settle before it is clocked into the latch 82.
The input channels operate in a very similar manner to the output channels, but data flow is in the opposite direction.
Referring particularly to Figs. 2 and 5, an input module 36 is employed with an input interface circuit 33 and an input inter-face module 22A to couple four bits of input data to the proces-sor l. Numerous types of input modules may be employed and the module 36 shown in Fig. 5 includes four a.c. input circuits which detect the presence of a 110 volt alternating current applied to their input terminals 100-103. Each input circuit includes a bridge rectifier 104 and filter circuit 105 which convert the a.c. input to a d.c. voltage, and each includes a zener diode 106 which reduces this d.c. voltage to a value which produces a ten milliampere current flow through the diode in an optical coupler 107.
The logic level signal generated by the optical coupler 107 in each input circuit is applied to the inputs of a 4-bit line driver circuit 108. When a logic low signal is generated on the input enable line 94 by the adaptor circuit 31, the state of the four input circuits is gated onto the I/0 expansion bus 27A.
These four digital signals are thus applied to the inputs of four identical interface circuits in the interface module 22A.
Each interface circuit in the module 22A includes diodes 110 and zener diodes 111 which protect the circuit from excessive voltage spikes and electric noise which may be induced onto the - I/0 expansion bus 27A. The input signals are applied to the base ~3~3 o~ a transistor 112 which amplifies the signal to drive both a light emitting diode 113 and a lead in the I/0 bus lOA. The state of each input point 100~103 is thus continuously applied to the respective leads in the I/0 bus lOA as four logic le~el signals.
It should be apparent that a number of variations can be made in the above described I/0 circuitry. In the preferred embodiment the input modules and output modules may be used either in the conventional con iquration of Fig. 1 or the ex-panded configuration of Fig. 2. While this reduces the number ofdifferent txpes of I/0 module constructions that are required, it does require that interfaced circuits 32-3~ be provided on each I/0 rack to connect these standard I/0 modules 35-37 to the I/0 expansion buses 26~-28A. An alternative design might include the interface circuits 32-34 as part of the I/0 module or as part of the adaptor circuit 31.
The microprocessor 40 executes program instructions stored in the ROM 55 to perform programmable controller functions. In general terms these functions include inputting the state o all sensing devices connected to input modules, executing a user control program comprised of programmable controller instruc-tions, and outputting state signals to operating devices con-nected to each output module. These functions are performed continuously and repeatedly when the controller is in the RUN
mode.
Referring particularly to Figs. 3 and 6, when the program-mable controller is powered-up it executes a number of instruc-tions indicated by process block 125 which initialize the hard-ware elements and the system data structures. Among these data structures is a 16-bit configure register which stores the I/0 configuration data which is input from the bus 12 through the data selectors 63 and 64. If an I/0 address module is connected ~L~93~3 (i.e. a pair of leads 12A or 12~ are both grounded), the I/O
expansion feature is indicated. This is tested at decision block 126, and if I/O expansion is indicatedl an expand flag is set at process block 1~7. A loop indicated generally by the arrow 128 is then entered.
The loop 128 is repeatedly executed while the controller is in the RUN mode. It in~ludes instructions indicated by decision block 129 which check the expand flag. If this flag is not set, an input scan subroutine is executed at process block 130 to update an image table 131 in the RAM 54 with the status of all sensing device.s connected to the controller input modules. In either case the user control program is then executed as indi-cated by process block 132. The user control program is executed by sequentially reading user instructions from the RAM 54 and interpreting them in a manner indicated in U.S. patent Nos.
4,165,534 or 4,282,584 or in U.S. patent No. 4,443,865 issued on April 17, 1984, and entitled "Processor Module for a Programmable Controller". When the "END" instruction is read from the user control program, the system resumes executing in-structions in the loop 128. These include instructions indicated by decision block 133 which test the expand flag, and if it is not set, an output scan subroutine indicated at process block 134 is executed. The output scan subroutine 134 transfers the contents of the I/O image table 131 to the output modules which are connected to the processor. On the other hand, if the expand flag is set, an expanded I/O scan subroutine is executed as indicated by process block 135. This subroutine 135 outpu-ts the contents of the I/O image table 131 and an expanded I/O image table 136 to the output modules and it then inputs data to these image tables 131 and 136 from the input modules. Listings in assembly language of the expanded I/O scan subroutine 135 as well as other programs stored in the ROM 55 is provided in Appendix A.
~L~93~3 COMPO~ENT APPENDIX
Microprocessor 40 8-bit microcomputer model 8051 manufactured by Intel Corp.
Octal Latch 44 Octal D-type latch model 74LS373 manufactured by Texas Instruments, Inc.
Decoder 56 Four-line-to ten-line decoder model 74LS42 manufactured by Texas Instruments, Inc.
Data Selectors 63-65 Data Selector/Multiplexer model 74LS251 mar.ufactured by Texas Instruments, Inc.
Gates 71 Octal bus transceivers model 74LS245 manuactured by Texas Instruments, Inc.
PIA 60 and 61 Peripheral interface adaptor model 68B21 manufactured by Motorola, Inc.
~3~323 APPENDIX A
I~r n ~r ~
MOVX @R0,A ;return output to output image table MOV C,MCRFLG iinitialize rung to mcr state INC DPTR ;set interpreter pointer to next op code MOVX A,@DPTR ;first byte of jump address into accumulator JNB P,PARITY ;parity error if even parit~
in op code CLR ACC.0 ;strip parity bit from opcode PUSH ACC ;start forming fake return address on stack PUSH TABMSB ;msb of jump table onto stack INC DPTR ;set data poi.nter to address of instruction MOVX A,@DPTR ;operand address to accumulator JB P,PARITY ;check for address parity error CLR ACC.7 ;clear parity bit in operand MOV R0,A ;operand address to R0 index register MOVX A,@R0 ;operand to accumulator RET ;jump to address created on the stack I/O_INITIALIZATION
IOS~TUP: MOV DPTR,#CONFIG ;set to confi space MO~ R2,~ ;set up loop count LOOPIO: MOVX A,@DPTR ;get config bits CLR C
ORL C,/ACC.0 ;get config bit inverted XCH A,IOCONFl ;get first confi.g register RRC A ;shift in first bit XCH A,IOCONFl ;restore configuration CLR C
ORL C,/AAC.l ;get other config bit MOV A,IOCONF2 ;get second i/o config bit RRC A ;shift in second bit MOV IOCONF2,A ;save configuration INC DPTR ;set to next config addr DJNZ R2,LOOPIO ;loop through rest of config MOV DPTR,#IOMAP ;address i/o direction map MOV R0,#IOCONFl ;index to first i/o config byte LOOPI02: MOV A,@R0 ;get config bits SET B TBIT ;set loop counter LOOPI03: MOV ATEMPC,#0 ;clear direction bits JB ACC.0,AOK ;test for output module ORL ATEMPC,#OFH ;set outputs AOK: JB ACC.2,AOK2 ;test for out in msb ORL ATEMPC,#OFOH ;set out in msb AOK2: XCH A,ATEMPC ;get directio~ byte MOVX @DPTR,A ;save in direction map XCH A,ATEMPC jreturn io bits SWAP A ;get other io bits in place INC DPTR ;address next direction cell JBC I'BIT,LOOPI03 jdo second half of word ~15-~93~23 INC R0 ;address next config bit CJNE Ro~#IocoNF2+l~LoopIo2 ;do next cell MOV A,IOCONFl ;test for expanded i/o ANI. A,#OCOH ;if both bits are 0, adr module CLR EXPAND ;reset expansion present bit JNZ NOEXPAND ;expanded i/o not present SETB EXPAND ;set expanded i/o bit MOV P2,#~IGH(FSELECT+5) ;don't want forces on adr field MOV Rl,#LOW(FSELECT-~5) MOV DPTR,#IOBITS+5 ;address first expansion byte MOV RO,#O ;clear address field LOOPXPAND: MOVX A,@DPTR ;get expansion i/o byte SWAP A ;addr to ls nibble ANL A,~OFOH ;clear address nibble ORL A,R0 ;enter expansion address ORL A,#8 ;turn off strobe byte SWAP A ;restore addr to ms nibble MOVX @DPTR,A ;restore to nv ram MOVX A, Rl ;get force select byte ANL A,#OFH ;zero forces on addr nibble MOVX @Rl,A ;restore to force table INC Rl ;addr ne~t force secret addr INC Rl INC DPTR ;inc to next rack address INC DPTR
INC R0 ;inc expand addr CJNE RO,#8,LOOPXPAND ;set remaining addresses INPUT SCAN SUBROUTINE
UPDIN: ACALL INIVECT iset up pointers UPDIN6: ACALL UPDIN5 ;read inputs ACALL INCVECTl ;increment the pointers CJNE R0,#LOW(RPRA)+4,UPDIN6;loop if not done yet RET
; read PIA inputs UPDIN5: MOV DPL,R5 jpoint to i/o direction MOVX A@DPTR iget i/o direction MOV R6,A ;save as output mask CPL A ;make input mask MOV R7,A ;1=inputs,0=outputs MOVX A~@Ro ;get data from 6821 PIAs CPL A ;convert to positive logic ANL A,R7 ;mask off outputs MOV Rl,A ;save new inputs force any inputs on or off as required MOV DPL,R3 ;point to force selected MOVX A,@DPTR ;get force selected bits ANL A,R7 ;make input force selected bits MOV R7,A ;save input force selected bits CPL A ;make lnput force selec-ted mask ANL A,Rl ;mask off forced inputs MOV Rl,A ;save unforced inpu~s MOV DPL,R4 ;point to force states MOVX A,@DPTR ;get force states ANL A,R7 ;make forced on selected bits ~93SJ ~
ORL A,P~l ;make new inputs with forces MOV Rl,A ;save new inputs with forces update a byte in the i/o status table MOV DPL,R2 ;point to i/o table MOVX A,@DPTR ;get old i/o states ANL A,R6 ;mask off old input states ORL A,Rl ;combine new inputs with old outputs MOVX @DPTR,A ;write to table RET
_ TPUT SCAN SUBROUTINE
UPDOUT: ACALL I~IOUT ;initialize output addresses MOV R7,#0 ;zero immediate output state UPDOUT6: ACALL UPDOUT5 ;update outputs ACALL INCVECT2 ;advance pointers CJNE R0,~LOW(WPRA)+4,UPDOUT5 ;loop if not done yet RET
, get output data from table UPDOUT5: MOV DPL,R2 ;point to i/o table MOVX A,@DPTR ;get data from table ORL A,R7 ;turn on immediate Olltput rung ~B TBIT2,SETQ ;test for rung on or off XRL A,R7 SETQ: MOVX @DPTR,~ ;restore updated output MOV Rl,A ;save outputs ; force any outputs on or off as required MOV DPL,R3 ;point to force selected MOVX A,@DPTR ;get force selected bits MOV R5,A ;save force selected bits CPL A ;make output force selec-ted mask ANL A,Rl ;mask off forced outpu-ts MOV Rl,A ;save unforced outputs MOV DPL,R4 ipoint to force states MOVX A,@DPTR jget force states ANL A,R5 ;make forced on selected blts ORL A,Rl imake new outputs with forces update PIA outputs CPL A ;convert to negative logic MOVX @R0,A jwrite to PIAs RET
INCVECTl: INC R5 ;advance pointers INCVECT2: INC R0 RET
INIOUT: MOV R2,#LOW(IOBITS) ipoint to i/o states MOV R3~#Low(FsELEcT) ;point -to force select 3~?~3 MOV R4,#Low(FSTATE) jpoint to force state MOV P2,#HIGH(WPRA) ipoint to PIAs page MOV R0,#LOW(WPRA) jpoint to write only outputs MOV DPH,#HIGH~IOBITS) ipoint to i/o page RET
EXPANDED I~O SCAN SUBROUTINE
EXPIO: MOV R2,#LOW(IOLITS+4) MOV R3,#LOW(FSELECT+4) MOV R4,#LOW(FSTATE+4) MOV P2,#HIGH~WPRA) jpoint to PIAs page MOV DPH,#HIGH(IOBITS) ;point to i/o page LOOPEXP: MOV RO,#LOW(WPRA) jpoint to write only outputs MOV R7,#0 jzero the immediate i/o state CALL UPDOUT5 ;sent out data CALL INCVECT2 ;address next i~o slot CALL UPDOUT5 ;send out nibble and address MOV DPL,R2 ;address i/o page MOVX A,@DPTR ;get i/o address ANL A,#7FH ;set strobe MOVX @DPTR,A ;restore to i/o page CALL UPDoUT5 ;turn on address ok strobe MOV R0,#LOW(RPRA) ;switch back to first address MOV R5,#LOW(IOMAP) ;set address i/o direction map CALL UPDIN5 ;read inputs CALL INCVECTl ;address next input slot CALL UPDIN5 ;read single nibble CALL INCVECT2 ;address next i/o CJNE R4,#LOW(FSELECT),LOOPEXP ;test for end of expand scan REl'
~L~93~3 COMPO~ENT APPENDIX
Microprocessor 40 8-bit microcomputer model 8051 manufactured by Intel Corp.
Octal Latch 44 Octal D-type latch model 74LS373 manufactured by Texas Instruments, Inc.
Decoder 56 Four-line-to ten-line decoder model 74LS42 manufactured by Texas Instruments, Inc.
Data Selectors 63-65 Data Selector/Multiplexer model 74LS251 mar.ufactured by Texas Instruments, Inc.
Gates 71 Octal bus transceivers model 74LS245 manuactured by Texas Instruments, Inc.
PIA 60 and 61 Peripheral interface adaptor model 68B21 manufactured by Motorola, Inc.
~3~323 APPENDIX A
I~r n ~r ~
MOVX @R0,A ;return output to output image table MOV C,MCRFLG iinitialize rung to mcr state INC DPTR ;set interpreter pointer to next op code MOVX A,@DPTR ;first byte of jump address into accumulator JNB P,PARITY ;parity error if even parit~
in op code CLR ACC.0 ;strip parity bit from opcode PUSH ACC ;start forming fake return address on stack PUSH TABMSB ;msb of jump table onto stack INC DPTR ;set data poi.nter to address of instruction MOVX A,@DPTR ;operand address to accumulator JB P,PARITY ;check for address parity error CLR ACC.7 ;clear parity bit in operand MOV R0,A ;operand address to R0 index register MOVX A,@R0 ;operand to accumulator RET ;jump to address created on the stack I/O_INITIALIZATION
IOS~TUP: MOV DPTR,#CONFIG ;set to confi space MO~ R2,~ ;set up loop count LOOPIO: MOVX A,@DPTR ;get config bits CLR C
ORL C,/ACC.0 ;get config bit inverted XCH A,IOCONFl ;get first confi.g register RRC A ;shift in first bit XCH A,IOCONFl ;restore configuration CLR C
ORL C,/AAC.l ;get other config bit MOV A,IOCONF2 ;get second i/o config bit RRC A ;shift in second bit MOV IOCONF2,A ;save configuration INC DPTR ;set to next config addr DJNZ R2,LOOPIO ;loop through rest of config MOV DPTR,#IOMAP ;address i/o direction map MOV R0,#IOCONFl ;index to first i/o config byte LOOPI02: MOV A,@R0 ;get config bits SET B TBIT ;set loop counter LOOPI03: MOV ATEMPC,#0 ;clear direction bits JB ACC.0,AOK ;test for output module ORL ATEMPC,#OFH ;set outputs AOK: JB ACC.2,AOK2 ;test for out in msb ORL ATEMPC,#OFOH ;set out in msb AOK2: XCH A,ATEMPC ;get directio~ byte MOVX @DPTR,A ;save in direction map XCH A,ATEMPC jreturn io bits SWAP A ;get other io bits in place INC DPTR ;address next direction cell JBC I'BIT,LOOPI03 jdo second half of word ~15-~93~23 INC R0 ;address next config bit CJNE Ro~#IocoNF2+l~LoopIo2 ;do next cell MOV A,IOCONFl ;test for expanded i/o ANI. A,#OCOH ;if both bits are 0, adr module CLR EXPAND ;reset expansion present bit JNZ NOEXPAND ;expanded i/o not present SETB EXPAND ;set expanded i/o bit MOV P2,#~IGH(FSELECT+5) ;don't want forces on adr field MOV Rl,#LOW(FSELECT-~5) MOV DPTR,#IOBITS+5 ;address first expansion byte MOV RO,#O ;clear address field LOOPXPAND: MOVX A,@DPTR ;get expansion i/o byte SWAP A ;addr to ls nibble ANL A,~OFOH ;clear address nibble ORL A,R0 ;enter expansion address ORL A,#8 ;turn off strobe byte SWAP A ;restore addr to ms nibble MOVX @DPTR,A ;restore to nv ram MOVX A, Rl ;get force select byte ANL A,#OFH ;zero forces on addr nibble MOVX @Rl,A ;restore to force table INC Rl ;addr ne~t force secret addr INC Rl INC DPTR ;inc to next rack address INC DPTR
INC R0 ;inc expand addr CJNE RO,#8,LOOPXPAND ;set remaining addresses INPUT SCAN SUBROUTINE
UPDIN: ACALL INIVECT iset up pointers UPDIN6: ACALL UPDIN5 ;read inputs ACALL INCVECTl ;increment the pointers CJNE R0,#LOW(RPRA)+4,UPDIN6;loop if not done yet RET
; read PIA inputs UPDIN5: MOV DPL,R5 jpoint to i/o direction MOVX A@DPTR iget i/o direction MOV R6,A ;save as output mask CPL A ;make input mask MOV R7,A ;1=inputs,0=outputs MOVX A~@Ro ;get data from 6821 PIAs CPL A ;convert to positive logic ANL A,R7 ;mask off outputs MOV Rl,A ;save new inputs force any inputs on or off as required MOV DPL,R3 ;point to force selected MOVX A,@DPTR ;get force selected bits ANL A,R7 ;make input force selected bits MOV R7,A ;save input force selected bits CPL A ;make lnput force selec-ted mask ANL A,Rl ;mask off forced inputs MOV Rl,A ;save unforced inpu~s MOV DPL,R4 ;point to force states MOVX A,@DPTR ;get force states ANL A,R7 ;make forced on selected bits ~93SJ ~
ORL A,P~l ;make new inputs with forces MOV Rl,A ;save new inputs with forces update a byte in the i/o status table MOV DPL,R2 ;point to i/o table MOVX A,@DPTR ;get old i/o states ANL A,R6 ;mask off old input states ORL A,Rl ;combine new inputs with old outputs MOVX @DPTR,A ;write to table RET
_ TPUT SCAN SUBROUTINE
UPDOUT: ACALL I~IOUT ;initialize output addresses MOV R7,#0 ;zero immediate output state UPDOUT6: ACALL UPDOUT5 ;update outputs ACALL INCVECT2 ;advance pointers CJNE R0,~LOW(WPRA)+4,UPDOUT5 ;loop if not done yet RET
, get output data from table UPDOUT5: MOV DPL,R2 ;point to i/o table MOVX A,@DPTR ;get data from table ORL A,R7 ;turn on immediate Olltput rung ~B TBIT2,SETQ ;test for rung on or off XRL A,R7 SETQ: MOVX @DPTR,~ ;restore updated output MOV Rl,A ;save outputs ; force any outputs on or off as required MOV DPL,R3 ;point to force selected MOVX A,@DPTR ;get force selected bits MOV R5,A ;save force selected bits CPL A ;make output force selec-ted mask ANL A,Rl ;mask off forced outpu-ts MOV Rl,A ;save unforced outputs MOV DPL,R4 ipoint to force states MOVX A,@DPTR jget force states ANL A,R5 ;make forced on selected blts ORL A,Rl imake new outputs with forces update PIA outputs CPL A ;convert to negative logic MOVX @R0,A jwrite to PIAs RET
INCVECTl: INC R5 ;advance pointers INCVECT2: INC R0 RET
INIOUT: MOV R2,#LOW(IOBITS) ipoint to i/o states MOV R3~#Low(FsELEcT) ;point -to force select 3~?~3 MOV R4,#Low(FSTATE) jpoint to force state MOV P2,#HIGH(WPRA) ipoint to PIAs page MOV R0,#LOW(WPRA) jpoint to write only outputs MOV DPH,#HIGH~IOBITS) ipoint to i/o page RET
EXPANDED I~O SCAN SUBROUTINE
EXPIO: MOV R2,#LOW(IOLITS+4) MOV R3,#LOW(FSELECT+4) MOV R4,#LOW(FSTATE+4) MOV P2,#HIGH~WPRA) jpoint to PIAs page MOV DPH,#HIGH(IOBITS) ;point to i/o page LOOPEXP: MOV RO,#LOW(WPRA) jpoint to write only outputs MOV R7,#0 jzero the immediate i/o state CALL UPDOUT5 ;sent out data CALL INCVECT2 ;address next i~o slot CALL UPDOUT5 ;send out nibble and address MOV DPL,R2 ;address i/o page MOVX A,@DPTR ;get i/o address ANL A,#7FH ;set strobe MOVX @DPTR,A ;restore to i/o page CALL UPDoUT5 ;turn on address ok strobe MOV R0,#LOW(RPRA) ;switch back to first address MOV R5,#LOW(IOMAP) ;set address i/o direction map CALL UPDIN5 ;read inputs CALL INCVECTl ;address next input slot CALL UPDIN5 ;read single nibble CALL INCVECT2 ;address next i/o CJNE R4,#LOW(FSELECT),LOOPEXP ;test for end of expand scan REl'
Claims (3)
1. In a programmable controller having a processor which repeatedly executes a user control program and an I/O scan program, and having a fixed number of I/O buses for interfacing the processor with a corresponding number of I/O modules, the improvement therein comprising:
an I/O address module connected to one of the I/O buses for receiving data from the processor and generating a rack address on a first I/O expansion bus said I/O address module including means for signaling the processor that the I/O address module is connected to said one I/O bus;
a set of I/O interface modules connected to a set of other ones of the I/O buses and to a corresponding set of additional I/O expansion buses, each I/O interface module being operable to couple data between one of said other I/O buses and one of said additional I/O expansion buses;
an I/O rack which includes:
(a) an adaptor circuit connected to the first I/O
expansion bus for receiving the rack addresses generated thereon and producing an enabling signal when its pre-selected rack address is received thereon; and (b) a set of I/O modules each coupled to one of the additional I/O expansion buses to couple data between devices on a machine being controlled and its associated additional I/O expansion bus when the enabling signal is produced;
wherein the processor is responsive to the signal from the I/O address module to alter the I/O scan sequence which is performed in response to the execution of the I/O scan program.
an I/O address module connected to one of the I/O buses for receiving data from the processor and generating a rack address on a first I/O expansion bus said I/O address module including means for signaling the processor that the I/O address module is connected to said one I/O bus;
a set of I/O interface modules connected to a set of other ones of the I/O buses and to a corresponding set of additional I/O expansion buses, each I/O interface module being operable to couple data between one of said other I/O buses and one of said additional I/O expansion buses;
an I/O rack which includes:
(a) an adaptor circuit connected to the first I/O
expansion bus for receiving the rack addresses generated thereon and producing an enabling signal when its pre-selected rack address is received thereon; and (b) a set of I/O modules each coupled to one of the additional I/O expansion buses to couple data between devices on a machine being controlled and its associated additional I/O expansion bus when the enabling signal is produced;
wherein the processor is responsive to the signal from the I/O address module to alter the I/O scan sequence which is performed in response to the execution of the I/O scan program.
2. The programmable controller as recited in claim 1 in which there are a plurality of I/O racks and the adapter circuit in each is responsive to a different rack address generated on the first I/O expansion bus.
3. The programmable controller as recited in claim 1 in which each I/O rack includes a set of interface circuits, each interface circuit being connected between an I/O module and its associated I/O expansion bus, and each interface circuit being operable to transform the voltage level used on the I/O module with the voltage level used on its associated I/O expansion bus.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/415,915 US4504927A (en) | 1982-09-08 | 1982-09-08 | Programmable controller with expandable I/O interface circuitry |
| US415,915 | 1995-04-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1193023A true CA1193023A (en) | 1985-09-03 |
Family
ID=23647753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000435127A Expired CA1193023A (en) | 1982-09-08 | 1983-08-23 | Programmable controller with expandable i/o interface circuitry |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4504927A (en) |
| CA (1) | CA1193023A (en) |
Families Citing this family (49)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4593380A (en) * | 1984-06-04 | 1986-06-03 | General Electric Co. | Dual function input/output for a programmable controller |
| US5101478A (en) * | 1985-06-28 | 1992-03-31 | Wang Laboratories, Inc. | I/O structure for information processing system |
| US4882702A (en) * | 1986-03-31 | 1989-11-21 | Allen-Bradley Company, Inc. | Programmable controller with I/O expansion module located in one of I/O module positions for communication with outside I/O modules |
| JPH0752420B2 (en) * | 1986-09-10 | 1995-06-05 | 株式会社日立製作所 | I / O device address method |
| US4787029A (en) * | 1986-09-29 | 1988-11-22 | Gte Communication Systems Corporation | Level converting bus extender with subsystem selection signal decoding enabling connection to microprocessor |
| WO1988010468A1 (en) * | 1987-06-19 | 1988-12-29 | Human Devices, Inc. | Multiply-installable, multi-processor board for personal computer and workstation expansion buses |
| US5113496A (en) * | 1987-08-04 | 1992-05-12 | Mccalley Karl W | Bus interconnection structure with redundancy linking plurality of groups of processors, with servers for each group mounted on chassis |
| US4876664A (en) * | 1987-08-26 | 1989-10-24 | Allen-Bradley Company, Inc. | Programmable controller with a dual intermodule message system |
| US4858101A (en) * | 1987-08-26 | 1989-08-15 | Allen-Bradley Company, Inc. | Programmable controller with parallel processors |
| US5193189A (en) * | 1987-10-07 | 1993-03-09 | Allen-Bradley Company, Inc. | Programmable controller with multiple priority level task processing |
| US4937777A (en) * | 1987-10-07 | 1990-06-26 | Allen-Bradley Company, Inc. | Programmable controller with multiple task processors |
| US4910659A (en) * | 1987-12-11 | 1990-03-20 | Square D Company | Input and output peripheral controller cards for use in a programmable logic controller system |
| US5038317A (en) * | 1988-07-25 | 1991-08-06 | Allen-Bradley Company, Inc. | Programmable controller module rack with a relative rack slot addressing mechanism |
| JP2685245B2 (en) * | 1988-10-05 | 1997-12-03 | 株式会社東芝 | Programmable controller |
| EP0374293A1 (en) * | 1988-12-22 | 1990-06-27 | Siemens Aktiengesellschaft | Output device |
| US5283869A (en) * | 1989-07-25 | 1994-02-01 | Allen-Bradley Company, Inc. | Interrupt structure for network interface circuit |
| DE69025618T2 (en) * | 1989-09-20 | 1996-07-04 | Aeg Schneider Automation Inc | INPUT / OUTPUT MODULE WITH INPUT / OUTPUT COMBINATION POINT |
| EP0443876A3 (en) * | 1990-02-23 | 1992-01-02 | Kabushiki Kaisha Toshiba | Computer system capable of connecting expansion unit |
| US5142469A (en) * | 1990-03-29 | 1992-08-25 | Ge Fanuc Automation North America, Inc. | Method for converting a programmable logic controller hardware configuration and corresponding control program for use on a first programmable logic controller to use on a second programmable logic controller |
| DE69131440T2 (en) * | 1990-08-20 | 2000-02-03 | Toshiba Kawasaki Kk | Connection status confirmation system and method for an expansion unit |
| US5663901A (en) * | 1991-04-11 | 1997-09-02 | Sandisk Corporation | Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems |
| US5159209A (en) * | 1991-04-12 | 1992-10-27 | Artisoft, Inc. | Circuit to selectively process dip switches onto bus lines |
| US5859994A (en) * | 1992-08-10 | 1999-01-12 | Intel Corporation | Apparatus and method for modifying instruction length decoding in a computer processor |
| WO1994011802A1 (en) * | 1992-11-12 | 1994-05-26 | New Media Corporation | Reconfigureable interface between a computer and peripheral devices |
| US5887145A (en) | 1993-09-01 | 1999-03-23 | Sandisk Corporation | Removable mother/daughter peripheral card |
| US7137011B1 (en) * | 1993-09-01 | 2006-11-14 | Sandisk Corporation | Removable mother/daughter peripheral card |
| US5619722A (en) * | 1994-01-18 | 1997-04-08 | Teramar Group, Inc. | Addressable communication port expander |
| US5862401A (en) * | 1994-10-11 | 1999-01-19 | Crown International, Inc. | Programmable central intelligence controller and distributed intelligence network for analog/digital control systems |
| US5737190A (en) * | 1995-08-30 | 1998-04-07 | Frick York International | Digital input/output circuit board |
| JP3225804B2 (en) * | 1995-09-05 | 2001-11-05 | 株式会社日立製作所 | I / O channel expansion method |
| US5881278A (en) * | 1995-10-30 | 1999-03-09 | Advanced Micro Devices, Inc. | Return address prediction system which adjusts the contents of return stack storage to enable continued prediction after a mispredicted branch |
| US5781747A (en) * | 1995-11-14 | 1998-07-14 | Mesa Ridge Technologies, Inc. | Method and apparatus for extending the signal path of a peripheral component interconnect bus to a remote location |
| US5864707A (en) * | 1995-12-11 | 1999-01-26 | Advanced Micro Devices, Inc. | Superscalar microprocessor configured to predict return addresses from a return stack storage |
| USRE42761E1 (en) | 1997-12-31 | 2011-09-27 | Crossroads Systems, Inc. | Storage router and method for providing virtual local storage |
| US5941972A (en) * | 1997-12-31 | 1999-08-24 | Crossroads Systems, Inc. | Storage router and method for providing virtual local storage |
| US6088752A (en) * | 1998-08-06 | 2000-07-11 | Mobility Electronics, Inc. | Method and apparatus for exchanging information between buses in a portable computer and docking station through a bridge employing a serial link |
| US7734852B1 (en) * | 1998-08-06 | 2010-06-08 | Ahern Frank W | Modular computer system |
| US7269680B1 (en) * | 1998-08-06 | 2007-09-11 | Tao Logic Systems Llc | System enabling device communication in an expanded computing device |
| US6070214A (en) * | 1998-08-06 | 2000-05-30 | Mobility Electronics, Inc. | Serially linked bus bridge for expanding access over a first bus to a second bus |
| US6160365A (en) * | 1999-03-11 | 2000-12-12 | Eaton Corporation | Interface module for a motor control system |
| US6505083B1 (en) | 1999-05-07 | 2003-01-07 | Seagate Technology Llc | Apparatus for assembling a disc storage system including a modular input/output board |
| JP2003523575A (en) | 2000-02-14 | 2003-08-05 | モビラティ、イレクトラニクス、インク | Coupling system and method |
| EP1653373B1 (en) | 2000-02-14 | 2013-11-13 | Tao Logic Systems LLC | Bus bridge |
| US6594719B1 (en) | 2000-04-19 | 2003-07-15 | Mobility Electronics Inc. | Extended cardbus/pc card controller with split-bridge ™technology |
| US6804737B2 (en) | 2000-12-26 | 2004-10-12 | Lsi Logic Corporation | Methods and systems for intelligent I/O controller with channel expandability via master/slave configuration |
| US20030135470A1 (en) * | 2002-01-16 | 2003-07-17 | Beard Robert E. | Method and system for credit card purchases |
| US6920574B2 (en) * | 2002-04-29 | 2005-07-19 | Apple Computer, Inc. | Conserving power by reducing voltage supplied to an instruction-processing portion of a processor |
| US7017373B2 (en) * | 2002-09-03 | 2006-03-28 | Owens-Brockway Glass Container Inc. | Glassware forming machine control system |
| US20060206677A1 (en) * | 2003-07-03 | 2006-09-14 | Electronics And Telecommunications Research Institute | System and method of an efficient snapshot for shared large storage |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4050098A (en) * | 1975-11-17 | 1977-09-20 | Gulf & Western Industries, Inc. | Self-addressing modules for programmable controller |
| US4162536A (en) * | 1976-01-02 | 1979-07-24 | Gould Inc., Modicon Div. | Digital input/output system and method |
| GB1574468A (en) * | 1976-09-30 | 1980-09-10 | Burroughs Corp | Input-output subsystem in a digital data processing system |
| US4200930A (en) * | 1977-05-23 | 1980-04-29 | Burroughs Corporation | Adapter cluster module for data communications subsystem |
| US4153945A (en) * | 1977-06-20 | 1979-05-08 | International Business Machines Corporation | Multiplexed control subsystem for sensor based systems |
| US4275455A (en) * | 1977-07-11 | 1981-06-23 | Automation Systems, Inc. | Output interface card suitable for use with a programmable logic controller |
| US4155115A (en) * | 1977-12-30 | 1979-05-15 | Honeywell Inc. | Process control system with analog output control circuit |
| US4276594A (en) * | 1978-01-27 | 1981-06-30 | Gould Inc. Modicon Division | Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and method for performing the same |
| US4207609A (en) * | 1978-05-08 | 1980-06-10 | International Business Machines Corporation | Method and means for path independent device reservation and reconnection in a multi-CPU and shared device access system |
| US4246637A (en) * | 1978-06-26 | 1981-01-20 | International Business Machines Corporation | Data processor input/output controller |
| US4215395A (en) * | 1978-08-24 | 1980-07-29 | Texas Instruments Incorporated | Dual microprocessor intelligent programmable process control system |
| US4254473A (en) * | 1979-01-29 | 1981-03-03 | Allen-Bradley Company | Rack adapter for serially connected I/O interface racks |
| US4293924A (en) * | 1979-05-30 | 1981-10-06 | Allen-Bradley Company | Programmable controller with high density intelligent I/O interface |
| US4250563A (en) * | 1979-08-09 | 1981-02-10 | Allen-Bradley Company | Expandable programmable controller |
| US4245307A (en) * | 1979-09-14 | 1981-01-13 | Formation, Inc. | Controller for data processing system |
| US4404651A (en) * | 1981-03-09 | 1983-09-13 | Allen-Bradley Company | Programmable controller for using coded I/O data technique |
| US4413319A (en) * | 1981-03-09 | 1983-11-01 | Allen-Bradley Company | Programmable controller for executing block transfer with remote I/O interface racks |
-
1982
- 1982-09-08 US US06/415,915 patent/US4504927A/en not_active Expired - Lifetime
-
1983
- 1983-08-23 CA CA000435127A patent/CA1193023A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4504927A (en) | 1985-03-12 |
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