CA1194192A - Circuitry for recovery of data from certain bit positions of a t1 span - Google Patents
Circuitry for recovery of data from certain bit positions of a t1 spanInfo
- Publication number
- CA1194192A CA1194192A CA000429475A CA429475A CA1194192A CA 1194192 A CA1194192 A CA 1194192A CA 000429475 A CA000429475 A CA 000429475A CA 429475 A CA429475 A CA 429475A CA 1194192 A CA1194192 A CA 1194192A
- Authority
- CA
- Canada
- Prior art keywords
- signal
- ccis
- circuitry
- data
- bit positions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q1/00—Details of selecting apparatus or arrangements
- H04Q1/18—Electrical details
- H04Q1/30—Signalling arrangements; Manipulation of signalling currents
- H04Q1/50—Conversion between different kinds of signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/12—Arrangements providing for calling or supervisory signals
- H04J3/125—One of the channel pulses or the synchronisation pulse is also used for transmitting monitoring or supervisory signals
Abstract
CIRCUITRY FOR RECOVERY OF DATA FROM
CERTAIN BIT POSITIONS OF A Tl SPAN
ABSTRACT OF THE INVENTION
This circuit provides for retrieving common control interoffice signaling (CCIS) data from a PCM
voice data stream of a Tl span. Tl spans interconnect switching offices. Unused data bits in these Tl spans are encoded with CCIS data and transmitted between the switching systems where the CCIS data is recovered.
CERTAIN BIT POSITIONS OF A Tl SPAN
ABSTRACT OF THE INVENTION
This circuit provides for retrieving common control interoffice signaling (CCIS) data from a PCM
voice data stream of a Tl span. Tl spans interconnect switching offices. Unused data bits in these Tl spans are encoded with CCIS data and transmitted between the switching systems where the CCIS data is recovered.
Description
CIRCUITRY FOR RECOVERY OF DATA FROM
CERTAIN BIT POSITIONS OF A Tl SPAN
_ _ ~
B~CK~R~O or ~ HE N~:ENTION
The present invention pertains to serial data link transmission techniques between digital switchlng systems and more particularly to circui-try for recovery of data from unused bit ~ositions of a Tl span.
Digital trunk units perform interface func-tions between Tl spans and the central processingunit (CPU) of a digital telephone switching system.
5ertaln bit positions in a I'l span are unused. These bit positions may be used to transmit other data. The problem is to recover this data from the unused bit position synchronously with the flow of the PCM data of a Tl span. A terminal equipment control circuit provides for detecting this data and retransmittinq it to the swltching system's CPU.
The terminal equipment control circuit must be synchronized with the particular Tl span from which it is receiving data. A digital trunk unit operates a number of Tl spans. Therefore, the terminal equip-ment control circuit of a common channel interoffice signaling (CCIS) system must be capable of synchronizing with a number of different Tl spans. If each Tl span generates its transmit and receive clocks, there will be a large number of clock circuits and connections required, one for each Tl span, to mainta;n synchronism between the digital trunk unit and the terminal equip-ment control circuit.
In order to accurately retrieve the CCISdata from the unused bit positions of the incoming Tl spans, a detection and synchronization scheme is required. Accordingly, it is the object of the present invention to provide for synchronously detecting CCIS
data in unused bit positions of a number of Tl spans while minimizing the number of synchronization clock sources.
~', t2 SUMMARY OF THE INVENTION
A digital switching system is operated by a central processing unit. This switching system operates to transfer voice data of Tl spans via the switching system.
Certain bit positions within the Tl span frame are unused. Therefore, CCIS data may be trans-mitted via the switching system in these unused bit positions. Accordingly, the circuitry for recovering the CCIS data from any one of a number of Tl spans is provided.
This circuitry includes a digital switching network with a master clock which provides a fixed frequency for operating the switching network. A
CCIS clock circuit is connected to the switching network's master clock and the CCIS clock operates to count down the master clock frequency to another frequency for use in detecting the CCIS data. A
digital trunk unit is connected between a number of T1 spans and the switching network. The digital trunk unit transfers PCM voice data from the Tl spans to the switching network. In addition, the digital trunk unit removes a synchronization/framing (S/F) bit from each Tl frame.
Converting apparatus is connected to the digital trunk unit and the CCIS clock. The converting apparatus receives these S/F bits and accumulates a fixed number of them ~or subsequent periodic exam-ination. At each particular time interval, eight values of the S/F bit are collected, one from each of eight consecutive Tl span frames. Four of these bits in alternate positions are synchronization, S
bits~ The other four alternate bits are framing, F bits.
Comparing apparatus is provided for examining the values of the F bits at each time interval period.
Four other bit values are input to the comparator apparatus for reference comparison and include two connections to the logic voltage source and two con~
nections to electrical ground. These connections are organized to form a particular binary pattern.
The comparing apparatus then tests the F bits input to it in each particular time interval with the ref-erence bit values which are hard wired. A signal indicating equality is produced by the comparing apparatus upon detection of a bit for bit match.
When this condition is achieved, it is known that the least recent S bit received by the converting apparatus contains the CCIS data to be retrieved.
This data is then in suitable form to ~e transmitted to the CPU.
DESCRIPTION OF THE DRAWINCS
Figure 1 is a block diagram of a portion of a digital switching system for recovering data from incoming Tl spans.
Figure 2 is a diagram o~ a sample Tl frame layout.
Figure 3 is a schematic diagram of the terminal equipment control circuitry shown in Figure 1.
DESCRIPTION OF THE PREFERRED EMBODIMENT
. ~ _ Referring to Figure 1, a number of incoming Tl spans are shown connected to a digital trunk unit 20. A terminal equipment control circuit (TECC) 10 is connected between a CCIS central processing unit (CPU) and digital trunk unit (DTU) 20. Digital trunk unit 20 is also connected to a switching network 30.
PCM voice data is transmitted from the digital trunk unit 20 to the switching network 30. Switching network 30 is further connected to CCIS clock 40 via a master clock lead. A master clock signal, transmitted via this lead, provides for synchronization and clocking to operate the switching network 30. The master clock signal is transmitted to CCIS clock 40 via the master clock lead. The frequency of this signal is 12.352 MHZ. There is an absence of a pulse in this master clock signal, at a frequency of 8 KHZ.
CCIS clock 40 is connected to TECC 10.
CCIS clock 40 operates in response to the master clock signal to detect the 8 KHZ absent pulse. As a result, clock 40 generates an 8 KHZ CCIS data clock signal which is synchroni~ed to the absent pulse.
The absent pulse is a sychronization/framing (S/F) bit of a Tl frame, see Figure 2. As shown in Figure 2, the Tl frame is 193 bits in length or 125 microseconds in duration. Twenty-four channels of 8 bits each are included in one Tl frame. The 193rd bit of each Tl frame is the S/F bit. This bit position is alternately a synchronization and a framing bit.
Since modern Tl carrier equipment does not use the synchronization bit, CCIS data may be trans-mitted in this bit position between digital switchingsystems. This synchronized 8 KHZ CCIS clock signal is transmitted from clock 40 to a number of TECCs (not shown). In addition, the DTU 20 may be connected to a number of TECCs, each TECC handling a different incoming Tl span~
The DTU 20 removes the PCM voice data from a particular Tl span and transfers this data to switching network 30. The S/F bits are transmitted to TECC
10 for analysis. Since the switching network clock operates the switching network and DTU and additionally the CCIS data clock is derived from it, the TECC, DTU and switching network will be operating synchro-nously with respect to a particular Tl span.
Since the S and F bits alternately appear in the Tl Erames, a method of distinguishing them is employed by the TECC. The synchronous 8 KHZ CCIS
data clock which was derived by CCIS clock 40 as a result of counting down master clock signal provides for gating the S/F bits into a converting apparatus.
The converting apparatus collects eight values of the S/F bit. These bits are collected and ordered for subsequent examination. Four of the bits in alternate positions are S bits and the other four ~41;~
alternate positions are F bits. The F bits are then compared against a fixed pattern of binary value "1010".
If a match of the F bits is detected, the least recent S bit received is CCIS data.
Figure 3 depicts the converting and com-paring apparatus of the terminal equipment control circuit 10, as shown in Figure 1. The S/F bits are transmitted via the S/F lead shown connected from the DTU 20 of Figure 1 to AND gate 307. An enabling signal is provided to ~ND gate 307 via control logic (not shown) under control of the CCIS CPU.
Gate 307 is connected to 8-bit shift register 31~ and provides for applying the S/F bits serially to shift register 315. Inverter 315 is connected to a clock input of shift register 316. The synchro-nized 8 KHZ clock signal, derived via the CCIS clock 40 of Figure 1, is transmitted through inverter 315 via the CCLK8 lead to shift register 316. This 8 KHZ signals provides for shifting each incoming S/F
bit into a parallel format for subsequent examination.
Shift register 316 provides for aligning the values of these eight parallel bit positions as outputs 00 through 07. ~eginning with output 00, each alternate bit position is connected via a corresponding lead to 4-bit comparator 320. These four bits represent one of the inputs which the comparator 320 is to examine.
The values of the second 4-bit input, which are to be examined by comparator 320, are con-structed as follows. A source of +5 volts or logic "1" is connected to comparator 320 in alternate blt positions beginning with the first bit position.
Electrical ground or logic "0" is connected to com-parator 320 in alternate bit positions beginning with the second bit position. As a result, the binary se~uence "1010" is input to comparator 320 as a ref-erence. Comparator 320 matches bit for bit the values of the first sequence of four bits input from shift register 316, with the values of the second sequence of bits input ln the hard wired form.
Comparator 320 produces an output if the values of the first sequence of bits is equal to the values of the second sequence of bits. This signal is transmitted to AND gate 325 via a lead connecting gate 325 to comparator 320. When the framing bits have the value of "1010", the least recently received S bit, which resides in bit position 07 of shift register 316, contains CCIS data. Bit position 07 of shift register 316 is connected to AND gate 325.
The enabling signal, generated by the equality of the F bits with the hard wired bit pattern, allows AND gate 325 to transmit the CCIS data bit to CPU
via the CCIS data out lead. The CPU will receive the CCIS data at a rate of 4K bits per second.
As mentioned above a number of terminal equipment control circuits TECCs 10 as shown in Figure 1, may simultaneously be recovering CCIS data and retransmitting it to the CPU.
Although the preferred embodiment of the invention has been illustrated, and that form described in detail, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims.
CERTAIN BIT POSITIONS OF A Tl SPAN
_ _ ~
B~CK~R~O or ~ HE N~:ENTION
The present invention pertains to serial data link transmission techniques between digital switchlng systems and more particularly to circui-try for recovery of data from unused bit ~ositions of a Tl span.
Digital trunk units perform interface func-tions between Tl spans and the central processingunit (CPU) of a digital telephone switching system.
5ertaln bit positions in a I'l span are unused. These bit positions may be used to transmit other data. The problem is to recover this data from the unused bit position synchronously with the flow of the PCM data of a Tl span. A terminal equipment control circuit provides for detecting this data and retransmittinq it to the swltching system's CPU.
The terminal equipment control circuit must be synchronized with the particular Tl span from which it is receiving data. A digital trunk unit operates a number of Tl spans. Therefore, the terminal equip-ment control circuit of a common channel interoffice signaling (CCIS) system must be capable of synchronizing with a number of different Tl spans. If each Tl span generates its transmit and receive clocks, there will be a large number of clock circuits and connections required, one for each Tl span, to mainta;n synchronism between the digital trunk unit and the terminal equip-ment control circuit.
In order to accurately retrieve the CCISdata from the unused bit positions of the incoming Tl spans, a detection and synchronization scheme is required. Accordingly, it is the object of the present invention to provide for synchronously detecting CCIS
data in unused bit positions of a number of Tl spans while minimizing the number of synchronization clock sources.
~', t2 SUMMARY OF THE INVENTION
A digital switching system is operated by a central processing unit. This switching system operates to transfer voice data of Tl spans via the switching system.
Certain bit positions within the Tl span frame are unused. Therefore, CCIS data may be trans-mitted via the switching system in these unused bit positions. Accordingly, the circuitry for recovering the CCIS data from any one of a number of Tl spans is provided.
This circuitry includes a digital switching network with a master clock which provides a fixed frequency for operating the switching network. A
CCIS clock circuit is connected to the switching network's master clock and the CCIS clock operates to count down the master clock frequency to another frequency for use in detecting the CCIS data. A
digital trunk unit is connected between a number of T1 spans and the switching network. The digital trunk unit transfers PCM voice data from the Tl spans to the switching network. In addition, the digital trunk unit removes a synchronization/framing (S/F) bit from each Tl frame.
Converting apparatus is connected to the digital trunk unit and the CCIS clock. The converting apparatus receives these S/F bits and accumulates a fixed number of them ~or subsequent periodic exam-ination. At each particular time interval, eight values of the S/F bit are collected, one from each of eight consecutive Tl span frames. Four of these bits in alternate positions are synchronization, S
bits~ The other four alternate bits are framing, F bits.
Comparing apparatus is provided for examining the values of the F bits at each time interval period.
Four other bit values are input to the comparator apparatus for reference comparison and include two connections to the logic voltage source and two con~
nections to electrical ground. These connections are organized to form a particular binary pattern.
The comparing apparatus then tests the F bits input to it in each particular time interval with the ref-erence bit values which are hard wired. A signal indicating equality is produced by the comparing apparatus upon detection of a bit for bit match.
When this condition is achieved, it is known that the least recent S bit received by the converting apparatus contains the CCIS data to be retrieved.
This data is then in suitable form to ~e transmitted to the CPU.
DESCRIPTION OF THE DRAWINCS
Figure 1 is a block diagram of a portion of a digital switching system for recovering data from incoming Tl spans.
Figure 2 is a diagram o~ a sample Tl frame layout.
Figure 3 is a schematic diagram of the terminal equipment control circuitry shown in Figure 1.
DESCRIPTION OF THE PREFERRED EMBODIMENT
. ~ _ Referring to Figure 1, a number of incoming Tl spans are shown connected to a digital trunk unit 20. A terminal equipment control circuit (TECC) 10 is connected between a CCIS central processing unit (CPU) and digital trunk unit (DTU) 20. Digital trunk unit 20 is also connected to a switching network 30.
PCM voice data is transmitted from the digital trunk unit 20 to the switching network 30. Switching network 30 is further connected to CCIS clock 40 via a master clock lead. A master clock signal, transmitted via this lead, provides for synchronization and clocking to operate the switching network 30. The master clock signal is transmitted to CCIS clock 40 via the master clock lead. The frequency of this signal is 12.352 MHZ. There is an absence of a pulse in this master clock signal, at a frequency of 8 KHZ.
CCIS clock 40 is connected to TECC 10.
CCIS clock 40 operates in response to the master clock signal to detect the 8 KHZ absent pulse. As a result, clock 40 generates an 8 KHZ CCIS data clock signal which is synchroni~ed to the absent pulse.
The absent pulse is a sychronization/framing (S/F) bit of a Tl frame, see Figure 2. As shown in Figure 2, the Tl frame is 193 bits in length or 125 microseconds in duration. Twenty-four channels of 8 bits each are included in one Tl frame. The 193rd bit of each Tl frame is the S/F bit. This bit position is alternately a synchronization and a framing bit.
Since modern Tl carrier equipment does not use the synchronization bit, CCIS data may be trans-mitted in this bit position between digital switchingsystems. This synchronized 8 KHZ CCIS clock signal is transmitted from clock 40 to a number of TECCs (not shown). In addition, the DTU 20 may be connected to a number of TECCs, each TECC handling a different incoming Tl span~
The DTU 20 removes the PCM voice data from a particular Tl span and transfers this data to switching network 30. The S/F bits are transmitted to TECC
10 for analysis. Since the switching network clock operates the switching network and DTU and additionally the CCIS data clock is derived from it, the TECC, DTU and switching network will be operating synchro-nously with respect to a particular Tl span.
Since the S and F bits alternately appear in the Tl Erames, a method of distinguishing them is employed by the TECC. The synchronous 8 KHZ CCIS
data clock which was derived by CCIS clock 40 as a result of counting down master clock signal provides for gating the S/F bits into a converting apparatus.
The converting apparatus collects eight values of the S/F bit. These bits are collected and ordered for subsequent examination. Four of the bits in alternate positions are S bits and the other four ~41;~
alternate positions are F bits. The F bits are then compared against a fixed pattern of binary value "1010".
If a match of the F bits is detected, the least recent S bit received is CCIS data.
Figure 3 depicts the converting and com-paring apparatus of the terminal equipment control circuit 10, as shown in Figure 1. The S/F bits are transmitted via the S/F lead shown connected from the DTU 20 of Figure 1 to AND gate 307. An enabling signal is provided to ~ND gate 307 via control logic (not shown) under control of the CCIS CPU.
Gate 307 is connected to 8-bit shift register 31~ and provides for applying the S/F bits serially to shift register 315. Inverter 315 is connected to a clock input of shift register 316. The synchro-nized 8 KHZ clock signal, derived via the CCIS clock 40 of Figure 1, is transmitted through inverter 315 via the CCLK8 lead to shift register 316. This 8 KHZ signals provides for shifting each incoming S/F
bit into a parallel format for subsequent examination.
Shift register 316 provides for aligning the values of these eight parallel bit positions as outputs 00 through 07. ~eginning with output 00, each alternate bit position is connected via a corresponding lead to 4-bit comparator 320. These four bits represent one of the inputs which the comparator 320 is to examine.
The values of the second 4-bit input, which are to be examined by comparator 320, are con-structed as follows. A source of +5 volts or logic "1" is connected to comparator 320 in alternate blt positions beginning with the first bit position.
Electrical ground or logic "0" is connected to com-parator 320 in alternate bit positions beginning with the second bit position. As a result, the binary se~uence "1010" is input to comparator 320 as a ref-erence. Comparator 320 matches bit for bit the values of the first sequence of four bits input from shift register 316, with the values of the second sequence of bits input ln the hard wired form.
Comparator 320 produces an output if the values of the first sequence of bits is equal to the values of the second sequence of bits. This signal is transmitted to AND gate 325 via a lead connecting gate 325 to comparator 320. When the framing bits have the value of "1010", the least recently received S bit, which resides in bit position 07 of shift register 316, contains CCIS data. Bit position 07 of shift register 316 is connected to AND gate 325.
The enabling signal, generated by the equality of the F bits with the hard wired bit pattern, allows AND gate 325 to transmit the CCIS data bit to CPU
via the CCIS data out lead. The CPU will receive the CCIS data at a rate of 4K bits per second.
As mentioned above a number of terminal equipment control circuits TECCs 10 as shown in Figure 1, may simultaneously be recovering CCIS data and retransmitting it to the CPU.
Although the preferred embodiment of the invention has been illustrated, and that form described in detail, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims.
Claims (8)
1. In a digital switching system having a CPU and a plurality of Tl spans, voice data of said Tl spans being switched by said system, circuitry for recovering CCIS data from any of said plurality of Tl spans, said circuitry comprising:
a digital switching network including a master clock providing a first signal of a first frequency;
a CCIS clock connected to said digital switching network and said master clock, said CCIS
clock being operated in response to said first signal to produce a second signal of a second frequency;
a digital trunk unit connected between said plurality of Tl spans and said switching network, said digital trunk unit operated to transfer said voice data of said Tl spans to said digital switching network;
said digital trunk unit further operated to transmit a third signal at a particular frequency;
means for converting connected to said digital trunk unit and to said CCIS clock, said means for converting operated in response to said third signal and said second signal to produce a fourth signal at periodic time intervals;
said fourth signal of any of said time intervals being values for a first sequence of par-ticular bit positions of one said Tl span;
means for setting predetermined values for a second sequence of bit positions; and means for comparing connected to said means for converting and to said means for setting, said means for comparing operated in response to said first and said second sequences of bit positions to produce a fifth signal of a first value for equality of said values of said first and second sequences of bit positions for indicating the detection of a CCIS data bit or alternatively to produce said fifth signal of a second value for inequality of said values of said first and second sequences of bit positions.
a digital switching network including a master clock providing a first signal of a first frequency;
a CCIS clock connected to said digital switching network and said master clock, said CCIS
clock being operated in response to said first signal to produce a second signal of a second frequency;
a digital trunk unit connected between said plurality of Tl spans and said switching network, said digital trunk unit operated to transfer said voice data of said Tl spans to said digital switching network;
said digital trunk unit further operated to transmit a third signal at a particular frequency;
means for converting connected to said digital trunk unit and to said CCIS clock, said means for converting operated in response to said third signal and said second signal to produce a fourth signal at periodic time intervals;
said fourth signal of any of said time intervals being values for a first sequence of par-ticular bit positions of one said Tl span;
means for setting predetermined values for a second sequence of bit positions; and means for comparing connected to said means for converting and to said means for setting, said means for comparing operated in response to said first and said second sequences of bit positions to produce a fifth signal of a first value for equality of said values of said first and second sequences of bit positions for indicating the detection of a CCIS data bit or alternatively to produce said fifth signal of a second value for inequality of said values of said first and second sequences of bit positions.
2. Circuitry as claimed in claim 1, wherein there is further included gating means connected to said means for converting and to said means for com-paring and said gating means operated in response to said fifth signal of said first value to transmit said indicated CCIS data to said CPU.
3. Circuitry as claimed in claim 2, said means for converting including:
a serial to parallel shift register;
a first gate connected to said shift register;
a first connection from said digital trunk unit to said first gate for transmitting a particular frequency of bit position values to said shift register via said first gate;
a second connection from said CCIS clock to said shift register for synchronizing said third signal for conversion to said fourth signal; and a plurality of third connections to said means for comparing for transmitting said values of first sequence of bit positions to said means for comparing.
a serial to parallel shift register;
a first gate connected to said shift register;
a first connection from said digital trunk unit to said first gate for transmitting a particular frequency of bit position values to said shift register via said first gate;
a second connection from said CCIS clock to said shift register for synchronizing said third signal for conversion to said fourth signal; and a plurality of third connections to said means for comparing for transmitting said values of first sequence of bit positions to said means for comparing.
4. Circuitry as claimed in claim 3, said means for setting including:
a voltage source;
a first plurality of connections to electrical ground;
a second plurality of connections to said voltage source; and said first and second pluralities of con-nections ordered to form said second sequence of bit positions having a binary value of 1010.
a voltage source;
a first plurality of connections to electrical ground;
a second plurality of connections to said voltage source; and said first and second pluralities of con-nections ordered to form said second sequence of bit positions having a binary value of 1010.
5. Circuitry as claimed in claim 4, said means for comparing including:
a comparator connected to said shift register via said plurality of third connections;
said comparator further connected to said means for setting via said first and second pluralities of connections to said voltage source and said electrical ground; and said comparator operated to detect equality of said values of said first and second sequences of said bit positions.
a comparator connected to said shift register via said plurality of third connections;
said comparator further connected to said means for setting via said first and second pluralities of connections to said voltage source and said electrical ground; and said comparator operated to detect equality of said values of said first and second sequences of said bit positions.
6. Circuitry as claimed in claim 5, wherein there is further included a connection from said gating means to said shift register for transmitting said CCIS data bit.
7. Circuitry as claimed in claim 5, wherein there is further included a connection from said gating means to said comparator for transmitting said fifth signal.
8. Circuitry as claimed in claim 5, wherein there is further included a connection from said gating means to said CPU for transmitting said CCIS
data to said CPU.
data to said CPU.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/435,196 US4467469A (en) | 1982-10-19 | 1982-10-19 | Circuitry for recovery of data from certain bit positions of a T1 span |
| US435,196 | 1989-11-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1194192A true CA1194192A (en) | 1985-09-24 |
Family
ID=23727423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000429475A Expired CA1194192A (en) | 1982-10-19 | 1983-06-01 | Circuitry for recovery of data from certain bit positions of a t1 span |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4467469A (en) |
| CA (1) | CA1194192A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59171353A (en) * | 1983-03-18 | 1984-09-27 | Fujitsu Ltd | Channel group connecting system |
| US4730312A (en) * | 1986-02-21 | 1988-03-08 | San/Bar Corporation | Voice, data or both over one telephone line in a T-1 carrier system |
| EP0262478B1 (en) * | 1986-09-29 | 1991-08-21 | Siemens Aktiengesellschaft | Method for frame synchronization of an exchange of a pcm-tdm telecommunication network |
| ATE134094T1 (en) * | 1987-03-03 | 1996-02-15 | Siemens Ag | CIRCUIT ARRANGEMENT FOR TRANSMITTING DATA SIGNALS OVER A TIME MULTIPLEX TRANSMISSION LINE |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3542957A (en) * | 1968-10-25 | 1970-11-24 | Stromberg Carlson Corp | Multiplex arrangement for pulse code modulated signalling system |
| CH621445A5 (en) * | 1976-09-09 | 1981-01-30 | Gretag Ag | |
| US4268722A (en) * | 1978-02-13 | 1981-05-19 | Motorola, Inc. | Radiotelephone communications system |
| US4191857A (en) * | 1978-09-28 | 1980-03-04 | Gte Automatic Electric Laboratories Incorporated | Digital trunk supervisory decoder multiplexor for ground start or E&M signalling on a common T1 span |
| US4314368A (en) * | 1978-10-12 | 1982-02-02 | Decoursey Calvin H | Receiver for pulse code multiplexed signals |
-
1982
- 1982-10-19 US US06/435,196 patent/US4467469A/en not_active Expired - Fee Related
-
1983
- 1983-06-01 CA CA000429475A patent/CA1194192A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4467469A (en) | 1984-08-21 |
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