CA1196388A - Radio paging receiver having stored message protection means - Google Patents
Radio paging receiver having stored message protection meansInfo
- Publication number
- CA1196388A CA1196388A CA000420608A CA420608A CA1196388A CA 1196388 A CA1196388 A CA 1196388A CA 000420608 A CA000420608 A CA 000420608A CA 420608 A CA420608 A CA 420608A CA 1196388 A CA1196388 A CA 1196388A
- Authority
- CA
- Canada
- Prior art keywords
- memory
- signal
- message
- read
- display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
- H04W88/02—Terminal devices
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W84/00—Network topologies
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W84/00—Network topologies
- H04W84/02—Hierarchically pre-organised networks, e.g. paging networks, cellular networks, WLAN [Wireless Local Area Network] or WLL [Wireless Local Loop]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
- H04W88/02—Terminal devices
- H04W88/022—Selective call receivers
- H04W88/023—Selective call receivers with message or information receiving capability
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
ABSTRACT
A radio paging receiver has circuitry for receiving and demodulating modulated carrier waves to provide demodulated paging and message signals and circuitry for detecting a specific paging signal thereby to generate an alert signal as is conventional. In conventional paging receivers the message sig-nals received can be stored up to a maximum depending upon the size of the memory used in the receiver so that when subsequent messages are received the earliest messages are progressively erased. The present invention provides a memory protect switch which allows the user to save any message which he has read out on his receiver and judged to be sufficiently important not to lose.
Operation of the memory protect switch causes the important message to be moved out of a first memory which is progressively erased as more messages come in to a second memory which is not subject to such erasure.
A radio paging receiver has circuitry for receiving and demodulating modulated carrier waves to provide demodulated paging and message signals and circuitry for detecting a specific paging signal thereby to generate an alert signal as is conventional. In conventional paging receivers the message sig-nals received can be stored up to a maximum depending upon the size of the memory used in the receiver so that when subsequent messages are received the earliest messages are progressively erased. The present invention provides a memory protect switch which allows the user to save any message which he has read out on his receiver and judged to be sufficiently important not to lose.
Operation of the memory protect switch causes the important message to be moved out of a first memory which is progressively erased as more messages come in to a second memory which is not subject to such erasure.
Description
3~ 1 R~DIO PAGING RECEIVER HAVING STORED MESSAGE
PF!OTECTION MEANS
BACKGROUND OF THE INVENTION
The present invention relates to a radio paging receiver for use in radio paging.
Owing to the remarkable progress of circuit integration technology in recent years, more compact radio paging receivers of a greater multiplicity of unctions and of smaller power consumption come to be developed. One aspect of this increase in functional multiplicity is the recent addition of message signals to the previous service of send-ing the selective calling or paging signal (a specificnumber assigned to each subscriber) alone. Furthermore, to cope with the expansion of the demand spectrum and to increase the reliability of communication, these paging and message signals are now digitized.
Meanwhile, the display of a message signal is achived, after the receipt of said paging signal, upon actuation of the function to indicate the receipt of the message signal.
There are provided within a receiver a plurality of message signal memory circuits, because the subscriber may be paged very frequently or may not promptly respond to every message signal received. The message signals stored in these memory circuits can be read out by a variety of methods. For instance, where there are n memory circuits, n read-out ''~
38~3 i switches may be provided to enable the subscriber to operate in one action the switch corresponding to the particular memory circuit in which the desired message signal is storea. ~lternatively, there may be one read-out switch, which the subscriber will have to operate n times at the maximum to have the desired message signal read out. A
radio paging receiver having one of such ~unctions, which indicates the receipt of and stores every message signal received, is very convenient because it allows a long enough time for its bearer to take a plurality of actions.
However, the number of memory circuits is limited by elements ar software and, accordingly, if more message signals than the memory circuits are received, the early signal or signals will have to be erased in the order of arrival. Thus, even if one of the plurality of memorized signals contains important information and has to be kept for a long period, it may have to be indiscriminately erased upon arrival of an extra message or messages. Normally, most of the message signals received can be promptly responded to and therefore erased soon, and keeping obsolete messages would unnecessarily complicate the subsequent procedures.
~ith the aforementioned setup which requires the read-out switch to be operated as many times as the desired memory circuit calls for, for instance, there would be a correspond-ing increase in the required number of switching actions or,switches would have to be correspondingly greater.
Moreover, a greater number of memory circuits means a ~6~8 correspondingly higher cost..
SUMMARY OF THE INVENTION
An ob]ect of the present invention therefore is to provide an economical radio paging receiver which is free from the above stated disadvantages of conventional such receivers, and of which the switch operation is simplified and the number of memory circuits is reduced by enabling only important messages to be stored as long as they are needed, regardless of the memory capacity, and unimportant messages to be sequentially erased as the memory circuits are overflown.
According to the invention, there is provided a raAio paging receiver comprising: means for receiving and demodulating a carrier wave modulated with paging and message signals to provide demodulated paging and message signals; means for detecting, out of said demodulated paging signals, the paging signal assigned to said radio paging ; receiver to provide a detection signal; means responsive to said detectlon signal for generating an alert signal; first memory means for storing a plurality of said demodulated message signals; second memory means for preventing from erasure and storing at least--one of the message signals stored in said first memory means; display means for displaying at least one of the message signals stored in said first and sscond memory means; and display control means connected to said first and second memory means and said display means for selectively providing said display means with at least one of the message signals stored in said first and second memory means.
BRIEF DESCRIPTION OF T~E D~AWINGS
Other objects, features and advantages of the present invention will be more apparent from the detailed description hereunder takPn in conjunction with the accompanying drawings, wherein:
FIG. 1 iS a schematic block diagram of the radio paging receiver according to the present invention;
FIG. 2 shows the format of the calling signal to be received by the receiver according to the pxesent invention;
FIG. 3 is a more detailed block diagram of the decoder of the receiver illustrated in FIG. l;
FIG. 4 is a time chart for describing the signal receiving operation of the decoder illustrated in FIG. 3;
FIG. 5 is a time chart for describing the message information reading and message information protecting operation of the decoder illustrated in FIG. 3;
FIG. 6 is a block diagram illustrating a modification of the memory protector section of the decoder illustrated in FIG. 3;
FIG. 7 is a time chart for describing the operation of the memory protector section illustrated in FIG. 6;
FIG. 8 is a functional block diagram illustrating another embodiment of the decoder of the receiver illustrated in FIG. l;
FIG. 9, appearing on the same sheet as FIG. 7, is a block diagram conceptually illustrating a part of the data memory in the de-coder illustrated in FIG. 8; and FIGS. 10 and 11 are flow charts respectively showing the calling signal receiving and memory protecting operation of the de-coder illustrated in FIG. 8.
DESCRIPTION OF T~IE PREFERRED EMBODIMENTS
Referring to FIG. 1, a radio carrier wave received by an antenna 1, after being respectively amplified and frequency-converted by a radio frequency-intermediate frequency (RF-IF) circuit 2, is demodulated by a discriminator 3. The demodulated signal is sub-jected to decision by a decoder 4 as to whether or not it is the selective calling or paging signal assigned to the receiver and, if it is, an output pulse is given to a speaker driver circuit 7 to let the bearer of the receiver know, by so1mding a loud-speaker 8, that the paging signal has been received. At the same time, ensuing mess-age information is stored in a memory in the decoder 4. If, at this time, a memory read-out switch 10 is closed, one out of the messages then stored is supplied by way of a display driver circuit 5 to a dis-play device ~.
While messages stored in the memory within the decoder 4 are erased in the order of their entry as the memory is overflown, a specific message can be protected Erom erasure by operating a memory protect switch 11 or the switch 10, as ., "
....
I
will be described in urther detail hereunder. The message thereby protected will never be erased unless a power swi~ch 12 is turned off or another message is protected by again operating the switche 10 or 11. A display selector switch 3 5 9 permits selection between the displaying of only stored messages or the displaying of the protected message.
Referring now to FIG. 2, section X shows a selective calling signal assigned to each receiver, consisting for example of BCH (31, 21) codes which are a kind of cyclic 10 code, while section Y shows a message signal for conveying message information, consisting, like the selective calling signal, of BCH (31, 21) codes.
With reference to FIG. 3, the decoder 4 comprises delay type (D-type) flipflops 401 to 405, shift registers 406 to 412, a clock pulse generator 413, timers 414 and 415, inverters 416 to 423, AND gates 424 to 437, OR gates 438 to 443, a counter 444 and xesistors 445 to 448. To distinguish the shift registers 409 to 412 from other shift registers, the shift register 409 shall be hereinafter called MR-1; 410, MR-2; 411, MR-n and 412, MR-p.
Next, the operation o the decoder illustrated in FIG. 3 will be described in detail with reference to FIGS. 4 and 5. The D-type flipflop 401 synchronizes the calling signal, demodulated by the discriminator 3 (FIG. 1), with the inverted output (FIG. 4(B)) of the inverter 416 deriving from the output of the clock generator 413, and supplies the synchronized signal to the shift register 406. As a result, 3~
if the demodulated signal is found identical with a pattern (the selective calling~signal) predetermined by the inverters 417, 418 and 419, an identity signal ~FIG. 4(C)) will be generated rom the AND gate 424 and supplied to the speaker driver circuit 7. At the samé time, the flipflop 402 is inverted to drive the timer 414 which has a period of time T1 required for writinginto the register 408 the incoming message immediàtelv following the selective calling signal via the AND gates 425 and 426 To the other input of the AND gate 426 is supplied the clock pulse from the clock pulse generator 413.
After the message is completely stored in the shift register 408, the content of MR-n-1 is written into the shift register 411 (MR-n) in response to the output of the shift register 407 which is in response to a res~t sitnal ~FIG.
4(E)) from the timer 414. Similarly, the content of -the shift register 409 (MR-1) is written into the shift register 410 (MR-2) and so on until the message stored in the shift register 408 is written into the shift register 409 (MR-1) (See FIGS. 4~E), 4(F), 4(G) and 4(H)). Thus, a maximum of n received messages can be stored, and if more than n are received~ earlier messages will be erased in the order of their arrival.
Next will be described how the bearer of the receiver can read out-.one of the stored messages. The display selector switch 9 being turned to the N side, he can press the memory read-out switch 10, and then a signal I will drive i38~
the tlmer 415 through the inverter 421 and the flipflop 403 t~
allocate a predetermined display duration T2 (of, say, 8 seconds). During T2, a signal J shown in FIG. 5(J) is fed to the display driver circuit 5 to display a message on the display device 6 (which may be, for instance, a liquid crystal device).
If the memory read-out switch 10 is pressed only once, the counter 444 will be actuated via the inverter 421 to start counting and, a signal K being supplied from its Q1 terminal, the AND gates 427 to 428 will be opened. As a result, the content of the shift register 409 (MR-1) is displayed on the display device 6 by way of the OR gates 438 to 439, the AND gates 433 to 434, and the OR gates 440 to 441. Since the display selector switch 9 is turned to the N side, the inverter 422 provides a high level signal to open the AND gates 433 to 434. If, during the display duration T2, the memory read-out switch 10 is pressed once again, the counter 444 will count 2, an output L will emerge at a terminal Q2, and the AND gates 429 to 430 will be opened to display the content of MR-2. As the timer 415 is reset through the OR gate 443, the duration T2 will be renewed (FIG. 5(J)). Here, the outputs of the D-type flipflop 403 and the inverter 421 are supplied by way of the OR gate 442 to the display driver circuit 5 so that the display driver circuit 5 be kept active even while the memory read-out switch 10 continues to be pressed again and again.
3~3 Similarly, if the memory read-out switch 10 is pressed n times, the AND gates 431 to 432 will be opened to display the content of MR-n. If the memory read-out switch 10 is pr~essed n~1 times, the counter 444 will re~urn to count 1 to display thë content of MR-1. Thus, as the memory read-out switch 10 is pressed n times, the messages stored in the shift registers MR-1 to MR-n will be read out in due se~uence.
When the display duration T2 is over, the display driver circuit 5 is stopped and the counter 444 is reset by a reset signal from the timer 415. Th~refore, next time the memory read-out switch 10 is pressed, the display will again start from MR-1.
Now will be described the procedure by which a specific message is protected from erasure. First the message to be protected is displayed on the display device 6 by the same method as the above described process for simply reading any message, and the memory protect switch 11 is pressed. By that time, the message to be protected will have already been supplied from the OR gates 438 through 439 to the input of the message-protection shift register 412 (MR-p). Upon presslng of the memory protect switch 11, a write-in pulse is generated by the inverter 420 and D-type flipflops 404 and 405, and is supplied to the shift register 412 (MR-p) by way ,... . .
of the AND gate 437. In this way, the message being 2S displayed is stored in the shift register 412 ~MR-p) for protection from erasure.
;
;38~
If the display selector switch 9 is turned to the P
side, the AND gates 435 to 436 are opened with the output of the inverter 4~3, so that the message stored in the shift register 412 (MR-p) is supplied to the display driver circuit 5 through the OR gates 440 to 441. Then, as the memory read-out switch 10 is pressed, the message from the shift register MR-p is displayed on the display device 6.
During this procedure, the messages stored in the shift registers MR-1 to MR-n are prevented from going to the display driver circuit 5 by the closure of the AND gates 433 to 434, to which the output o~ the inverter 422 is fed~
When nothing or the content of MR-p is displayed on the display device 6, the memory protection mechanism is prohibited from functioning even if the memory protect 15 switch 11 is pressed. This is done by the AND gate 437.
The resistors 445 to 448 are pull-up resistors for securing a high level when the inputs to the inverters 420 to 423 are open. As mentioned above, with storing in the shi~t register MR-p, the message stored in MR-p can remain there indefinitely and can be displayed as required unless another message is shifted to the MR-p or the power supply is cut off.
Although the embodiment illustrated in FIGS. 1 and 3 has three switches, i.e., the memory read-out switch 10, the memory protect switch 11 and the display selector switch 9, if it is so rearranged as to enable the protected message to be read out, for instance, by pressing the memory read-out 638~
switch 10 n+1 times, the display selector switch 9 can be dispensed with. ~f, further, a timer is appropriately used, the memory protect switch 11 too can be dispensed with.
A version with such a timer will be described next.
In the circuit shown in FIG. 6, a timer ~49 is provided to dispense with the switch 11. The functioning of this circuit`will be described with reference to FIG. 7. When the memory read-out switch 10 is pressed, the timer 449 starts counting. When the switch 10 has been kept pressed longer than T3 (for instance, between tl and t2 in FIG. 7(I)), the timer 449 provides a high level signal. In response to this high level signal, the D-type flipflops 404 and 405 generate a write-in pulse O (FIG. 7(0)) to write into the shift register 412 (MR-p) the message being displayed on the display device 6. Thus, the displayed message is protected by keeping the memory read-out switch 10 pressed for a longer duration than the period T3 times by the timer 449. If it is further so arranged that the loudspeaker 8 (FIG. 1) be driven to emit a short sound upon generation of the write-in pulse O, greater convenience can be achieved because the bearer of the receiver will thereby confirm that the desired message is duly protected.
Referrlng now to FIG. 8, a decoder 4I having an LCD
controller/driver can use a single-chip control proces~sing unit (CPU), such as the microprocessor ,uPD7502 manufactured and mark~ted by the assignee of the present application, Nippon Electric Co., Ltd. A controller 501 decode command ti 38~
codes to be executed and controls the other blocks to execute the decoded command. In a program memory 502 are stored a group of commands to be executedu A program counter 503 is intended for addressing a program written - 5 into the program memory 502. A data memory 504 is provided for temporary storage of messages and the like. Clock pulses required by the decoder 4' are generated by a counter 505 receiving exterior clocks.
An arithmetic and logic unit (ALU) 506 executes arithmetic calculations, result of which is stored in an accumulator 513. The accumulator is also used for data exchange among the memory, input/output ports and registers.
An input port 507 is intended for receiving rectangular signals from the discriminator 3 and a read-out signal from the memory read-out switch 10. An output port 508 supplies an address signal for reading out the content of a programmable read-only memory (P-ROM) 513, in which is stored the selective calling signal assigned to the receiver. The signal read out of the P-FOM 513 is brought into the decoder 4' through another input port 509. An alert tone signal is supplied to the speaker driver circuit 7 by way of an output port 510. An LCD controller/driver 511, in response to the supply af data to be displayed from the data memory 504, displays the data on the LCD 6.
Referring now to-FIG. 9, a part of the data memory 504 includes four message memories MDATA 1 to MDATA 4, memory addresses MAD 1 to MAD 4 for designating one or another of 1~36388 , ~
the message memoxies, a protect 1ag PF and a read counter RC. If the content of the memory address MAD 1 is, for instance, "1", the messary memory MDATA 1 is addressed.
For a detailed description of the CPU shown in FIG. 8, reference is made to the User's Manual of the ~PD7502, published by Nippon Electric Co., Ltd., May 23, 1980.
Next will be described the calling signal receiving operation and the memory protecting operation of the decoder 4' with reference to the flow charts of FIGS. 10 and 1 1 .
In the following description, the step numbers in the flow charts are mentioned parenthesized after the respectively corresponding phrases, clauses or sentences. First, _ referring to FIG. 10, when the power supply is turned on (801), the content of each memory is initially set (802).
Into the memory address MAD 1 is entered "4"; into MAD 2, "3"; into MAD 3, "2", and into MAD 4, "1~'', and the message memories MDATA 1 to 4, the protect flag PF and the read counter RC are all cleared.
After the selective calling signal is received (803), the message is received (804) and simultaneously the alert tone sounding and the display start (805). Then whether or not the memory address MAD 1 is protected is checked (806) and, if it is not, the memory addresses MAD 1 to 4 will be passed forward by one each (80i) to have the message memory MDATA x ~x = 1, 2, 3 or 4) addressed by the memory address MAD 1 store the received message (808~. If the memory address MAD 1 is found protected, the memory addresses MAD 2 to 4 will be passed ~orward by one each (809) to have the message memory MDATA x addressed by the memory address MAD
PF!OTECTION MEANS
BACKGROUND OF THE INVENTION
The present invention relates to a radio paging receiver for use in radio paging.
Owing to the remarkable progress of circuit integration technology in recent years, more compact radio paging receivers of a greater multiplicity of unctions and of smaller power consumption come to be developed. One aspect of this increase in functional multiplicity is the recent addition of message signals to the previous service of send-ing the selective calling or paging signal (a specificnumber assigned to each subscriber) alone. Furthermore, to cope with the expansion of the demand spectrum and to increase the reliability of communication, these paging and message signals are now digitized.
Meanwhile, the display of a message signal is achived, after the receipt of said paging signal, upon actuation of the function to indicate the receipt of the message signal.
There are provided within a receiver a plurality of message signal memory circuits, because the subscriber may be paged very frequently or may not promptly respond to every message signal received. The message signals stored in these memory circuits can be read out by a variety of methods. For instance, where there are n memory circuits, n read-out ''~
38~3 i switches may be provided to enable the subscriber to operate in one action the switch corresponding to the particular memory circuit in which the desired message signal is storea. ~lternatively, there may be one read-out switch, which the subscriber will have to operate n times at the maximum to have the desired message signal read out. A
radio paging receiver having one of such ~unctions, which indicates the receipt of and stores every message signal received, is very convenient because it allows a long enough time for its bearer to take a plurality of actions.
However, the number of memory circuits is limited by elements ar software and, accordingly, if more message signals than the memory circuits are received, the early signal or signals will have to be erased in the order of arrival. Thus, even if one of the plurality of memorized signals contains important information and has to be kept for a long period, it may have to be indiscriminately erased upon arrival of an extra message or messages. Normally, most of the message signals received can be promptly responded to and therefore erased soon, and keeping obsolete messages would unnecessarily complicate the subsequent procedures.
~ith the aforementioned setup which requires the read-out switch to be operated as many times as the desired memory circuit calls for, for instance, there would be a correspond-ing increase in the required number of switching actions or,switches would have to be correspondingly greater.
Moreover, a greater number of memory circuits means a ~6~8 correspondingly higher cost..
SUMMARY OF THE INVENTION
An ob]ect of the present invention therefore is to provide an economical radio paging receiver which is free from the above stated disadvantages of conventional such receivers, and of which the switch operation is simplified and the number of memory circuits is reduced by enabling only important messages to be stored as long as they are needed, regardless of the memory capacity, and unimportant messages to be sequentially erased as the memory circuits are overflown.
According to the invention, there is provided a raAio paging receiver comprising: means for receiving and demodulating a carrier wave modulated with paging and message signals to provide demodulated paging and message signals; means for detecting, out of said demodulated paging signals, the paging signal assigned to said radio paging ; receiver to provide a detection signal; means responsive to said detectlon signal for generating an alert signal; first memory means for storing a plurality of said demodulated message signals; second memory means for preventing from erasure and storing at least--one of the message signals stored in said first memory means; display means for displaying at least one of the message signals stored in said first and sscond memory means; and display control means connected to said first and second memory means and said display means for selectively providing said display means with at least one of the message signals stored in said first and second memory means.
BRIEF DESCRIPTION OF T~E D~AWINGS
Other objects, features and advantages of the present invention will be more apparent from the detailed description hereunder takPn in conjunction with the accompanying drawings, wherein:
FIG. 1 iS a schematic block diagram of the radio paging receiver according to the present invention;
FIG. 2 shows the format of the calling signal to be received by the receiver according to the pxesent invention;
FIG. 3 is a more detailed block diagram of the decoder of the receiver illustrated in FIG. l;
FIG. 4 is a time chart for describing the signal receiving operation of the decoder illustrated in FIG. 3;
FIG. 5 is a time chart for describing the message information reading and message information protecting operation of the decoder illustrated in FIG. 3;
FIG. 6 is a block diagram illustrating a modification of the memory protector section of the decoder illustrated in FIG. 3;
FIG. 7 is a time chart for describing the operation of the memory protector section illustrated in FIG. 6;
FIG. 8 is a functional block diagram illustrating another embodiment of the decoder of the receiver illustrated in FIG. l;
FIG. 9, appearing on the same sheet as FIG. 7, is a block diagram conceptually illustrating a part of the data memory in the de-coder illustrated in FIG. 8; and FIGS. 10 and 11 are flow charts respectively showing the calling signal receiving and memory protecting operation of the de-coder illustrated in FIG. 8.
DESCRIPTION OF T~IE PREFERRED EMBODIMENTS
Referring to FIG. 1, a radio carrier wave received by an antenna 1, after being respectively amplified and frequency-converted by a radio frequency-intermediate frequency (RF-IF) circuit 2, is demodulated by a discriminator 3. The demodulated signal is sub-jected to decision by a decoder 4 as to whether or not it is the selective calling or paging signal assigned to the receiver and, if it is, an output pulse is given to a speaker driver circuit 7 to let the bearer of the receiver know, by so1mding a loud-speaker 8, that the paging signal has been received. At the same time, ensuing mess-age information is stored in a memory in the decoder 4. If, at this time, a memory read-out switch 10 is closed, one out of the messages then stored is supplied by way of a display driver circuit 5 to a dis-play device ~.
While messages stored in the memory within the decoder 4 are erased in the order of their entry as the memory is overflown, a specific message can be protected Erom erasure by operating a memory protect switch 11 or the switch 10, as ., "
....
I
will be described in urther detail hereunder. The message thereby protected will never be erased unless a power swi~ch 12 is turned off or another message is protected by again operating the switche 10 or 11. A display selector switch 3 5 9 permits selection between the displaying of only stored messages or the displaying of the protected message.
Referring now to FIG. 2, section X shows a selective calling signal assigned to each receiver, consisting for example of BCH (31, 21) codes which are a kind of cyclic 10 code, while section Y shows a message signal for conveying message information, consisting, like the selective calling signal, of BCH (31, 21) codes.
With reference to FIG. 3, the decoder 4 comprises delay type (D-type) flipflops 401 to 405, shift registers 406 to 412, a clock pulse generator 413, timers 414 and 415, inverters 416 to 423, AND gates 424 to 437, OR gates 438 to 443, a counter 444 and xesistors 445 to 448. To distinguish the shift registers 409 to 412 from other shift registers, the shift register 409 shall be hereinafter called MR-1; 410, MR-2; 411, MR-n and 412, MR-p.
Next, the operation o the decoder illustrated in FIG. 3 will be described in detail with reference to FIGS. 4 and 5. The D-type flipflop 401 synchronizes the calling signal, demodulated by the discriminator 3 (FIG. 1), with the inverted output (FIG. 4(B)) of the inverter 416 deriving from the output of the clock generator 413, and supplies the synchronized signal to the shift register 406. As a result, 3~
if the demodulated signal is found identical with a pattern (the selective calling~signal) predetermined by the inverters 417, 418 and 419, an identity signal ~FIG. 4(C)) will be generated rom the AND gate 424 and supplied to the speaker driver circuit 7. At the samé time, the flipflop 402 is inverted to drive the timer 414 which has a period of time T1 required for writinginto the register 408 the incoming message immediàtelv following the selective calling signal via the AND gates 425 and 426 To the other input of the AND gate 426 is supplied the clock pulse from the clock pulse generator 413.
After the message is completely stored in the shift register 408, the content of MR-n-1 is written into the shift register 411 (MR-n) in response to the output of the shift register 407 which is in response to a res~t sitnal ~FIG.
4(E)) from the timer 414. Similarly, the content of -the shift register 409 (MR-1) is written into the shift register 410 (MR-2) and so on until the message stored in the shift register 408 is written into the shift register 409 (MR-1) (See FIGS. 4~E), 4(F), 4(G) and 4(H)). Thus, a maximum of n received messages can be stored, and if more than n are received~ earlier messages will be erased in the order of their arrival.
Next will be described how the bearer of the receiver can read out-.one of the stored messages. The display selector switch 9 being turned to the N side, he can press the memory read-out switch 10, and then a signal I will drive i38~
the tlmer 415 through the inverter 421 and the flipflop 403 t~
allocate a predetermined display duration T2 (of, say, 8 seconds). During T2, a signal J shown in FIG. 5(J) is fed to the display driver circuit 5 to display a message on the display device 6 (which may be, for instance, a liquid crystal device).
If the memory read-out switch 10 is pressed only once, the counter 444 will be actuated via the inverter 421 to start counting and, a signal K being supplied from its Q1 terminal, the AND gates 427 to 428 will be opened. As a result, the content of the shift register 409 (MR-1) is displayed on the display device 6 by way of the OR gates 438 to 439, the AND gates 433 to 434, and the OR gates 440 to 441. Since the display selector switch 9 is turned to the N side, the inverter 422 provides a high level signal to open the AND gates 433 to 434. If, during the display duration T2, the memory read-out switch 10 is pressed once again, the counter 444 will count 2, an output L will emerge at a terminal Q2, and the AND gates 429 to 430 will be opened to display the content of MR-2. As the timer 415 is reset through the OR gate 443, the duration T2 will be renewed (FIG. 5(J)). Here, the outputs of the D-type flipflop 403 and the inverter 421 are supplied by way of the OR gate 442 to the display driver circuit 5 so that the display driver circuit 5 be kept active even while the memory read-out switch 10 continues to be pressed again and again.
3~3 Similarly, if the memory read-out switch 10 is pressed n times, the AND gates 431 to 432 will be opened to display the content of MR-n. If the memory read-out switch 10 is pr~essed n~1 times, the counter 444 will re~urn to count 1 to display thë content of MR-1. Thus, as the memory read-out switch 10 is pressed n times, the messages stored in the shift registers MR-1 to MR-n will be read out in due se~uence.
When the display duration T2 is over, the display driver circuit 5 is stopped and the counter 444 is reset by a reset signal from the timer 415. Th~refore, next time the memory read-out switch 10 is pressed, the display will again start from MR-1.
Now will be described the procedure by which a specific message is protected from erasure. First the message to be protected is displayed on the display device 6 by the same method as the above described process for simply reading any message, and the memory protect switch 11 is pressed. By that time, the message to be protected will have already been supplied from the OR gates 438 through 439 to the input of the message-protection shift register 412 (MR-p). Upon presslng of the memory protect switch 11, a write-in pulse is generated by the inverter 420 and D-type flipflops 404 and 405, and is supplied to the shift register 412 (MR-p) by way ,... . .
of the AND gate 437. In this way, the message being 2S displayed is stored in the shift register 412 ~MR-p) for protection from erasure.
;
;38~
If the display selector switch 9 is turned to the P
side, the AND gates 435 to 436 are opened with the output of the inverter 4~3, so that the message stored in the shift register 412 (MR-p) is supplied to the display driver circuit 5 through the OR gates 440 to 441. Then, as the memory read-out switch 10 is pressed, the message from the shift register MR-p is displayed on the display device 6.
During this procedure, the messages stored in the shift registers MR-1 to MR-n are prevented from going to the display driver circuit 5 by the closure of the AND gates 433 to 434, to which the output o~ the inverter 422 is fed~
When nothing or the content of MR-p is displayed on the display device 6, the memory protection mechanism is prohibited from functioning even if the memory protect 15 switch 11 is pressed. This is done by the AND gate 437.
The resistors 445 to 448 are pull-up resistors for securing a high level when the inputs to the inverters 420 to 423 are open. As mentioned above, with storing in the shi~t register MR-p, the message stored in MR-p can remain there indefinitely and can be displayed as required unless another message is shifted to the MR-p or the power supply is cut off.
Although the embodiment illustrated in FIGS. 1 and 3 has three switches, i.e., the memory read-out switch 10, the memory protect switch 11 and the display selector switch 9, if it is so rearranged as to enable the protected message to be read out, for instance, by pressing the memory read-out 638~
switch 10 n+1 times, the display selector switch 9 can be dispensed with. ~f, further, a timer is appropriately used, the memory protect switch 11 too can be dispensed with.
A version with such a timer will be described next.
In the circuit shown in FIG. 6, a timer ~49 is provided to dispense with the switch 11. The functioning of this circuit`will be described with reference to FIG. 7. When the memory read-out switch 10 is pressed, the timer 449 starts counting. When the switch 10 has been kept pressed longer than T3 (for instance, between tl and t2 in FIG. 7(I)), the timer 449 provides a high level signal. In response to this high level signal, the D-type flipflops 404 and 405 generate a write-in pulse O (FIG. 7(0)) to write into the shift register 412 (MR-p) the message being displayed on the display device 6. Thus, the displayed message is protected by keeping the memory read-out switch 10 pressed for a longer duration than the period T3 times by the timer 449. If it is further so arranged that the loudspeaker 8 (FIG. 1) be driven to emit a short sound upon generation of the write-in pulse O, greater convenience can be achieved because the bearer of the receiver will thereby confirm that the desired message is duly protected.
Referrlng now to FIG. 8, a decoder 4I having an LCD
controller/driver can use a single-chip control proces~sing unit (CPU), such as the microprocessor ,uPD7502 manufactured and mark~ted by the assignee of the present application, Nippon Electric Co., Ltd. A controller 501 decode command ti 38~
codes to be executed and controls the other blocks to execute the decoded command. In a program memory 502 are stored a group of commands to be executedu A program counter 503 is intended for addressing a program written - 5 into the program memory 502. A data memory 504 is provided for temporary storage of messages and the like. Clock pulses required by the decoder 4' are generated by a counter 505 receiving exterior clocks.
An arithmetic and logic unit (ALU) 506 executes arithmetic calculations, result of which is stored in an accumulator 513. The accumulator is also used for data exchange among the memory, input/output ports and registers.
An input port 507 is intended for receiving rectangular signals from the discriminator 3 and a read-out signal from the memory read-out switch 10. An output port 508 supplies an address signal for reading out the content of a programmable read-only memory (P-ROM) 513, in which is stored the selective calling signal assigned to the receiver. The signal read out of the P-FOM 513 is brought into the decoder 4' through another input port 509. An alert tone signal is supplied to the speaker driver circuit 7 by way of an output port 510. An LCD controller/driver 511, in response to the supply af data to be displayed from the data memory 504, displays the data on the LCD 6.
Referring now to-FIG. 9, a part of the data memory 504 includes four message memories MDATA 1 to MDATA 4, memory addresses MAD 1 to MAD 4 for designating one or another of 1~36388 , ~
the message memoxies, a protect 1ag PF and a read counter RC. If the content of the memory address MAD 1 is, for instance, "1", the messary memory MDATA 1 is addressed.
For a detailed description of the CPU shown in FIG. 8, reference is made to the User's Manual of the ~PD7502, published by Nippon Electric Co., Ltd., May 23, 1980.
Next will be described the calling signal receiving operation and the memory protecting operation of the decoder 4' with reference to the flow charts of FIGS. 10 and 1 1 .
In the following description, the step numbers in the flow charts are mentioned parenthesized after the respectively corresponding phrases, clauses or sentences. First, _ referring to FIG. 10, when the power supply is turned on (801), the content of each memory is initially set (802).
Into the memory address MAD 1 is entered "4"; into MAD 2, "3"; into MAD 3, "2", and into MAD 4, "1~'', and the message memories MDATA 1 to 4, the protect flag PF and the read counter RC are all cleared.
After the selective calling signal is received (803), the message is received (804) and simultaneously the alert tone sounding and the display start (805). Then whether or not the memory address MAD 1 is protected is checked (806) and, if it is not, the memory addresses MAD 1 to 4 will be passed forward by one each (80i) to have the message memory MDATA x ~x = 1, 2, 3 or 4) addressed by the memory address MAD 1 store the received message (808~. If the memory address MAD 1 is found protected, the memory addresses MAD 2 to 4 will be passed ~orward by one each (809) to have the message memory MDATA x addressed by the memory address MAD
2 store the received message and to keep the memory address MAD 1 protected ~810). The alert tone and the dlsplay will be automatically discontinued (812) after the timer (T2) - finishes its action.
Meanwhile, with reference to FIG. 11, when the receiver is in a wiating mode (901), whether or not the memory read-out switch 10 (FIG. 1) has been pressed is constantly checked (902) and, if it is found pressed, either the memory protecting operation or the reading operation will be started. Fist, the-.read counter RC is set at "1" (903); the count of the RC is supplied into the x register (904), and the content of the message memory MDATA y (y = 1, 2, 3 or 4) addressed by the memory address MAD x is displayed (904).
At the same time, the display timer and the protection timer are started (905 and 906, respectively) and, after that, whether or not the read-out switch 10 is released is checked (907).
If the read-out switch is kept pressed until the time (T3) of the protection timer lapses (gO8), the memory protecting action will then start to have the message memory MDATA x addressed by the memory address MAD 1 store the data currently displayed and to shift the three other stored 25 messages by one each (909). Thus, if the`message at the memory address MAD 3 is protected, the address of this MAD 3 will be shifted into the memory address MAD 1, followed by ~63~
the shifts of the content of the memory address MAD 1 to the memory address MAD 2 and that of the memory address MAD 2 to the memory address MAD 3. Then, the pxotect flag PF is set in the memory address MAD 1 (910), and the displayed message is turned on and off (911) to indicate that the displayed message is protected. Upon release of the read-out switch 10, the display is erased, and the receiver will return to its initial waiting mode (912 and 917, respectively).
If the read-out switch 10 is released within the period of time T3 prescribed by the protection timer (907), there will be the routine reading operation: either the display will be continued until the time of the display timer lapses (913) or, if the read-out switch is pressed again (914), the read counter RC will be counted up by 1 (915) and the contents of the message memories can be suc¢essively read out until the read counter counts beyond. 4 (916). In this arrangement, no special memory is provided for the protective purpose, but a memory addressed by the memory address MAD 1 is used sometimes as an ordinary memory or at other times as a protection memory. In this instance, unlike in the foregoing case where the messages themselves are shifted, only the addresses (MAD 1 to 4) are shifted, and the memory addressed by MAD 1 is either the latest memory or the protected memory.
AS is evident from the foregoing description, the present invention enables a radio paging receiver to store important messages withaut fail and to read them out at any 38~3 time as re~uired. The present invention, therefare, can greatly contribute to the reliability and economy of the receiv~r.
Meanwhile, with reference to FIG. 11, when the receiver is in a wiating mode (901), whether or not the memory read-out switch 10 (FIG. 1) has been pressed is constantly checked (902) and, if it is found pressed, either the memory protecting operation or the reading operation will be started. Fist, the-.read counter RC is set at "1" (903); the count of the RC is supplied into the x register (904), and the content of the message memory MDATA y (y = 1, 2, 3 or 4) addressed by the memory address MAD x is displayed (904).
At the same time, the display timer and the protection timer are started (905 and 906, respectively) and, after that, whether or not the read-out switch 10 is released is checked (907).
If the read-out switch is kept pressed until the time (T3) of the protection timer lapses (gO8), the memory protecting action will then start to have the message memory MDATA x addressed by the memory address MAD 1 store the data currently displayed and to shift the three other stored 25 messages by one each (909). Thus, if the`message at the memory address MAD 3 is protected, the address of this MAD 3 will be shifted into the memory address MAD 1, followed by ~63~
the shifts of the content of the memory address MAD 1 to the memory address MAD 2 and that of the memory address MAD 2 to the memory address MAD 3. Then, the pxotect flag PF is set in the memory address MAD 1 (910), and the displayed message is turned on and off (911) to indicate that the displayed message is protected. Upon release of the read-out switch 10, the display is erased, and the receiver will return to its initial waiting mode (912 and 917, respectively).
If the read-out switch 10 is released within the period of time T3 prescribed by the protection timer (907), there will be the routine reading operation: either the display will be continued until the time of the display timer lapses (913) or, if the read-out switch is pressed again (914), the read counter RC will be counted up by 1 (915) and the contents of the message memories can be suc¢essively read out until the read counter counts beyond. 4 (916). In this arrangement, no special memory is provided for the protective purpose, but a memory addressed by the memory address MAD 1 is used sometimes as an ordinary memory or at other times as a protection memory. In this instance, unlike in the foregoing case where the messages themselves are shifted, only the addresses (MAD 1 to 4) are shifted, and the memory addressed by MAD 1 is either the latest memory or the protected memory.
AS is evident from the foregoing description, the present invention enables a radio paging receiver to store important messages withaut fail and to read them out at any 38~3 time as re~uired. The present invention, therefare, can greatly contribute to the reliability and economy of the receiv~r.
Claims (4)
1. A radio paging receiver comprising:
means for receiving and demodulating a carrier wave modulated with paging and message signals to provide demodulated paging and message signals;
means for detecting, out of said demodulated paging signals, the paging signal assigned to said radio paging receiver to provide a detection signal;
means responsive to said detection signal for generating an alert signal;
first memory means for storing a plurality of said demodulated message signals;
second memory means for preventing from erasure and storing at least one of the message signals stored in said first memory means;
display means for displaying at least one of the message signals stored in said first and second memory means; and display control means connected to said first and second memory means and said display means for selectively providing said display means with at least one of the message signals stored in said first and second memory means.
means for receiving and demodulating a carrier wave modulated with paging and message signals to provide demodulated paging and message signals;
means for detecting, out of said demodulated paging signals, the paging signal assigned to said radio paging receiver to provide a detection signal;
means responsive to said detection signal for generating an alert signal;
first memory means for storing a plurality of said demodulated message signals;
second memory means for preventing from erasure and storing at least one of the message signals stored in said first memory means;
display means for displaying at least one of the message signals stored in said first and second memory means; and display control means connected to said first and second memory means and said display means for selectively providing said display means with at least one of the message signals stored in said first and second memory means.
2. A radio paging receiver, as claimed in Claim 1, wherein said display control means comprises:
first switching means for generating a first read-out signal;
timer means responsive to said read-out signal for generating a timer signal for a predetermined duration;
second switching means for generating a write-in signal;
memory circuit means responsive to said read-out or timer signal and said write-in signal for storing at least one of the contents stored in said first memory means;
third switching means for generating a second read-out signal;
means responsive to said first read-out signal for providing said display means with at least one of the message signals stored in said first memory means; and means responsive to said first and second read-out signal for providing said display means with said message signal stored said second memory means.
first switching means for generating a first read-out signal;
timer means responsive to said read-out signal for generating a timer signal for a predetermined duration;
second switching means for generating a write-in signal;
memory circuit means responsive to said read-out or timer signal and said write-in signal for storing at least one of the contents stored in said first memory means;
third switching means for generating a second read-out signal;
means responsive to said first read-out signal for providing said display means with at least one of the message signals stored in said first memory means; and means responsive to said first and second read-out signal for providing said display means with said message signal stored said second memory means.
3. A radio paging receiver, as claimed in Claim 1, wherein said display control means comprises:
first switching means for generating first and second read-out signals;
first timer means responsive to said first read-out signal for generating a first timer signal for a first predetermined duration;
second timer means responsive to said first reas-out signal for generating a second timer signal for a second predetermined duration;
memory circuit means responsive to said first read-out or first timer signal and said second timer signal for storing at least one of the contents stored in said first memory means;
means responsive to said first read-out signal for providing said display means with at least one of the message signals stored in said first memory means;and means responsive to said second read-out signal for providing said display means with said message signal stored in said second memory means.
first switching means for generating first and second read-out signals;
first timer means responsive to said first read-out signal for generating a first timer signal for a first predetermined duration;
second timer means responsive to said first reas-out signal for generating a second timer signal for a second predetermined duration;
memory circuit means responsive to said first read-out or first timer signal and said second timer signal for storing at least one of the contents stored in said first memory means;
means responsive to said first read-out signal for providing said display means with at least one of the message signals stored in said first memory means;and means responsive to said second read-out signal for providing said display means with said message signal stored in said second memory means.
4. A radio paging receiver, as claimed in Claim 1, wherein said detecting means, first and second memory means and display control means are formed in a single-chip micro-processor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57013343A JPS58131831A (en) | 1982-02-01 | 1982-02-01 | Radio selection and calling receiver |
| JP13343/1982 | 1982-02-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1196388A true CA1196388A (en) | 1985-11-05 |
Family
ID=11830465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000420608A Expired CA1196388A (en) | 1982-02-01 | 1983-01-31 | Radio paging receiver having stored message protection means |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US4477808A (en) |
| JP (1) | JPS58131831A (en) |
| KR (1) | KR860001456B1 (en) |
| AU (1) | AU550302B2 (en) |
| CA (1) | CA1196388A (en) |
| GB (1) | GB2116340B (en) |
| HK (1) | HK37289A (en) |
| SG (1) | SG50488G (en) |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2149164B (en) * | 1983-09-30 | 1987-06-17 | Nec Corp | Pager receiver |
| EP0136677B1 (en) * | 1983-09-30 | 1990-08-16 | Nec Corporation | Multifunctional pager receiver capable of reducing the number of manual switches |
| JPS6074736A (en) * | 1983-09-30 | 1985-04-27 | Nec Corp | Radio selective calling receiver with display function |
| JPS60191531A (en) * | 1984-03-13 | 1985-09-30 | Nec Corp | Radio selective call receiver with display function |
| AU578995B2 (en) * | 1984-12-05 | 1988-11-10 | Seiko Corporation | Watch pager system and communication protocol |
| JPS61177035A (en) * | 1985-01-31 | 1986-08-08 | Nippon Telegr & Teleph Corp <Ntt> | Silent mode setting system |
| JPS61198931A (en) * | 1985-02-28 | 1986-09-03 | Nec Corp | Radio selective call receiver with display function |
| JPH0648798B2 (en) * | 1986-09-26 | 1994-06-22 | 松下電器産業株式会社 | Selective call receiver |
| US4851829A (en) * | 1986-12-04 | 1989-07-25 | Motorola, Inc. | Paging receiver with alert indicating status of memory |
| US4949085A (en) * | 1987-06-30 | 1990-08-14 | Motorola, Inc. | Prioritization of stored messages in a digital voice paging receiver |
| JPS647448U (en) * | 1987-07-03 | 1989-01-17 | ||
| JPH0533084Y2 (en) * | 1987-07-03 | 1993-08-24 | ||
| JP2629715B2 (en) * | 1987-07-16 | 1997-07-16 | カシオ計算機株式会社 | Message receiver |
| JP2700809B2 (en) * | 1988-02-15 | 1998-01-21 | チャイニーズ コンピュータズ リミテッド | Display device |
| GB2219422B (en) * | 1988-06-02 | 1991-12-18 | Multitone Electronics Plc | Pager display control |
| KR930002752B1 (en) * | 1988-09-29 | 1993-04-09 | 삼성전자 주식회사 | Method for display messages of paging receiver |
| JPH0352338A (en) * | 1989-07-19 | 1991-03-06 | Toshiba Corp | Selective call receiver |
| WO1991002434A1 (en) * | 1989-08-09 | 1991-02-21 | Motorola, Inc. | Automatic message protection for selected addresses in a selective call receiver |
| US5177477A (en) * | 1989-08-14 | 1993-01-05 | Motorola, Inc. | Selective call receiver having a file for retaining multiple messages |
| SG43192A1 (en) * | 1990-11-30 | 1997-10-17 | Nec Corp | Data display radio pager |
| DE69434932T2 (en) | 1993-06-15 | 2007-11-08 | British Technology Group Inter-Corporate Licensing Ltd. | TELECOMMUNICATIONS SYSTEM |
| DE4496561T1 (en) * | 1993-08-31 | 1995-09-21 | Ericsson Ge Mobile Communicat | Device for storing messages in a cellular mobile terminal |
| JP2806494B2 (en) * | 1994-04-20 | 1998-09-30 | カシオ計算機株式会社 | Message receiving device |
| US5805095A (en) * | 1997-01-10 | 1998-09-08 | Motorola, Inc. | Two's complement digital to analog converter |
| KR100251679B1 (en) * | 1997-06-25 | 2000-04-15 | 윤종용 | Method for holding in common memory in digital wireless telephone comprising radio pager |
| US6125287A (en) * | 1997-09-05 | 2000-09-26 | Fujitsu Limited | Wireless telephone having an improved user interface |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5383436A (en) * | 1976-12-28 | 1978-07-22 | Fuji Electric Co Ltd | Memory protector |
| JPS584289Y2 (en) * | 1978-04-18 | 1983-01-25 | 日本電気株式会社 | Radio selective calling receiver with display device |
| US4336524A (en) * | 1979-07-17 | 1982-06-22 | Levine Alfred B | Video display pager receiver with memory |
| JPS5652944A (en) * | 1979-10-06 | 1981-05-12 | Nec Corp | Selective inter-call receiver |
| US4383257A (en) * | 1979-12-26 | 1983-05-10 | Millicom Incorporated | Message communication system with message storage |
| US4385295A (en) * | 1981-09-29 | 1983-05-24 | Motorola, Inc. | Pager with visible display indicating unread messages |
-
1982
- 1982-02-01 JP JP57013343A patent/JPS58131831A/en active Granted
-
1983
- 1983-01-31 CA CA000420608A patent/CA1196388A/en not_active Expired
- 1983-02-01 KR KR1019830000377A patent/KR860001456B1/en not_active IP Right Cessation
- 1983-02-01 AU AU10884/83A patent/AU550302B2/en not_active Expired
- 1983-02-01 US US06/462,867 patent/US4477808A/en not_active Expired - Lifetime
- 1983-02-01 GB GB08302718A patent/GB2116340B/en not_active Expired
-
1988
- 1988-07-23 SG SG50488A patent/SG50488G/en unknown
-
1989
- 1989-05-04 HK HK372/89A patent/HK37289A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US4477808A (en) | 1984-10-16 |
| JPS58131831A (en) | 1983-08-05 |
| HK37289A (en) | 1989-05-12 |
| JPH023340B2 (en) | 1990-01-23 |
| KR860001456B1 (en) | 1986-09-25 |
| KR840003942A (en) | 1984-10-04 |
| SG50488G (en) | 1989-04-14 |
| GB2116340B (en) | 1985-09-04 |
| GB2116340A (en) | 1983-09-21 |
| GB8302718D0 (en) | 1983-03-02 |
| AU550302B2 (en) | 1986-03-13 |
| AU1088483A (en) | 1983-08-11 |
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Effective date: 20030131 |