CA1198223A - Method and apparatus for enhancing the operation of a data processing system - Google Patents

Abstract

ABSTRACT

A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability.
The system includes a processor having dual ALC and microcode processors, and an instruction processor. Also included are a processor incorporating a multifunction processor memory, a malfunction nibble shifter, and a high speed look-aside memory control.

Description

DIGITAL D~TA PROCESSING SYSTEM/420 Cross Reference ~o Related Applica~ions The present application is relat~d, in partO ~o copen~ing Canadian Patent Appli.cations Serial ~u~ers 43977~5O
439~798D ~39,799, 439,~no, 43g~B01, ~3~,8~2 ~n~ ~3g~03 all filed Oetober 26~ 1983~
1~ Field of the Invention The present invention relates to a high spee~, compact data processing system an~7 more particularly, to clrcuitry .therein to enhance operating speed, efficiency and capabilities of such a system.

2. Description of Priox ~rt A common p~actice in the computer i~dustry i-~for a manufacturer to ~rovide a family of related computer~
or data processing, systemsO Various compu~ers in such a family ~ill be distinguished by 5ize9 complexity7 capability and cost. Because of cost and, therefore, complexity cons raints, lower level systems in such a family are usually not able to pro.vide the capabilities and functio~s of the higher level systems. A lower level system may not~ for example, provide as high a sp~ed o operation or as large a memory space as a higher level system~ In addition~ a lower level system often may not be able to execute a program w.ritten for a higher level system because the lower level system does not orfer the full functions and capabilities of the higher level system. Such a ~amily of systems may therefore have upward compatibility, that is, programs written on lower level systems may be executed on higher level systems, but will not provide corresponding downward compatibility. For full compatibility ~ithin 2 computer system family, the lower level systems sht)uld offer, in general, the functionality and capabilities of the higher leTJel systemsO
The present lnvention provides computer system improvements which bear upon the a~ove noted computer syste~ capabilities, thus improving computer system speed, efficiency and capability, and also providing a .olution for the aforementioned problem~ and limitations of the prior art, as will be discussed in detail herein bçlowO
SUMMARY OF THE INVENTION
The present invention relates to computer system elements providing increased capability and efficiency~
The present i-nvention includes a system havin~ separate kernel, vertical and horizontal microcode, separate ~2--32~3 loading of vertical microcode and 2 permzne~tly resident kernel m;crocode, and a soft console with dual levels o~
capabilityO The pres.nt invention includes a processor having dual ALC and microcode processo}sr an~ 2n instruction processorO Also included 15 a processor incorporating a multifunction processor memory, a multifunction nibble shifter, ~nd a nigh speed look-aside memory control.
It is thus advantzgeous to incorporate the pre~ent invention into a computer system because capabllity a~d efficiency is increased.
It is thus an object of the present in~en~ion .o provide an improved computer system.
It is another object of the present invention to provide an improved com~uter System pro~idiin~ increased speed and efficiency o~ operation~
It i.s yet another object o the present nvention to provide an improved computer system providing increased capability and functionality.

In accordance with the present invention there is provided in a data processing system including processor means for pxocessing the data, memory means for storing the data and instruction for directing operations of the system, bus means for conducting the data and instruction between the memory means and the processor means, external terminal means for providing command for directing the operation of the system, external memory m~ans, and I~O means connected between the terminal means, the external memory means and the bu9 means for conducting the commands and data between the terminal means, the external memory means and the bus means, microcode control means for pro~idin~ sequences of microinstruction for controlling the operation of the system, comprising: kernel microcode memory means responsive to first certain of the instruction and co~mands permanently for storing and providing to the system corresponding first certain of the microinstruction sequences for controlling first certain of the operations J writable microcode memory means responsive to second certain of the instruction ~nd ~ommanas ~0 for storing and providing to the system corresponding second cer~ain of microinstruction sequences for controlling secon~
certain of the operation, and the external memory means for stor.tng an initial copy of the second certain of the microinstruction sequences, the first certain of the microinstruction sequences including microinstruction sequences for (a) controlling the system to read a secon~ copy of the second certain of the microinstruction sequences from the external memory means to memory means, and (b) to read the - 3a -cr/~.

~8~
second copy of the second certain o the microinstruction sequences from the mernory means to the writable microcode memory means~
In accordance with a second aspect there is provided a method of enhancing the operation of a data processing systemr the data processing system includi~g:
memory means for storing the data and for storing instructions for directing operations of the system; external memory means;
and microcode control means for providing sequences of microinstructions for controlling the operation of the system, comprising: kernel microcode memory means responsive to first certain of the instructions and comman~s for storing and providing to the system corresponding first certain of the microinstruction sequences for controlling first certain of the operations; and writable microcode memory means responsive to second certain of the instructions and commands for storing and providing to the system corresponding second certain of microinstruction sequences for controlling second certain of the operations, and the method comprising the steps of:
initially loading the writable microcode memory means with initial versions of the second certain microinstruction sequences from the external memory means; in response to the first certain microinstruction sequences, loading the writable microcode memory means with alternate versions of the second certain microinstruction sequences from the external memory means.
Other objects and advantages of the present invention will :be understood by those of ordi.nary skill in the art, ater referring to the ollowing detailed - 3b -cr/J~

;
'23 description of a preferred embodiment and drawings wherein:
BRXEF DESCRIPTION OF DRAWINGS
FigO 1 is a block diasram of a computer sys~em incorporating the present inYention, Fig~ 2 is an illustration of certain, typical instructions;
Fig. 3 is a diagrammic representation of a single level address translation;
Fig. 4 is a diagrammic representation of a two le~el address translation;
Figs. 5 and 5A are a detailed block diagram of the present system control unit;
Figs. 6 and 6A are a detailed block diagrz~ of the present system processor unit, and Fig 7 is a-detailed block diagram of a portion of a memory control unit.

~ESC~IPTION OF THE PBEFERRE~ EM~ODIME~T

The foliowing description presents the structure and operation o a computer system incorporating a presently preferred embodirnent of the present invention.
In the followi.ng description, the general structure! and operation of the present system will first be described in an introductory overview. Next, certain basic featllres of the present system will be further described as a further introduction to following detailed cescriptions of the system. The system will then be described in detail, followed by yet further detailed descriptions of certain features of the present system as necessary~
Certain conventions are used throughout the following descriptions to enhance clarity of presentation. First, each figure ele~ent referred to in the rollowing descriptions will be referred to by a three OL' four digit reference number- The most significant digit of a three digit reference number or most significant two digits of a four digit reference number identify the particular figure in which an element referred to by that reference number first appears. The two least significant digits of a particular r~ference number identify the particular element appearing in that figure~ For example, 2~

reference number 319 refers to the ninteenth element appearing in Figure 3 while reference number 1020 refers to the twentieth element appearing ln Figure 10. A
particular reference number assi~ned to a particular figure element is therefore always used to refer to that particular f gure element. Therefore, element 319, which first appears as element 19 in Figure 3, will thereafter be referred to by reference number 319 in all figures or descriptions.
Next, certain of the figures presented in conjunction with the following descriptions may occupy more than one drawing page. In such instances, a common figure number will be assigned to the drawing pages comprising that figure, and a letter designation will be a~pended to identify a particular drawing page of the figure. For example, figure 3 may occupy three drawing pages. The first page will be identified as Fig. 3, the second as Fig. 3A, and the third as Fig. 3B.
Finallyr interconnections between related circuitry or system elements may be represented in two ways.
First, lnterconnections between system elements may be represented by common signal names or references rather than by drawn representations of wires or buses~
Second, common connections between circuitry or system elements may be indicated by a ~racket terminating a lead and enclosing a designa~ion of the form l'A-b~o ~A"
indicates other figures having a connection to the same common point while "bn designates a particular connection point.

The following introductory overview will first identify and briefly describe the ma~or elements of the present digital computer system~ Cectain features of operation of the present system will then be described in further detail as an introduction to following detailed descriptions of the present system.

A. System o~ L~ L
Referring to fig~ 1, a block diagram of Computer System (CS) 101 is shown. Major elements of CS 101 are Memory (MEM) 102, Control Unit tCU) 104, and Processor Unit ~PU) 106. MEM 102 is used to store, for example, O ' ~ 2~
user programs comprising data and instruction3. ~E~ la2 ls descrIbed in detail in related copending Canadian Patent Application Serial No~ 441,2389 filed October 26, 1983 ~EM 102 wil~ not be described in further detail herein except as necessary for understanding of the structure and operation of the remaining elements of CS 101. CU 104 and PU 1O6D
which wili be described in detail in the following descriptionsJ
respectively perform system control and program execution fur.ctions.
Major buses of CS 101 include ~emory Address ~MADl Bus 108, which conducts memory read and write addr~sses from PU 106 and CU 104 to MEM 102. Memory Data (MDA~ Bus 110 conducts data and instructions from .~M 102 to CU 104 and PU 106. Data (D) Bus 112 is cvnnected between CU 104 and PU 106 as a primary path of information exchange bet~een CU 10~ and PU 106.
Referring to CU 104, major elements of CU 104 are Instruction Prefetch and Decoder IIPD) 114, Microsequencer ~US) 116, Memory Control IMC~ 118, and System Cloc~
Generator (SCG) 120. IPD 114 is connected from MDA Bus 110 to xeceive instructions from MEM 102.

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82~3 IPD 114 operates in conjunction with certain elements of PU 106 to perorm instruction prefetch operations, in addition, IPD 114 performs certain initial instruction decode operations~ for example, ~ith respect to instruction and data type7 to initially determine certain subsequent o~erations to be per~ormed by CU 104 and PU 106 with respect to execu.ion of received instructions. IPD 114 provides certain outputs to D Bus 11~, for example, information used by PU 106 in addressing and fetching data from MEM 102. IPD 114 also provides instruction outputs to US 116 for use by US 116 in controlling opexations of CS 101.
As will be described in detail in following descriptions, US 116 includes memory and logic for providiilg microinstruction control of CS 101. In addition to certain outputs described below to D Bus 112, US 116 provides control outputs to other elements o CS 101 and accepts control inputs from other elements of CS 101.
Finally, SCG 120 comprises a central clock generator which prcvides clock outputs to all elements of CS 101. For clarity of presentation, the clock _9_ .. ~ .

outputs of SCG 120 are not shown individually, but will be aescribed in the followlng detailed descriptions as appropriate.
Referring to PU 106, as described above PU 106 performs functions directly associated with execution o user's programs. In this respect, Central Processing Unit Processor (CPUP) 122 performs arithmetic and logic functions and i5 connected between D Bus 112 and Y Bus 124. Y BUS 124 is an information transfer path within PU 106. Nibble Shifter (NIBS) ].26, also connected between D Bus 112 and Y Bus 124r operates in conjunction with CPUP 122 and other elements of CS 101 to perform, for example, nibble shifting~ memory address and data alignment operations.
Scratch Pad and Address Translati~n Unit (SPAD) 128 is a multifunction element also connected between D Bus 112 and Y Bus 124~. SPAD 128 operates as a scratch pad memory for PU 106 and also performs certain address mapping operztions, as will be c3escribed in detail in the following descri.ptions.
Memory ~ddress Unit (MAD) d.30 is connected rrom SPAD 128 and has outputs connect:ed to MAD Bus 108 M~D

- ~LO~

130 prov des read and write addresses to MEM 102. In addition to other functions, MAD 130 operates in conjunction with IPD 114 to perform instruction prefe~ch operations~
Memory Data Buffer lMDB) 132 is connected between ~IDA Bus 110 and D Bus 112 and Y Bus 124 and i5 a primary path for data transfer between PU 106 and MEM 102~
Finally, Serial I/O (SIO) 134 and Data and Burst Multiplexer Channel I/O (DBI0) 136 operate as principal paths of information exchange between CS 101 and external devices, such as terminals and bulk memory storage units. SI0 134 is used for communication o~
serial information between CS101 a.nd, for example~ a terminal. DBIO 136 provides, for example, three modes of parallel inrormation trans~er, such as, Programmed I/0, Data C~annel I/0, and a Bursc Multiplexer Channel~
As indi.cated in ~ig. 1, SI0 134 has a bi-directional connection from D Bus 112 while DBI0 has an input path rrom D Bus 112 and an output path to Y Bus 124.
~ aving briefly described ~he overall structure and unctional elements of CS 101 with reference to Fig. 1, l, certain basic features of CS 101 will be described next below.
B~ InulJ~ Lc~
The present implementation of CS 101 is as a ~2 bit computer system; that is, CS 101 generates and manipulates 32 bit addresses and 32 bit data elements CS 101 is desisned to be com~atible with t~o earlier generations of data processing systems, that is, capable of executing programs created for use on the earlier data processing systems. One earlier family of data processing systems is a 16 bit system, for example, the Data General Corporation ECLIFSE~ computer systems. A
second earlier family of computer systems are 8 bit systems, for example, Data General Corporation NOVA~
computer systems. As such, CS 101 is capable of executing three different instruction sets, the NOV~
instruction set, the ECLIP~E instruction setr and a new instruction set, that for the Data General Corporation LECLIPSE MV/8000~ systems. Each of these instruction sets contain two classes of instructions: Arithmetic and Logic Class (ALC) instructions, which define an arithmetic or logic operation to be performed, and Z,~

memory reference instructions, which define operations to be performed with data to be written into or read from memory~ ALC instructions in general include only an operation code (opcode) field defining the operation ~o be performed In kmemory reference instructionsr a displacement field containing in crmation relating to the location, or address, of the data to be opera~ed upon is added to the opcode fieldO NOVA instructions use 8 bit opcode fields while ECLIPSE and MV,/8000 instructions use 16 bit opcode fields. ~OVA and ECLXPSE
instructions use r respectively, 8 and 16 bit displacement fields, while ~V/8000 instructions use 16 or 32 bit displacement fields. NOVA and ECLIPSE
ins~ructions are referred to as "narrow" inst:ructions and MV/8000 instruc~ions as "wider~ instructions.
CS 101's instruction set allows C5 101 to manipulate data elements having widths of 8, 16, or 32 bits~ In addition, and as will be described further below, CS 101 i5 capable of generating addresses ln two ranges. The first range, using 32 bit addresses, allows CS 101 to address a logical address space of 4~3 billion bytes, or four gigah~tes. The second, using 16 bit -addresses, allows CS 101 to utilize a 64 kilabyte addressing range7 During the following descriptions, a byte is defined as 8 bits of information, a word is de~in.ed as 16 ~its (2 bytes), and a double word is defined as 32 bits (2 words, or 4 bytes). In general, most operations performed by CS 101, for example, generation of addresses and man.ipulation of data, are performed in double word (32 bit) elements.

- C., ~
As described above, CS 101 may utilize 32 bit addresses for byte addressing, or 31 bits in word addressing,and thereby has a logical address space, that is, a user visible address space, of our gigabytes.
This logi.cal address space is partitioned or purposes of memory management into eight ~12 megabyte sections calied sesments and referred to as segments O to 7 r Each logical address containsr in the three most signi~icant bits, in~ormation identiying a particular segment in which a data item is locatedO The remainlng 29 bits identify the location of the data item in the segment.

The size of CS lOl's logical address space means that not all logical address locations can be represented in MEM 102 ~t the same time. For this reason, C5 lOl's logical address space is further divided into pages. Each page is a two kilobyte block o~ contlguous logical or physical addresses. A demand paging system moves pages between MEM 102 and external storage devices upon demand and tracks pages currently in MEM 102u An address translation unit, described in detail below, translates logical addresses into correspcnding physical addresses in MEM 102 for pages represented in MEM 102.
Logical addresses may use to reference two types of information, data and instructionsO To reference instructions, PU 106 uses logical addresses generated by a program counter (PC), located in PU 106, which is incremented to read sequential instructions from memory.
As described above, bits 1 to 3 o the PC specify a current segment from which instructions are being read, while bits 4 to 31 specify an address within that segment. It should be noted that logical addresses generated by the PC contain 31 bits of address rather than 32 as CS 101 performs addressinng on the word level~ As will be described further below, CS 101 actually reads or writes only double words to and from MEM 102, thus requiring 30 bits of address rather than 31 oz 32 bits.
In contrast to instructions, which are addressed directly, data is addressed indirectly through instructions. CS 101 utili~es information coded in the re~erencing instructions to construct the logical addresses of the data so referenced~ Among other factors, data appears in dif~erent types and lengths and the structure of the data effects the generation oS
logical addresses referencing data. The Data types may include, for exampler fixed point numbers, floating point numbersf decimal numbers, alphanumeric character strings, and bit strings. Data lengths may,for example, include bits~ bytes (8 bits), words (16 bits), and double words (32 bits). In addition, the locations of various data items may be specified as a displacement, or offset, relative to various base addresses, as will be described belowu 1 ~ ~
~ w~

To reference an element of information in logical memory, therefore, a referencing instruction will provide information used by CS 101 to construct a logical address of the referenced data item. Various typical instruction formats used in CS 101 and containing such information are illustrated in Fig. 2.
The instruction illustratecl on line A represents a narrow instruction of 8 bits, while the instructions illustrated on the remaining lines represent typical 16 and 32 bit instructions, as previously described. As shown in Fig. 2, each instruction includes an Operation, (O~) Code indicating an operation to be performed with the referenced data, and an Accumulator (AC) Field designating a source or destination accumulator as appropriate~
Each instruction includes a displacement field of 8, 15, 16, 31, or 32 bits, depending upon whether the instruction is referencing a byte or a word of data.
Each instruction further includes an index bit field (e) identi~ying the source of the base addxess from which the displacement (offset) specified in the displacement field i.s taken to determine the logical address. The index bits are capable of specifying four different addressing modes, that is, four different sources for a base address from which displacement is taken to locate the data referred to by the instruction displacement field. A first mode lis Absolute mode and uses logical address zero as base address~ A second mode is Program Count (PC~ relative wherein the present PC address is used as base address~ The remaining two modes select as base address the contents of either of two accumulator registers residing in PU 106. Both the instructions and the logical addresses resulting rrom the operation described above contain a single bit field which identifies whether the logical address i5 a final logical address, or whether indirect addressing has been specified. In indirect addressing, a logical address resulting from resolution of the instruction is treated as a pointer to yet another address~ The address pointed to may, in turn, be a final logical address or, as indicated by its indirect bit field, may be an indirect pointer to yet another logical address.
Pinally, as previously described the logical address space of CS 101 is larger than the physical .

i .

address space of MEM 102. As such, two Rbyte pages of information storage containing instructions or data, or both, are transferred between MEM 102 and external storage devices as required. As a result, logical addresses generated by CS :L01 must therefore be translated into equ~valent physical addresses in MEM 102 of pages residlng thereinO
CS 101 performs logical to physical address translation operations through the use of Page Tables (PTs~ and Segment Base Registers (SBRs)~ A PT is a table of entries containing inform2tion for translating logical addresses to a physical addresses. Each entry in a PT, referred to as a Page Table Entry (PTE), contains the necessary information relevant to one page of storage residiny in MEM 102. In cor.junction, there exists a SBR for each segment of CS 1011s logical address space. Each SBR contains the physica]. base address of a PT containing entries for those pages of the corresponding segment residing MEM 102. The contents of each SBR indicates whether the corresponding segment is c~rrently defined, tnat is, usuable by CS
101, the number of PT levels necessary for logical -19~

address translation, ~s will be des~ribed further below, and the address translation information~
Each PTE contains information indicating whether a particular page is currently de~ined, that is7 accessible to CS 101, and whether the correspondin~ page is presently residing in MEM 102. Each PTE also contains information regarding access rights to the information stored in the correspondiny page; that is, whether a reference to the corresponding page may perform a read operation, a write operation, or execute ins~ructions contained thereinO Each PTE also contains physical page address information defining the physical address or location in MEM 102 of the page corresponding to a particular logical address. The physical address contained in each PTE may reference either of two items, depending upon whether a one level PT translation is to be performed or a two level PT translation is to be performedO Xf a one level translation is to be performed, the PTE physical address contains the physcial address of the page referenced by the corresponding logical address~ If a two level translation is to be performed, the PTE address field -20~

contains the address of a second PT, which in turn contains the final physical address of the page referenced by the logical address9 The utilization of both one and two level PT translations allows CS lOl's address space to be tailored to a particular user program~ For a smaller program, a one level mechanism would be utili~ed, while for larger programs two level translations would be performed.
Reerring to Fig. 3, a diagramic representation of a one level page table translation is shown.
Represented therein is a logical address to be translated, one of CS lOl's SBRs, and a typical page table containing a plurality of PTEs As indicated in Fig. 3, the logical address includes an SBR Field identifying a particular one of CS
lOl's SBRs~ in this case the SBR represented in Fig. 3, a single level page table address field, and a page offset field. CS 101 utilizes the SBR field of the logical add.ess to select a corresponding one of CS
lOl's eight SBRs. CS 101 reads from that SBR a physical address field which identifies the start, or base address, of a corresponding page table, that is, the page table represented in Fig. 3. The single level page table address field of the ,logical address represents an offset~ from the start of the page table located by the physical address field of the SBR, to the particular PTE
containing the physical address information corresponding to the logical address to be translatedq Together, therefore~ the physical address field of the ~BR identified by the SBR field of the logical address and the single level page table field of the logical address identify the physical address of a corresponding P~E in the page table.
A PTE so identified incluaes, as indicated in Fig.'

3, a valid resident physica~l address field which identifies the physical starting address of a particular page residing in MEM 102. The page offset field of tne logical address specifies an offset, relative to the star~ of the page in MEM 1()2 identified by the valid resident physical address field, of the PTE of the particular word to be addressed. The physcial address field of the PTE and the page offset field of the logical address thereby together comprise the physical address in MEM 102 of the word referenced by the logical ~22-address represented ln FigO 3 and the logical to physical address translation has been completed.
Refe~ring to Fig. 4, a two level page table translation is represented. As indicated therein the seneral proce2ure for a two level page table translation is similar to that of a one level page table translation except that an additional reference through a second page table is performedO ~he logical address includes, in addition to the single level page table address field, a double level page table address field. The double level page table address field of the logical address is utilized, together with the physical address field of the SBR identified by the SBR field of the logical address, to generate a physical address of a particular PTE in a first page table. The valid resident physical address field o~ the PTE of the irst page table is then combined ~ith the single level page table address field of the logical address to generate a physical address of a second PTE in a second page table.
In this caser t~e valid resident physical address field of the PTE of the first: page table identifies the physical starting address of the second page tableO The I

single level page table address field of the logical word address identifies an offsetl relative to the start of the second page table, of the second PTEo The physical address field of the second PTE is then combined with the page offset fleld of the logical address to generate the final physical address referred to by the loyical address.

Finally, as described above, CS 101 transfers pages between MEM 102 and extenal storase as necessary. This operation is performed by CS lOl's memory management system, of which CS lOl's address transiation mechanism is a part. CS lOl's address translation mechanism performs, in particular, two functions with regard to CS
lOl's memory management mechanism~ First, CS lOl's address translation mechanism monitors which of the pages resident in MEM 102 are referenced in read or write operations, and which pages are most frequen~ly referenced. When it is necessary to transfer a page out o MEM 102 to external storage in order to transfer in another pase~, CS lOl's memory manasement system utilizes this reference information to determine which pages have -2~-not been referenced cr have been least frequently referenced in determining which pages resident in MEM
102 can be replaced. Secondly, CS lOl's address translation mechanism monitors which of the pages in MEM
102 have been referenced by wrlte operations, that is, which pages in MEM 102 have been modified and are no longer identical to the copies o those pages residing in external storage. If a particular page has been referenced in a ~rite operation, it is necessary for CS
101 to copy that page back external storage when that page is replaced by another page fro~ external storage.
If that particular page has not, ho~ever, been referenced in a write operation, CS 101 may simply discard that page by writing a new page from external storage in o the same address locations in MEM 102, thereby reducing the execution time required for a page swap~ CS lOl's address translation mechanism stores the above described memory management information, in the form o~ referenced/modified bits, in MC 118, wnich will be described in greater detail below.

:~9~3~23 Having described the overall structure and operation and certain basic features of CS 101 above, CS
101 will be described belo~ in further detail~ CU 104 will be described firstt followed by PU 106O
Reerring to Figs 0 5, 5A, 6 and 6A, these figures comprise a detailed block diagram of C~ 104 and PU 106-Figures 5 and SA present CU 104 and Figures 6 and 6A
present PU 106. Figures 5, 5A, 6 and 6A may be placed side to side, in that order from left to right, to comprise a complete detailed block diagram of ~U 104 and PU 106. ~or purposes of certain of the following discussions, it will be assumed that the reader has so assembled Figures 5 and 6 into such a block diagram.
A. 59~13~.~E ~
Referring to CU 104 in Figs. 5 and 5A, as previously descr-ibed the major elements of CU 104 are Microsequencer (US) 116, Instruction Prefetch an~ Decode (IPD) 114, Memory Control (MC) 118, and System Clock Generator (SCG) 120. These elements will be described next below in that Referri.ng to US 116, US 116 contains CS lOlts microcode control logic, inclucling microcode memories ~26-.23 for storing microinstruction sequences for controlling operation of CS 101, microcode sequencing control logic for selecting and manipulating microinstruction sequences, and condition logic for providing microinstruction control of CS 101 in response to certain conditions occurring therein and, for example, branches in microinstruction sequences. Microcode control functions providecl by US 116 also include microcode state save and restore mechanisms or use in executing microcode traps and interrupts. In addition to the above functions directly concerned with execution of users programs, US 116 also provides all console control functions through the provision of microcode therein direct7y responsive to commands entered through a 50f t console, that is, a user keyboard as opposed to front panel s~itches.
As will be described furthQr below, US 116 microcode resides in three microcode memories, reflecting the microcode or~anization of CS lOlo A
first microcode set, referred to as kernel microcode, resides permenently in US 116, as does horizontal microcode. Vertical microcode is not permanently ~ ~ 9 ~3 ~ ~ ~

resident in US 116. That is, vertical microcode is stored in ~andom Access Memories (RAMs) comprising writable control store ancl are loaded into CS 101 at system startup. Briefly, kernel microcode reside~
permenently in US 116, ancl in addition to providing console and other functions, is available at ~ystem startup to perform system initialization, including loading of vertica~ microcode. Typically, vertical microcode will reside in external memory devicesr such as disk memories. At time system's initialization, vertical microcode is read from external memory and, under control of kernel microcodet is transferred into ME.~ 102 a file to reside therein~ Then, still under control of kernel microcode~ vertical microcode is read from MEM 102 and loaded into vertical microcode memory in US 116. At that time, the full functionality of CS
101 is available~
The core of ~S 116's microsequencer is comprised of Microsequence Control Logic (USCL) 500. USCL 500 is comprised, for example, of 4 A~D AM2930 bit-slice program control units connected in parallel. USCL 500 includes logic to implement Microprogram Count (UPC) ;

increment, a seventeen word deep last in first out stack, a separate register as a source of microinstruction addressesl an input port for jumping out of sequential microprogram execution, and an output port for providing microinstruction add.resses to US
116's microcode memoriesO USCL 500 also includes an internal microprogr2m control unit for controlling operation of USCL 500.
USCL 500ls microinstruction address output is provided from the output of Microinstruction Address Multiplexer (UAM) 502. UAM 502 is provided with a first input from USCL 500's input, which i5 connected from Microinstruction Input (UIN) Bus 504. ~ second input of UAM 502 is connected from Micxoinstruct;on Address Register (UAR~ 506, whose input is connected from Microinstruction Address Register Multiplexer (UARM) 508~ UARM 508 is provided with a first input connected from USCL 500's input, that is, from UIN Bus 504, and a second input from output of U~ 5020 UAM 502's third input is connected rom output of ~llcrostack (USTACK) 510; as described above, USTACK 510 is a seventeen word deep last in Eirst out stack. USTACK 510 :has a first I

~98~Z~3 input connected from UIN Bus 504 and a seconcl input connected USCL 500's microprogram counter, described next belowO UA~ 502's fourth input is similarly connected from the output of USCL 500's microprogram counterq USCL 500's microprogram counter includes Microprogram Counter Register (UPCR) 514 whose output is connected to inputs of UAM 502 and USM 512, Input of UPCR 514 is connected from outpu~ of Microprogram Count Incxement (UPCI) 516, which has an input connected from Microprogram Count Multiplexer (UPCM) 518. Inputs of UPCM 518 are connected from the ouiput of UAM 502 and from the output of UPCR 514O UPC~ 518 allows an initial microcode starting address to be loaded from output of UAM 502 and into UPCR 514 through UPCI 516~ Thereafter, Microprogram Count (UPC) may be sequentially incremented by transferring current UPC from output of UPCR 514 and through second input of UPCM 518 to UPCI 51~; current UPC may then be incremented by one by UPCI 516 and the resulting next sequential UPC loaded into UPCR 514.
Other operations of USCL 500 in generating ~30-:

Z~3`

microinstruction addresses for US 116's microcode memories ~ill be describecl further below.
Finally, USCL 500 includes internal microcode control logic USCLC, which USCLC receives and decodes control and instruction inputs from Microinstruction Decode (UID) 522r which will be described below, to control operation of USCL 500.
Referring to the output of USCL S00, 16 bit microcode address output of UAM 502 is connected to UY
Bus 524~ UY Bus 524 in turn provides a single bit input to Microprogram Counter Save Register (UPCSR) 526 and a sixteen bit input to UY Regi~ter (~"R) 5~8. UYR 528 in turn provides a sixteen bit outpu~ to D Bus 108.
Sixteen bit UY Bus 524 is connected, through a buffer, to sixteen bit ~ext Microprogram Counter (NXUPC) Bus 530. NXUPC Bus 530 also receives, through a buffer, a sixteen bit input from UIN Bus 504. NXUPC Bus 530 provides sixteen bit address inputs to Rernel Microcode Memory (RUM) 532 and Vertical Microcode Memory (W M) 534~ NXUPC Bus 530 also provides a fifteen bit input to UPCSR 526.

. . -31-l i ~ 2 3 Referring to KIJM 532 and WM 534, thirty-two bit microinstruction outputs of kernel and vertical microcode memories are provided to Microcode Output (UCO) Bus 536. Thirty-two bit input of Microinstruction Register (VIR) 538 is connected from UCO Bus 536, and thirt -two bit output o:E UIR 538 is connected to Microinstruction Register (UIR~ Bus 540. As will be described urther below, kernel and vertical microinstructions are distributed to other portions of CS 101 frol~ UIR Bus 540.
Returning to UCO Bus 53~, UCO Bus S36 provides sixteen bit microinstruction inputs to Microinstruction Save Hiyh Register (UIRSEII) 542 and to Microinstruc:tion Save Low Resister. (UIRSLO) 544. Sixteen bit microlnstruction outputs of UIRSIII 542 and UIRSLO 544 are connected to D Bus 112. Certain bits of thirty-two bit UCD Bus 546 are provided as data input to VUM 534 through Buffer 535.
Returning ~o UUR Bus 540, UIR Bus 540 provides an address input to Horizontal Microcode Memory (HUM) 548.
As described above, and described in further detai:L
belo~, HUM 548 stores and provides horizontal extensions -3~

2~

to vertical microcode dealing with random control of CU
104, IPD 114, and D Bus 112, among other functions. UIR
540 also provides certain selected microinstruct:ion bits as inputs to UID 522. UID 522 in turn provides instruction and control out:puts to USCL 500 and to SCG

UIR 3us 540 also provldes control inputs to Condition Multiplexer tCONM) 550~ Data inputs to CONM
550 are registered and unregistèred conditions occurring at var.ious points throughout CS 101~ CONM 550 ~; output is provided as an input to UID 522 and as an input to Condition Save Register ~CONSR~ 552. An output of UPCSR
526 is connected through a buffer to the output o~ CONM
550 so that UPCSR 526's output may be provided tG the same inputs of UXD 522 and CONSR S52 as the output of CONM 555.
Finaily, certain of UIR Bus 540's thirty-two microinst~uction bits are provided as one of five inputs to Microinsturction Multiplexer (UIM) 554. UIR Bus .
540's input to UIM 554 is, as will be describecl urther below, provided to implement o~t of sequence jumps to L

Q S,~ ~ r~ ' ~I)IJPIO~D

new microinstruction addresses while executing microinstruction sequences.
Referring to ~M 554, UIM 554's ou~pu.t is connected to UIN Bus 504 and UIM 554''s inputs are connected to various sources used, as described below, to seleet mieroinstruction sequences to be executed by US 116 and, therefore, CS 101. As just described, one input of UIM
554 is connected from certain bits of UIR Bus 540, Another input o UI~ 554 is eonnected from D Bus 112, yet another input is eonnected from CONSR 552, and another input connected rom UPCSR 526. Finally, a last input of UI~ 554 is, as will be deseribed in detail below, connected from an output I~D 114, Referring finally to the upper porti.on of US 116, therein are represented three registers having outputs conneeted to D Bus 112. These registers are provided to store certain conditions and flags occurring in CS 101, for subsequent transer on to D Bus 112. A irst register is Error Log Register (ERRLR) 556, a second register is Diagnostic Register (DIAGR) 558, and a third reg.ister is ~lag Register (FLAGR) 560.

~8~

Having described the overall structure of US 116 and certain features oE the operation thereof, the operation of US 116 will be described in further detail next below~

b. ~ Q~ iQn 1. I~tro~ iQ~
As described above, USCL 500 provides functionality for microprogram control and selection operations.
Input to USCL 500 is through UIM 554 and UIM 8us 504 while USCL 500's output is through NXUPC Bus 524.
Referring first to USCL 500~s input through UIM
5~4 and UIN Bus 504, UIM 554 is provided with inputs from five sources~ A first input source for UIM 554 is f rGm D Rus 108 and provides, for example, instruction from IPD 114. A second source is from UIR Bus 540 and is utilized for jumping to nonsequential microinstruction addresses in microcode memory. A third source is from IPD 114, described below, and is used for certain instruction pre-e:cecution operations and certaln preliminary operations regarding addressing from instructlon4 A fourth source is a microcode conditional ~35--~ a input comprised of selected portions of UIM 554's inputs frcm UPCSR 526 and UIR Bus 540. Finally~ the fifth source is again a conditional input provided by the output of UPCS~ S~6.
Referring to ~XU~C Bus 530, either UY Bus 524, w~ich is ~SCL 500's direct output, or UIM Bus 504 may be selested to drive NXUPC Bus 530 and thereby directly address ~M 532 and W M S34.
For a microinstruction fetchi that is, a microinstruction read from microinstruction memory/
either R~M 532 or W ~ 534 is enabled~ based upon the state of a Rernel Flag (RFLAG) stored in FLAGR 560 and asserted duxing fetch operations. If ~FLAG is asserted, fetch is from ~UM 532 and, if ~FLAG is not asserted, fetch is from VUM 534. KFLAG may be set, or asserted~
~or example, on system initialization or upon occurrence o~ a microparity error, as described below. RFLAG may be loaded into ~FLAGR 560 as a bit output from VIR Bus 540 through operation of an NCU random control output provided fro~ ~UM 548 .
The 32-~it outputs of RUM 532 and W M 534 axe ORed together on UCO Bus 536 and are loaded into UIR 538 at ~W~3 the end of each microinstruction read cycle to appear on UIR BUS 540~ RUM 532 and VUM 534 outputs may each be selectively disabled for this ORing operation~ All microcode visible operations of CS 101 are controlled by the 32 bit microinstruction appearing on UIR Bus 5A0 from ~IR 538.
In addition to beins loaded into UIR 538, microinstruction outputs apprearing on UCO Bus 536 may be loaded into and saved in UIRSHI 542 and UIRSLO 544.
Outputs of UIRS~I 542 and UIRSLO 544 may then be transferr2d onto D Bus 112 to allow reading of kernel Gnd Jertical microcode memories.
As will be described further below~ all microins~ructions appearing at UIR 538 output on VIR Bus 540 are checked for error by operation of Microparity Checker (UPARC) 5621 which is connected from UIR Bus 540.
As described above~ each microinstruction output appearing on UIR Bus 540 from UIR 538 contains 32 bits of microcode control information, Although there is certain overlap of functions controlled by various microinstruction ~ields, certain portions of each microinstruction may be generally described as controlling certain CS 101 functions. For example~ in general UIR Bus 540 bits 0 and 3 through 30 are provided to PU 106 to control all PU 106 microcode visible functions. UIR Bus 540 bits 7 through 13 may be used to select a detected and registered condition occurring in CS 101 to be tested during a current microinstruction cyele~ For this purpose, bits 7 through 13 fro.-n VIR Bus 540 are provided as control inputs to CONM 550, which in turn selects conditions to be tested. Other microcode controlled functions will be described further in the following descriptions.
Having described the general operation of US 116, certain features of US 116 operation will be described in urther detail next below.
2. Basic ~ic~inL~uGtion F~tch A microinstruction cycle is defined, for purposes of the following descriptions, as ~he time between consecutive CS 101 clock cycles and is the period of time during which single microinstruction functions are executed. In general, during each microinstruction cyele the microinstruction is fetched rom either KUM

-3~-532 or W M 534 and 2 previously fetched microinstruction stored in UIR 538 is executed.
The following presents a typical sequence of steps occurring in US 116 during consecutive microinstruction cycles:
1~ USCL 500 has placed on UY Bus 524 a microinstruction memory address specified by decode of the certain bits (0 6) currently appearins on UIR Bus 540 and the output of CONM 550. Information appearing on CONM 550's output ~rom CO~M 550 and UPCSR 526, may include the contents of UPCSR 526, information indicating the current top of USTAC 510, the contents of UAR 506, or on input appearing on UIN Bus 504~
~ ) The microcode address appearing on UY Bus 524 is incremented by UPCI 516 and the incremented microprogram count loaded into URCR 514. In all microsequencer operations, except certain operations described below, the microcode address appearing on UY
Bus 524 is transferred onto NXUPC Bus 530 to address either KU~ 532 or VUM 534. Thereore, UPCSR 526 will contain the ~ddress of the currently executing microinstruction plus one.

-3) A new microinstruction addressed by the address presently appearing on NXUPC 530 is loaded into UIR 538~

4) The address presently appearing on NXUPC
530 is loaded into and saved in UPCSR 526l so that UPCSR
526 always contains the address of the currently executing microinstruction except on a TRA~ condition as described below~

5~ The output of CONM 550 from the microcycle just ending is loaded into CONSR 5520

6) US 116's pointer to the top of the mierostack residing in USTAC~ 510 is changed if the current US 116 operation specified in the cycle just ending has affected US 116's microstaek.

7) The contents of UAR 526~ whose operation is described further in following descrlptlons, is changed if the US 116 operations specified in the microcycle just ending has affeeted UAR 506, or if other operations, deseribed helow, occurred during the same microcycle~

8~

Having described a typical microinstruction cycle sequence, US 116 operation for TRAPS will be described next below.
3~ uL~`u~ L~n A TRAP condition occurs during execution of microcode when an exceptional condition occurs and it is desirable to stop the execution of a misroinstruction in pro~ress, service the exceptional condition, and then resume execution of microcode from the suspended microinstruction. A TRAP process must save suf~icient machine state so that the stopped microinstruction may be restarted. For those T~APs that can be serviced entirely by microcode, the two pieces of state information that must be saved in US 116's microstack residing in ~STACR 510 are, (1) address of the stopped microinstruction;
and (2) the output of COMM 550 from the stopped microinstruction; that is, all conditions currently present.
CONM 550 output must be saved because the inputs to CON~I 550 are registered, or stored, state that may 2~3 change- during servicing of a TRAP condition and the microinstruction which was interrupted must recover the correct conditions selected upon resuming.
A signal, TR~P is asserted by IPD 114 During execution of any microinst3-uction which is to be suspended. This event causes the ollo~ing to occuro (1) Clock to all CS 101 registers under explicit microcode control is stopped so that these registers are not loaded with altered information during servicing of the TRAP condition;
(2) USCh 500's control input from UID 5~2 is forced into a state to force USCL 500 to do a jump operation to a TRAP handling microinstruction sequence;
and (3) Control input to UIM 554 is forced to the appropriate state to select UIM 554's input to be that provided from IPD 114.
The address o a TRAP handling microinstruction sequence is provided to UIM 554's inpu~ from IPD 114 by either CU 104 or PU 106, depending upon whether CU 104 or PU 106 is,the source of the ~RAP signal. If both CU
104 and PU 106 have provided TRAP signals, then a -~2-98' '~``

priority mechanism will determine the TRAP handling microinstruotion sequence to be selected. A TRAP
handling address is the starting address of a TRAP
handling microinstruction sequence and is placed directly upon NXUPC Bus 530 from UIN 504 through Buffer 5~5.
At the end of a microcycle in which a TRAP
condition occurs, the following occurs:
51~ UI~ 538 is loaded with the microinstruction beginning the TRAP handling microinstruction seauence;
(2) WPCSR S2~ is nQ~ loaded with the microinstruction address appearing on NXUPC :3us 530;
UPCSR 526 will therefore contain the address of the t.rapped, t~at is, interrupted, microinstruct:ion during the first microinstruction of the TRAP handling microinstruction sequence;
(3) The output of CONM 550 is loacled into At conclusion of handling of the TRAP condition the or1ginal state of execution of the interrupted microinstruction sequence is restored, using information retained in UPCSR 526 and CONSR 552 and throug]l the state save/restore mechanism described next be:Low.
4~ s-3~ L~-~h~--L~ çh~ni~m US 116's Basic State Save/Restore Mechanism is USCL
500ls microstack residing in US~ACK 510.
During the first microinstruc~ion cycle of a trap handling microinstruction sequence, signal TRAP is not asserted and any the information stored in UPSC:R 526 may change state. The first microinstruction cycle of a TRAP handling ~licroinstruction sequence must therefore do a state save/restore operation to save current state of US li6 and USTACR 510. During this operation, the contents of CONSR 552, khat is, previous conditional states of execution, and the contents of UPSCR 5~6, that is, the address of interrupted microinstruc~ion, are transferred through UIM 554 and onto UIN Bus 504. This state information is then transferred through USM 512 and onto the top of microstack residing in USTAIK 510, thereby saving the conditions and address cf the interrupted microinstruction.
If a TR-AP may be totally handled by a microcode, no further microsequencer state save is required. Resuming -~4-~9~

execution of the stopped microinstruc~ion is accomplished by leaving the saved condition state and microinstruction address at the top of microstack ~esiding in US'rACK 510 and performing a resume oper.ation which "pOpsn the top entry in USTACK 510. A ~pop'l operation ~etches the sto~ped microinstruction while reading the saved condition state information from top of microstack and transferring this information from top of microstack through ~AM 502 and into UPCSR 526. Saved condition state is a single bit of information rom UPCSR 526 and which represents the saved outpu~ of CONM
550. After being transferred into UPCSR 526, and during re-execution of the interrupted microinstruction, the saved condition state information is transferred onto CC)NM ~50's output through Buffer 527, thereby providing saved condition state information to CONSR 552 and UID
~22. Saved address of the interrupted microinstruct:ion is concurrently transferred through UAM 502, UPC~ 51iB
and UPCR 516 to UPCR 514. At this point execution oi-the interrupted microinstruction may be resumed.
Having described US 116's basic state save/restore mechanism, US 116's state save/restore mechanism for conditions requiring assistanee from macroeode, that is, from instruetion stored in MEM 102, will be deseribed next belowq 5- ~9r=z~D~ lu~ Qr~sist~d State ~v~sL~l~

When a trap condition oeeurs requiring maerocode assistance for handling, the trap handler must save all mierosequeneer state and other PU 106 state in MF.M 102 rather than in USTACX 510's mierostaek~ State saved in sueh eonditions ineludes the eurrent eontents of USTACK
510's mierostaek ineluding the address of the eurrently e~eeuting microinstruetions and eurrent state condition information pertaining to the interrupted mieroinstrlletion, and the current eontents of U~R 506 As in the ease described above, eurrent condition fro;m CONSR S52 and UPCSR 526 are first pushed onto USTACK
510. Full state save then saves the contents of USTACK
510 and MAR 506 in MEM 1~2.
Current state eonditions and current microinstru~tion address are read rom CONSR 5S2 and UPCSR 526, respectively, and through UIM 554 to UIN 3usg 504. This information, together with informa~ion from UAR S06 and the contents of USTACK 510's microstac~, are read through ~AM 502 and UY Bus $24 into UYR 528. Sl:ate information so read from US 116 may then be transferred through D Bus 112 to MEM 102, or to scratch pad memory in PU 106, described in a :Eollowing description o ~J
10~ 4 State restore is accomplished by reading US 116lS
saved state inormation from MEM 10~, or scratch pad memory in ~U 106, to D Bus 112. This information is then transferred into UIM 554's input from ~ Bus 112, and onto UIN Bus 504. The saved contents of UAR 50~ and USTACK 510 may then be transferrecl through UARM 508 to UAR 506 or through USM 512 to USTACR 510. Once completed, the saved condition state and interrupted mi~roinstruction address will be the top entry in USTACR
510 and the interrupted microinstruction may be resumed as described in section 3 above.
6. B~in~ nd Wri~in~ Microcode Memory As previously described, CS 101 implements vert:ical microcode in a writable control` store, that is, W M 534.
A meansr described next below, is provided to write vertical microcode rom external memory to MEM 102 and from MEM 102 to VUM 534. This means also allows t:he contents of WM 534 and and RUM 532 read from VUM 534 or E~UM 532 to D Bus 112, for example~ to verify microcode residing in VUM 534 or RUM 532 or to be read as a source of literal data. This mechanism operates under microcode control and the functions described may be performed under control of microcode provided from either P~UM 532 or WM 534O
During a microcode write to VUM 534, or a microcode read from VUM 534 or RUM 532, USCL 500 is ~orced to perform a conditional microinstruction jump to the appropriate microinstruction sequence, by means of a microcode input to UID 522 and a corresponding instruction to USCLC 520. Microcode memory read and write addresses are provided t o NXUPC Bus 530 from UAR
506 through UA,'I 502 and I~Y Bus 524. UAR 506, in turn, is provided with read and write addresses from D Bus 112 throu~h UIM 554 and UIM Bus 504.
In microcode write operations to WM 534, microinst:ruction words are pro~rided on D Bus 112 and are trans~erred through UCD Bus 546 to VUM 534's data input ~9~ 3 through Buffer 535. In microcode read operations from either RUM 532 or VUM 534, microinstruction words are read from RUM 532 or VUM 534 onto UCo Bus 536 and into UIRS~I 542 and UIRSLO 544. Microinstruction words may then be transferred from UXRS~I S42 and UIRSLO 544 to UCV Bus 546 and to D ~us 112~
7 Microcode ParitY Errors Each microinstruction provided by RUM 532 or by VUM
534 is a 32 bit word comprising 31 bits o microcode information, plus 1 parity bit which is set to preserve odd parity. Parity of each microinstruction appearing in UIR 538 is checked by UP~RC 562 after each fetch of a microinstruction from KUM 532 or VULM 534. If a parity error occurs, ~P~RC 562 will initiate a microparaty error trap that prevents execution of the microinstruction in error and transfers control to Kernel microcode in KUM 532 for error handling.
8. ~
In the above descriptions, IPD 114 was described as the source of instructions to be executed by means of corresponding microinstruction sequences provided by US
116. An instruction boundary is crossed when the 1 198~.2~

microinstructi.on sequence corresponding to a first instruction is ended, for example, by completing execution of the sequence or becau-,e of a trap condition, and execution of a second instruction is ir.itiatedO ~licroinstruction sequences provided by US
116 provide a mechanism for initiating the execution of new instructions.
End of execution o~ a current instruction may be indicated by the appearance in UIR 538 of a particular microinstruction in the correspona.ing microinstruction sequenceO If such an end of execution microinstruction occurs, UID 522 and USCLC 520 provide an instructlon to USCL 500 to jump to a state for receiving a next instructionO At this time, UIN 554 is instructed to accept as input to UIN ~us 504 UIM 554's input from IPD
114. IPD 114 will then provide, through UIM 554 and UIM
Bus 504, the starting address in microinstruction memory of the next instruction to be executed.
If an interrupt is pending, or if the next instruction has not yet been fetched, or if any one of several othe~ conditions occurs, a next instruction may not appear or be available. IP~ 114 will then provide ~ ~r~

to UI~l 554 the address in, microinstruction memory of an appropriate routine to handle the existing condition~

9. ~9~
As previously described, CU 101 incorporates a "soft consolen. That is, opera~:or console type commands may be entered through a terminal rather than through front panel switches. US 115 wLll detect the initiation of such a console command entry by means of a non maskable interrupt initiated by an initial console command. Vpon such occurrence, an address will be forced at UIM 5547s input from IPD 114 whichr provided to USCL 500 and thus to NXUPC Bus 530, is the initial address in RUM 532 of console microcode sequences stored therein.
As previollsly described, at system initiation US
116 microcode memory contains only kernel microsode. In a present embodiment of the present invention, kernel microcode includes at least a portion of the MOVA
instruction set microcode and is responsive to sinsle character commands provided from a terminal through SIO
120. Vertic~l microcode include microcode for the full NOVA, ECLIPSE and MV/8000 instruction sets and is responsive tG multiple character commands provided froma terminal through SIO 120. CS 101 thereby provides a limited "raft" console, that: is, from a terminal~ at system start-up, and full console functions ater vertical microcode has been loaded.
Having described the s1ructure and operation of US
116, the structure and operation o IPD 114 will be described next below.

3 . 3 t~usti ~3~ h~Ad Decode ~IPD~ ...(F~s . S, ~L
As indicated in Fig. 5 and SA, and as previously described, IPD 114 is connected between memory data (MDA) Bus 110 ~nd D Bus 112 with an output to an input o~ UIM 554 in US 116~ IPn 114 opera~es as aan u~ to four instruction deep instruction prefetch, and as an initial instruction decoder. Some typical formats of instructions used in C5 101 have been previously described with reference to Fig. 2.
a. 5~ ture of IP~
Referring to IPD 114, 16 bit Pree~ch Register A
(PRA) 564 and 16 bit Prefetch Register B (PRB) 566 have -5~-inputs connected from MDA Bus 110. 16 bit outputs of PRA 564 and PRB 566 are connected to 16 bit Prefetch Register (PR) Bus 568, P~ Bus 568 is connect.ed to 16 bit input of Displacement ~igh Latch (DISP~IL) 57Q and to 16 bit input of Diqplacement Low Latch (DISPLOL) 572. 16 bit outputs of DISPHII- 570 and~ DISPLOL 572 are connected to first and second 16 bit inputs of IPD Ou~,put Multiplexer ~IPDOM) 574.
Next Instruetion Register (NIR) 574 has a 16 bit input connected from PR Bus 568 and 16 bit output connected to 16 bit input of Instruction Register (IR) 578. IR 578 in turn has al 16 bit output connected to a third input of IPDOM 574.
Finally, PR Bus 568 i.s connected to 16 bit input of Single Le-~el Instruction ('racker (SLIC) 580~ 9 bit output of SLIC 580 is connected to the input of 9 bit Single Level Instruction Cracker Register (SLICR~ 582, and 9 bit output of SLICR 582 is connected to input of Macroinstruction Decode ~lemory ~MIDM) 584.
A first output of ~1IDM 584 is connected to the input of Decoded Instructi.on Register (DIR) 586. A

~53-first output of DIR 586 is connected to a ouxth input of IPDOM 574 and in part cc:~ntrols IPDOM 574 Second outputs of DIR 586 are provided to other portions of CS
101~ as will be described in following descriptions.
A second output of MII)M 584 is connected to a firs~
input of ~1icroinstruction Address Multiplexer (UADRM) 588. A second input of UA~IRM 588 is connected from Trap Addresses (TA) 590~
Finally, IPD 114's first output, from output of IPDOM 574, is connected to D Bus 112 while IPD 114lS
second output, from output of UADRM 588, is connected to the previously described input of UIM 554 in US 116.
~ aving described the overall structure of IPD 114, tne operation or IPD 114 will be described next below~
2. Ip~ iQn As has been previously described, a typical instruction of CS 101 may contain 32 bits, including. 16 bits of instruction information (opcode Eield) and 15 or 16 bits of address displacement information (displacement fie1d). Certain instructions, however, will have a total length of 16 bits or will have a double word displacement field of 32 bits, for a total of 48 bits. As also previously described~ and as will be further described in foLlowing descriptions, all writes to and reads from MEM 102 by CS 101 are of double words, that is, of two 16 bit words at a time. Upon each read from MEM 102, therefore, PRA 564 and PRB ;66 will receive a 3~ bit double word from MDA Bus 110, with one 16 bit word being received in PXA 564 and the other 16 bit word being received in P~'~ 556~ A Prefetch Register (PR) pointer generated by US 116 indicates, at any time, which o~ PRA 56~ or PRB 566 presently contains or will contain a 16 bit instruction information of a current instruction field or which contains or will contain displacement field inforn~ation.
Instruction displacement field information may be transferred from either PRA 564 or PRB 566 PR Bus 568 and toeither of DISHIL 570 or ~ISPLOL 572. Diplacement field information may then be transferred from DISP~IL
570 or DISPI,OL 572 and through IPI~OM 574 to D Bus 112 for use by PU 106 in addressing data re~erer.ced by an instruction. Two displace field latches, that is, DISP~IL 570 and DISPLOL 572, are provided to enable displacement field information to be transferred to PU

.. .

106 in a single cycle for 15, 1~ or 32 bit displacement fields.
Instruction information fields may be transferred from either PRA 564 or PRB 566 to PR Bus 568 and NIR 576 and in turn to IR 578. From IR 578, instruction information ields may be transferred, simultaneously with the corresponding decoded output of SLIC 580 to SLIC~ 582, througb IPDOM ~74 to D Bus 112 and thereby to US 115 through UIM 554 to select corresponding microinstruction sequences to be executed by CS lOlo NIR 576 and IR 578, together with PRA 564 and PRB 566, provide an up to four instruction deep prefetch mechanism, allowing CU 104 to fetch instructions in advance of the instruction currently being executed.
Certain of CS lOl's instructions cannot be executed immediately as received from MEM 102. ~or example, instructions will frequently require aclditional processing of the instructions addressing in~ormation before the data referenced by the instruction can be fetched from MEM 102. Additionally, due to the variety of instruction formats used by CS 101, CS 101 and US
116~ in particular, must perform certain preliminary ~ 4~

operations in order to properly lnterpret: and respond to instructions.
The instruction crack ! ng and decoding circuitry provided by SLIC 580 and MIDM 584 and related logic provides a mechanism for interpreting instructions First, SLIC 580 examines the 16 bit instruction information field of each instruction and extracts therefrom 9 bits, depending upon the instruction format, defining the operation to be pexformed. A first output is.a 9 bit predecode address which is pro~ided as an input to MIDM 584, described below. A second, 2 bit, output defines the index made for the instructions being decoded and o~er output may define the instruction class. The information ~o extracted includes information relating to data addressing, such as data width, displacement type and instruction w:idth.
MIDM 584 is a read-only-memor-. addressed by the 9 bit output of SLIC 580 and providing appropriate control o~tputs. MIDM 584's first output to DIR 586 provides information relating to data width, displacement type and data length. MIDM 584's second output, to UADRM 588 provides to US 116 the starting microaddress cf ~g~3 "

microinstruction sequences to be executed, as previously described in the description of US 116.
UADRM 58~'s second inputt from TA 590, provides information to UIM 554, and thus to US 116, regarding the starting microaddress of microinstruction sequences to handle trap conditions occuring in CS 101~ as previously described.
~ aving described th~ structure and operation of IPD
114, the structure and operation of MC 118 will be described next below.
3~ ~mQ~y-5Q~trsl (MÇ~ 118 (Fig. 5, 5~ and 7) MC 118, as previously described, performs interface functions between CU 101 and MEM 1020 MC 118 is a "look aside" interface device, that is, is connected in parallel from MAD Bus 108 and MDA Bus 110, rather than being connected in series in these buses between CS 101 and MEM 102. MC 118 operates, however, as if connected in series in MAD Bus 108 and MDA Bus 110 betwee:n CS 101 and MEM 102. MC 118 allows CS 101 and MEM 102 to share the same address and data signals on MAD Bus lOB and MDA
Bus 110 while, at the same time, allowing CS lO:L and MEM
102 to have different interface protocolsO

11 9 It ~ L~ ' 7 In addit:ion to perforrning translation between C~
101's memory bus protoco~ and ~M 102's memory ~us pr.otoco1.
MC ~18 prov1des MEM 102 refresh and "snifing~. Sniifing~
as described in US Patent 4,380,812, issued April 19,, 1983, is a mechanism and method for scanning M~M 102 1Ocati.ons being refreshed~ detecting errors therein, and correc:ting such errors~ In addition, MC 118 performs memory error logging. Finally, as previously described wit~ reference to CS 101's addressing mechanisms and in particular CS 101is demand p~ging mechanism, MC 101 monitors and 1Ogs, or records~ referenced and modified pages residing in ~M 102 a. Structure of MC 118 Referring to Fig. 5, MC 118 inc1udes a Memory Control Sequencer ~MCSj 592, which provides timing and contro1 fo~ all memory related operations, in particular those of MC 118. MCS 592 has a c1Ock input fxom SCG ll20 a refxesh timing input from Refresh Timer (REFT) 594, and an ~rror input ~rom MC 118's ERCC logic, describedl be1Ow~ In addition to other control output~0 -_ 59 ,~
c~/,l.

~ ~ ~ Q ~ ?~2 MCS 592 provides outputs to Refresh Address CounterBuffer tRACB) 596 and to Re~erenced/Modified ~its Logic (REF~OD) 598.
Xn addition to a timing output to MCS 532, REFT 'i94 provides a timing output to Refresh Address Counter (RAC) 501. RAC 501 in turn provides refresh address outputs to RACB 596, and RACB 596 in turn provides refresh address outputs to MAD Bus 108 under control of the previously described control input from MCS 592a REFMOD 598, as previously described, monitors and logs referenced and modified pages in MEM 102 as part of CS 101's demand paging system by storing inormation bits pertaining to referenced and modified pages residing in MEM 102. In addition to a control input from MCS 592, RRF.~IOD 598 includes an input from ~D Bus 108 and a bidirectional connection to M~A Bus 110.
Finally, MC 118 incorporates Error Checking and Correction (ERCC) logic which includes a first level ERCCER (FLE) 503 and a second level ERCCER (SLE) 505.
FLE 503 and SLE ~05 are implemented with Advanced Microdevices AM 2960g connected in a 32 blt configurationO

~ ~ v~t~

MC 118 ' s ERCC logic is provided with an internal data bus, Check Data (CDATA) 507 ,which allows data to be transferred from MDA Bus 110 to MC 118 ERCC logic, manipulated, and transferred back onto MDA Bus 110.
~ata is transferred from ~lDA Bus 110 to CDATA Bus 507 through ERCC D2ta.Input Bu:ffer (EDI~) 509, and from CDAq~A Bus 507 to MDA Bus 110 through ERCC Data Output Buffer (EDOB~ 511.
FLE 503 and SLE 505 each have a 16 bit bidirectional data input/output connection to CDATA E~us S07 for receiving data from and transferring data to CDATA Bus 507. FLE 503 receives 7 bits of chec!c bit ~ERCC) information, from MDA Bus 110 through FLE 503'1s check bit (CB) input connected from MDA Bus 110 and provides a check bit output to check bit input of SL];
505's CB input. SLE 505 provides 7 check bits of ERCC
information c:o MDA Bus 110 through ERCC Check bit Oul-put Buf~er ~ECBOB) 513. SLE 5n5 also provides error outputs~ as previously described, to MCS 592 and to ERRLR 556 in US 116.

~61--Having described the structure ~nd certain :Eeatures of the operation o~ MC 118~ cexta~n features of ~C 11$ will be described further next below~
2~ Op~ration of MC 118 The operation of MEM 102, and ~EM 102's interface to MAD Bus 1~8 and MDA Bus 110 are described in Canadian Patent Application No. 441,238, filed October 26y 1983, ~E~
102 and MEM 102~ 5 interface to CS 101 will thexeby not be described further in detail her~in. The ~ollowing description will pertain to CS 101 and CS lOlis inter~aces to MAD Bus 108 and MDA Bus 110 and CS 101's func~ionc~ y with respect to memory operations.
As described above~ CS 101 and ~EM 102~ wi]Ll have differing interface protocols but share the address and data signals appearing on MAD Bus 108 and MD~ Bus 110.
Translation between CS 101 and MEM 102 interface protocols involves the control signals exchanged therebetween ,~nd manipulation oE check, or ERCC~ bits appearin5 on ~A Bus 110. It should be noted t~at CS 101 may pro~i~e 30 :bi-ts of address, since, as previously cr/l~

described, CS 101 performs reads from and wri~es to MEkl 102 double words only~
The least significant bit of CS lOl's addresses are exchanged to be the least signi~icant bit of the addresses received by MEM 102. This implies that consecutive double words written or read by CS 101 never appear in consecutive locations in MEM 102, allowing faster double word instruction fetches when ME~ 102 ~nterleave operation is considered.
MC 118 operations may be divided inta, two broad classes, read operations and write operationsO Read and write operations differ in that read operations may be pipelinedl whereas write operation may nol:, due to the operation o the MEM 102. That is, address and control signals for a next read operation may be sent to MEM 102 while reading and checking the data read L rom MEM 102 in a present read operation. ~11 data control and add~ess control functions for a present write operation must~
however~ be fully completed before initiating a subsequent write operation.
MCS 592~may be regarded as performing two mutually dependent operations with regard to memory read and write operations, address control and data control~
Address control monitors o~eration of MEM 102 through control signals provided rom MEM 102, initiates addressing operations, detexmines acceptance of addresses by MEM 102~ and generates control si~nals to initiate oEeration of MCS 592~s data control logic on inormation transfersO MCS 592's address control also monitors refresh operations, to allow sniffing operations.
MCS 592's data control logic generates all data control signals for MEM 102's CS lOl's inter~aces to MAD
Bus 108 and MDA 110. MCS 592's data control logic also generates all control signals for MC 118 ERCC functions and monitors the ERCC outputs of MC 118's ERCC logic.
As described above~ MC 118 performs reresh operations upon information stored in MEM 102. Refresh . is performed through "cycle stealingl operations, wherein MC 118!s refresh control circuitry takes control of MAD 108 and MDA Bus 110 at periodic intervals to refresh successive portions of MEM 102's address space.
REFT 594 generates a refresh rèquest signal at periodic intervals and, at time of a refresh c~cle, increments -6~--~C 501 to generate successive refresh addressesO RAC
501 genexates 21 bit addresses specifying double words to be read and checked for errors.
A snif operation~ that is examining information stored in MEM 102 in storac~e locations currently being refreshed for error checking and corxection, begins by requesting a refresh c~cleO During refresh cycle, MC
118 takes control of M~D Bus 108 and MDA Bus 110 and asserts a refresh address from RAC 501 through RACB 596 to MAD 8us 108. Information read from corresponding locations in MEM 102 is checkecl for errors, ~hile CS 101 is allowed to continue makin~ memory references. If a correctible error is found, a refresh write back operation is initiated. A refresh write back operation is performed in the same manner as the original refresh except that the information is corrected and written back.
When RAC 501 generates an address greater than the present address space of MEM 102l that address will address nonexistant memory. When this event occurs, MEM
102 will not,generate a signal ~indicating that the refresh addxess has been accepted. This event causes RAC 501 to be reset to zero, allowing refresh to start over at the beginning of MEM 102 address space~ A
refresh and sniff in MEM 102's address zero is performed immediately upon this occurrence.
As described above, ERCC and error logging is accomplished through MC ll~'s ERCC logic, including FLE
503 and SLE 505. Data inputs to FLE 503 and SLE 505 from MDA Bus 110, and data outputs from FLE 503 and SLE
505 tG MDA Bus 110 are isoLated from MDA Bus 110 th~ough the bidirec.lonal buffer comprising EDIB 509 and EBOB
511~ As described above, CDATA Bus 507 operates as the data port on of MDA Bus 110, but is isolated from MDA
Bus 110 by this bidirectional buffer. Check bits, that is ERCC bits appearing on MDA Bus 110, are, however, provided directly to FLE 503's check bit (CB) input from MDA Bus 110. Check bit output SC of MC 118's ERCC logic is provided rom check bit: output SC of SLE. 505 to MDA
Bu~ 110 throu~h ECBOB 513 MCS 592 provides individual and separate controls of all data and check bit transfers through EDIB 50!~, EDOB 511, FLE 503, SLE 505, and ECBOB 513.

I

f~3 ERCC upon information read from MEM 102 on to MDA
Bus 110 is accomplished by reading data bits from MDA
Bus 110 and through EDIB 509 to CDATA Bus 507, and thus into FLE 503 and SLE ~05, while check bits are read directly into FLE 503. It should be noted that FLE 503 receives the 16 least significant bits of data whlle SLE
505 receives the most significant 16 bits of data. FLE
503 utilizes the chec~ bit inputs from MDA Bus 110 and the 16 least significant dzta bits received from CDATA
Bus 507 to generate an appropriate check bit output to SLE 505 for those chec~ cmd inormation bits. SLE 505 in turn utilizes the most: significant 16 bits of data from CDATA 507 and the check bit input ~rom FLE 503 to generate a final check blt output.
ERCC upon lnformation read from MEM 102 is performed at the same time that the information is passed on to the requestor, in most cases PU 106. That is, ERCC is performed in parallel with the read operation.
If an ERCC error is detected, a signal halting memory operations is asserted and a correction cycle initiated.
During correction cycle, error syndrome bits indicating the error which has occurred are provided at output of SLE 505 and are driven onto MDA Bus 110 through ECBOB
513. From MDA Bus 110, error syndrome bits are transferred into FLE 503,. which provides appropriate outputs to the check ~it input of SLE 505. FLE 503 and SLE 505 then generate corrected data onto CDATA Bus 507.
The corrected data is then transferred through EDOB511 to MDA Bus 110 and thereby to the requester. Because comparitively few read operations will result in correction cycles, the parallel operation of MC 118~s ERCC Logic, wherein in~ormation is passed on to the requester while ERCC's performea, will result in faster a~erage read operations than will a series E~CC
operation.
MC 118's E~CC Logic also generates ERCC bits during write operations to MEM 10~. As previously described, all write operations, as are all read operations, are of double words. Data appeclring on MDA Bus 110 to be written into MEM 102 is accepted on to CDATA Bus S07 through EDIB 509. FLE 503 and SLE 505 accept this data as inputs and generate correspo`nding check bits from the output of SLE 505. These write check bits are then 8~3 transLerred onto the check bit portion of MDA Bus 110 throuqh ECBOB S13, and the data and corresponding check bits written into MEM 1020 CS 101 may also perfocm partial write operations, that is~ writes of single words of single bytes.
As described above, all read and write operations of CS 101 from and to MEM 102 are of double words, that is, of two sixteen bit words at a time. As has also been previously described, CS 101 is also capable of generating read and ~rite addresses referenclng single words (16 bits) and single bytes (8 bits). The operation of CS 101, and in particular MC 118, in performing single word and byte read and write operations will be described next below.
Referrina to Fig. 7, a block diagram of certain portions of CU 104 and PU 106 is shown, in par~icular CU
104's ERCC circuitry, including FLE 503 and SLE 505 and CDATA Bus 507, and PU 106's MDS 132, in particular MDR
602. In Fig. 7, FLE 503, SLE 505, EDIB 509, EDOB 511, MDR 602, and MDRB 603 have been redrawn to illustrate the o~eratio~ of these elements in yet greater detail.
In particular, ~DR 602 and MDRB 603 of MDS 132 are . ..:

~91~,,2.~

indicated as operating, respectively, as four independently controllable 8 bit registers and buffers, C, D, E, and F, rather than as a single 32 bit register and buf~er. In FL~ 503 and SLE 505, input latches I
have been represented as each comprising two independently controllable 8 bit latches Aand B, ~hile output latches O have been similarly represented as each comprising two inZependently controllable 8 bit latches, A and B. Similarly, EDIB 509 is represented as comprising four independently controllable 8 bit input bufferst while EDIB Sll is represented as comprising four independently controllable 8 bit output buffers.
For clarity oE presentation of the following description, CDATA Bus 507 is shown as divided in two parts, one part corresponding to FLJE 503 while the second part is associated with Sl.E 505. This division is made for illustrative purposes only and the two halves of CDATA Bus 507 shown in Fig. 7 are in fact a single bus. MDA Bus 110 is represented as being comprised of a 32 bit data bus and ~ 7 blt check bit bus for ERCC bits.

:' ~9~

In as much as CS 101 performs only double word reads from and writes to MEM 102, a wrlte of a single word or byte to MEM 102 is performed as a read, modify and write of a double word. Tthe doub3e word containing the address location of the single worci or byte to be written into MEM 102 is read from MEM 10~. The double word read from MEM 102 is effectively modified by ha~ing the single word or byte written into the appropriate location in the double word, and the double word is then written back into MEM 102~ The following will describe the operation of CS 101 in writing a single byte ~8 bits~ into MEM 102. A single word write, that is, of 16 bits, or two bytesy is performed in the sa~.e manner except that two bytes rather than one are written into the appropriate location in the double word.
Referring to Fig. 7, at start of a single byte write operation a doub~e word is read from MEM 102 on M~A Bus 110. Thirty-two data bits appear upon the data portions of MDA Bus 110, while seven check bits appear on the chec~ bit portion thereof. The four 8 bit bytes comprising the 32 bit double word are transferred through the corresponding portions of EDIB S09 to CDATA

~3~

Bus 507 and into the corresponding A and B portions of FLE 503's and SLE 505's input (I) latches. The check bits are transferred directly into FLE 503 ' s check bit ~B) inputO The 32 bit word received f rom MEM 102 and to FLE 503's and SLE 505's I latches are checked for errors, corrected if necessary, and transferred into FLE
503's and SL~ 505's four 8 bit output (O) latches A and At the same time, the byte to be written into MEM
102 is loaded into one of MDR 602's four single byte (8 bi t) latches, C, D, E, and F, from D Bus 112. The byte to be written into ME~I 102 will appear in the one of MDR
6 02 ' s latches cor .responding to the locatlon that the byte is to be written into in the double word initially read from MEI~ 102. The byte to be written is then transf erred f rom the corresponding byte resister of ~5RD
602 and through the correspondiny portion of MDRB 603 to the data portion of MDA Bus 110 and theref rom into the corresponding single byte input latch cf FLE 503 or SLE 505. For example, a byte appearing in MDR 602 byte register E Gould correspondingl~ be transf erred into FLE

503's I latch Ar while a byte appearing in MDR 602is latch D would appear in SLE 505's I latch B, A~ this timer three of FL~ 503's and SLE 505's input latches contain corresponding bytes rom the double word orisinally read from MEM 102 while one of FLE 533's or SLE 505's input latches contains t:he byte to be written into MEM 102. FLE 503's and SLE 5051S
input latches thereby contain the modified double word to be written back into MEM 102, that is, the dlouble word containing the byte to be written into MEM 10~.
FI,E 503 and SLE 505 will then ~enerate the new seven check bits for the modified double word. The check bits in modified double word are then transferred to FLE
503's and SLE 505's output latches and on to CDATA Bus 507 and MDA Bus 110 to be written into MEM 102, thereby completing the write of a single byte into ME~I 102. As descrlbed above, a write o a single word, that is o two bytes at a time, is perEormed in the same manner as a single byte write operation except that two bytes are received from MDR 602 and used to generate the modified double word.

f~i3 Finally~ as previously described, MC 118's REF~OD
598 operates as part of CS 101's demand paying system by monitoriny and storing information relating to referenced and modified pages residing in MEM 102.
REFMOD 598 may store information pertaining to up to, for example, 8 megabytes of inormation storage in MEM
1~2~
REFMOD 598 stores two different types of information pertaining to each page in MEM i02. F:irst, REFMOD 598 stores, for each page residing in MEM 102, a bit indicating whether the page has been reerenced by CS 101, for example, in executing a user's programv Secondly, REFMOD 598 stores, again for each page in MEM
102, a bit indicating whether CS 101 has modified, that is, performed a write operation to, that page in MEM
102. Referenced information bits are updated upon occurrence of each read or write operation to ME~ 102, while modified ~it information is updated during each write operation~ Updating of referenced and modified information in REFMOD 598 is performed under control of CU 104 random control outputs fxom ~UM 548 and US 116 as previously described.

--7~--~ aving described the structure and operation of ~U
104, the structure and operation of PU 106 will be corresponding described next below.
B. PROÇESSO~ rJNIT (PU~ 106 STRUC~
QEE~35Q~ 6 and 5~
Referring to ~ig. 6, a detailed block diagram of PU
06 is shown. As previously described, PU 106 operates under microinstruction control of CU 104 to e~ecute user's progra~.s. That is, PU 106 performs all data manipulation and calculation oF~rations, addressing operations, and inormation transfers between CS 101 and external storage devices.
l. Genera] Structure and Oper~tion of PU_lQ
As previously described and as shown in Fig. 6, PU
106 includes CPU Processor (CPUP) 122, Nibble Shif,er (NIBS) 126, Stratch Pad and Address Translation Unit (SPA~) 128, Memory Addressing (MAD) 130, Memory Data Store (MDS) 132, Serial Input/Output (SIO) 134~ and Data/~MC Input/Output (DBIO) 136.
Referring first to C?UP 122, CW P is a 32 bit processor comprised of 8 four ~it Advanced Micro Devices (AMD) 2901C microprocessGrs connected in parallel.

I

~L:l 9~32r~3 CPUP 122 performs all CS 101 arithmetic operations under microcode control of CU 104. CPUP 122 includes a random access memory (RAM~, a shift register/buffer, a register file, an ariLhmetic and logic unit (ALU~, and other registers, shifc registers, and multiplexers as needed to perform general purpose data manipulation operations, including arithmetic operationsO CPUP 122 further includes internal microcode control, which receives instruction inputs from US 116. CPUP 122 receives two inputs, AREG and BREG from US 115 microcode con~rol output which selects, for certain operations, source and destination registers in CPUP 122's register file. As indicated in Fig. 6, C~UP 122 has a 32 bit data input connected from D Bus 112 and a 32 bit output connected to Y Bus 124. The circuitry comprising CPUP
122 are commercial].y available components well known to those of ordinary skill in the art, and will not be described ~urther except as required for a more thorough understandiIlg of CS 101 during the following detailed descriptions of other portions of PU 106.
Having described PU 106's CPUP 122, the transmission paths by which information, primarily data s~;3 and addresses, are transferred between MEM 102 and PU
106, and in particular CPUP 122, will be described next below. These transmission paths include MAD ESus 108, by which read and write addresses are provided to MEM 102 by PU 106, and MDA ~U5 110~ by which instructions and data are communicated between PU 106 and M~M 102~
Pa~hs internal to PU 106 include D Bus 112 and Y
Bus 124. As indicated in Fig. 6, MDS 132 is connected between D Bus 112 and MDA Bus 110 and between MDA Bus 110 and Y bus 124. MDS 13~ includes Memory Data Register (MDR) 602, having a 32 bit input connected from D Bu~ 112 and a 32 output connected through buf~er driver MDRB 602 to MDA Bus 110. .~BS 132 also includes Memory Data Latch (MDL) 604, which has 32 bit input connected from MDA Bus ]10 and a 32 bit output connected to Y Bus 124. Finally, PU 106's internal dat2 path further includes NIBS 126, having a 32 bit input connected from ~ Bus 124 and a 32 bit output connected to D Bus 112. MAD 130, comprising PU 106's address output to ~A3 Bus 108, will be discussed separately rurther below, in conjunction with the discussion o~
SPAD 12~.

Considering first data transfers from ME~ 102 to PU
106, data read from MEM 102 appears on MDA Bus 110 and may be received and stored in MDL 604. That data may be then transferred rom MD~ 604 to Y Bus 124, and may then be transferred from Y Bus 124 to NIBS 126.
NIBS 126 is a nibble shifter and i.s capable of either passing data straight through or. performins right or left shifts of data on a nibble by nibble basis.
NIBS 126 is used, for example, to shift data within words received from MEM 102 into differing formats for subsequent operations by CPUP 122. NIBS 126 may, for example, be Eurther used to reorganize data resulting from operations CP~P 122 into formats selected for storing such data in MEM 102~
As previously described, NIBS 126's output is connected to D Bus 112, so that data appearing on Y Bus 124 may be transferred onto D Bus 112, either directly as a straight through-put or after being operated upon by NIBS 126.
As previously described the output of CPUP 122 is connected to Y Bus 12~, so that data generated as a result oE CPUP 122 operations may be transferred, ~ .73 through NIss 126, to D Bus 112. Again, data transferred through NIBS 126 from output of CPUP 122 may be passed directly through NIBS 126 or may be oF~ra~ed upon by NIBS 1260 For example, NIBS 126 may perfor~ ali~nment operations upon data outputs of CPUP 122 in preparation for subsequent write operation to MEM lC2~
Data appearing on D BU5 112 may then be transferred into MDR 602 and subse~uently transferred through ~DRB
603 to M~A Bus 110 and thus written into MEM 102.
Alternately, data appearing on D Bus 11~ may be transferred into CPUP 122's data input. Data appearing on D Bus 112 ~ay also be transferred through Buffer 606 to DBIO 136 for subsequent transfer to external stora9e devices.
Before describing SPAD 128 and MAD 130, two ~urther features asociated with operation of CPUP 122 wi].l be described next. The first is the use of CPUP 122 to perform increment by two operations and the second is the multiple uses of Temporary Register (TREG~ 608, which is bi-directionally connected from ~ Bus 112.
A common operation, for example, in manipulating addresses and other arithmetic operations, is to ~79-I

increment a given number by two. The AMD 2901Cs utilized in CPUP 122 are, however~ not directly capable of performing an increment by two operation. Minus 2 Source ~MINUS2) 610 having an output to D Bus 112, znd a microinstruction sequence Erom US 116, allow CPUP 122 to perform increment by two operations. MINUS2 610 is a source for placing on D Bus 112 a 32 bit number havlng a nu~eric value of minus 2. CPUP 122 contains the number to be incremented by 2 in its register file. It accepts the minus 2 operand provided ~y MINUS2 610~ and compliments it (giving a ~1) and performs an add operation with the number to be incremented to give a number equal to the operand to be incremented plus 1~
At the same time, a plus 1 is ~orced into CPU 122's ~LU
carry input to provide a further plus 1 increment~ The output of CPUP 122's ALU will thereby be the original operand incremented by 2. MIIYUS2 610 thereby allcws CPUP 122 to perform a commonly desired operation not originally provided for by the AMD 2901ccircuits employed therein.
Referrlng now to TREG 608, TREG 608 is a 32 bit shift register which may be used for temporary storage ~8~

of data appearing on D Bus 112, from which TREG 608 is connected by a bi-directiorlal 32 bit bus~ TR~G 608 is further utilized to gene}at:e 32 bit long control word sequences for controlling other operations of CS 101.
Under micxocode control~ a 32 bit pattern of ones and zeros is loaded into TREG 608. That 32 bit pattern is then shifted right or left as necessary to generate bit se~uences which are used, or example, to perfor~ system resets, to Ferform timed input/output operations~ and to control ~uffers for programmed input and ou~put operations. TR~G 608 thereby provides an extended means or controlling certain operations of CS 101 while utilizing already existing circuitry normally intended for temporary data storage functions~
Referring now to SPAD 128 and MAD 130, SPAD 128, having inputs connected from Y Bus 12~, performs address translation and mapping functions as previously described~ SPAD 128, for example, accepts logical addresses from Y Bus 12~ a.nd provides corresponding physical addresses to MAD 130. MAD 130 transfers addresses from SPAD 128 to MAD ~us 108. In addition, MAD 130 operates in coniunction with IPD 114 as a prefetch mechanism by generating and providing prefetch read addresses to MEM 102 through ~AD Bus 108, Referrins first to SPAD 128, the core of SP~D 128 is SPAD Memory (SPADM~ 129 SPADM 129 is a random access memory used in parl by ~U 106 and CS 101 as a scratch pad me~ory. SPADM 129 is further utilized to store address mapping information, and thus is a par~ of CS 101's addressing mechanism. For example, SPADM 129 may be used to store address translation maps for CS
lOl's data channel, burst multiplexer channel, progra~med I/O, through DBIO 136~ SPA~M 129 is also used to store addressing maps for logical to physical address translations. In addition, SPADM 129 contains cs lOl's ~e~lent Base Registers ~SBRs), previously described, and a portion of SP~DM 129 is utllized as accumulators ~or floating point operations.
As indicated in Fig. 6, SPAD 128 includes an internal addressing ~us, referred to as Logical Address ~egister (LAR~ Bus 132, and a data bus, referred to as SPAD Bus 134. L~R Bus 132 is connected f.om Y 3us ]24 through Loylcal Address Register ~I,ARR) 136 and Logical Address Register Multiplexer ~LARM) 138. LARR 136 has a 32 bit output to LAR Bus 132 and has inputs from ~ Bus 124 and from LARM 138.
LARR 136 and LARM 138 are utilized to provide logical and physical addresses to SPAD 128 and MAD 130.
The general format of CS 10115 logical addresses has been previouslv described. In th.ose descriptions, certain bits we~e indicated as representing physical or logical page numbers and paye offsets, while other bits comprise various control fields. As shown in Fig~ 6, LARR 136 has a first 16 bit input connected rom Y Bus 124 for receiving 16 bit ~hysical and logical page ofset fields from Y Bus 1240 LARR 136's second input is connected fro~ LARM 138 and comprises those 16 bits of address used for logical and physical page number fields" various control fields, and also fsr short addresses. LARM 138 includes a first 16 bit input conne~ted from Y Bus 124 to receive, for example, a correspondins 16 bits of page numbe~ field from Y Bus 124 when LARR 136's first input i5 receiving a page offset fieldO LARM 138 further includes 2 inputs to enable varyi~g formats to be selected for bits 0 to 16 of addresses to be provided to SPAD 128. Fox example, ~ ~ ~8~

three bits (CRE~ of each of these two inputs represents which of CS lOl's 8 memory space segments CS 101 is to be addressed by a particular address, while other bits of these two inputs are taken from Y Bus 124.
As indicated in Fig. 6, LARR 136's 32 bit output is connected to L~ Bus 132, whicn in turn ls a source of addresses to S~ADM 129, to CS lOl's address translation unit control, TG 146 and ATC 1~8, and to MAD 13~
A first output of LAR 3us 132 is directly to MAD
130, and in particular to an input of ~AD Multiplexer (MADM) 14~. As will be described further below, MADM
140 is a source-of physical address offset fields for M~D 130's output. LAR Bus 132's output directly to MADM
140 is used, for example, to provlde physical page offsets to MADM 140 when PU 106 is directly physically addressing MEM 102. This path is also used, in furLher example, to provide single and double level page table ofset fields when performing single and double level page table translations of logical to physical addresses~ as previously described.
LAR Bus 132 i.s further provided with a direct path through E~uffer 142 to SPAD Bus 134. As will be :11 9B;~3 described further below, this path may be used to provide physical page number fields directly to Memory Address Latch tMAL) 150 in MAD 130 from ~AP~R 136 in conjunction with the corresponding offset field of a physical address as described above. Finally, will be described further below, SP~DM 129 is proJided with a bi-directional data input/output connection to SP~D Bus 134~ The path cornprising LAR Bus 132, Buffer 142, and SPAD Bus 134 may also be used, for example, to write information, such as adaress maps, into SPADM 129 from LARR 136.
LAR Bus 132 also provides an input into SPAD
Multiplexer (SPAM) 144, which has an address output connected to SPADM l~9's address input (~D). SP~M 144 is the means by which SPADM 129 is addressed for read and write operations. The path comprising L~R Bus 132 and first input of SPAM 144 is used, in part, to address SPADM 129~
SPAM 144 is provided with three further inputs.
Two of these inputs, ACD and ACS, are provided from IR
578 in IPD 114, respectively, a`nd identify destination and source accumulators. ACD and ACS may be used, for 8~,t~

example, in addressing SPADM 129's address locations assigned, for example, as ~loating point accumulators.
SPAM 144's fourth input is connected from UIR Bus 540 in US 116 is used to microinstruction control in addressing SPADM.
The above combination of address sources for SP~M
144 allowsr for example, ACS or ACD inputs to specify a base address in SPADM 129 and VIR microinstruction inputs to specify an offset from such a base address to a floating point source or destination accumulator.
This addressing mode also allows the ACS field of IR 578 -to be determined without performing a mask and shift operation to read ACS field from I~ 578; the information is instead determined from a read from SPADM 129, with the results of such an ACS read indicating the contents of IR 578's ACS field. Microinstruction and IR 578 addressing of SPADM 129 also allows constants to be stored in and recovered from SPADM 129 as required.
Finally, LM Bus 132 provides an output to SPAD
128's address translation control unit, comprising Tag Compare tTC) 146 and Address Translation Control (ATC) 148. TC 146 receives certain portions of addresses $~

appearing on LAR Bus 132 and SPAD Bus 134 and, utilizing this information, generates control inputs to ATC 14~.
A~C 148 has a bi-directional connection to Y Bus 124 to receive address translation control information thererom and to provide such control infor~ation on~o Y
Bus 124 Referring to SPAD Rus 134, as previously described SP~D Bus 134 has a direct 32 bit connection from LAR Bus 1~2 ~hrough Buffer 142 and has a bi~directional 32 bit input/output to SPADM 129~ Certain address fields~ that is, physical page number fields, appearing on SPAD Bus 134 from SPADM 129, or from Buffer 142, may be transferred into Memory Address Latch (~AL) 150 in M~D
130.
Finally, SPAD Bu5 134 has a 32 bit bi-directional input/output connection to D Bus 112 throug~ SPAD Buffer tSPADB) 152. SPADB 152 allows operations to be performed on SPAD Bus 134, for example writing a page number into MAL 150, while leaving D Bus 112 free for other, concurrent operations. SPADB 152 allows information to be transferred between D Bus 112 and SPADM 1~9 or ~C 146. For example, address information may read from SP~DM 129 to D ~us 112, or may be read from D Bus 112 and written into SPADM 129 for example, when loading address maps into SPADM 129. SPADB 152 is particularly used, for example, in floating point operations ar.d fo~ any operation wherein SPADM 129 is being used as PU 106's scratchpad memory, or general registers.
~ aving described SPAD 128, MAD 130 will be described next below.

3~ ~ 95~ 13~
As previ.ously described, MAD 130 is connected from outputs of SPAD 128 and in turn has an output connected to MAD Bus 108. MAD 130 receives physical addresses from SPAD 128 and transfers those physical addresses to MAD Bus 108 to àddress M~M 102 for read and write operations. MAD 130 also operates in conjunction with IPD 114 as an instruction prefetch mechanism by providing instruction prefetch physical addresses to M~M
102.
As also previously described, physical addresses for reading from or writing to M~M 102 are comprised or -8~-~9~

a physical page n~ber field and a physical page ofrset ~ield. As described above, physical pa~e number fields are provided by SPAD 128 to MAL 150 through SPAD Bus 134, either fronl SPADM 12g or from LARR 136 through Buffer 14~. Physical page offset fields are provided to MADM 140 by LARR 136 through the bus connection directly from LAR Bus 132 to an input of MADM 140.
Outputs of MAL 150 and MADM 140 are connected to Memory Addressing Internal (MADI) Bus 154, which is connected in turn through Memory Address Buffer (MADB) 15~ to ~AD Bus 108~ Physical addresses received by MAD
130 from SP~ 128 may thereby be assembled from MAL 150 and MADM 140 onto MADI Bus 154 and trans~erred onto MAD
Bus 108 to address :fEM 102.
That portion of l~A~ 130 which operates as part of CS 101's prefetch mechanism includes Prefetch Page Number Register (PPNR) 158, Prefetch Page Offset Counter (PPOC) 160, and Write Compare (WCOMP) 162. PPNR 158 has an input connected from and an output connected to MADI
Bus 154. PPOC 160 has an input connected from ~IADI Bus 154 and an output connected from PPNR 158 and MADI Bus 154 and provides outputs to IPD 114.

I

An initial physical address, including page number and page offset, from which instructiorl prefetch is to begin is generated by SPAD 128 and is transferred onto MA~I Bus 154. Page number and page offset are then transferred from MADI Bus 154 into, respectively, PPNR
158 and PPOC 160. Thereafter, page cf~set in PPOC 160 is successively incremented and combined, through ~AD~
140, with pase number read from PPNR 158 to provide successiYe instruction prefetch read addresses on MADI
Bus 154 and thus onto MAD Bus 108 to fetch successive double words containing instructions from MEM 1023 Sequential instructions are fetched from consecutive lQ~iç~l pages, thus baxring address j~mps. Consecu~ive loglcal pages need not be consecutlve ~h~i5~1 pages.
PPNR 158 is implemented as a register, rather than a counter, to prevent prefetch from crosslng physical page boundariesO When PPOC 160 overflows, preretch is stopped until PPNR 158 is loaded ~ith a new physical page number, corresponding to the next sequential logical page of execution.
WCOMP 162 checks each physical address to MEM 102 for write operations and compares such addxesses to ,.. . . . . . .

addresses of instructions prefetched by MAD 130 2nd IPD
114. If a write operation is executed to a physical address within the same pase as a prefetched instruction, WCOMP 1~2 provides an output lndicating that the contents of IPD 114 are no longer valid~ CS
101 will respond by reinitlatins prefetch to obtain new valid instructions from MEM 102.
~ escription of a preferred embodiment of the present invention is hereby concluded. The inver.tion may be em~odied in yet other specific forms without departing from the spirit or essen~ial characteristics thereof. Thus, the present embodiments are to be considered in all respects as illustratlve and not restric'ive, the scope of the invention being indicated by the appended claims rather th2n by the foregoing description, and all changes which come within the meanir.g and range of equivalency of the claims are therefore intended to be embraced therein.

Claims

What is claimed is:

1) In a data processing system including processor means for processing said data, memory means for storing said data and instruction for directing operations of said system, bus means for conducting said data and instruction between said memory means and said processor means, external terminal means for providing command for directing said operation of said system, external memory means, and I/O means connected between said terminal means, said external memory means and said bus means for conducting said commands and data between said terminal means, said external memory means and said bus means, microcode control means for providing sequences of microinstruction for controlling said operation of said system, comprising:
kernel microcode memory means responsive to first certain of said instruction and commands permanently-for storing and providing to said system corresponding first certain of said microinstruction sequences for controlling first certain of said operations, writable microcode memory means responsive to second certain of said instruction and commands for storing and providing to said system corresponding second certain or microinstruction sequences for controlling second certain of said operations, and said external memory means for storing an initial copy of said second certain of said microinstruction sequences, said first certain of said microinstruction sequences including microinstruction sequences for (a) controlling said system to read a second copy of said second certain of said microinstruction sequences from said external memory means to memory means, and (b) to read said second copy of said second certain of said microinstruction sequences from said memory means to said writable microcode memory means.

2) The microcode control means of claim 1, wherein said first certain of said instructions comprise an instruction set for an eight bit data processing system and said first certain of said microinstruction sequences allow said system to operate as said eisht bit data processing system, and said second certain of said instruction comprise a second set of instruct;ons comprising an extension of said first certain of said instruction and said second certain of said instruction and said microir.struction sequences allow ,aid system to operate as a si~teen and thirty-t~o bit instruction set.

) The microcode control means of claim 1, wherein said first certain of said command comprise single character commands, and said second set of commands comprise mul~iple character commands~

4) The microcode control means of claim 1, wherein said first certain of said commands include a system reset command.

5. A method of enhancing the operation of a data processing system, the data processing system including:
memory means for storing said data and for storing instructions for directing operations of said system;
external memory means; and microcode control means for providing sequences of microinstructions for controlling said operation of said system, comprising:
kernel microcode memory means responsive to first certain of said instructions and commands for storing and providing to said system corresponding first certain of said microinstruction sequences for controlling first certain of said operations; and writable microcode memory means responsive to second certain of said instructions and commands for storing and providing to said system corresponding second certain of microinstruction sequences for controlling second certain of said operations, and the method comprising the steps of.
initially loading the writable microcode memory means with initial versions of the second certain microinstruction sequences from the external memory means;
in response to the first certain microinstruction sequences, loading the writable microcode memory means with alternate versions of the second certain microinstruction sequences from the external memory means.
6. The method of claim 5, wherein in the data processing system:
said first certain of said instructions comprise an instruction set for an eight bit data processing system and said first certain of said microinstruction sequences allow said system to operate as said eight bit data processing system; and said second certain of said instructions comprise a second set of instructions comprising an extension of said first certain of said instructions, and wherein said second certain of said instructions and said microinstruction sequences allow said system to operate as a sixteen and thirty-two bit instruction set.
7. The method of claim 5, wherein in the data processing system:
said first certain of said commands comprise single character commands, and said second set of commands comprise multiple character commands.
8. The method of claim 5, wherein in the data processing system said first certain of said commands include a system reset command.