CA1198235A - Audio response system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

The system includes a processing section, a computer and an interface circuit. The processing contains components for receiving tone coded messages from a telephone line, transmitting voice synthesized messages over the same line and connecting and discon-necting the telephone line. The interface circuit contains components for transmitting data to and from the computer and controlling the operative state of each component of the processing section. More than one processing section can be controlled by a single interface circuit.

Description

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AIJDIO RESPONS~E SYSTEM
__ 13ACRGROIJND OF rll~ T_O~

Field of the Invention __ ~___ The invention relates to sys~ems designed ~o automatically provide answers to inquiries received over a telephone line and especially to such systems in which the answers are provided in ~he form of an audible human voice response.

There are many situations in which it is desirable to provide an audible human voice re~ponse to inquiries received over a telephone line, These situations include inquiries regarding credit card account balances for point of sale account status checks and other types of credit authorizations, lS t21ephone ordering, stock quotations, locator service~, pay by phone services, home banking and 3~
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check guarantee systems~ In each instance, the information requested can be stored in a computer data bank and can readily he ac~essed by a computer terminal under the direction of a terminal operatorO
A difficulty arises when this information is to be transmitted over a telephone line to a particular requester. The most commonly used method is to have a terminal operator verbally transmit the information.
However, this method can be excessively expensiv~ due to the high cost of labor.
Systems have been sug~ested for eliminating the use of a human operator. For instance, UOS.
Patent No. 4,088,338 to Nakata et al shows a voice response system in which information is fed from i5 telephone lines through a switching network to a receiver. The inormation is fed ~rom the receiver ~o a da~a processor which operates to provide responses.
The responses are fed to a voice synthesizer. Th~
frequency spectrum of the synthesized voice is

2~ flattened for transmission over the telephone lines.
U.S. Patent No. 4,013,838 to Tsai discloses a telephone inquiry system in which an automatic, instant response to a mailbox renter's telephone inquiry can be had, To inquire about a mailbox status, the renter calls a number and u~ses push buttons to anter his mailbox code. The system checks the status of the mailbox in ques~ion and informs the caller vocally by a voice response generator.
U~S. Patent No. 3~800,283 to Gropper shows a 30 I credit verifying unit in which information stored on a credit card i~ read and transmitted to a computer by touch tone signals. The comput~r evaluates the information and transmits a signal which is displayed visually on a terminal at the point of sale.

v U.S. Patent No~ 3,647,972 to ~lover et al shows a portable terminal which generates and transmits selected tones over telephone lines to provide input to a computer.
U.~O Patent No. 3,820,071 to Angus shows a credit card risk evaluation system in which a credit card reader transmits coded information to a central processing unit. The central processiny unit evaluates the information and transmits a signal which is supplied to an audio play~ack device which stores and ~ransmits several recorded messages U.S~ Patent No. 4,023,014 to Goldberg shows a credit card verifier which makes use of a computer for answering questions received over a telephone line in the form of tone signals. The tone signals are co~ve~ted ~o digital signals and the answered questions are converted from digital ~o tone signals and transmitted over the same line.
While the patents discussed above show various substitutes for a human operator, none shows a system which is relatively inexpensive, compact and reliable, and capable of easily interfacing with known computer hardwa~e. Many of the systems require point of sale terminals which greatly increase the cost of the s~stemO Other of the systems are so complex as to require a large start-up cost and high maintenance costs thereby reducing their effectiveness as substi-tutes for human operators.

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An objt~ct of the present invention is to provide an audio response system which is capable of decoding touch tone coded signals containing infor~
mation to be responded to and producing a human voice audio response which can be readily understood.
Another object of the present invention is to provide a relatively inexpensive! system for responding to telephone inquiries, which system includes a hardware oriented line i.nterface system which is easily compatible with known digi~al compu~ers.
A further object of the present invention is to provide an audio response system having a hardware oriented line interface system which can be used in a plurali~y of applications regardless of the data being transmi~ted and received.
Another object of the present invention is ~o provide an audio response system which is hardware oriented and designed such that an.y software required for th~ system can easily be generated by persons wi~h minimal programming skill7 An even further object of the present invention is to provide an audio response system in which all of the hardware for the interface system of one or m~re communication lines can be mounted on a single printed circu.it board.
An even still further object of the presenl-invention is to provide an audio response system which is suficiently inexpensive to manufacture that spare circuit boards containing the interface system hardware can be kept on hand to serve as replacements for mal-functioning circuit boards -thereby substantially reduc-ing the down time of the system due to malfunctions and, at the same time, reducing the level of skill required for on site repair and maintenance personnel.
Another object of the present invention is to provide an audio response system having a hardware oriented line interface system which can be used both remotely as a local concentrator for incoming information or on site at a main switching facility.
In accordance with the above and other objects, the present invention is a system for receiving line signals including tone signals comprising tone coded information re~uest messages from a telephone line, and transmitting synthesized human voice response messages along the same line. The system includes a programmed computer and line control circuit means connected to the telephone line for connecting the telephone line to the system and disconnecting the telephone line from the system and for producing an off hook signal in response to an incoming line signal on the telephone line. Tone decode circuit means are connected to the telephone line for producing digital signals in response to received tone signals, the tone decode circuit means including means for producing a decod~r status signal in response to a received tone signal. Voice synthesizing means are connected to the telephone line for producing a synthe-sized voice signal, the voice synthesizing means including a storage buffer for storing data to be synthesized and means for producing a buffer status signal when the buffer is loaded to a predetermined amount. An interface circuit means establishes communication between the line control circuit means and the computer, between the voice synthe-sizing means and the computer, and between the computerand the tone decode circuit meansw The interface circuit ~ :r, 1~

means includes interrupt circuit means connected to receive the off hook signal, the decoder status signal, and the buffer status signal, and causes an interrupt signal to be transmitted to the computer in response to the off hook signal, the decoder status signal or the buffer status signal. Also included are status check means for storing an indication of the circuit causing the interrupt signal, and a -tone decode interface for receiving digital signals from the tone decode cir~
cuit means and transmitting the digital signals to the computer in serial format. The computer is prograrnmed to interrogate the status check means in response to the interrupt signal and to co~nunicate to the circuit caus-ing the interrupt signal through the interface circuit means to selectively acknowledge an incoming call to the line control circuit means, provide response messages to be synthesized to the voice synthesizing means, and to accept digital signals from the tone decode circuit means through the tone decode interface. The computer is further programmed to determine appropriate respons~ to decoded request messages received through the tone decode inter-face and to load the storage buffer with data representing the response.
In accordance with other aspects of the invention, the tone decode circuit includes structure for producing a decode status signal in response to a received tone signal.
The interrupt circuit is connected to receive the decode status circuit and cause an interrupt signal to be trans mitted in response there-to. The interface circuit also includes a multiplexing control for individually enabling the voice syrlthesiziny circuit or the tone decode circuit.
The multiple~ing control includes a first addressable latch circuit having an enable input and a data input connected to the computer. The latch also has a plurality of addres,sable outputs and a plurality of gate circuits conne!cted to the outputsO The multi-- 6a -ple~ing control also operates a second addressable latch circuit which has an enable input connected to an output of one of the gate circuits and a data input connected to the computer. The second latch circuit also has a plurality of addressable outputs which are connected, respectively, to the line control circuit and the tone decode circuit. Each of the latch eircuits is connected to a corNmon address bus over which the computer sends address codes. The codes are divided into a first set of addresses which operates the first lateh and a second set of addresses whieh operates the second latch as well as interface circuitry for the tone decoder and voice synthesizer.

. ~,;,,~, ~ 7 The interrupt circuit includes a status cheek circuit comprising a clata selector having a plurality of addre~sable inputs connected respectively to receive signals from the line control circuit~
voice synthe~i2ing circuit and tone to code circuitO
The data selector has an enable input connected to the computer and an output connected to the computer. The addressable inpu~s are accessed in accordance with addresse~ received from the computer on the address 10 bus. The addresses are those of the second set of addresses .
The tone decode circuit, ~oice synthesizing circuit and line control circuit :Eorm one processing section ~or one telephone line. Each interface 15 circuit can accommodate more than one procPssing section on a ti.me sharing basis under computer control. The interface circuit and associated processing sections are mounted on a single prin~ed circuit board~ and a plurality of such circuit boards can be connected to a single computer~ Accordingly, as many telephone lines as desired can be easily accommodated by simply duplicating the contents of a circuit board as many times as desired.

~l33 3~583~3~ON ~F TH~ DRAWINGS

The above and other obje~cts of the present invention will become more readily apparent as the invention becomes more fully understood based on the folLowing detailed description, reference being had to the accompanying drawings in which like reference numerals represent like parts throuyhout and in which:

3~i Figure l is a block diagram of the syst2m of the present invention;
Figure 2 is a schematic diagram of a line control circuit of the present invention, Figure 3 is a schema~ic diagram of an interval timer of the presellt invention;
Figure 4 is a schematic diagram of the ~peech synthesizer status regist,er of the present invention;
Figure 5 is a schematic diaqram showing the speech synthesizer circuit and tone decoder circuit of the present invention;
Figure 6 is a schematic diagram of the primary multiplexer circuit of the present invention;
and Figure 7 is a schematic diagram showing the secondary multipl~xer circuit7 interrup~ circuit, ~one decode interface and speech synthesizer interface o the present inven~ion~

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Figure 1 is a bloc~ diagram of the voice rasponse system of the present invention. The system includes a minicomputer lO0 which is preferably a member o the Texas ~nstruments Model 99~ minicomputer familyn In practice, a Model 990,/5 has been used.
Minicomputer 100 may contain system operating software and may be interconnected wlth larger rnain frame computer ~ystems which contain dal:a bases for ~ ~ A

answering inquiries to the system~ Inquiries and responses are received and transmitted, respectively, over telephone lines I and II. The telephone lines enter direct access devices (DAA) 101 and 102, respec~
5 tively. D~As 101 and 10~ are standard FCC approved station couplers. In practice, ~lgin ~lectronics Model ESC20721 station couplers have been used. Of course, any similar device may also be used. D~As 101 and 102 connect to proce~sing sections 103 and 104, respectively. Processing sections 103 and 104 are identical in construction and, ~hus t only the connections between DAA 102 and processing section ln4 are shown for simplicity, it being understood ~hat similar connections are made between DAA 101 and section 103. Processing sections 103 and 104 both interconnect to interface section 105. Thle inter-connections between interface section 105 and processing sections 103 and 104 are similar and, thus, for simplicity, only the interconnections between processin~ section 104 and interface section 105 are shownq Interface section 105 connects through interconnect device 106 to minicomputer 100.
Processing section 104 comprises line control circuit 107 which senses the existence of an incoming call by receipt of an "off hook" signal from DAA 102 on line 136, and controls the status of DAA
102 and telephone line II by signals transmitted on line~ 137 and 138. Incoming touch tone signals are received on line 139 through DAA 102 and decoded in tone decoder 109. Outgoing speech signals are synthesized in speech synthesizer 108 and transmitted through lin~e 139 and DAA 102 to the telephone line.

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Processing section 104 also contains an interval timer 110 which can be used to tirne the duration of various functions5 such as providing a predetermined time period for an incoming call to be processed.
Ultimate control of circuits 107 through 110 is effected by minicomputer 100. Computer 100 outputs signals on a reset line 131 by which all of the circuits of sections 103, 104 and 105 are reset upon start-up. A computer clock signal is emitted on line 127 for controlling timi~g functions and a module selec~ line 126 controls the cperative state of inter-face circuit 105 with which the computer communicates.
Circuit components of circuit 105 are controlled by address bus 132 which contains four address lines and operates in conjunction with data output line 130.
Data being r~ad by the computer is received in serial format on data input line 1~9 while any interrupts generated are received on inter~upt line 1280 Computer control of the sys~em is effec~ed through primary multlplexer 112 which individually enables secondary mui!tiplexer 113, interrupt 116, tone decode interface 118 or speech synthesizer interface 120 as well as controls certain functions o line control circuit 107 and speech synthesiæer 108.
Multiplexer 112 is enabled by a signal through line 126 and operates under control of address information re~eived on bus 132.
Secondary multiplexer 113 is e.nabled by primary multiplexer 11~ and functions under control of addresses received on address bus 132 to control the status of l.ine control circuit 107, tone decode circuit 10~ and interval timer 110. The state of each 3~

of the circuits 107 through 110 is transmitted by a signal on a separate line to interrupt circult 116.
Upon receipt of any status signal, circuit 1].6 outputs an interrupt on line 128 t:o cvmputer 100. Status information concerning the circuit causing the interrupt can be obtain2d by the computer by enabling interrupt cirouit 116 through mutliplexer 112 and accessing various lnput lines under the control of addres~ bus 132. In~ormation ls then sent in serial format by circuit 116 to the computer over input l.ine 129.
Information generated by tone decode circuit 109 is transmitted on data bus 133 to tone decode interface 1180 When enabled by multiplexer 112, decode in~erface 118 transmits the informa~ion in serial format across line 129 in a sequence determined by address bus 132.
Infor~ation can be transmltted to and received from speech synthesizer circuit 108 thsough a data bus 135 which connects to speech syn~hesizer interface circuit 120. Circuit 120 is enabled by multiplexer 112 and receives information in serial format from computer 100 on line 130, which infor-mation is then transmitted t:o circuit 108 in parallel format. Conversely~ parallel information from synthe-sizer circuit 108 is received by circuit 120 and ~ransmitted in serial format along line 129 to computer 100. Circuit 120 operates under the control o addresses on address bus :L32~
';peech synthesizer status circuit 12~ can be interroyated by computer 100 to determine when i.nfor-mation is heing written into or read out of speech synthesizer- circui.t 108.

It should be clearly understood that only one interface CiLCUit lOS is u~ed for both processing section 104 and processillg section 103~ Consequently, each component of circuit 105 performs the same function with respect to section 103 cir~uits as has just been descxibed with re~;pec:t to circuits of section 104. The connectiolls are the same but have been dele ted f or s impl ic i ty .
The basic ope~ation of the sy~tem will now 10 be discussed. When a call is sensed on telephone line II by DAA 102, an off hook ~ignal is transmitted to line s:ontrol circuit 107 on line 13~. Line control 107 then sends a signal to interrupt circuit 116, Circuit 116 immediately transmits an interrupt signal on line 1~8 to computer 100. Computer 100 then interrogates circ:uit 1:16 through mul~iplexer circuit 112 by tran~mission of an appropriate module select signal on line 126, an appropriate signal on bus 132 and a data signal on line 130. Mul~iplexer circui~
112 en~bles the ~tatus check function of interrupt circuit 116 and various inputs to circuit 116 are accessed by computer 112 along address 132. In this manner, compute~ 112 determines that the interrupt was caused by an off hook signal from line control circuit 107. In response, computer 100 then resets line control circuit 107 ~hrough primary multiplexer 112 and secondary multiplexer 113. Secondary multiplexer 113 is enabled by appropriate instructions through primary multiplexer 112. Thereaf ter, secondary multiplexer 113 resets circuit 107 in accordance with an add.re~s on bus 132 a~nd data on line 130 ~

Thereafter, a synthesized message is sent through speech synthesizer circuit 108 for the caller to input the request information. Inormation to be synkhe-sized is inputted to circuit 108 through synthesizer interface 120 which is ~nab:Led by multiplexer 112 and receiv~s the information in serial ormat from computer 100 on line 130. The information is output in parallel format on bus 135 to synthesizer 108, which is also enabled by multiplexer 1120 Information is inputted to circuit 108 one byte at a time and the status o the information being inputted is monitored through status circuit 122. Computer 100 periodically checks circuit 122 which indicates when information is being written into or when information is being read from circuit 108. After the informai:ion to be synthe-sized is written into synthesizer circuit 108, the synthesis process begins. After a predetermined amount of the information has been synthesized, a memory status output signal i5 transmi~ted to interrupt 116 indicating that more speech information should be input to synthesizer 108. The signal produces an interrupt to computer 100 which int~rrogates interrupt circuit 116 to determine the cause of the interruptO Thereafter, additional information to be synthesi2ed is input to synthesizer 108 as discussed above. Synthesizer 10~ can be interrogated by synthesi~er interface 120 whereby information is read through bus 135 to determine when all synthesized speech has been output through line 139. When this is done, interval timer 110 can be started through multiplexers 112 and 113 to provide a predetermined amount of time for request information to be received along the telephone l.ine.

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Incoming request information is in the form of touch tone code pulses which are received by tone decoder circuit 109. Upon receipt of each tone~
circuit 109 outputs a decode status signal to interrupt 116 which transmits an interrup~ signal to computer 100 and is interrogated thereafter. Decoder circuit 109 translates the received tone into a digital number and outputs the number in parallel format on data bus 133. Computer 100 thereafter enables tone decode interface circuit 118 through multiplexer circuit 112. Tone decode interface 118 ~ransmits the digi~al information in serial format along line 129 und~r contro.L o the computer on address bus 132. After the digital numeral is received by computer 100, a signal is transmitted ~o tone decoder circuit 1û9 by appropriate operation of primary multiple~er 11~ and secondary mul~iplexer 113 to clear the decoder. This clear signal resets the tone decoder to prepare it for reception of a further 2 o tone .
After all digital information has been received by computer 100, an appropriate response is ~ransmitted to synthesizer 108 and output as a voice signal along telephone line II. Compu~er 100 monitors the status of synthesizer 108 through interface 1~0 and when all speech signals have been output causes the phone line to be disconnected through line control cir~uit 107.
The individual components of the system will now be discussed.
Figure 6 shows interconnect circuitry 106 and the primary multiplexer circuit 112. In~erconnect circuitry 106 comprises NOR gates 620~ 622, NAND gates 624, 625 and amplifiers 626-631~ Module select line 126 and slock line 127 are connected respectively to NOR ~ates 620 and 622. Interrupt line 128 connects to NAND gate 624 which also rec:eives an enable input on line 611 from integrated circuit 600 o multiplexer circuit 112. Data input line 129 is connected to inverter 650, the output of which connects to N~ND
gate 6250 The o~h~r input of N~ND gate 625 is coupled to module select line 12S such that the data input is disabled when line 12~ is active. Data output line 130, reset line 131 and lines Al through A4 of address bus 132 are connected to amplifiers 626 through 631, respectively.
lS Primary multiplexer 112 contains an 8-bi~
addressable latch circuit which can be, for example, a Texas Instruments type SN54259 integr~ted circuit~
Circuit 600 is a regis~er having 8 addressable outputs connected to lines 604, 606, 608, 609, 610, 611, 224 and 225~ respectively. Circuit 600 also has three latch select inputs which are connected to lines A2, A3 and A4 of address bus 132. A data input is con-nected to line i30, an enable input is connected to line 602 and a clear input is connected to line 131.
At sys~em start-up, circuit 60Q is cleared by a signal on line 131. ~hereaf~er, data on line 130 in the form of a high or low signal is stored and transferred to the output line addressed by the inputs on address bus 132.
Enable line 602 is connected to the output of NAND gate 612 which receives inputs from module sel~ct line 126, clock line 127 and address bus line Al. The output of NAND gate 612 should be low to enable circuit 600~ Accordingly, circuit 600 is r - 1~

enabled whenever module select line 126 is high, line Al is high and clock line 127 goes high. At this time, whatever data is on line 130 is transferred to the output indicated by lines A2 through A4 of address bus 132~
The outputs of circuit 60Q are connected to gating ircuits comprisi~g NAND gates 635 through 643, NO~ gate 633 and inverter 632. Output lines 644 through 646 from NAND gate~ 635 through 637 enable secondary multiplexer circuit 113, the status check function of interrupt circui.t 116 and tone decode interface, respectively. Output lines 511 and 513 from NAND gates 638 and 639 enable the read and write functions of the speech synthesi2er circuit of processing sec~ion 103 while output lines 51~ and S10 fro~ NA~ gate~ 640 and 641 enable the wri~e and read functions o~ speech synthesizer 108 of processing rircuit 104. Output lines 647 and 648 rom NAND gates 542 and 643, respectively, enable the read and write functions of speech synthesizer interface 120.
NA~D ga~e 635 also has an input from clock line 127 and another input fro~ a network co~prising NAND gate 618, MA~D gate 616 and inverter 614. The input to in~erter 614 is from line ~1 and the inputs to N~ND ga~e 616 are from the inverter 614 and from module select line 126. In order for the secondary multiplexer to be enabled, the signal on line 644 must be low. Accordingly, it can be seen that the signal on output line 604 must be high when the module select sign~l on line 126 is high and the signal on line ~1 must go low for the secondary multiplexer to be selected. Conversely, in order for circuit 600 to be enabled, line ~1 must be high at the same time that clock line :L~7 and module select line 126 are high.

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The result of this configuration is that with line Al high, the primary multiplexer i~ enabled and siynals on lines A2 through A4 are used to address an output line of circuit 630. Once a circuit is selected~ line Al is dropped to a low state and addresses on lines A2 through A4 are used to address locations in the circuit selected by the primary multiplexer circwit.
The inpu~s to NA~D gate 636 are ~he same as to NAND gate 635 except the:re is no input from the clock line 127. Accordingly, the status check function of interrupt circuit 116 is enabled each time the secondary multiplexer circuit is enabled except that the interrupt circuit can be enabled whether the clock output is high or low. ~ccordingly, the computer is progra~med 5uch that when the clock output is high, any signals on data input line 129, which may come from interrupt circuit 116, are ignored and the signals are only retrieved when the clock signal is lOwr The inputs to NAND gate 637 consist of output lines 606 from circui~ 600 and ~he output from NAND gate 618. `Accordingly, the touch ~one decode interface circuit is enabled when line 606 goes high after which line Al goes low so that the enabled touch tone decode interface circuit 120 can be operated by address information on address bus 132 lines A2 through A4.
Output line 608 constitutes the control line for the voice synthesizer circuit of processing section 103 and connects to NAND gates 638 and 639.
Line ~09 perorms the s~me function for voice synthe si~er circuit 108 of processing section 104. Line 610 controls the read/write function for the voice synthe-sizer circuits. This function will be d~scribed in detail hereinafter. When li.ne 610 is high9 either the voice synthesizer circuit of processing section 103 or processing section 104 is placed in the read mode, dependlng on whether line 608 or 609 is high.
Conv~rsely, if line 610 is low, the write function of the appropriate sy~thesizer is enabled depending on whether line 608 or 609 is high. An additional output is taken from inverter 632 on line 649. This output serves to disable a buffer in the write portion of speech syn~hesizer interface 120 when read operation is commanded.
NAND gates 642 and 643 each contain an input from NOR gate 6330 The inputs of NOR gate 633 are from lines 604 and 606, respectively. N~D gates 642 and 643 control the write and read functions, respectively, of speech synthesizer interface 120.
Accordingly, NOR gate 633 ensures that both write and read functions are disabled when any one of the secondary multiplexer circuits, the interrupt status check circuits or the tone decode interface circuit is enabled. NAND gates 642 and 643 each also have an input connected to the output of NAND gate 618.
25 Con~equently~ it can be seen ~hat the read function of interfaca circuit 120 is enabled when~ver the output of NAND gate 618 goes high and lines 604 and 605 are low. NAND gate 642 has an additional input from clock line 127. Accordingly, the write function of in~er-fac~ 120 i~ only enabled when the clock input is high.To distinguish between th~ read and write functions of synthesizer interface 120, the computer would only read information received from the synthesizer when the clock :L:ine is low.

'' t-Figure 2 shows line control circuit 107.
Circuit 107 comprises input line 136 from DAA 10~.
Line 136 acts as an input to inverter 200, the output from which enters monostable multivibrator ~02 which is set for a pulse width of 50 milliseconds. The output of inverter 200 also enters inverter 210 and the data input of D-type flip flop 204~ The output is al50 passed along line 206 t:o interrupt circuit 116.
In operation~ when an off hc~ok signal is received on line 136, the signal is inverted in inverter 200 and inverted again in inverter 210. The voltage on line 136 goes low to indicate an off hook condition.
Accordingly, the output of in~erter 210 goes low thus illuminating LED 212 indicating the presence of a call on line II~ The output of inverter 200 is also passed through li~e 206 to interrupt circuit 116 where it acts as a status indicating signal when accessed by the computer, as will be discussed hereinafter~ The output of inverter 200 also initiates operation of MMV
202. When M~V 202 times out, a high signal at the data input of flip flop 204 causes the non-inverting output of the flip flop to go to a low state causing a low signal to be passed along line 208 to interrupt circuit 116 which causes an i.nterrupt signal to be passed to computer 100. MMV 202 and flip flop 204 act as a time delay to compensate for any switch bounce effects which may cause a false interrupt signal. In other words, the off hook signal must remain for at least 50 milliseconds to ensure that L~ iS a true si~nal. After the interrupt signal has been recogni~ed by computer 100, an o~f hook acknowledge signal is returned along line 250 to reset flip flop 204.

Line 218 controls the operat.ion of relay 214 through inverter 216. Relay 214 includes normally closed contacts 215 which ar.e connected by line 137 to D~A 102. In order to disconnect telephone line II 7 compute.r 100 causes a hangup signal to be sent from secondary multiplexer 113 along line 218. The signal causes relay 214 to open contacts 215 thereby disconnecting tne telephone line.
Line 214 is also connected to secondary multiplexer 113. Line 214 operates the contacts of relay 220 through inverter 222~ In the open position, the cont~cts of relay 220 enable DAA 102.
Accordin~ly~ computer 100 can cause D~A 102 to be disabled by energizing relay 220 thus closing contacts 221. Di5abling D~A 102 ensures that no incoming calls on line II will be answered. This function is useful if, for e~ample, the data re~rieval system of computer lt)0 is not operative.
Figure 3 shows interval timer 110. Interval timer 110 is a combination of monostable multivibrator 24t) and D~type flip flop 242. The inverting output of M~V 240 is connected to the clock input of flip flop 242. The outpu~ of flip flop 242 is connected through line 246 to interrupt circuit 116. The timer opera-tion is initiated by a pulse on line 244 which presetsflip flop 242 and trigyers MMV 240.
Figure S shows the circuit configuration for speach syn~hesizer circuit 108 and tone decoder circuit lt)9.

Synthesizer circuit 108 comprises synthe-sizer chip 500 which is a TMS 5200 Voice Synthesis Processor integrated circuit manufactured and sold by Te2as Instruments, Inc. Synthesizer chip 500 can be used with ROM 502 which is a~ TMS 6100 128R bit ROM
manufactured and sold by Texas Instruments, Inc~
Speech data that has been compressed using pitch excited linear predictive coding is supplied to synthesizer chip 500 either by computer 100 or by ROM
502. In the present inventi.on, all speech data is supplied by computer 100. ~owever, ROM S02 is made available for use, if desired.
Speech data can be entered in a memory buffer of synthesizer chip 500 one byte at a time through 8-bit bus 135. Bus 135 is a bidirectional bus and can also be used to read the status of ~he memory buffer. In order to write speech data into the memory buffer, write line 510 must be low and read line 512 must be high~ In order to complete a read operation, line 510 must be high and line 512 must be low. Lines 510 and 512 are operated through N~ND gates 641 and 640, respectively, of primary mu~tiplex~r 112, shown in Figure 6. Dàta bus 135 connects to computer 100 ~hrough speech synthesizer interface 120.
The buffer memory of synthesizer chip 500 is a slow memory and requires wait states to successfully ~complete memory cycles. For this reason, a ready output is provide~ ~his output is connected to line 504~ The ready output gaes high immediately when either line 510 or 512 goes active (low). Line 504 will stay high unt:il synthesizer chip 500 has ~ 22 -established stable data on data bus 135 in the case of the read operation or has completed latching data into the buffer memory from the data bus in the case of the write operationq Line 504 connects directly to speech synthesizer status cir~uit :L~2, shown in Figure 1.
Circuit 122 is interrogated periodically by computer 100 to determine when read and write operations have been completed.
Synthesizer chip 500 also includes an interrupt output connected to line 504. The interrupt output goes from low to high when the bufer memory is half depleted, that is, when half of the information in the buffer memory has heen processed~ A high sta~us on line 504, therefore, indicates that more speech data should be supplied on bus 135. Line 504 connects to interrup~ circuit 116.
The audio output of chip 500 is take on line 514~ ~ine 514 is an input to filter circuit 516.
Filter 516 is an active filter which enhances the high frequency component of the signal and limits the frequency spectrum to 3~8 ~HZo This is the parmissible frequency limit for transmission over telephone lines; ~he output of filter 516 is passed through potentiometer 518 at which the voltage limit of the signal is set at approximately .5 volts, the parmissible voltage limit for telephone lines. Th~
signal is then passed through output line 51g to transformer 522~ Diodes 520 are connec~ed to the line 19 and act as surge suppressing cliodes. The output of transformer 522 is passed through line 139 to DAA 10~, as seen in Figure 1.

~ 23 -Touch tone decode circuit 109 comprises a tone decode integrated circuit 530~ Inte~rated circuit 530 is preferably a dual tone multiple frequency re~eiver Model SSX 201, manufactured and sold by Silicon Systems, Inc. Circuit S30 has an analog input connected to line 533. Line 538 is connected to receive analog touch tone signals rom line 139 thrcugh transformer. 522 and capacitor 539.
Circuit 530 provides digital code in parallel format on an output bus 531 through buffer 532 to bus 133 whieh connects to tone decode interface 118, shown in Figure 1. When a received tone has been decoded by circuit 530, a tone decode status signal is output on line 533 through buffer 532 to line 534 which connects to interrupt circuit 116, shown in Figure 1. The same signal passes through buffer 532 to line 535 which is connected to monostable multlvibrator 540. Monostable multivibrator 540 outputs a pulse which causes LE~ 542 to illuminate!. ~cco~dingly, LED 542 lights each time 20 a tone signal is decoded by circuit 530.
Computer 100 senses the signal on line 534 through interrupt circuit 116 and causes the digital signal on bus 133 to be input to the computer through tone decode interface circuit 118. After each decoded tone is input to computer 1~0, a signal is passed through seconldary multiplexer circuit 113 to line 536 which clears circuit 530 to prepare for the next received tone.
Figure 4 shows the speech synthesizer status 3G circuit L22. Status circuit 122 comprises a data ~ 3 p~ ~ ~D

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selector integrated circuit 400 which may be a Texas Instruments t:ype SN54LS251 integrated circuit. Data selector circuit 400 has inputs connected to lines 128, 409, 410 and 411. Circuit 400 also has data S select Lnputs connected to lines A~, A3 and A4 of address bus 132~ Circuit ~00 causes the information on one of lines 128 and 40g through 411 to be trans-ferred to line 129 connected to the circuit output dependence upon the address on address bus 132. The 10 information o:n the addressed input line i5 transf~rred to output line 129 when the circuit is strobed by a signal on line 412 connected to t.he strobe input.
~ine 412 is an ou~put line from NAND ga~e 408. The inputs to gate 408 constitute address bus line Al and 15 module select line 126. When both of these lines are high~ the strobe input of circuit 400 is actuated~
Input line 409 is directly connected to line 402 from synthesizer circuit 108 shown in Figure 5O
Line 402 is al.so connected to monostable multivibrator 20 404 and monostable multivibrator 406. The outputs of these multivibrators are connectd to lines 410 and 411, respectively. Multivibrator 404 is constructed to produce a 12 microsecond time delay and multi-vibrator ~06 produces a 50 microsecond time delay.
25 Accordingly~ line 409 inputs the signal from line 402 immediately, line 410 inputs a similar signal with a 12 microsecond delay and line 411 inputs a similar signal with a !;0 microsecond time delay. The purpose of the time de:lays is to make the system compatible 30 with various m;Ln Lcomputers.

35 ```
~ 25 -Input line 128 is connected to interrupt circuit 116 and provides an indication to the computer of the existence of an interrupt when lnputs of circuit 400 are being interrogated.
Line 403 shown in Figure 4 comprises an input from processing section 103 having similar conn~ctions as l:hose of line 402 from processing section 104.
Figure 7 shows secondary multiplexer circuit 113, interrupt circuit 116, tone decode interface 118, and speech synthesizer interface 120~
Secondary multiplexer 113 comprises a Texas Instruments type SN74LS259 ~ bit addressable latch similar ~o circuit 600 used in primary mul~iplexer circuit 112. The data input to circui~ 700 i~ taken from line 130 froin computer 100~ The enable input is on line 644 from MAND gate 635 of primary multiplexer 11~ shown in Figure 6. A clear input is taken from reset line 131 from computer 100~ The latch select inputs are connectea to lines A2, A3 and A~ of addre~s bus 132. The outputs include line 536 which is the clear input line for circuit 530 shown in Figure 5 Line 537 makes ~ similar connection i.n procPssing section 1030 Output lin~ 218 transmits a hangup signal to line control circuit 107. Qutput line 219 makes a similar connection in processing section 103.
Output line 244 constitutes the timer start line for timer circuit 110, shown in Figure 3. Line 245 constitutes a similar start line for the timer of processing section 103. Output line 205 constitutes the off hoolc acknowle~dge line used to clear flip 10p 204 in line control c:ircuit 101, shown in Fiyure 2.

3~i ~6 -Line 207 performs a similar function in the line control circuit of processing s~ction 103. As can be easily seen, circuit 700 is enabled by p~imary multiplexer circuit 112 and the data provided on line 130 is latched onto the output line addressed by bus 132 to control the associated circuit components.
Interrupt circuit 116 comprises data selector circuit 702 and NAND gate 7120 Circ~it 702 can be a Texas Instruments type SN74LS251 similar to circuit 400 of speech synthesizer status circui~ 1220 Circuit 702 has an output connected to data input line 129 of computer 100~ A strobe input is connected to line 645 from primary mu;Ltiple~er 112. Lines A2, A3 and A4 of daka bus 132 are connected to the data select inputs of the circuit, Qne of the addressable inpu~s is connected to tone decode inkerrupt line 534.
Line 534 is also an input to NAND gate 712~ ~nput line 531 is connected to a second input of circuit 702 and to a second input o~ NAND gate 712. Line 531 has connections in the tone decode circuit of proce~sing section 103 similar to the connections of line 504 in tone de~ode circuit 109. A th kd input is connected to line 206 ~hirh transmit:s the off hook signal from line control circuit 107. Line 209 is connected to a fourth input and transmits a similar off hook signal from the line control circuit of proc~ssing section 103. Line 208 transmits the off hook interrupt signal from line control circuit 107 and constikutes another input to NAND gate 712. Line 211 serves a similar function w:Lth respect to the line con~rol circuit of processing section 103 and constitutes yet another input to ~AND gate 712~ Line 246 is the output line ~rom timer 110 and provides inputs to circuit 702 and gake 712. Line 248 is the output line from the timer 35~

~ ~7 --of processing section 103. Line 504 is the synth2-si2er interrupt line from synthesizer chip 500 and provides input signals to circui t 7û2 and gate 712 .
Lin~ 505 is a similar synthesizer interrupt line from 5 the synthesizer of processor section 103.
Clearly, a signal on any line connected to NAND gate 7ï2 causes an interrupt siynal to be transmitted along line 128 to computer 100~, The computer then enables circu:it 702 through primary multiplexer 112 on line 645 and s quentially accesses each of the inpu~ lines connected to circuit 702 ~o determine the cause of the interrupt. Onc:e the cause of the interrupt is determined, the computer then ~akes other appropriate action, as discussed above.
TonQ decode interface circuit 118 comprises a data select circuit which can be a ~exas Instruments type SN74LS251 similar ~o circuit 702. The addressable inputs to circuit 704 are connected to two data buses. Four of the inputs ar* connected to data bus 133 which transmits decoded ~one information from tone decode circuit 109 while the other data bus, data bus 134, i5 similarly connected to the tone decode circuit in procèssing section 1.03. The output of circuit 704 is connected to data input line 129 to computer 100 and the strobe input is connected to line 546 ~rom N~ND gate 637 of primary multiplexer 1120 The data select inputs are connected to lines A2, A3 and A4 of data bus 132. Circuit 704 acts as a parallel to serial convexter under control of computer 100. The lines of each data bus 133, 134 are accessed ~equentially thus serially inpu~ting the data on one or both o~ the data buses to the computer under computer control.

Speech synthesizer interface 120 comprises a data selector circuit 706 which is another Texas Instruments typ SN74LS251~ The eight addressable inputs of circuit 706 are connected to data bus 135.
Data bus 135 is connected to speech synthesizer 108 and is also connected to the speech synthesizer of processing section 103. The data select inputs are connected to lines A2, A3 and A~ of address bus 132 and the strobe input is connected to line 648 which is connected to NAND gate 643 of the primary multiplexer circuit. The output of circuit 706 i5 connected to data inpu~ line 129 of computer 100. Circuit 706 acts as a parallel to s*rial converter under control of the computer for serially inputting information to the computer from a speech synthesiz2r during a read mode.
Circuit 120 also includes addressable latch 710 which can be a Te~as Instruments type SN74LS259 integrated circuit. ~he addre~sable outputs of circuit 710 axe connected to the inputs of octal buffer circuit 708 which can be a Texas Instrum~nts SN74LS244 integrated circuit. Circuit 70~ is enabled by a signal on line 649 which causes each input to feed the sign~l thereon to a corresponding output.
The ~utputs of circuit 708 are connlected to respective lines of bus 13S for inputting information to buffer memories in the voi~e synthesizer circuits in parallel format during a wxite operation. Circuit 710 acts in conjunction with circuit 708 as a serial to parallel converter. Speech related in~ormation is presented to the da~a input o~ circuit 710 on line 130 and latched onto the output lines in accordance with addresses received rom lines A2, A3 and ~4 o~ address bus 132.

23~
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The clear input of circuit 710 is connected to reset line 131~ In operation/ inormation is presented on line 131 one bit at a time and latched onto the output lines one line at a time~ When all eight output lines have the appropriate information latched onto them, buffer 708 is activated to transmit the information in parallel along bus 135 ~o the appropriate syn~hesizer circuit.
The complete operation of the system should be apparent ~rom the foregoing description. However, in order to ensure an understanding of the invention, a detailed description of the major functi3ns of the system will now be made~

Referring irst to Figure 1, an incoming call on line II causes an off hook signal to be transmitted along lina 136 from DAA 102. Figure 2 shows that the signal on line 136 causes LED 212 ~o be lit. The signal is passed along line 206 to circuit 702 of interrupt circuit 11~. The siynal is also delayed in time by operation of ~MV 202 and flip flop 204 and passed along line 208 to NAND gate 712 of interrupt circuit 116. Interrupt circuit NAND gate - 712, shown in Figure 7, passes an interrupt signal on line 1~ through NAND gate 624 of Figure 6 to compu~er 100 in re5pon~e to the delayed signal on line 208. At this time~ NAND gate 6~ has been enabled by a high outpu~ from circuit 600 on line 611 by a previous operation. Computer 100 responds by outputting signal9 to ;Lines 126, and Al which cause circuit 600 of primary multipLexer 11~. to be enabled upon the next occurrence of a high clock pulse on line 127. At the same time, data is passed along line 130 from the computer and lines A2 r A3 and A4 of data bus 132 are activated so as to latch the data onto line 604 5 causing that line to go high. Line Al is then dropped to a low state causing circuit 600 to be disabled and the output of NAND gate 618 to go high thus passing a low signal along line 645 to the s~robe input of ci~cuit 702 in Figure 7 . At this time, lines A2 A3 and A4 of address bus 132 are actuated to sequentially access each of the input lines to ci~cui~
702. This procsdure continues until the off hook signal on line 206 is detected thus indicatiny to ~he computer that a call is present on telephone line II.
15 It should be noted ~hat the computer reads information from line 129 during a low state on clock lin~ 127.
During the next high state of clock line 127, circuit 700 of secondaxy multiplexer 113 is enabled through line 644 from NAND gate 635 of the primary multiplexer 20 ~Figure 6) because all inputs of circuit 635 would then be high. With circuit 700 enabled9 data is tran~mit:ted along line 130 and latched onto output line 205 by the computer sending the appropr iate address signal on bus 132.. This signal is an off hook 25 acknowLedge signal which is received by flip flop 2û4 of line control circuit 107 (Figure 7) ~hus clearing the flip flop and removing the si~nal from line 208.

Voice data is generated in computer 100 (Figure 1). The computer initially enables circuit 60Q (Figure 6) as discussed above and causes lines 604 and 605 to go low thus makiny the output of NOR gate 633 high. This output is an input to NAMD gates 642 and 643O Line Al is droppeld low by the computer thus causing the output of NAND gate 618 to go high making ~he second input of NAND gates 642 and 643 high~ Upon a hiqh clock pUlSQ on line 127, the output of NAND
gate 642 Gauses line 647 to go low ~hus enabling circuit 710 (~îg~re 7). Upon each such transition of the clock pul~e~ one bit of inEormation is transmitted to one of the output lines of circuit 710.
The peech information yenerated in ~he computer is transmitted one bit at a time along line 130 to the data inpu~ of circuit 710. The correct output line for that data bit is addressed by bus 132. Once all of the ou~put lines have the correct data bits latched onto them, the computer causes output lines 60g and 610 of circuit 600 ~Figure 6) to go high thus sending a low signal along line 512 and a high signal along line 510 to synthesi~er chip 500 ~Figure 5~ thereby enabling the write func~ion on that chipr At the same time, due to the high signal on line 610, line ~49 goes low to enable buffer 708 (Figure 7) which then outputs in parallel format the byte of information recei~ed from circuit 710. This in~ormation is transmitted along bus 135 to circuit 500 into which the information is written. Clearly, the same opera~
tion wauld apply or writing information into the synthesizinlg circuit oE section 103 ~Figure 6) except that the signals on lines 511 and 51~ would b 3~

controlled to place that synthesizer in the write mode. While the information is being written, rircuit 500 outputs a signal on line 506 which is inverted and passed along line 402 to status check circuit 122 (Figure 4~. The signal is presented directly on line 409 to circuit 400 and is delayed in cirsuits 4a4 and 406 and presented respectiv~ly on lines 410 and 411. Computer 100 raises line Al high again and interrogates the appropriate input line to circuit 400 through lines A2 9 A3 and A~l of data bus 13~ to determine the presence of a signal. These interrogations are conducted on a low state of clock line 127 so as not to inadvert~ntly enable circuit 600 of the primary multiplexer. As long as a signal i9 received from circuit 400, the computer remains idle waiting for the write function to be completed. As soon as the write function is completed, a second byte of inormation is written into the buffer memory o synthesizer circuit 500 in the same manner as the previous byte. The information continLes to be inputted one byte at a time until the buffer is loaded.
Synthesizer chip 500 outputs audio signals in response to the written information. The signals are sent through line 514, filter 516 and potentiomenter 518 to transformer 522 and output line 139 to DAA 102 and telephone line II. When the buffer memory has been depleted by one-half o~ the stored information, a signal is passed from synthesizer circult 500 along line 504 to interrupt circuit 116, ~Figure 7). The signal on line 504 .immediately causes an interrupt signal to be passed along line 128 to computer 100 which then interrogates circuit 702, as discussed above, to determine the cause of the interrupt. Once determined, the computer again inputs speech information to synthesizer chip 500 one byte at a time as discussed above~
In order to determine when all the stored information has been prvcessed and output on line 514 by circuit 5~0~ computer 100 enables circuit 600 (Figure 6) of the primary multiplexer as discussed above. The computer then causes lines 604 and 606 to go low thus sending a high .signal to gates 642 and 643. The f-omputer also causes line 609 to go high anld line 610 to go low. Buer 708 (Figure 7) is disable,d by the signal on line 649 which is the low si~nal fro~m line 610 inverted by inverter 632. The read ~unction of synthesizer circuit S00 (Figure S) is enabled by a low signal on line 510 and a high signal on line 512 produced by lines 609 and 610. Computer 100 th n drops line Al low causing the output of gate 618 (Figure 6) to go high thus producing, with the output of gate 633, a low output on line 648~ This enables the read fu~c ion of synthesizer interface 120 ~Figure 7) by enabling circuit 706, When in the read mode, circuik 500 sends data in parallel format on bus 135.
This data indicates the amount of speech information remaining to be synthesized. This data is read by computer 10~ which sequentially addresses each input of circuit 706 such that the data on bus 135 is serially output along line 129. It should be noted that ~his accessing takes place during low cycles of clock line 127 so as not to inadvertently operate circuit 710.
W'hile circuit 500 is outputting data onto bus 135, a signal i5 passed along lines 506 and 402 to circuit 400 (Figure 4). rrhis signal i3 sensed by computer 100 which waits until all data is output before performing its next function~

3~

Tone signals are received on line 139 shown in Figure 5 and transmitted through line 53a tc) the input of circuit 530. As soon as a tone signal is received and decoded, an output is transmitted along line 533 to lines 534 and 535~ The signal on line 535 causes LED 542 to light while the signal on line 534 causes an interrupt ~o be generated through NAND
gate 71~ and line 128, ~Figure 7). Computer 100 receives the interrupt and interrogates circuit 702~
as discussed above, to determine that the cause of the interrupt is cir~uit 530. ~rhe computer then enables circuit 704, ~Figure 7), through the primary multiplexer (~igure 6) by enabling circui~ 600~ as discussed above, and causing line 606 to go high.
Line Al is then dropped to the low ~tate causing the output of NAND gate 618 to go high and thus causing line 646 to go low. The decoded information in circuit 530 ~Figure 5) is passed through bus ~3 ~ and buffer 53~ to bus 133 which connects to four of the input~ of circuit 704 (Fiyu.r~ 7). The computeE
addres5es each o~ these inputs sequentially by appropriate addresses on address bus 132. As 500n as the decoded information i5 ;serially inp~tted to the computer, circuit 700 is enabled by the primary multiplexer, as discussed above, and a signal is caused to be sent on line 536 to clear circuit 530.
Each recei~ed tone is thus decoded and transmi~ted serially tv the computer.

Line ~a~5L~? O~ tlon When all information has been received and/or transmitted, computer 100 disconnects the ~ `'~

appxopriate telephone line by enabling circuit 700 (Figure 7) of secondary multiplexer 113, as discussed above and causing a signal to be transmitted along line 218 causing relay 214 ~Figure 2) to open contacts 215.
The above clescription is considered to be illustrative of the i.nvention but should not be considered to limit t:he scope thereof. Additional modifications, additions ancl other changes can be made to the invention as would be obvious to one of ordinary skill in the art without depar~ing from ~he scope thereof as .se~ forth in the appended claims.

Claims (18)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A system for receiving line signals including tone signals comprising tone coded information request messages from a telephone line, and transmitting synthesized human voice response messages along the same line, comprising:
a programmed computer;
line control circuit means connected to said telephone line for connecting said telephone line to said system and disconnecting said telephone line from said system and for producing an off hook signal in response to an incoming line signal on said telephone line, tone decode circuit means connected to said telephone line for producing digital signals in response to received tone signals, said tone decode circuit means including means for producing a decoder status signal in response to a received tone signal;
voice synthesizing means connected to said telephone line for producing a synthesized voice signal, said voice synthesizing means including a storage buffer for storing data to be synthesized, and means for produc-ing a buffer status signal when said buffer is loaded to a predetermined amount;
interface circuit means for establishing com-munication between said line control circuit means and said computer, between said voice synthesizing means and said computer, and between said computer and said tone decode circuit means, said interface circuit means including: interrupt circuit means connected to receive said off hook signal, said decoder status signal, and said buffer status signal, and causing an interrupt signal to be transmitted to said computer in response to said off hook signal, said decoder status signal or said buffer status signal, status check means for storing an indication of the circuit causing said interrupt signal, and a tone decode interface for receiving digital signals from said tone decode circuit means and trans-mitting said digital signals to said computer in serial format, said computer being programmed to interrogate said status check means in response to said interrupt signal and to communicate to said circuit causing said interrupt signal through said interface circuit means to selectively acknowledge an incoming call to said line control circuit means, provide response messages to be synthesized to said voice synthesizing means, and to accept digital signals from said tone decode circuit means through said tone decode interface, said computer further being programmed to determine appropriate res-ponses to decoded request messages received through said tone decode interface and to load said storage buffer with data representing said response.

2. The system as set forth in claim 1, wherein said interface circuit means includes multiplexing control means for enabling individually said voice synthesizing circuit means or said tone decode circuit means.

3. The system as set forth in claim 2, wherein said multiplexing control means includes a first address-able latch circuit having an enable input and a data input connected to said computer and a plurality of addressable outputs, and a plurality of gate circuits connected to said outputs.

4. The system as set forth in claim 3, wherein said multiplexing control means further includes a second addressable latch circuit having an enable input connected to an output of one of said gate circuits, a data input connected to said computer and at least two addressable outputs connected to said line control cir-cuit means and said tone decode circuit means, respect-ively.

5. The system as set forth in claim 4, wherein said first and second addressable latch circuits are connected to a common address bus from said computer, said outputs of said first latch circuit being addressed by a first set of addresses on said bus, said outputs of said second latch circuit being addressed by a second set of addresses on said bus.

6. The system as set forth in claim 5, wherein said status check means comprises a data selector cir-cuit having a plurality of addressable inputs connected to receive said off hook signal, said decoder status signal and said buffer status signal, respectively, an enable input connected to an output of one of said gate circuits, a data output connected to said computer, and address inputs connected to said address bus, said inputs being addressed by said second set of addresses.

7. The system as set forth in claim 1, wherein said voice synthesizing means includes a synthesizing circuit having a memory, and a plurality of data termin-als for writing information to be synthesized into said memory, and reading information out relating to the status of said memory, and said interface circuit means includes a synthesizing interface containing a serial/
parallel converter for transmitting information from said computer to said terminals and a parallel/serial converter for transmitting information from said terminals to said computer.

8. A system for receiving line signals containing tone coded information request messages on at least two separate telephone lines and producing human voice res-ponse messages on the same lines, comprising:

a programmed computer, a first telephone line, a second telephone line;
a first processing section containing circuit means for processing signals received on said first telephone line, said first processing section including a first line control circuit means for producing a first off hook signal in response to a line signal on said first line;
a second processing section containing circuit means for processing signals received on said second telephone line, said second processing section including a second line control circuit means for producing a second off hook signal in response to a line signal on said second line;
each of said processing sections containing a separate tone decoder circuit for outputting digital codes in response to received analog tones, and voice synthesizer means for outputting synthesized human voice signals in response to data from said computer; and interface means connected to said first and second processing sections and to said computer for providing communication between said first and second processing sections, respectively, and said computer, said interface means including interrupt processing circuit means for receiving status indicative signals including said first and second off hook signals, respectively, from said first and second processing sections, and outputting an interrupt signal to said computer in response to said status indicative signals, said interface means including status indicator means for maintaining data indicative of the source of said interrupt signal;
said computer being programmed to interrogate said status indicator means in response to said interrupt circuit to determine the source of said interrupt signal and establish communication through said interface means with the processing section causing said interrupt signal.

9. The system as set forth in claim 8, wherein said interface means comprises a control section and status read/write section containing elements having addressable terminals said elements being connected to a common address bus from said computer, said control section being constructed to respond to a first set of addresses on said bus and said status read/write section being constructed to respond to a second set of addresses on said bus.

10. The system of claim 9, wherein said status read/write section contains a plurality of elements, each of which is constructed to respond to said second set of addresses, said control section being constructed to individually enable each element of said status read/write section in response to addresses of said first set.

11. The system of claim 10, wherein one element of said status read/write section is a status read circuit having inputs for receiving said status indicative signals from said first and second processing sections and being responsive to said addresses of said second set to transmit the signal on each input to said computer, when enabled by said control section.

12. The system of claim 10, wherein one element of said status read/write section is a status write circuit for controlling the status of said first and second pro-cessing sections, said status write circuit having a data input for receiving a data signal from said computer and transmitting said data signal to one of a plurality of outputs in response to addresses of said second set, when enabled by said control section.

13. The system as set forth in claim 12 or 8, wherein each tone decoder circuit outputs a signal responsive to a tone being received, which output signal is one of said status indicative signals.

14. The system as set forth in claim 12 or 8, wherein said voice synthesizer means contains a memory for storing said data from said computer and contains a status output for producing a status output signal when said memory is depleted by a predetermined circuit, said status output signal being one of said status indicative signals.

15. The system as set forth in claim 8, wherein each processing section contains a line control circuit for outputting an off hook signal in response to a telephone line signal, each off hook signal being one of said status indicative signals.

16. The system as set forth in claim 15, wherein said line control circuit contains a timing circuit for indicating the duration of a signal.

17. The system as set forth in claim 8, wherein said first processing section, said second processing section and said interface means are all contained on one printed circuit board.

18. A system for receiving signals from a telephone line including analog tone coded information request signals, processing said signals received on said tele-phone line and producing a human voice response signal on said telephone line, comprising:
a stored program computer;
a processing section connected to receive signals from said telephone line and containing a line control circuit for connecting or disconnecting said line, a tone decoder circuit for outputting parallel format digital codes in response to received analog tones, and a voice synthesizer circuit for outputting synthe-sized human voice signals in response to parallel format input data, said tone decoder circuit and said voice synthesizer circuit including means for producing, respectively, first and second status indicative signals representing an operational condition, res-pectively, of said tone decoder circuit and said voice synthesizer circuit; and interface means for providing communication between said processing section and said computer, said interface means including interrupt processing circuit means for receiving said status indicative signals from said processing section, and outputting an interrupt signal to said computer in response to said status indicative signals, said interface means further including means for storing data indicative of the circuit causing said interrupt signal, and said interface means including serial-to-parallel converter means for converting serial format data to parallel format data for said voice synthesizer circuit and parallel-to-serial converter means for converting parallel format data from said tone decoder circuit to serial format data for said computer;
said computer being programmed to interrogate said storing means and communicate with the circuit indicated by said storing means as causing said interrupt signal, said communication including receiving data from said tone decoder circuit through said parallel-to-serial converter, and passing data to said voice synthesizer through said serial-to-parallel converter.