CA1198521A - Structure of an access point toward a data pack broadcasting network - Google Patents

Abstract

ABSTRACT OF DISCLOSURE

The structure of an access point to a data packet broadcasting network comprises a plurality of couplers (Cx), a buffer memory (MTP) and a central control unit (MPC) interconnected by a main bus (MB).
Each coupler (Cx) is connected to a plurality of data sources. The buffer memory (MTP) is connected to a transmission equipment of the data packet broadcasting network. Each coupler (Cx) includes a dual access (MCx), a microprocessor (MUPx), a read only memory (ROMx), a plurality of access circuits (CAS1-CAS4 and CAP1-CAP4) each connected to a data source, a local bus (Bx). In each coupler there is stored, in addition to the coupler control software, a set of subroutines for exchanging information with the buffer memory (MTP).
The memory of the central control unit (MPC) stores the connection table relating to the established time-division switched connections between the couplers (Cx) and the buffer memory (MTP) as well as the subroutines of the interconnections established between every coupler and the data sources connected thereto.
Each coupleur (Cx) still includes a local access circuit (CALx) between the dual access memory (MCx) and the local bus (Bx), and a general access circuit (CAGx) between the dual access memory (MCx) and the main bus (MB), the local access circuit (CALx) and the general access circuit (CAGx) being controlled by a control circuit (CGMx) connected to the main bus (MB).

Description

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01 ~rhe present invention relates to the 02 structure of an access point toward a data pack 03 broadcasting network and, more particularly, to a DIDON*
04 broadcasting network.
05 A data pack broadcasting system with its 06 various embodiments has been described in the IJS patents 07 4,0S8,830 and 4,115,662. Such a system has been 08 implemented by the French public broadcasting company 09 "Télédiffusion de France" and is known as the "DIDON
system".
11 In the article "Construction d'un reseau de 12 diffusion de données par paquets: le point d'acces 13 DIDON", published in ~he technical review 14 "Radiodiffusion-Television" ~o. 60, november-december 1979, by Y. ~oirel the analysis of the recent and 16 desired development of the video-data multiplexing 17 equipments is made with the conclusion that the access 18 to the DIDON system, input and output, should be 19 processed through a special coupler mounted within a switching node, called ~'access point", which es~ablishes 21 a number of connections between a set of inputs and a 22 set of outputs. In particular, in this article an 23 access point is described which comprises a set of 24 network couplers, a DIDON system coupler, a main memory and a central unit which are connected through a bus of 26 the "multibus type". In addition to the coupler control 27 software, a number of subroutines are established in

2~ each network coupler for allowing the exchanges with the 29 main memory. The inter-network communications are established through virtual channels. The main memory, 31 wherever the transmitted data are stored, comprises a 32 connection table describing the connections established 33 through the virtual channels.
34 A purpose of the present invention is to provide an access point .structure which may be used in 36 the trans-mitting equipments o~ such a data broadcas-ting 37 * trade mark

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01 network.
02 It will be reminded that a data broadcasting 03 network should be able to serve a number of sources in a 0~ time-division mode. The sources may have very different 05 characteristics with respect to their through-puts and 06 their intelligence. For some sources, it is necessary 07 to control high-level protocols such as X25 for 08 instance, while for others a buffer memory is needed in 09 the broadcasting networX for cyclically broadcasting ~heir messages. Finally the number of the sources to be 11 connected at a particular si-te of the broadcasting 12 network may vary within a large range.
13 According to a feature of the invention, a 14 shared intelligence access point structure is provided, which comprises a number of modules connected through a 16 bus, the modules comprising a central processing module 17 for insuring in par~icular the general functions of the 18 central of the o~her modules, a multiplier module for 19 acquiring the data packs formed in the various ne~work access couplers, an inser-ting-modulating module directly 21 connected to the output of the multiplexer module while 22 insuring the matching to the broadcasting network, and a 23 control and supervision organ.
24 According to another feature of the invention, the access point comprises a plurality of 26 couplers, a buffer memory and a central control unit 27 which are connected through a bus, each coupler being 28 connected from a plurality of data sources, the buffer 29 memory being connected to a transmission equipment of the broadcasting network, a set of subroutines being 31 stored in each coupler in addition to its control 32 software for allowing the exchanges with the buffer 33 memory, the memory of the central control unit 34 containing the connection table describing the connections which are established between the couplers ~19~35~.~
01 and the bufer memory in a time-division mode, as well 02 as, ~or each coupler, the subroutines oE the 03 interconnections between said coupler and the sources to 04 which it is connected from.
05 In general, the invention i5 an access point 06 structure for a network which broadcasts data packets, 07 the access point comprising a plurality of coupler 08 circuits, buffer memory circuitry, and central control 09 circuitry all being interconnected by a main bus;
circuitry for coupling the buffer memory circuitry to 11 data packet transmission equipment of the broadcasting 12 network, each of the coupler circuits including dual 13 access memory circuitry, microprocesssor circuitry, and 14 a read only memory circuit, and a plurality of access circuits all being interconnected by a local bus, each 16 of the access circuits being connected to a data source, 17 circuitry in each of the coupler circuits for storing 18 couplar control software and a set of subroutines Eor 19 exchanging information with -the buffer memory circuitry;
and switching memory circuitry in the central control 21 circui-try for storing a connection table relating to a 22 sequence for establishing time-division switched 23 connec-tions between the coupler circuits, and the buffer 24 memory circuitry, and for storing subroutines for controlling interconnections between each coupler 26 circuit and its associated data source.
27 The ahove mentioned features of th~ present 28 invention as well as others will appear more clearly 29 from the following description of a particular embodiment, said description being made in conjunction 31 with the accompanying drawings, wherein:
32 Fig. 1 is the block-diagram of an access 33 point according to the invention, 34 Fig. 2 is -the block-diagram of a coupler shown in Fig. 1, 36 Fi~o 3 is the block-d:iagram of the 37 multiplexer showrl ln Fiy. l, 3~3 85Zl 01 Fig. 4 is the bloc~-diagram of the modulator 02 shown in Fig. 1, 03 Fig. 5 is the hlock-diagram of the control oryan 04 shown in Fig. 1, 05 Fig. 6 is a schematic diagram illustrating the 06 operation of the access point shown in Fig. 1, 07 Figs. 7-13 illustrate the control modes soEtware 08 of the access point shown in Fig. 1, 09 Figs. 14-20 illustrate the software of the central processor shown in Fig. 1, and 11 Figs. 21-30 illustrate the software of a coupler 12 shown in Fig. 1.
13 The access point shown in Fig. 1 comprises a 14 central processor MPC, a multiplexer MX, a number of access coupler Cl-Cn, a bus MB interconnecting those 16 circuits, a control and supervision organ OCC connected 17 tG the processor MPC, and an inserting-modulating 18 circuit MOD mounted between the multiplexer MX and the 19 used broadcasting network. In practice, a printed circuit card is provided for each circuit MPC, OCC, MX, 21 Cl-Cn and MOD.
22 The bus MB is of the MULTIBUS type manufactured 23 by the US company INTEL*.
24 An input coupler Cx is shown in Fig. 2.
Physically, it is an eight input microcomputer type 26 card. The eight inputs comprise four series inputs ESl 27 ES4 and four parallel inputs EPl EP4. The series inputs 28 ESl ES4 comply with CCITT standard V24 of CCITT, while 29 parallel inputs EPl EP4 comply with the data processing liason described in the French Patent 2,268,308.
31 The coupler Cx comprises a double access shared 32 memory MCx, a microprocessor MUPx, a random access 33 memory RAMx, a read only memory ROMx, an interrupt 34 circuit INTERx, a clock CLx, a number of contacts SWx, a number of series access circuits CASl CAS4 respectively 36 * trade mark 37 - 3a -sz~

connected to the series inlu1i E~] ES4, and a number of parallel access circuits CAPl CAP4 respectively connected -to the paral~el inputs EPl EP4. The shared memory MCx is associated with a loca~
access circuit CALx and a general access circuit CAGx. Toward outside (with respect to memor MCx), the circuit CALx is connected to the other circuits of the coupler through a local bus Bx while -the circuit CAGx is connected to the multibus ~B. Toward inside, circuits CALx and CAGx are conventionally connected to the memory MCx. Finally, the respective control inputs of the circuits CALx and CAGx are connected to the corresponding outputs of a control circuit CGMx which is itself connected to the multibus MB.
Thus, the memory MCx may be either addressed by the processor MUPx through the bus BX and the circuit CALx, or by any other processor of the other modules of the access point through the multibus MB. In the latter case, the coupler is operating in slave mode. In addition, the circuit CAGx allows the coupler to access also to the multibus in master mode for accessing to external ressources, such as memories or input/output devices.
The interrupt circuit INTERx makes it possible to detect a incoming data on one of the eight access ESl-ES4 and EPl-EP4. The clock CLx generates the bit frequencies needed for the operation of the series inputs ESl to ES4. The group of microcontacts SWx allows to change at will the operation parameters of the series inputs ESl to ES4, such as the length of the characters , the number of elements STP, the parity.
The internal random access memory RAMx is used f`or storing the coupler data which are purely local, thus preventing the shared memory MCx from being unnecessarily charged, the memory MCx being thus only assigned to the data to be transferred through the multibus MB.
The software stored in a coupler will be described in details in the following.

By way of illustratins purposes, a coupler card is preferably made by using the circuits Ii~TEL ~325l for CAS1 CAS4, the circuits LATCH 74LS374 for CAP1 CAP4, a circui-t INTEL 80~5 for MUPx, a 2K octet mernory llM6116 for RAMx, two 4K oc-te-t memory circuits 2732 for ROMx, a circuit INTEL ~2~9 for INTERx, a circuit INTEL 8253 for CLx, two 4K
octet memory circuits Hi~16116 for MCx, a circuit 74LS240 for CALx, a circuit INTEL 8286 for CAGx, a circuit INTEL 8219 for CGMx, and switches AMP for SWx.
The multiplexer MX is snown in Fig. 3. It is a non-intelligent circuit without any processor.
The multiplexer MX comprises an access eircuit CA used as an interface between the multibus MB and a local bus BMX, a simultaneous eontrol cireuit CGMX connected to MB and CA, a pack buffer memory MTP
whieh is assoeiated to a wri-te access circuit CA and a series/parallel converter P/S of which the input circuit is used as a read access circuit for the memory MTP. It also comprises a memory direct access circuit CADM, page address registers RAP and octet address registers RAO, a stroke memory MF, a eontrol eireuit PROT and a cloek CLMX. The bus BMX intereonneets the eircuits CA, CAE, CADM and the memory MF.
The memory MF controls the circuit CAE and the converter P/S. The circuit PROT is eonnected to the memory MF and the converter P/S.
The basic function of the multiplexer MX is to operate as a buffer memory between couplers C1 Cn and the modulator MOD. If the transmission support of the network is a TV public broadcasting network as hereinabove mentioned, the multiplexer has specific eharaeteristies whieh will be mentioned hereinafter.
The DIDON paeks previously formed in one or more of the couplers C1 Cn ean be read into the rnultip1exer, through the memory direct access circuit CADM associated with the central circuit CA of -the multibus MB. So it can access to the bus MB in master rmode for generating the memory addresses corresponding to -the location of the packs in the couplers Cl Cn.
The mernory MTP is arranged in pages the prograrnmable size is adjusted with res;,eet: t.o thc size of Ihe ~roadcasted packs. The memory MTP is a double access nlemory, one for the write mode controlled by the memory direct access circuit CADM through CAE, the o1,her for the read mode controlled by a dispatch boolean circuitry compri.sing -the group of circuits MF and PROT.
The pack buffer mernory MTP is addressed at two levels:
- a page selection level: at any tiMe in the register ~AP, the number of the last written page and the one of t}~e last read page are marked by pointers~
- an octet level in the page: in RAO, an index operates both in write and read phases.
The pack dispatch boolean circuitry is provided for the use of the DIDON network on a video support. It i.s necessary that the packs can be inserted on one or several selected previously l.ines in each TV
frame. Furthermore, within a line, it is necessary that the pack can be inserted at a precise time corresponding to the beginning of the active line.
To this end, the central circuit PROT insures the central of the protocol with the modulator MOD, the latter allowing to acquire the insertion time sl.ots. The number of the TV lines for which the data insertion is authorized are stored in the stroke memory MF. The memory MF may be programmed from the central processor MPC through the multibus MB. Readout of the buffer memory ~STP is authorized by the memory MF only at the times for which the latter has beel1 programmed.
Readout of a pack is indeed started by the dispatch boolean circuitat a precise time provided from the modulator MOD, of course when the memory MTP is no-t empty. The data read out from memory MTP are arranged in series in the converter P/S the output of which is connected to the modulator MOD. The da-ta are supplied from the converter P/S at a bit frequency which is determined by the clock CLMOD of the modulator. I'he internal clock CLMX of the mul-tiplexer may be used in case the clock CLMOD is defective.

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Tile (>utput of the conver~r ,'/S is connec'~ed to the modulator MOD through the connection EU. Two inputs A~E and ENV and an output DPE of the circuit P~OT are connected to the corresponding outputs and input of the modulator MOD. The signal AUE: "transmission authorized"
received at input AUE indicates to the circuit PROT -that the circuit ~OD is ready to receive a transmission demand. The signal DPE:
"transmission demanded" formed on the output DPE is the answer from the circuit ~X to the signal AUE and indicates that the multiplexer has data to be transmitted. The signal ENV: "send data" received on the input ENV is the logical effect of the dialogue AUE-DPE and invites the multiplexer MX to transmi-t.
~ y way of illustration purposes circuits CG~, CADM, ~TP, MF, RAP, RAO, CA, CAE, P/S and PROT are preferably and respectively made with the circuits INTEL 8218, ~237, HM6176 (four 2K octet circuits), 2125, 74LS150, 74LS491, INTEL 82~6, S2~6, 74LS166 and 74LS74.
The general function of the modulator MOD shown in Fig. q is to adapt the data supplied by the multiplexer MX to the transmission support which, in this case, is a video signal.
The video input EV of the modulator, which is connected from the output of a video genera-tor such as a TV camera, is connected to an amplifi.er A1 on one hand, and, on the other hand, to the input of an separating circuit SYNC for providing line and frame sync signals. The output of the amplifier A1 is connected to the input of another amplifier A2 through a connecting capacitor C. The output of the amplifier A2 is connected to a first signal input of a video-data switch SWV/D.
One output of the circuit SYNC is connected -to the input of a characteristic time generator GEN. That output transmi-ts the lir~e sync signals to the generator G~N. Two other outputs S2 and S3 of the circuit SYNC are connected to the con-trol input of the stroke rnemory of the rnultiplexer ~X. The leading signal of a TV picture are transmitted through the output S2 and the output S3 is used for identifying the linex of the picture by coun-ting those lines. At last, one output of the circuit SYNC, which supplies the line frequency signal, is connected to the sync input of a crystal clock CLMOD of which the output is also connected to the generator GEN.
Two outputs of genera-tor GEt~ constitute the outputs A~E et ENV
of the modulator MOD toward the circuit PROT of the multiplexer MX.
Two other outputs are respectively connected -to the signal inputs of two level adaptors AD1 and AD2, of which the control inputs are connected to the input DPE of the modulator. The last output of the generator GEN is connected to the inpu-t of the amplifier A2 through a clamping circuit VL and a resistor R.
The data to be transmitted by the modulator MOD are supplied by the converter P/S, Fig. 3, through the wire ED which is connected to the input of a filter LP. The output of filter LP is connected to the input of an amplifier A3 of which -the output is connected to the second input of the switch SWV/D. The output of -the switch SWV/D is connected to a broadcasting transmitter, not shown, through an amplifier A4.
- The switch SW/D comprises two diode bridges BRl and BR2 of which the inputs are respectively controlled by the ou-tputs of the circui-ts AD1 and AD2. The outputs of the bridges BRl and BR2 are connec-ted to the output of the switch. In practice, only one of the bridges BR1 and BR2 operates at a given time, the operation times thereoIbeing deterrnined by the generator GEN, through the level adaptors AD1 and AD2.
The filter LP is used as a shaping circuit for -the binary data transmitted from the multiplexer MX in such a way -that their frequency spectrum coincides with -the width of the video cha~nel used in the broadcasting transmitter. On the other hand, the arnplifiers A3 and A4 and the adaptors AD1 and AD2 are so designa-ted that the output electric level of A4, for the bits "1", has a value equal to the white level(700mV) or a given adjustable propor-tion of the white level.

The generator GE~ may be a RO~ addressed by the c~ock CLMOD for supplying the following signals:
- a data/video switchirlg signal which will be described hereinafter, - an insertion start signal AUE intended for the multiplexer MX, and - a line start for synchronising the clamping circuit VL.
In the switch SWV/D, the switching between -the two bridges BR1 and BR2 is controlled at a characteristic time at the beginning of the line, by the data-video switching signal supplied by the generator GEN, on one hand, and, on the other hand, by the insertion window signal supplied to DPE by the stroke memory. For a TV line transmitting standard video signal, the adaptor ADl is enabled for insuring the transmission through the bridge BR1, and the clamping circuit VL adjusts the blanking level of -the incoming video channel to OV, i.e. a potential e~ual to the "O" level on the data channel at the output of A3. For a data transmitting line, the adaptor AD2 is enabled for insuring the transmission through the bridge BR2, from the beginning of the active line which follows the standard analog line start signal.
For illustration purposes, the various circuits of the modulator r~OD may be selected as it follows: TDB2022 for amplifiers Al and A4;
LH0033 for amplifiers A2 and A3; 1~ octet rnemory 6349 for generator GEN; HP2813 for bridges BRl and BR2, the filter LP being a low-pass filter.
The control and supervision circuit OCC show in Fig. 5 is used for insuring the connection be-tween the operator and the central processor MPC of the access point.
The circuit OCC comprises an alphanumeric keyboard CLA, a display AFF, a processor M~PCC and a read only memory PROI1lCC, said devices being connected through the bus BCC. The processor MUPCC is connected to an input/output port PE/S which is connected to the ~91~3~2:~
cer,-tral processor MPC.
The keyboard CLA has twelve keyr. and the display device AFF has six electroluminescent elements.
The processor MUPCC is so programrned that it detects when a key has been pushed by the operator and transrni-ts -the code of the pushed key to the central processor MPC, through PE/S. In the other direction, the processor MUPCC receives the codes transmitted by the central processor MPC, through PE/S, said codes being displayed on one of the six elements of the display unit AFF.
A short protocol for the dialogue between the central processor MPC and the control circuit OCC allows to perform some elementary functions such as the erasing of the display and the enabling or disabling of the keyboard.
By way of examples, the various circuits of OCC may be selected as follows: Keys PREH for keyboard CLA; display elements TIL311 for devices AFF; processor 8035 for MUPCC; 2K octet memory 2716 for PROMCC, and circuit 82~6 for PE/S.
The cen-tral processor MPC operates as a master. It performs the connection with the operator -through OCC. It perforrns -the test of the couplers C1 Cn and informs the multiplexer MX of the loca-tions where the packs to be transmitted are. It will be recalled tha-t, contrary to the couplers, the multiplexer is not an in-telligent organ and that i-t cannot perform by itself the test of the couplers. A-t last, -the processor MPC controls the synchronization of all the processors of the access point when the system is first initiated. The processor may be a processor of the type INTEL 8024-2.
As shown in Fig. 6, the data flows, as indicated by -the full line FD from Cx to ~X, are obviously carried through the bus i1lB of the type MULTIBUS, bu-t they are no-t transrnitted through the central processor l.lPC. A direct access is provided -to the mernory of a coupler from the multiplexer.
The signalling flows indicated by the dotted line FS are also 8S~;~
carried thr~ough the bus ,i~/.
Two modes may be defined for the r~lles of the dialogue between the coupler processors and the central processor:
- the transfer mode for a dialogue controlling the DID0~ pack exchanges between the couplers and the multiplexer, under control of the central processor, which is in fact -the dialogue in continuous mode, - the control rnode, for a dialogue controlling the signal information exchanges between the central processor and the couplers.
For the dialogue rules in control mode, and before describing the control software, it will be recalled that while the couplers are intelligent, but yet they are slaves and they canno-t appropria-te the general bus ~. The couplers Cl-Cn operate only as rnemories with respect to the central processor MPC. The dialogue in control mode is performed through write/read operations in tables located in the memories RAMx of the couplers. More specifically, the dialogue tables are located at the beginning of the memories RAMx.
Concerning the software of the control mode, the notion of "context" will first be defined.
All the variables of such a software are grouped in a "general context". It is this group and only -this group which can be changed by -the operator; a parameter which is not in the general context is considered as a constant.
In fact, there is a group of eigh-t general contexts in the central memory of the central processor MPC, which are shown Fig. 7.
Said general contexts are preprogrammed and added to the software of the central processor MPC. At a given time, one of -the general contexts chosen by the opera-tor is enabled, i.e. the values of its variables are used by the central processor MPC and also by the couplers C1 Cn and -the rnultiplexer ~
A general context comprises two parts-- a "central context" which groups all the data relative to the S~
cen-t;ral ~ rt ol t~ Jster,: cen~i-a] ,r~cos.;or i;,PC, rn~] ~ ]cxer ;~, modulateur MOD, and - a set of "local con-texts" which group the data relative to each of the couplers.
A central con-text is shown in Fig. 8 and comprises two parts:
- a "standard zone" comrnon for all the applications;
- an "optional zone" depending on the application.
~ standard zone comprises, in order:
- the length, in octets, of the general context, the length information occupying two octe-ts;
- the number of couplers, occupying one octet;
- the adresses of the contexts of the couplers with reference to the beginning of the general context, each address occupying two octets with -the light weight octet in first, 8 addresses being provided9 that corresponds to a field having a size of 16 octets;
- the maximwn length of the DIDON packs, occupying one octet, being understood that the maximum number of octets in a pack comprises the header;
- the context zone of the channels comprising, per channel, the number of the digital channel XYZ and the number of the coupler which manages the access which channel XYZ is connected to, two octets being used for each channel, the firs-t octet indicating the values of X and Y and the second one the values of Z and -the coupler number, resulting in a zone of 64 octets for simultaneously con-trolling 32 channels DIDON.
Under the channel context, a zone of 128 octe-ts is reserved to the options.
It will be no-ticed that, in -the following and in compliance with the rules defined for the circuits INTEL, any data or address value occupying two octets in -the rnemory has its light weight octet in first.
In the described embodiment, the couplers are numbered from 1 to ~ 12 -~. A commorl nllrnh(n~ "l'5" is userl ~or materializing the central processor ~ilPC in ordcr to have the possibility of generatin~ digital channels within the access point, as a test channel for instance.
A local conteY.t is shown in ~ig. 9 and comprises two parts:
- a coupler context grouping the data common to all the channels processed by the coupler, and - a channel con-text groupin~ the data respectively relating to each channel processed by the coupler.
A coupler context comprises, in order:
~ the total length of the local con-text, occupying two octets;
- the number of the coupler, between 1 and 8, thus occupying 1 octet, that number allowing to identify a coupler with respect to the others, and a specific RA~`l memory addressing field correspor~ding to each coupler number;
- the type of coupler, occupying one octet, indicating the physical structùre of the coupler, without any indication as for the stored application software;
- the state of the coupler, occupying one octet, with one bit indicating if the coupler is operative or not, and - a zone of 8 octets reserved to the options.
A channel context is arranged as it follows:
- one octet indicating the number N of channels processed by the coupler;
- a N octet table describing the state of the N channels and indicating wether or not the channel is in operation, with its priority;
- a synchronising word table, i.e. a word of one octet per channel, i.e. N octets;
- a rate table, a code between 1 and 25 indicating the maximurn authorized rate for each channel, i.e. a field of N oc-tets;
- a maxirnum format table, i.e. of the maximum number of oc-tets in a data block, or N oc-tets;

- a table for '},( channel numbcr~; XYZ, i . c . ~r3 oc-tets, arld - a zone of ~ octe-ls reserved for the options.
A control operation will be now describecl.
As hereinbefore mentioned, the set of the operating parameters for the access point according to the invention is grouped wi-thin a context. As far as it is concerned, the latter is used by the central processor. But the major part of the parameters concerns the couplers, which corresponds to the notion of local context. Therefore, it is necessary to provide a transfer processus of the information from the central processor MPC which rnonitors the context, to the couplers. In practice, the image of the local context relating -to -the involved coupler is stored in each coupler. A control from the central processor consists in a comple-te or partial change of the image of the local contex-t, the corresponding information being -transferred to the coupler.
Indeed a control is a dialogue between the central processor MPC
which sends the control and the coupler Cx which receives it, takes it into account and suppl ies an execution acknowledgment.
That dialogue is established within a table shown in Fig. lO and located in the shared memory MCx of the coupler Cx. More precisely 9 the table begins at the first address of the shared memory zone MCx, i.e. the memory to which the local processor MUPx and the central processor ~PC have access through the bus MB. That address is a specific parameter of an application and is implicitly known by the central processor.
The dialogue table comprises:
- one octet for the control word used by the central processor MPC for indicating the type of the sent con-trol, and in which the bi-t "7" is a synchronizing flag allowing the central processor to indicate that it has sen-t a control by setting said flag -to 'l", and the coupler -to indicate that i-t has taken the control into account by setting said f`lag to "O";

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- one octet ~or the control ackow]edgment, ~Jhich a~lows the coupler to indicate the answer given to the control;
- one octet giving the operation state of -the coupler, in which the bit "7" indicates tha-t a fault in the coupler keeps it from operating, the other bits being possibly used within the scope of an application;
- a zone of 8 octets for the control parameters, which allows the transmission of specific parameters which cannot find place in -the local context;
- 2 octets for the address of the output buffer state table, that address concerning the transfer mode which will be described in the following;
- Z octets for the address of the local context image, the coupler being capable to s-tore its own local context image at any place in the shared rrlemory MCx.
The flow chart of the control operations is shown in Fig. ll and will be now described by using the various enti-ties constituing the contexts and the dialogue table which have just been described.
~ he central processor MPC has always the initia-tive, frequently at the request of the operator by means of the keyboard of the circuit OCC. First, the processor MPC makes sure that the last control concerning the involved coupler has been taken into account by examining the bit "7" of the control acknowledgment word; then, i-t updates the image of the local context by a par-tial or total re-write operation, and, at last, it positions the control word by setting its bit "7" to "l".
Each coupler is permanently in a control wait condition, i.e. it observes the control word and de-tects when the synchronising flag bit "7" is set to "l". The system could have another possibility which consists in generating an interruption on control word write. It will be recalled that the address of such a word is not free since it is imperatively the firs-t in the shared memory MCx.

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ThCrl, tlle contr~ol i'. Inrllysed, the acknowledgll(nt is positioncd, the correct processing is perfornled and the synchronising flag bit is set to "O".
It has been possible to determine general rules for the control mode, but it remains necessary to provide for a number of options which are different for each application and have to take into account the specifici-ty of a given coupler or a given application software.
On the contrary, in the transfer mode, the rules are simpler and completely and definitively determined for all the applications.
The couplers Cl-Cn, simple or complex, single or mul-ti-path, supply to the multiplexer MX, under control of the central processor MPC, the data grouped in a same and unchanging form, i.e. the complete DIDO~ pack, wi-th the header and the data block, stored in a buffer of which the size is a-t least equal to the rnaximum length of the packs for -the involved application.
A polling concept has been chosen instead of -the in-terrup-tion process which would have been difficult -to implement due to the fact that the architecture is greatly decentralized. Anyway, polling has the advantage of insuring a minimum processing power adjusted at will for the background tasks such as the operator dialogue or the supervision of the channel activities.
When incoming through an access circuit CASl-CAS4 or CAPl-CAP4 of a coupler Cx, -the data octets are stored in a buffer. They remain in the buffer up -to the dispatch time, at which -time -tl~ey are transferred into the buffer memory MTP of the multiplexer M~ . An instantaneous state is assigned to each buffer in order to deterrDine the evolution of a DIDOI~ pack. The opera-tions ~Inder-taken by the processors will depend on the value of said state, in conformi-ty wi-th the precise rules of the transfer mode.
The sta-te of a buffer comprises three symbols, all of -the binary type:
- symbol l: FREE/BUSY

- symbo] 2~ l'UT/OUTPUT
- symbol 3: EMPTY/FULL
If the buffer is free (syrnbol 1), the other two syrnbols are not significan-t.
The state diagram of the buffers is shown in Fig. 12. The zone processed by the coupler, a-t the left hand, has been distinguished from the zone processed by the central processor, at the right hand.
The state FREE is the wait condition, when the buffer is unoperative.
The state BUSY-INPUT-EMPTY means that the buffer is assigned to an access and that it is under filling. Thus, the word "empty" has not here its conventional meaning.
The state BUSY-INPUT-FULL means that -the DIDON pack contained in the buffer is ready for dispatching, and, in particular, that the index and the forrnat have been updated in its header and -that the flow control conditions have been checked. The latter state is the rnost important as it cons-titu-tes the interface between the coupler and the cen-tral processor.
The following state BUSY-OUTPUT-FULL corresponds to the fact that the buufer is now handled by the central processor which transmits polling orders -to the couplers. If -the conditions allow it, the central processor MPC then initiates the exchange ADM, i.e. the mernory direct access exchange, between the rnernory MCx of -the coupler and the memory MTP of the multiplexer MX; -the buffer is then set to the state BUSY-OUTPUT-EMPTY, indica-ting that an exchange ADM is under process. At the end of -the exchange ADM, -the buffer is disengaged (state FREE) and is thus ready for being filled again.
The state octet of the buff`er is comple-ted by a page number of 4 bits. I-t indicates the page of 64K octets wherein the buffer is. Thus it is possible -to have an adress field of lM octets, bu-t a buffer cannot straddle two pages of 64K octets.
It is necessar~y that the instantaneous sta-tes of the buffers can 85i~
be storerl. Also, it 1.; neccssary to know the actual address of the buffers in order to ~ive it to the circui-t cADrli.
In the dialogue -table shown in Fig. 10, a buffer sta-te address table is provided. In practice, said table shown in Fig. 13 is made of zones respectively corresponding to the buffers processed by the concerned coupler.
Each of the zones shown in Fig. 13 comprises:
- the state of the buffer, on one octet;
- the address of the buffer, on two octets;
- a chaining address corresponding to the state address of the next buffer, on two octets.
The chaining makes unnecessary for the central processor MPC to know the number of buffers used by the concerned coupler.
The above mentioned zones with the dialogue table and the context image are located within the shared memory MCx to which the central processor MPC has access. Since said zones are chained, they can be jointed or not.
In order to ascertain that the multiplexer operates in an optimum manner, the minimum nurnber of buffers is equal to 2, so that a pack is always ready at the end of the exchange ADM.
In anticipation with respect to the following description, il will be noticed that the behaviour of the coupler is very simple in the transfer mode.
For avoiding any overflow, the rule is to search for a free buffer by examining the states of the various buffers according to the following two rules:
- a FREE buffer is taken and assigned to one access;
- if the buffer is not FREE, i-t is a saturation case and it is necessary to wait for its disengagement.
A11 the buffers are set to the state FREE when the s~stem is initialized.
The rules for taking -the initializations into account will now be de~scribed.
It is necessary that cach processor can be selfini-tialized, in particular when the system is turned on. The central processor is the absolute master of the system, particulary at -the tirne of the general initialization.
Two initialization levels are defined as it follows:
- Ini-tialization level 1, controlled by a ~ESET of the multibus, i.e.
by a control of the type 01;
- Initialization level 2, controlled by the transmission of a control of the type 02; it is the case of the context change.
The two levels are chronologically in the described order.
The behaviour of each coupler is as follows:
- for an initialization level: the coupler becornes inoperative;
it initializes its dialogue table and its internal variables, i.e. the variables which do not depend on the local context. After that, it enables the control by the bit b~ of -the control word and waits for a control of the type 02 while as any other control must be disregarded.
- for an initializa-tion level 2: the coupler initializes the variables which depend on the local context, which is now available, and becomes normally operative.

The software of the cen-tral processor MPC will now described, that software being called "central software" in the following.
The central software has several functions which cornprise:
- initialization of all the entire access points;
- supervision of couplers and multiplexing;
- supervision of the outgoing channels;
- dialogue with the operator.
The modules corresponding to those various tasks are grouped in the general diagrarn shown in Fig. 14. Each module comprises a number of processus. Among those processus, the initialiæation processus allows each module to prepare its internal variables and initialize S2:1 the pripherals lhat it COIlt,l'O~';, in conformity wit}l the principle of a decentralized ini-tializal;ion.
Thus, in practice, the subroutine entity is the processus. A
processus may be initiated in three different manners:
- by another processus said "calling processus";
- by the synchroneous scheduler XSCS; or - by the asynchroneous scheduler XSCA.
All the tasks to be performed by the routine need a cyclic initia-tion of those processus according two methods:
- the synchroneous initiation, with a fixed period provided by a clock, of processus having real-time imperatives, which essentially relates to the proprely said multiplexing function, which must be enabled at "fixed hours" in order to have a minimum ou-tput flow whatever be the charge of the central processor, and the timing central function.
- the asynchroneous ini-tiation in which the asynchroneous scheduler XSCA operates background task, i.e. it initiates its processus during the non-active periods of the synchroneous scheduler XSCS, and -that concerns in particular the opera-tor dialogue and the supervision of the outgoing channels.
In addition to schedulers XSCA and XSCS, Fig. 14 shows a system module XSYS, a multiplexing module OUDI, a supervision module SURV and a dialogue module DIAL, plus a group "INITIALIZATION" wherein are grouped the initialization processus XINI, OINI, DINI and SINI
relative to the various modules are grouped.
The processus of the system module are summed up hereinafter, with, for each processus, the type, -the call mode and the function(s):

XINI - Initialization processus of the access point, - type: subrou-tine - call mode: Reset interruption by the c,perator - functions:

5~:~

- initiali.za~ioll c,f thc acce~.s poinl varlablec;, - initialization of the peripherals, - initiation of the initialization processus of the other modules - initia-tion of the initialization control.s for the couplers, - initiation of` the asynchroneous scheduler XSCA.

XSCA - Asynchroneous scheduler, which is also schema-tically shown, ou-t of XSCS j for a better understanding of the description.
- type: background task - call mode: none - function: initiation of the asynchroneous processus.

XSCS - Synchroneous scheduler, also shown separa-tely.
- type: subrou-tine - call mode: clock interruption - function: initiation of the synchroneous processus XTES - Timing control - type: processus, - call mode: synchroneous scheduler - function: control of every -timing in the access point, of which the list is as follows:

l Processor, indica-tor RUN
2 Saturati.on indicator 3 Supervision flag

4 Indicator display Closure operator control ~ Transmission of` time to the couplers It will be recalled -that a timing is defined by:

- a reference value, a current value, and - a state.
The processus XTES increments the current values and positions the state at "incoming timing" when the current value has reached the reference value. Any other processus may initiate one or another timing, or synchronize one or another timing, i.e. reset its reference value, whether or not the timing has been initiated. The flow diagram shown in Fig.15 illustrates the processus XTES.
Furthermore, in the box "Service Routines", the module XS~S
contains a set of service subroutines as follows:

XCO~ - Transmission of the controls -to a coupler Call mode: Calling processus which defines the coupler number, the control number and the control conditions.
For the acknowledgment type9 XCOM waits for the acknowledgment of the coupler before passing the reins to the calling processus.

XCPT~ - Reading of the control account of a coupler.

XCPET - Reading of the operating state of a coupler.

XEXPA - Generation of the expanded identifier table (XTvoi) It will be recalled that, in the contexts, the channel identifications or numbers are in a packed form:

X Y
Z ~
U being the number of the coupler managing the channel XYZ.
In order to facilitate the processing of said identifiers, it is preferable to use a table said "expanded table XTvoi", wherein the identifiers are in the form:

- 22 ~

XEXPA reads the lis-t of ~he identifi.ers ou-t of the general context under progress, and duplicates it in expanded form in XTvoi.

XCTX - Loading of a contex-t XCNTX is the variable zone of the con-text under program a-t a given time. XCNT1, XCNT2, etc., are cons-tan-t zones of contexts among which a choice may be n,ade. The subroutine XCTX will search one of those 7.0nes for duplicating it in to the zone X~NTX.

XEFEN - Equalization of the windows of the two frames If DIDON is normally used, the window is the sarne in the two TV
frames. XEFEN insures that the windows are identical by duplicati.ng the state of the odd frarne in to the even frame since i-t can be deduced from the odd frame by initiating the subroutine XEFEN.

XMOV - Transfer of a memory zone, XFIL - Filling of a memory zone with a fixed value.

XHAMB - Hamming decoding XHBCD - hexadecimal/BCD conversion XBCDB - Dialogue BCD/binary, with result on 1~ bits XMUL - Multipl.ication of a by-te with a double byte XDIV - Division of a double by-te by a double byte XRII - Searching for the channel index

5;~
The channels are id~ntifie(l ~)y their identifiers ~YZ. All -the tables of ~he sys~em re]a-tive to -the channels are ~rouped in -the same order, so tha-t the channels may be defined wi-thin the routine by their indexes in said tables.

Indeed multiplexing module perforMs the base function of the access point. That module has -two types of activity:
- scanning of the couplers, - initiation of DMA exchanges to the multiplexer M~.
It comprises four processus:

OINI - Initialization processus Call mode: calling processus In addi-tion of the initialization to the internal variables of the module, it has to initialize the multiplexer, i.e.:
- position the control register, - initialize the DAM, and - initialize the window.

OSCR - Supervision of the buffers Type: processus Call mode: synchroneous scheduler It has to scann the coupler buffers so as to detect a full buffer, as indicated in the flow diagram shown in Fig. 16. In -this case, the processus set -the buffer in to wait condition, and it stores its address, in particular. That buffer, in wait condi-tion, will be re~processed by the processus ODMA.

ODMA - Dispatching packs Type: processus Call rnode: synchroneous schedu]er It has to supervise whether:

sz~
l) a buffer is in wait condition , 2) ADM has completed for the previous exchange, 3~ the multiplexer is ready -to acrluire a pack.
During that subroutine, three -tables are looked up: a table OBLEC storing the addresses of the packs in the various coupler~s, a table OBPRE storing the address of the buffer which has been put in wait condition by OSCR, and a table OBSOR storing the address of -the buffer which has been pu-t in dispatch condition by ODMA.
Those tes-ts are shown in the flow diagrarn of the Fig. 17, and, where they are positive, ODMA initiates the ADM exchange. Furthermore, -the condition "full memory'' of the multiplexer MX is tested by ODMA
which eventually activates the indicator SATUR.
In practice, ADM hereabove mentioned exchange involves the transmission, from the central processor MPC, to the circui-t CADM of the multiplexer MX, of the identity of the coupler Cx wherein a buffer has been found in wait condition, and the address, found in that waiting buffer, the buffer Ai or Bi of MCx wherein the pack to be transferred into MTP is located. How a buffer is put in wait condition will be described in the following.

ODMA - End of` the ADM
Type: subroutine Call mode: interruption When the ADM exchange has been completed, it has to release the buffer which has been dispatched. The corresponding flow diagrarn is shown in Fig. 18.
The supervision module SURV is enabled by the asynchroneous scheduler. It is thus performed in the form of a background -task.
It has to supervise the buffers which are dispatched by the multiplexer MX, i.e. by the module OUDI, and to no-te the channels which effectively transmit the packs.
The channels are identified by their identifier XXZ read out of the buffer. i`ventua~ly, ~he chanrlel in(3e~. allows to find the coupler number and -the access nurnber ir1 thc coupler so that to display therr, by means the correct indicators.
It will be noticed -that it is a statiscal measure because every pack is not analysed. In practice, it can be noted thak the number of e~arnined samples is sufficien-t to ascertain the activity of the channels. The module SURV controls the tables SSURV, SNI, SNTOT, SNPA
respectively storing the results of the samplings (i.e. -the presence of a channel in line), the number of samples for each channel, the total number of saMples, and the total number of the dispatched packs.
The latter values allow to calculate an evaluation of the flow of each channel in order to indicate it to the operator.

SEXP Scanning of the output buffers Type: processus Call mode: asynchroneous scheduler.
The processus S~XP is illustrated in the flow diagram shon in ~ig. l9. It has to observe if a pack has been dispatched, if so, it searches for XYZ in the pack header, then, it computes the channel index by means of XRII and positions the tables of SURV for the involved channel, i.e. :
- the bit Bo of SSURV, flag of an active channel;
- SNI(i) the number of samplings per channel is incrementated, - SNTOT the total number of sampling is incrernented.
It has also to test a supervision timing and, if so, to store the results of the previous measures. To th:is end, all the tables of SURV (SNI, SNTOT, SNPA) are duplicated in the tables SNIV, SNOTV, SNPAV storing the results of the previous samples. The results are thus determined values which can be read out a-t any time, contrary to the first ones which change at any tirne.

SSOR - Indicator output 35~

r~'ype: processuci Call mode: asynchroneous scheduler The processus is illus-trated by the flow diagram shown in Fig.
20. It has to read the result of the statistical measures of SEXP by means of the tables SSUR, and therefore, to display it on the channel indicators. In fac-t, the indicators represent coupler physical accesses, the correspondence being made with the data contained in the channel contexts.
Furthermore, it also contro]s the general indicators of which the conditions are stored in the variable XVOYG. Among those indicators, there are:
- indicator RUli which blinks under control of SSOR with an appropriate timing, - indicator INSERT IN THE IMAGE which is controlled by the processus ~INI, initialization of the multiplexer, and - indicator SATUR which is controlled by ODMA when the packs are dispatched and by the SSOR when it is reset after a certain time.

The dialogue module DIAL provides the interface with the operator by means of the control circuit OCC which comprises a keyboard and a number of hexadisplays. The LED indica-tors of channel activity are directly managed by the survey module SURV. Depending on the type of operation and the training of the operator, three complexity modes may be defined for the action of said operator:
- level 0: initialization of the system, the simplest operation which consists in resetting the apparatus to a fixed and known base s-tate.
- level 1: selection of a context. Ten different contex-ts are s-tored in the ROM" and the operator may select a con-tex-t said "current context". ~Yhen the systern is initialized level 0, the context O is taken as the current contèxt.
- level 2: change in the context; a context having been S2~

previously selected (~evel 1), the operator may change any of the parameters within that context by means of specific con-t;ro]s.

The coupler software is implanted in the read only memory ROMx of the coupler Cx. The coupler software tasks are the following:
- reading the incoming characters applied to the 8 accesses CASI
CAS4, and CAP1 CAP4, and packing them.
- dispatching the packs of the eight digital channels to the multiplexer MX.
-- regulating the flows through the eight channels.
- controlling the interface protocol with the central processor MPC.
The architecture of the coupler sofware, which is shown in Fig.
21~ is similar to the central softwre, but it is simpler. It is a programming with well identified modules called by a scheduler.
The essential part of the programm comprises four groups of modules:
- a module ACCESS which insures the reading of the incoming data and their packing; indeed it comprises eight subrnodules which are identical, each of them controlling an access and being enabled by interruptions.
- a module OUTPUT whieh is assigned to supervise the pack buffers of the modules ACCESS and deeide the dispatching in eonformity with a number of criteria.
- a flow regulating module TMP which has to control the pack transmission timings for each channel.
- a module COM which processes the controls from the cen-tral processor MPC.
The module ACCESS is enabled by the in-terrup-ts from the input circuits of the eigh-t aeeesses. The modules OUTPUT and T~IIP are called a-t fixed periods by a synchroneous scheduler CHO~ which is itself controlled by a clock.

_ 28 -The module ('O~ has a backJroun~ tcls~. statuci, and, I'neeerore, it makes use of the available computer time when -the other -tasks have besn completed.
The greater part of the data is arranged in correspondance with the eight controlled accesses.
First, there are the pack buffers: two buffers Ai and Bi per access, and an output buffer C. The buffer Ai is used as the buffer under filling, and the buffer Bi is used as the dispatch wai-t buffer.
The other data are variable tables arranged in eight boxes for the eight accesses, with, in particular (Fig. Z2):
- a table AETABU for the conditions of buffers Ai and Bi, each of the sixteen buffers Ai and Bi being characterized by seven elements: priority or not, rninimum time reached, maximwn time reached, empty, partially full, full, type A or B; those conditions are analysed for the dispatch decision.
- a table ADRBUF for the addresses of the buffers - a table APTBLC for the pack data block pointers.
- a table AFORMA for the current channel formats.
- a table SINDIS for the current channel indexes, and - two tables TMIN and TMAX for the dispatch timingsO

The various modules of the coupler software will be now described.
In general, the notion of processus does not exist; only the mode COM is divided in three parts: CINI, CHOR and POLL which are described hereinafter:

CINI - Initialization of the coupler routine Type: processus Call mode: interruption by RESET or call by POLL
The processus is illustrated in the flow diagram shown in Fig.
23. It has to provide the control of the initalization protocol with 3Z35~

the central processor MPC, i.e. the receptio1- of the contro] 01, then of the control 02; then, C~I performs the initializatiorls of the peripherals and the variable tables.
The module rnay be enabled either when -the system is turned on, RESET, or in normal operation by the control management processus when the latter receives -the control Ol.

CHOR - Scheduler Type: processus Call mode: clock interruption.
The processus is illustrated in the flow diagram shown in Fig.
24. It is a mini-scheduler which has to successively initiate the modules OUTPUT and TMP. When those two modules are running, the parallel accesses CAPl CAP4 are inhibited in order that the dispatching and the time calculation are not delayed. On the contrary, -the series inputs CASl CAS4 which are free-running cannot be inhibited without risking the loss of an octet. However, it is no-t a real difficulty since the flows of those accesses are relatively low: at most, one input every mil]isecond.

POLL - supervision of the controls of the central processor MPC
Type: background task Call mode: none (loop) ~ he subroutine is illustrated in Fig. 25. One of its functions is to scan the table provided for the dialogue with the central processor MPC. ~hen it detects a control Ol, it jumps to the initialization procedure (CINI). In any other case, i-t initia-tes the routine corresponding to the received control. The flow diagrams of these routines are illustrated in Fig. 26.

Control routine Type~ subroutine Call mode: calling processus POLL
The routine functions consist in perforrning the specific tasks corresponding to each of the processed controls.
- control 02: context change Practically, it results in the re-initialization of every table in the system.
- control 03: change in maximum formats It is used for updating table AFORMA.
- control 04: coupler on/off The coupler is turned off simply by inhibiting any interruption.
It will be noticed that, in this condition, the coupler continues to receive the eventual controls from the central processor MPC.
- control 20: channel on/off Suffice it to mask/unmask the corresponding interrupt - control 21: change of the channel identifiers The header of the packs is changed in buffers Ai and Bi.
- control 22: STARTS change The header is changed as for control 21.
- control 23: change in the flows The tables TMIN and TMA~ which give the timing value for each channel are changed.

Any other control is disregarded.

The other modules are described hereinaf-ter.
ACCESS - reading of an octet on one of the accesses CAS1 CAS4 and CAPl CAP4, Type: module, Call mode: interruption The module is illustrated in the flow diagram shown in Fig. 27.
It has in charge to read the octet and store it in the buffer Ai. It manages the transfer into Bi when Ai is full. To this end, it changes L98~
-the cond-itior) Or A allC3 ~3 rl~ ad(3itioll, in case Or saturat;iorl, it inhibits -the input by inhibiting t~le interrup-t, -the latter being re-activated when a pack belonging -the corresponding channel is dispatched. The module access is the most critical part of the software since it operates at the level of one octet. It has been duplicated eight times for cancelling the indexed addressings which are very long if a microprocessor INTEL 80~5 is used. Furthermore, it has been optimized to the maxirmim for limiting the number of instructions executed in the more frequent branch of -the module.

OUTPUT - pack dispatching Type: module Call mode: scheduler The module has two different functions: first, it has to analyse the conditions of buffers ~i' 3i' in order to decide wether or not a pack must be dispatched; -then, if yes, it has to transfer -the pack into the buffer C in order to dispatch it.
The selection of the buffer to be dispatched is made in two phases: first, a higher priority "eligible" buffer is looked up, bit O
of the buffer condition; if the search is negative, a lower priority eli~ible buffer is looked up in the eight channels.
"Level 1" is the scan level for the higher priority buffers, and "level 2" is the scan level for the lower priority buffers. Within the same level, the buffer Bi, then -the buffer Ai are successively examined. ~or each additional scan, i.e. for an additional call of the module OUTPUT, the buffer B of the access following the one of the last dispa-tching is first analysed. It follows that -there is no priority between the accesses, which are exarnined one after the another in a cyclic rnanner The dispatch decision is taken in conformity with the principle of the decision table. Ihe table, Fig. 28, is addressed by ~he value of the buffer condition, and six outpu-t signals are retrieved which 3~

indicate wether tbe dispatching ~ay be Made at ~eve] 1 or 2, or wether the dispatching is not possible.
On the other hand, the dlspatching from a buffer Ai is distin~uished from the one from a buffer Bi of which the signals are different, the processing being not the same for the two cases as described hereafter with reference to the flow diagrarn shown in Fig.
29.
- Case of dispatching from a b~lffer ~: it is sufficien-t to update the index and the format which is -the maximum format, since B
is unavoidably full.
- Case of dispatching from a buffer A: a buffer A is not unavoidably full; it must be verified that the current format pertains to the list used for this channel. Ai is then transferred into Bi which is empty, and the parameters of Ai are re-initialized in view of the formation of another pack.
At last, the processus for preparing the dispatching is completed by programming of the condition of the buffer C: BUSY INPUT
FULL condition and address of the pack. It will be noticed that the buffer C is in fact a fictive buffer. At any time, it represents one of the buffers Ai and B .
In fact, the dispatching of a pack is decided in two cases:
- the buffer is ful1 and the -time in-terval t . between the mln transmission of two packs is reached, or - the buffer is only partly full, and the time in-terval t between the transmission of two packs is reached.
However, it will be noticed that, in the case of level 1, (high priority), the buffer is dispatched even if t a is not reached. Thus, a grea-t number of incomplete packs may be dispatched, but this is necessary by the fact of -the high priori-ty character of the channel.

TMP - flow regulation Type: module sz~

Call mode: selleduler The flow diagram of this Module is shown in Fi~,. 30. The module has to manage the bits tmin and tmaX of t~le condition of the buffers A
and B; those signals are timing signals or timers. Thus, -they mus-t be processed in real time due to the synchroneous aspect of the scheduler, so that TMP is called with a constant and known periodicity.

A number of counters, in the form of tables tmi and t , are associated with each channel and decremented by TMP. When one of the timers has completed its cycle, the corresponding bit t . or t is m1n max set in one of the conditions of Ai and Bi. Thus, the table TMIN is the base of the flow regulation which is thus performed at the level of the pack.
It will be noticed that, in theory, said regulation is fault-less, as the actual flow of a source does not depend of the flow of the other sources at a given time.
However it is possible to program the channels with a maximum flow, corresponding to a value said "maximum flow", corresponding to a value t i = In this case, the regulati~n by TMP does not operate. The resource is shared through interruption priorities some-how or other.

Claims (11)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. An access point structure for a network which broadcasts data packets, said access point comprising a plurality of coupler means, buffer memory means, and central control means all being interconnected by a main bus; means for coupling the buffer memory means to data packet transmission equipment of the broadcasting network;
each of said coupler means including dual access memory means, microprocessor means, read only memory means, and a plurality of access circuits all being interconnected by a local bus, each of said access circuits being connected to a data source means, means in each of said coupler means for storing coupler control software and a set of subroutines for exchanging information with the buffer memory means;
and switching memory means in the central control means for storing a connection table relating to a sequence for establishing time-division switched connections between said coupler means, and the buffer memory means, and for storing subroutines for controlling interconnections between each coupler means and its associated data source.

2. The access point structure of claim 1 wherein each of said coupler means further includes a local access circuit means coupled between said dual access memory means and the local bus, and a general access circuit means coupled between the dual access memory means and control circuit means for controlling the connections between the main bus, the local access circuit means and the general access circuit means.

3. The access point structure of claim 1, and multiplexer means comprising said buffer memory means in association with write access circuit means and parallel-series converter means, and direct access memory circuit means, strobe memory means, multiplexer control circuit means, all being interconnected by a local bus, and a main bus control circuit for controlling the write access circuit, the buffer memory means storing data in adjustable sizes in response to the size of the broadcasted packets.

4. The access point structure of claim 2, and multiplexer means comprising said buffer memory means in association with write access circuit means and parallel-series converter means, and direct access memory circuit means, strobe memory means, multiplexer control circuit means, all being interconnected by a local bus, and a main bus control circuit for controlling the write access circuit, the buffer memory means storing data in adjustable sizes in response to the size of the broadcasted packets.

5. The access point structure of claim 1, wherein each of said coupler means receives data from the associated data sources connected thereto, said data being stored in the dual access memory means to form data packets which are ready to be transmitted, said dual access memory means having a plurality of buffers, two of said buffers in said dual access memory means being assigned to each of said data sources, testing means responsive to a degree of a filling of one of said two buffers for changing the data storage to feed into the other of said two buffers when said one buffer is full, means for scanning in a predetermined order the conditions of the two buffers, an output buffer, and means reponsive to the result of the scanning and to the levels of priority for informing the output buffer of the address of a buffer having a data packet which is ready to be transmitted and for setting the ready buffer in a waiting condition.

6. The access point structure of claim 2, wherein each of said coupler means receives data from the associated data sources connected thereto, said data being stored in the dual access memory means to form data packets which are ready to be transmitted, said dual access memory means having a plurality of buffers, two of said buffers in said dual access memory means being assigned to each of said data sources, testing means responsive to a degree of a filling of one of said two buffers for changing the data storage to feed into the other of said two buffers when said one buffer is full, means for scanning in a predetermined order the conditions of the two buffers, an output buffer, and means reponsive to the result of the scanning and to the levels of priority for informing the output buffer of the address of a buffer having a data packet which is ready to be transmitted and for setting the ready buffer in a waiting condition.

7. The access point structure of claim 3, wherein each of said coupler means receives data from the associated data sources connected thereto, said data being stored in the dual access memory means to form data packets which are ready to be transmitted, said dual access memory means having a plurality of buffers, two of said buffers in said dual access memory means being assigned to each of said data sources, testing means responsive to a degree of a filling of one of said two buffers for changing the data storage to feed into the other of said two buffers when said one buffer is full, means for scanning in a predetermined order the conditions of the two buffers, an output buffer, and means reponsive to the result of the scanning and to the levels of priority for informing the output buffer of the address of a buffer having a data packet which is ready to he transmitted and for setting the ready buffer in a waiting condition.

8. The access point structure of claim 1 wherein each of said coupler means includes buffer storage means, the central control means scanning the conditions of the buffer storage means in the coupler means, multiplexer means for completing data packet transfer, means jointly responsive to an output buffer storage means in a waiting condition and to said multiplexer means having completed the multiplexing of a previous data packet for transferring the next data packet to the multiplexer means, direct access memory means, the central control means transmitting to the direct access memory means, the address read out of the waiting buffer storage means and the address of the coupler means associated therewith, and ordering a data packet transfer from the coupler means identified by the address read out of the said waiting buffer storage means.

9. The access point structure of claim 2 wherein each of said coupler means includes buffer storage means, the central control means scanning the conditions of the buffer storage means in the coupler means, multiplexer means for completing data packet transfer, means jointly responsive to an output buffer storage means in a waiting condition and to said multiplexer means having completed the multiplexing of a previous data packet for transferring the next data packet to the multiplexer means, direct access memory means, the central control means transmitting to the direct access memory means, the address read out of the waiting buffer storage means and the address of the coupler means associated therewith, and ordering a data packet transfer from the coupler means identified by the address read out of the said waiting buffer storage means.

10. The access point structure of claim 3 wherein each of said coupler means includes buffer storage means, the central control means scanning the conditions of the buffer storage means in the coupler means, multiplexer means for completing data packet transfer, means jointly responsive to an output buffer storage means in a waiting condition and to said multiplexer means having completed the multiplexing of a previous data packet for transferring the next data packet to the multiplexer means, direct access memory means, the central control means transmitting to the direct access memory means, the address read out of the waiting buffer storage means and the address of the coupler means associated therewith, and ordering a data packet transfer from the coupler means identified by the address read out of the said waiting buffer storage means.

11. The access point structure of claim 4 wherein each of said coupler means includes buffer storage means, the central control means scanning the conditions of the buffer storage means in the coupler means, multiplexer means for completing data packet transfer, means jointly responsive to an output buffer storage means in a waiting condition and to said multiplexer means having completed the multiplexing of a previous data packet for transferring the next data packet to the multiplexer means, direct access memory means, the central control means transmitting to the direct access memory means, the address read out of the waiting buffer storage means and the address of the coupler means associated therewith, and ordering a data packet transfer from the coupler means identified by the address read out of the said waiting buffer storage means.