CA1198825A - Data processing system having a performance measurement system - Google Patents
Data processing system having a performance measurement systemInfo
- Publication number
- CA1198825A CA1198825A CA000431520A CA431520A CA1198825A CA 1198825 A CA1198825 A CA 1198825A CA 000431520 A CA000431520 A CA 000431520A CA 431520 A CA431520 A CA 431520A CA 1198825 A CA1198825 A CA 1198825A
- Authority
- CA
- Canada
- Prior art keywords
- measurement
- interrupt
- state
- instruction
- setting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/24—Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/348—Circuit details, i.e. tracer hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
Abstract
ABSTRACT OF THE DISCLOSURE
A data processing system having a performance measure-ment system which is capable of setting desired performance measurement items. In the performance measuring system, an inter-rupt by internal timer is used for triggering performance measure-ment, the performance measurement system executes the processings by this timer interrupt, and processing results of each measure-ment item is collected on the main storage.
A data processing system having a performance measure-ment system which is capable of setting desired performance measurement items. In the performance measuring system, an inter-rupt by internal timer is used for triggering performance measure-ment, the performance measurement system executes the processings by this timer interrupt, and processing results of each measure-ment item is collected on the main storage.
Description
~9~82S
This invention relates to a data processing sys-tem in-cluding a performance measurement system and more specifically to a data processing system capable of measuring performance using a timer provided therein.
The background of the invention and the invention itself are described with reference to the accompanying drawings, in which:
Figure 1 is a block diagram illustrating a prior art data processi.ng system;
Figure 2 is a block diagram illustrating a data proces-sing system according to one embodiment of the present invention;
E`igure 3 illustrates an example of the log area used in the system of Figure 2;
Figure 4 illustrates an example of the measurement con-trol table used in the system of Figure 2;
Figures 5 through 9 are flow charts particularly illus-trating the process steps occurring in the performance measurement setting part oE Figure 2;
Figures lO and ll are flow char-ts particularly illus-trating the process steps occurring in the performance measure-ment processing part of Figure 2; and Figure 12 illustrates the structure of hardware used in implementing the system of Figure 2.
Performance measurement of a data processing system which executes instructions on the main storage by fetching them gives an important guideline to development of a system for the next phase, for example, and design of software.
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~882S
Figure 1 is an example of the existing system. An exis-ting performance measurement of a data processing system is con-figurated, for example, by the logic circuits of hardware as shown in Figure 1. A processing system 1 is provided, for example, with the counter circuits 4-1 to 4-n for each performance measure-ment item such as instruction appearing frequency measurement etc. and a selection circuit 3 selects a signal of the point for performance measurement through the control of con-trol circuit
This invention relates to a data processing sys-tem in-cluding a performance measurement system and more specifically to a data processing system capable of measuring performance using a timer provided therein.
The background of the invention and the invention itself are described with reference to the accompanying drawings, in which:
Figure 1 is a block diagram illustrating a prior art data processi.ng system;
Figure 2 is a block diagram illustrating a data proces-sing system according to one embodiment of the present invention;
E`igure 3 illustrates an example of the log area used in the system of Figure 2;
Figure 4 illustrates an example of the measurement con-trol table used in the system of Figure 2;
Figures 5 through 9 are flow charts particularly illus-trating the process steps occurring in the performance measurement setting part oE Figure 2;
Figures lO and ll are flow char-ts particularly illus-trating the process steps occurring in the performance measure-ment processing part of Figure 2; and Figure 12 illustrates the structure of hardware used in implementing the system of Figure 2.
Performance measurement of a data processing system which executes instructions on the main storage by fetching them gives an important guideline to development of a system for the next phase, for example, and design of software.
~ ?
~882S
Figure 1 is an example of the existing system. An exis-ting performance measurement of a data processing system is con-figurated, for example, by the logic circuits of hardware as shown in Figure 1. A processing system 1 is provided, for example, with the counter circuits 4-1 to 4-n for each performance measure-ment item such as instruction appearing frequency measurement etc. and a selection circuit 3 selects a signal of the point for performance measurement through the control of con-trol circuit
2 and thereby each counter circuit 4-1 to 4-n is operated by the trigger signals determined for respective measuring items. Accor-ding to such system of the prior art, a large amount of hardware only for perfoxmance measurement is necessary, the performance measurement items are fixed and performance of other items than that stored in the computer system precedingly cannot be measured.
However, iE performance measurement is carried out by the soft-ware operating under the usual operating system, it is requested to consider -that execution of a program itself for performance measurement realized by the software does not give any adverse effect on the result of measurement.
It is an object of this invention to provide a perfor-mance measurement system which eliminates the above problems and has flexibility so that desired performance measurement items canbe set without using hardware fixing the performance measure-ment items.
Therefore, in this invention, in order to attain this object, control is txansferred to the performance measurement ~98~S
system utillzing external interruption of a timer by a setting value of the timer within the processing system for triggering performance measurement, and the results of processings for each measurement item obtained by such performance measurement are col-lected, for example, on the main storage.
According to one broad aspect, the present invention provides a data processiny system, comprising: measurement infor-mation storing means for storing measurement information corres-ponding to performance measurement items; measurement control information storing means for storing performance measurement item information and performance measurement condition information;
: a timer; measurement control information setting processing means for controlling information setting in said measurement control information storing means; and performance measurement processing means which is started by sampling an interruption by said timer and for collecting measurement information and storing same in said measurement information storing means based on said perfor-mance measurement item information and performance measurement condition information.
According to another broad aspect, the present invention provides a data processing sys-tem performance measuring system using instructions having invalid operation codes, comprising:
storage means for storing an operating system program ln an oper-ating system storage area and a measurement system program in a measurement system program storage area; and a central processing unit operatively connected to said storage means and comprising:
an instruction register; a control storage operatively connected to 2~i -3a-said instruction register and storing micro-operation words each having an invalidity indicator and corresponding to the invalid operation codes, a control storage data reyister operatively connected to said control storage and generating a first inter-rupt signal when the invalidity indicator is present; a timer for generating a second interrupt signal; an interrupt control circuit, operatively connected to said control data storage register and said timer, ~or outputting the address of the opera-ting system storage area; an address register, operatively connec-ted to said interrupt control circuit and said storage means, forreceiving the output from said interrupt control circuit and addressing said storage means; and address modifying means, oper-atively connected to said control storage data registe.r and said ti.mer, for modifying the address in said address register to address the measurement system program area in dependence upon the first and second interrupt signals.
According to a further broad aspec-t, the present inven-tion provides a data processing system performance measurement process using instructions having an invalid operation code in the data processing system which includes an interrupt timer, comprising the steps of: (a) detec-ting an interrupt by one of the instructions; (b) setting measurement parameters and a mode, starting the performance measurement by loading the interrupt timer with an interrupt interval, stopping the performance mea-surement and resetting the mode; (c) detecting an interrupt by the interrupt timer; and (d) collecting performance measurement data, updating a performance log and loading the interrupt timer .~ ~
:.~
-3b~
with the interrupt interval.
The invention will no~ be described with reference to Figures 2-12.
In Figure 2, l i5 a processing sys-tem, 5 is a perfor-mance measurement instructing part, 6~1 to 6-4 are performance measurement setting instructions and particularly 6-l is a mode set instruction, 6-2 is a start instruction, 6-3 is a stop in-struction and 6-4 is a mode reset instruction. 7 is a program state word (PSW), 8 is an external 8~5 interruption processing part, 9 is a performance measurement setting part, lO is an external interruption processiny part, 11 is a performance measurement processing part, 12 is a timer, 13 is a log area, 14 is a measurement control table, lS is a state control information setting area, 16 is an itme informa-tion setting area.
The processing system 1 executes instructions on the main storage by fetching them and performs data processings.
The performance measurement instructing part 5 is composed of machine words instruction groups indicating performance measure-ment of processing system 1, and particularly operates the firmware to be described later by issuing the performance measurement setting instructions 6-1 to 6-4 provided in this invention. As the performance measurement setting instruc'-tions, for example, the mode set instruction 6-1 for setting the performance measurement items by selecting them, start instruction 6-2 for instructing start of performance measure-ment, stop instruction 6-3 for ins-tructing end of performance measurement, and mode reset instruction 6-4 releasing setting of selected performance measurement items. Generally, the machine word instruction consis-ts of the instruction code indicating kind of instruction and operand indicating an object of operation, but undefined instruction code is assigned to above performance measurement setting instructions 6-1 ~ 6-4. Therefore, when these instructions 6-1 ~ 6-4 are executed by the processing system 1, a program interrupt is generated hy operation exception due to detection of ~19~325i invalid instruction.
The program interrupt processing part 8 executes proc-essings corresponding to various program interruption through the processings that when program interrupt is generated by various exceptional conditions detected by execution of in-structions, control is transferred through the save of content of PSW 7 and update of it. If program interrupt occurs by execution of performance measurement setting instructions 6-1 ~ 6-4, the performance measurement setting part 9 structured by the firmware is started.
The performance measurement setting part 9 sets the control information designated by the mode set instruction 6-1 to the measurement control table 14 and controls start of measurement by setting the timer 12 in the timing of the start instruction 6-2. Details processings are described later.
The timer 12 operates in the same way as the ordinary CPU
timer and when the present time has passed, an external inter-rupt is generated. A timer can newly be provided ~or per-formance measurement but an existing timer such as dispatch timer, for example, used for dispatch of virtual computer system may also be used. In this embodiment, a dispatch timer is used.
When an external interrupt is generated, an external interrupt processing part 10 is started. The external inter-rupt processing part 10 starts the performance measurement processing part 11 by the interrupt code when such interrupt is caused by the timer 12. The performance measurement proc-~8~
essing part 11 is structured by firmware and as describedlater, collects the performance measurement information and stores it to the log area 13. An external interrupt due to the timer 12 is generated with a period designated freely by the mode set instruction 6-1 and therefore the performance measurement processing part 11 randomly performs sampling of measurement data with an external interrupt considered as a trigger.
As a performance measuxement item, there is, for ex-ample, a appearing frequency measurement of each instruction.
The log area 13 for the instruction appearing frequency measurement is for example constructed as shown in Fig. 3 and is reserved within the main storage. The area of 4 bytes is reserved in each instruction code for each of the supervisor (SUP) mode of the processing system 1 and a problem program (PP) mode, and a xelative address in the log area 13 is deter-mined, as sho~n in the figure, by the state mode obtained from -the 15th bit of PSW7 and the instruction code of 16th bit containing the instruction sub-code. Therefore, the per-formance measurement processing part 11 is capabel of counting up the directly checked instruction appearing frequency.
The measurement control table 14 is for example con-figurated as shwon in Fig. 4. In the state control informa-tion setting domain 15 of the measurement control table 14, the state flat 15-1 which is set to "1" by the mode set in-struction 6-1 or to "O" by the mode reset instruction 6-4 and the state falg 15-2 which is set to "1" by the start instruc-tion 6-2 or to "0" by the stop instruction 6-3. In addition, the sampling interval control bit 15-3 is also provided.
In this embodiment, the sampling period o~ 3.3 ms or 422.4ms can be selected by OFF/ON of said bit 15-3, it is naturally possibel to freely select more sampling periods by increasing a number of instructing bits. In the item information setting domain 16, for example, the tem ID indicating the measurement items and the address indicating the collecting range thereof are set for each item. FLAG16-1 indicates whether the logical address indicating the collecting reange is valid or invalid.
3y referring to Fig. 5 through Fig. 9, processings of the performance measurement setting part 9 is descxibed.
When, a program interrupt is generated, the program interrupt processing part 8 is started and the program in-terrupt processing part 8 judges first, by the processing 20 shwon in Fig. 5, whether the program interrupt code is the operation exception (X'01') or not. When it is not operation exception, ordnary program interrupt processing is executed.
In case it is opertion exception, an instruction code which has caused program interrupt is fetched by the processing 21 and then analyzed. As a result o~ analysis, when the performance measurement setting instruction 6-1 to 6-4 is judged, the per~ormance measurement setting part 9 is started.
The performance measurement setting part 9 calls, with the instruction code, the mode set instruction processing part 22, start instruction processing part 23, stop instruc-tion processing part 24 and mode reset instruction processing ~98~3~S
part 25, executes the processing of instructions 6-1 to 6-4 as described later. Then processing returns to the interrupt generating area after the condition code (CC) indicating result of execu~ion is set.
The mode set instruction processing part 22 executes processings as shown in Fig. 6. First, according to the processing 30 shown in Fig. 6, it is checked, by referring to the state flag 15-1 of the measurement control table 14 shown in Fig. 4, whether current state is ENABLE or DISABLE.
If current state is ENABLE, CC is set to "1" by the processing 36 and the processing returns to the calling area. If the state is DISABLE, the state flag 15-1 is turned ON by the pxocessing 31 and thereby the state becomes ENABLE. Then, the log area 13 is initialized by the processing 32 and the item information is set to the measurement control table 14 on the basis of the information designated by the operand of mode set instruction 6~1 by the processing 33. Moreover, the sampling interval control bit 15-3 is set to "O" or "1" by the process-ing 34 and finally CC is set to "O" indicating the normal end by the processing 35 and then processing returns to the cal]-ing area.
The start instruction processing part 23 executes proc-essing as shown in Fig. 7. First, the state flags 15-2 and 15-1 of the measurement control table 14 are checked by the processings 40 and 41 shown in Fig. 7. If the STA~T state is already started, CC is set to "1" by the processing 49, and when the current state is DISABLE, CC is set to "2" ky the ~L98~5 processiny 48, and the processing returns to the called area.
If the current state is STOP state and ENABLE state, control is transferred to the processlng 42, the state flag 15-2 is turned ON and thereby the START state appears. Then, if the sampling interval control bit 15-3 is ON as a result of reference thereto, the dispatch timer 12 is set to 422~4 ms by the processing 44, or such bit is OFF, the dispatch timer 12 is set to 3.3 ms by the processing 45. Moreover, external interrupt mask of timer 12 is turned ON by the processing 46 and thereby inhibit of external interrupt is cancelled.
Thereby, an external interrupt is generated after time passage of 3.3 ms or 422.4 ms. When the external interrupt mask is turned ON, CC is set to "0" by the processing 47 and the proc-essing returns to the calling area.
The STOP instruction processing part 24 executes proc-essing as shown in Fig. 8. First, the START state has started or not is judged by the processing 50. If current state is START, CC is set to "2" by the processing 54 and the process-ing returns. When the current stae is START, it is changed to the STOP state by the processing 51, and external interrupt mask due to the timer 12 is turned ON by the processing 52, thereby inhibitting interruption. Thereby, sampling is suspended. Then CC is set to "0" by the processing 53 and thereafter the processing returns to the calling area.
The mode reset instruction processing part 25 executes the processings as indicated in Fig. 9. It is first checked whether current state is START or not by the processing 60.
8~32S
When the START state has started, CC is set to "2" by the processing 65, and the processing returns to the calling area.
Then, it is chec~ed by the processing 61 whether current state is DISA~LE or not. When current state is DIS~BLE, CC is set to "l" by the processing 64. When it is ENABLE, it is changed to DIsAsI.E and CC is set to "0" by the processing 63. Then, processing returns to the calling area.
Processings of the performance measurement processing part 11 is then described by referring to Fig. 10 and Fig. ll.
When an external interrupt is generated, the external interrupt processing part 10 is started. The external in-terrupt processing part 10 judges whether the external in-terrupt code is X'1008' or not, namely it is an interrupt by the dispatch timer 12 or not by the processing 70 whown in Fig. 10~ If not, existing ordinary interrupt processing is carried out. If an interrupt by timer 12 is generated, control is transferred to the performance measurement processing part 11 .
The performance measurement processing part ll turns ON the internal flag by the processing 71. This internal flag is a control flag for sequential processing in such a case that the external interrupt is generated in double. Then, an address of log area 13 is fetched by the processing 72 and the measurement item is decoded based on the measurement control table 14. Thereafter, according to the result of decoding, various measurement processing part such as the instruction appearing frequency measurement processing part ~Lg8~2~
73, PSW instruction code trace processing part 74, 0xecutable instruction logic address distribution measurement processing part 75 in the problem program mode, executable instruction logic address distribution processing part 76 etc. are called.
By these processings, measurement information about processing system 1 at the interrupt timing is collected in the specified area of the log area. For the next sampling, a value of 3.3 ms or 422.4 ms is set to the dispatch ~imer 12 by the process-ing 77. Then after said internal flag is turned OFF by the processing 78, the processing returns to the interrupt generat~
ng polnt.
The instruction appearing frequency processing part 73 executes processings, for example, as shown in Fig. 11.
First, the old PSW oE external interrupt to which the PSW 7 at the ti.me when external interrupt is generated is fetched by the processing 8~ shown in Fig. 11. Then, it is checked whether the logical address is valid or not by referring to the FLAG 16-1 of the measu~ement control table 14 by the processing 81. If it ls invalid, it is checked, by the proc-essing 82, whether an instruction address obtained from said old PSW is wi-thin the measurement information collecting range, designated by the measurement control table 14, or not. If it is out of the range, no information is collected. If within the range, the instruction code and instruction sub-code at the time when an interrupt is generated is fetched on the basis of the instruction address of the old PSW by the proc-essing 83. As described for Fig. 3, the relative address in ~9~825i the log area 13 is generated by the processing ~4 and appear-ing frequency of the corresponding instruction is updated by the processing 85. ~hen above processings are repeated for each external interruption generated with the preset sampling synchronization, a randomized accurate instruction appearing frequency information as a whole can be obtained. If the executing period of each instruction in the processing system 1 is different, it is necessary to adjust result of collect-tion by weighting them with the inverse value of executing time.
The PSW instruction code trace processing part 74 performs the execution to directly trace contents or instruc-tion code of PSW when an interrupt is generated to the log area 13. The executable instruction logic address distribution measurement processing parts 75 and 76 execute the processing for counting the appearing frequency o~ executable instruc-tion for each presegmented logical address range. In the same way, the instruction can ~e called by providing the process-ing part which collects desired measurement information.
The, hardware operation in this embodiment is described.
In FigO 12, 100 is a central processing unit (CPU), 101 is a mian storage (MS), 102 is a firmware domain, 103 is an operat-ing system (OS) doman, 104 is an instruction register, 105 is an OP code part, 106 is a control storage (CS), 1~7 ~ 110 are micro operation words corresponding ~o MODE SET instruc-tion 6-1, START instruction 6-2, STOP instruction 6-3 and MODE RESET instruction 6-4 shown in Fig. 2. 111 is an invalid instructing ~lag, 112 is a CS data register, 113 is a timer circuit, 114 is a timer interrupt flag, 115 is an interrupt control circuit, 116 is a system control latch, 117 is a system base register, 118 is an address register, 119 is an interrupt signal line instructing ordinary interrupt to the OS domain, 120 is an interrupt signal line instructing in-terrupt to the firmware domain, and 121 is a control gate.
First, during execution of the ordinay program process-ings, the MODE S~T instruction 6-1, START instruction 6-2, STOp instruction 6-3, MODE RESET instruction 6-4 are read and they are set to the instruction register 104. Then~ the corresponding micro operation words 107 ~ 110 in the CS106 are alos read by the OP code 105 of it. Since above instruc-tions are invalid instructions, the invalid instructing flag 111 in the micro operation word is turned ON("l") and this invalid instructing flag is held by the CS data register 112.
When the invalid instructing flag becomes ON, the interrupt control circuit 115 is started through the interrupt signal line 120 and simultaneously, the system control latch 116 is set. The interrupt control circuit 115 sets the specified address in the OS area 103 to the address xegister 118 but when the system control latch 16 is ON, contents of system base register 117 is coupled to the upper part of the address register 118 through the control gate 121. For this reason, when the system control latch 11~ is in the set state, start to the OS area 103 is not triggered but start to the firmware domain 102 is triggered. Thereby, the instruction groups ~9~5 within the firmware domain are sequentially read and the perfor-mance measurement setting processing is carried ow-t.
When a count value set by the timer circuit 113 is completed, the timer interrupt flag 11~ becomes ON and the inter--rupt control circuit 115 is started throwgh the interrupt signal line 120. At this time, the operation similar to that carried out when the invalid instructing flag is ON is also carrled out and start to the firmware domain 102 is trig~ered. In the case of this timer interrupt, the performance measurement processing etc.
is carried out by the instruction groups within the firmware domain.
In the case of ordinary interrupt operation to the OS
area 108, the interrupt signal line 119 becomes ON and the system control latch 116 is reset. Therefore, any incremental shift of address is not carried out.
As described above, this invention is capable of set-ting desired performance measurement items without using hardware exclusively set aside for determining the performance measurement i-tems. Particularly, various functions of an existing processing system can be used directly. Therefore, this invention can be introduced rather easily into the existing processing systems.
A log area of the desired size can also be provided, ensuring ex~
cellent flexibility and expandability. Moreover, since the samp-ling interval can also be adjusted freely, desired measurement information can be obtained at any time desired by prGperly adjusting the overhead for the ordinary processing by the perfor-mance measurement system.
'3 ~ ~,~,
However, iE performance measurement is carried out by the soft-ware operating under the usual operating system, it is requested to consider -that execution of a program itself for performance measurement realized by the software does not give any adverse effect on the result of measurement.
It is an object of this invention to provide a perfor-mance measurement system which eliminates the above problems and has flexibility so that desired performance measurement items canbe set without using hardware fixing the performance measure-ment items.
Therefore, in this invention, in order to attain this object, control is txansferred to the performance measurement ~98~S
system utillzing external interruption of a timer by a setting value of the timer within the processing system for triggering performance measurement, and the results of processings for each measurement item obtained by such performance measurement are col-lected, for example, on the main storage.
According to one broad aspect, the present invention provides a data processiny system, comprising: measurement infor-mation storing means for storing measurement information corres-ponding to performance measurement items; measurement control information storing means for storing performance measurement item information and performance measurement condition information;
: a timer; measurement control information setting processing means for controlling information setting in said measurement control information storing means; and performance measurement processing means which is started by sampling an interruption by said timer and for collecting measurement information and storing same in said measurement information storing means based on said perfor-mance measurement item information and performance measurement condition information.
According to another broad aspect, the present invention provides a data processing sys-tem performance measuring system using instructions having invalid operation codes, comprising:
storage means for storing an operating system program ln an oper-ating system storage area and a measurement system program in a measurement system program storage area; and a central processing unit operatively connected to said storage means and comprising:
an instruction register; a control storage operatively connected to 2~i -3a-said instruction register and storing micro-operation words each having an invalidity indicator and corresponding to the invalid operation codes, a control storage data reyister operatively connected to said control storage and generating a first inter-rupt signal when the invalidity indicator is present; a timer for generating a second interrupt signal; an interrupt control circuit, operatively connected to said control data storage register and said timer, ~or outputting the address of the opera-ting system storage area; an address register, operatively connec-ted to said interrupt control circuit and said storage means, forreceiving the output from said interrupt control circuit and addressing said storage means; and address modifying means, oper-atively connected to said control storage data registe.r and said ti.mer, for modifying the address in said address register to address the measurement system program area in dependence upon the first and second interrupt signals.
According to a further broad aspec-t, the present inven-tion provides a data processing system performance measurement process using instructions having an invalid operation code in the data processing system which includes an interrupt timer, comprising the steps of: (a) detec-ting an interrupt by one of the instructions; (b) setting measurement parameters and a mode, starting the performance measurement by loading the interrupt timer with an interrupt interval, stopping the performance mea-surement and resetting the mode; (c) detecting an interrupt by the interrupt timer; and (d) collecting performance measurement data, updating a performance log and loading the interrupt timer .~ ~
:.~
-3b~
with the interrupt interval.
The invention will no~ be described with reference to Figures 2-12.
In Figure 2, l i5 a processing sys-tem, 5 is a perfor-mance measurement instructing part, 6~1 to 6-4 are performance measurement setting instructions and particularly 6-l is a mode set instruction, 6-2 is a start instruction, 6-3 is a stop in-struction and 6-4 is a mode reset instruction. 7 is a program state word (PSW), 8 is an external 8~5 interruption processing part, 9 is a performance measurement setting part, lO is an external interruption processiny part, 11 is a performance measurement processing part, 12 is a timer, 13 is a log area, 14 is a measurement control table, lS is a state control information setting area, 16 is an itme informa-tion setting area.
The processing system 1 executes instructions on the main storage by fetching them and performs data processings.
The performance measurement instructing part 5 is composed of machine words instruction groups indicating performance measure-ment of processing system 1, and particularly operates the firmware to be described later by issuing the performance measurement setting instructions 6-1 to 6-4 provided in this invention. As the performance measurement setting instruc'-tions, for example, the mode set instruction 6-1 for setting the performance measurement items by selecting them, start instruction 6-2 for instructing start of performance measure-ment, stop instruction 6-3 for ins-tructing end of performance measurement, and mode reset instruction 6-4 releasing setting of selected performance measurement items. Generally, the machine word instruction consis-ts of the instruction code indicating kind of instruction and operand indicating an object of operation, but undefined instruction code is assigned to above performance measurement setting instructions 6-1 ~ 6-4. Therefore, when these instructions 6-1 ~ 6-4 are executed by the processing system 1, a program interrupt is generated hy operation exception due to detection of ~19~325i invalid instruction.
The program interrupt processing part 8 executes proc-essings corresponding to various program interruption through the processings that when program interrupt is generated by various exceptional conditions detected by execution of in-structions, control is transferred through the save of content of PSW 7 and update of it. If program interrupt occurs by execution of performance measurement setting instructions 6-1 ~ 6-4, the performance measurement setting part 9 structured by the firmware is started.
The performance measurement setting part 9 sets the control information designated by the mode set instruction 6-1 to the measurement control table 14 and controls start of measurement by setting the timer 12 in the timing of the start instruction 6-2. Details processings are described later.
The timer 12 operates in the same way as the ordinary CPU
timer and when the present time has passed, an external inter-rupt is generated. A timer can newly be provided ~or per-formance measurement but an existing timer such as dispatch timer, for example, used for dispatch of virtual computer system may also be used. In this embodiment, a dispatch timer is used.
When an external interrupt is generated, an external interrupt processing part 10 is started. The external inter-rupt processing part 10 starts the performance measurement processing part 11 by the interrupt code when such interrupt is caused by the timer 12. The performance measurement proc-~8~
essing part 11 is structured by firmware and as describedlater, collects the performance measurement information and stores it to the log area 13. An external interrupt due to the timer 12 is generated with a period designated freely by the mode set instruction 6-1 and therefore the performance measurement processing part 11 randomly performs sampling of measurement data with an external interrupt considered as a trigger.
As a performance measuxement item, there is, for ex-ample, a appearing frequency measurement of each instruction.
The log area 13 for the instruction appearing frequency measurement is for example constructed as shown in Fig. 3 and is reserved within the main storage. The area of 4 bytes is reserved in each instruction code for each of the supervisor (SUP) mode of the processing system 1 and a problem program (PP) mode, and a xelative address in the log area 13 is deter-mined, as sho~n in the figure, by the state mode obtained from -the 15th bit of PSW7 and the instruction code of 16th bit containing the instruction sub-code. Therefore, the per-formance measurement processing part 11 is capabel of counting up the directly checked instruction appearing frequency.
The measurement control table 14 is for example con-figurated as shwon in Fig. 4. In the state control informa-tion setting domain 15 of the measurement control table 14, the state flat 15-1 which is set to "1" by the mode set in-struction 6-1 or to "O" by the mode reset instruction 6-4 and the state falg 15-2 which is set to "1" by the start instruc-tion 6-2 or to "0" by the stop instruction 6-3. In addition, the sampling interval control bit 15-3 is also provided.
In this embodiment, the sampling period o~ 3.3 ms or 422.4ms can be selected by OFF/ON of said bit 15-3, it is naturally possibel to freely select more sampling periods by increasing a number of instructing bits. In the item information setting domain 16, for example, the tem ID indicating the measurement items and the address indicating the collecting range thereof are set for each item. FLAG16-1 indicates whether the logical address indicating the collecting reange is valid or invalid.
3y referring to Fig. 5 through Fig. 9, processings of the performance measurement setting part 9 is descxibed.
When, a program interrupt is generated, the program interrupt processing part 8 is started and the program in-terrupt processing part 8 judges first, by the processing 20 shwon in Fig. 5, whether the program interrupt code is the operation exception (X'01') or not. When it is not operation exception, ordnary program interrupt processing is executed.
In case it is opertion exception, an instruction code which has caused program interrupt is fetched by the processing 21 and then analyzed. As a result o~ analysis, when the performance measurement setting instruction 6-1 to 6-4 is judged, the per~ormance measurement setting part 9 is started.
The performance measurement setting part 9 calls, with the instruction code, the mode set instruction processing part 22, start instruction processing part 23, stop instruc-tion processing part 24 and mode reset instruction processing ~98~3~S
part 25, executes the processing of instructions 6-1 to 6-4 as described later. Then processing returns to the interrupt generating area after the condition code (CC) indicating result of execu~ion is set.
The mode set instruction processing part 22 executes processings as shown in Fig. 6. First, according to the processing 30 shown in Fig. 6, it is checked, by referring to the state flag 15-1 of the measurement control table 14 shown in Fig. 4, whether current state is ENABLE or DISABLE.
If current state is ENABLE, CC is set to "1" by the processing 36 and the processing returns to the calling area. If the state is DISABLE, the state flag 15-1 is turned ON by the pxocessing 31 and thereby the state becomes ENABLE. Then, the log area 13 is initialized by the processing 32 and the item information is set to the measurement control table 14 on the basis of the information designated by the operand of mode set instruction 6~1 by the processing 33. Moreover, the sampling interval control bit 15-3 is set to "O" or "1" by the process-ing 34 and finally CC is set to "O" indicating the normal end by the processing 35 and then processing returns to the cal]-ing area.
The start instruction processing part 23 executes proc-essing as shown in Fig. 7. First, the state flags 15-2 and 15-1 of the measurement control table 14 are checked by the processings 40 and 41 shown in Fig. 7. If the STA~T state is already started, CC is set to "1" by the processing 49, and when the current state is DISABLE, CC is set to "2" ky the ~L98~5 processiny 48, and the processing returns to the called area.
If the current state is STOP state and ENABLE state, control is transferred to the processlng 42, the state flag 15-2 is turned ON and thereby the START state appears. Then, if the sampling interval control bit 15-3 is ON as a result of reference thereto, the dispatch timer 12 is set to 422~4 ms by the processing 44, or such bit is OFF, the dispatch timer 12 is set to 3.3 ms by the processing 45. Moreover, external interrupt mask of timer 12 is turned ON by the processing 46 and thereby inhibit of external interrupt is cancelled.
Thereby, an external interrupt is generated after time passage of 3.3 ms or 422.4 ms. When the external interrupt mask is turned ON, CC is set to "0" by the processing 47 and the proc-essing returns to the calling area.
The STOP instruction processing part 24 executes proc-essing as shown in Fig. 8. First, the START state has started or not is judged by the processing 50. If current state is START, CC is set to "2" by the processing 54 and the process-ing returns. When the current stae is START, it is changed to the STOP state by the processing 51, and external interrupt mask due to the timer 12 is turned ON by the processing 52, thereby inhibitting interruption. Thereby, sampling is suspended. Then CC is set to "0" by the processing 53 and thereafter the processing returns to the calling area.
The mode reset instruction processing part 25 executes the processings as indicated in Fig. 9. It is first checked whether current state is START or not by the processing 60.
8~32S
When the START state has started, CC is set to "2" by the processing 65, and the processing returns to the calling area.
Then, it is chec~ed by the processing 61 whether current state is DISA~LE or not. When current state is DIS~BLE, CC is set to "l" by the processing 64. When it is ENABLE, it is changed to DIsAsI.E and CC is set to "0" by the processing 63. Then, processing returns to the calling area.
Processings of the performance measurement processing part 11 is then described by referring to Fig. 10 and Fig. ll.
When an external interrupt is generated, the external interrupt processing part 10 is started. The external in-terrupt processing part 10 judges whether the external in-terrupt code is X'1008' or not, namely it is an interrupt by the dispatch timer 12 or not by the processing 70 whown in Fig. 10~ If not, existing ordinary interrupt processing is carried out. If an interrupt by timer 12 is generated, control is transferred to the performance measurement processing part 11 .
The performance measurement processing part ll turns ON the internal flag by the processing 71. This internal flag is a control flag for sequential processing in such a case that the external interrupt is generated in double. Then, an address of log area 13 is fetched by the processing 72 and the measurement item is decoded based on the measurement control table 14. Thereafter, according to the result of decoding, various measurement processing part such as the instruction appearing frequency measurement processing part ~Lg8~2~
73, PSW instruction code trace processing part 74, 0xecutable instruction logic address distribution measurement processing part 75 in the problem program mode, executable instruction logic address distribution processing part 76 etc. are called.
By these processings, measurement information about processing system 1 at the interrupt timing is collected in the specified area of the log area. For the next sampling, a value of 3.3 ms or 422.4 ms is set to the dispatch ~imer 12 by the process-ing 77. Then after said internal flag is turned OFF by the processing 78, the processing returns to the interrupt generat~
ng polnt.
The instruction appearing frequency processing part 73 executes processings, for example, as shown in Fig. 11.
First, the old PSW oE external interrupt to which the PSW 7 at the ti.me when external interrupt is generated is fetched by the processing 8~ shown in Fig. 11. Then, it is checked whether the logical address is valid or not by referring to the FLAG 16-1 of the measu~ement control table 14 by the processing 81. If it ls invalid, it is checked, by the proc-essing 82, whether an instruction address obtained from said old PSW is wi-thin the measurement information collecting range, designated by the measurement control table 14, or not. If it is out of the range, no information is collected. If within the range, the instruction code and instruction sub-code at the time when an interrupt is generated is fetched on the basis of the instruction address of the old PSW by the proc-essing 83. As described for Fig. 3, the relative address in ~9~825i the log area 13 is generated by the processing ~4 and appear-ing frequency of the corresponding instruction is updated by the processing 85. ~hen above processings are repeated for each external interruption generated with the preset sampling synchronization, a randomized accurate instruction appearing frequency information as a whole can be obtained. If the executing period of each instruction in the processing system 1 is different, it is necessary to adjust result of collect-tion by weighting them with the inverse value of executing time.
The PSW instruction code trace processing part 74 performs the execution to directly trace contents or instruc-tion code of PSW when an interrupt is generated to the log area 13. The executable instruction logic address distribution measurement processing parts 75 and 76 execute the processing for counting the appearing frequency o~ executable instruc-tion for each presegmented logical address range. In the same way, the instruction can ~e called by providing the process-ing part which collects desired measurement information.
The, hardware operation in this embodiment is described.
In FigO 12, 100 is a central processing unit (CPU), 101 is a mian storage (MS), 102 is a firmware domain, 103 is an operat-ing system (OS) doman, 104 is an instruction register, 105 is an OP code part, 106 is a control storage (CS), 1~7 ~ 110 are micro operation words corresponding ~o MODE SET instruc-tion 6-1, START instruction 6-2, STOP instruction 6-3 and MODE RESET instruction 6-4 shown in Fig. 2. 111 is an invalid instructing ~lag, 112 is a CS data register, 113 is a timer circuit, 114 is a timer interrupt flag, 115 is an interrupt control circuit, 116 is a system control latch, 117 is a system base register, 118 is an address register, 119 is an interrupt signal line instructing ordinary interrupt to the OS domain, 120 is an interrupt signal line instructing in-terrupt to the firmware domain, and 121 is a control gate.
First, during execution of the ordinay program process-ings, the MODE S~T instruction 6-1, START instruction 6-2, STOp instruction 6-3, MODE RESET instruction 6-4 are read and they are set to the instruction register 104. Then~ the corresponding micro operation words 107 ~ 110 in the CS106 are alos read by the OP code 105 of it. Since above instruc-tions are invalid instructions, the invalid instructing flag 111 in the micro operation word is turned ON("l") and this invalid instructing flag is held by the CS data register 112.
When the invalid instructing flag becomes ON, the interrupt control circuit 115 is started through the interrupt signal line 120 and simultaneously, the system control latch 116 is set. The interrupt control circuit 115 sets the specified address in the OS area 103 to the address xegister 118 but when the system control latch 16 is ON, contents of system base register 117 is coupled to the upper part of the address register 118 through the control gate 121. For this reason, when the system control latch 11~ is in the set state, start to the OS area 103 is not triggered but start to the firmware domain 102 is triggered. Thereby, the instruction groups ~9~5 within the firmware domain are sequentially read and the perfor-mance measurement setting processing is carried ow-t.
When a count value set by the timer circuit 113 is completed, the timer interrupt flag 11~ becomes ON and the inter--rupt control circuit 115 is started throwgh the interrupt signal line 120. At this time, the operation similar to that carried out when the invalid instructing flag is ON is also carrled out and start to the firmware domain 102 is trig~ered. In the case of this timer interrupt, the performance measurement processing etc.
is carried out by the instruction groups within the firmware domain.
In the case of ordinary interrupt operation to the OS
area 108, the interrupt signal line 119 becomes ON and the system control latch 116 is reset. Therefore, any incremental shift of address is not carried out.
As described above, this invention is capable of set-ting desired performance measurement items without using hardware exclusively set aside for determining the performance measurement i-tems. Particularly, various functions of an existing processing system can be used directly. Therefore, this invention can be introduced rather easily into the existing processing systems.
A log area of the desired size can also be provided, ensuring ex~
cellent flexibility and expandability. Moreover, since the samp-ling interval can also be adjusted freely, desired measurement information can be obtained at any time desired by prGperly adjusting the overhead for the ordinary processing by the perfor-mance measurement system.
'3 ~ ~,~,
Claims (14)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A data processing system, comprising: measurement infor-mation storing means for storing measurement information corres-ponding to performance measurement items; measurement control information storing means for storing performance measurement item information and performance measurement condition information;
a timer; measurement control information setting processing means for controlling information setting in said measurement control information storing means; and performance measurement processing means which is started by sampling an interruption by said timer and for collecting measurement information and storing same in said measurement information storing means based on said perfor-mance measurement item information and performance measurement condition information.
a timer; measurement control information setting processing means for controlling information setting in said measurement control information storing means; and performance measurement processing means which is started by sampling an interruption by said timer and for collecting measurement information and storing same in said measurement information storing means based on said perfor-mance measurement item information and performance measurement condition information.
2. A data processing system according to claim 1, further comprising performance measurement setting instructions, and said measurement control information setting processing means is started by an interrupt caused by said instructions.
3. A data processing system according to claim 1 or claim 2, wherein said performance measurement condition information comprises sampling period information to be loaded into said timer.
4. A data processing system according to claim 1 or claim 2, wherein said system further comprises main storage having a firmware domain storing instruction groups, and processing by said measurement control information setting processing means and said performance measurement processing means is executed by the instruction groups provided in the firmware domain of said main storage.
5. A data processing system performance measurement process using instructions having an invalid operation code in the data processing system which includes an interrupt timer, comprising the steps of: (a) detecting an interrupt by one of the instruc-tions; (b) setting measurement parameters and a mode, starting the performance measurement by loading the interrupt timer with an interrupt interval, stopping the performance measurement and resetting the mode; (c) detecting an interrupt by the interrupt timer; and (d) collecting performance measurement data, updating a performance log and loading the interrupt timer with the inter-rupt interval.
6. A process according to claim 5, wherein step (a) com-prises the steps of: (ai) determining whether the interrupt is by one of the instructions; and (aii) decoding the invalid operation code.
7. A process according to claim 5, wherein the instructions include a mode set instruction, a start instruction, a stop in-struction and a mode reset instruction, and said step (b) com-prises the steps of: (bi) setting the measurement parameters and the mode if the instruction is a mode set instruction; (bii) star-ting the performance measurement if the instruction is a start instruction; (biii) stopping the performance measurement if the instruction is a stop instruction; and (biv) resetting the mode if the instruction is the mode reset instruction.
8. A process according to claim 7, wherein the measurement process has enable and disable states, and step (bi) comprises the steps of: (1) setting a condition code to a first value if the process is not in the disable state; (2) changing the state from disable to enable if the process is in the disable state; (3) in-itializing the performance log if the process state has been changed in step (2); (4) loading the measurement parameters into a measurement control table if the process has been changed in step (2); (5) setting a sampling interval control bit if the process has been changed in step (2); and (6) setting the condition code to a second value if the process has been changed in step (2).
9. A process according to claim 7, wherein the measurement process includes enable, disable, start and stop states and a sampling interval control bit, and step (bii) comprises the steps of: (1) setting a condition code to a first value if the process is in the start state; (2) setting the condition code to a second value if the process is in the disable state and not in the start state; (3) changing the state from stop to start if the process is not in the start state and not in the disable state; (43 load-ing the interrupt timer with a first value if the sampling inter-val control bit is set and if the state has been changed in step (3); (5) loading the interrupt timer with a second value if the sampling interval control bit is not set and if the state has been changed in step (3); (6) turning on an interrupt mask if the state has been changed in step (3); and (7) setting the condition code to a third value if the state has been changed in step (3).
10. A process according to claim 7, wherein the measurement process includes start and stop states, and step (biii) comprises the steps of: (1) setting a condition code to a first value if the process is not in the start state; (2) changing the state from start to stop if the process is in the start state; (3) turning off an interrupt mask if the state has been changed in step (2);
and (4) setting the condition code to a second value if the state has been changed in step (2).
and (4) setting the condition code to a second value if the state has been changed in step (2).
11. A process according to claim 7, wherein the measurement process includes start, disable and enable states, and step (biv) comprises the steps of: (1) setting a condition code to a first value if the process is in the start state; (2) setting the condition code to a second value if the process is not in the start state and in the disable state; (3) changing the state from enable to dis-able if the process is not in the start state and not in the dis-able state; and (4) setting the condition code to a third value if the state has been changed in step (3).
12. A process according to claim 5, wherein step (d) com-prises the steps of: (di) turning on an internal flag; (dii) fetch-ing a log area address and decoding a performance measurement identifier; (diii) collecting performance measurement data corres-ponding to the identifier and updating the performance log;
(div) loading the interrupt timer with the interrupt interval;
and (dv) turning off the internal flag.
(div) loading the interrupt timer with the interrupt interval;
and (dv) turning off the internal flag.
13. A data processing system performance measuring system using instructions having invalid operation codes, comprising:
storage means for storing an operating system program in an oper-ating system storage area and a measurement system program in a measurement system program storage area; and a central processing unit operatively connected to said storage means and comprising:
an instruction register; a control storage operatively connected to said instruction register and storing micro-operation words each having an invalidity indicator and corresponding to the invalid operation codes; a control storage data register opera-tively connected to said control storage and generating a first interrupt signal when the invalidity indicator is present; a timer for generating a second interrupt signal; an interrupt control circuit, operatively connected to said control data stor-age register and said timer, for outputting the address of the operating system storage area; an address register, operatively connected to said interrupt control circuit and said storage means, for receiving the output from said interrupt control cir-cuit and addressing said storage means; and address modifying means, operatively connected to said control storage data regis-ter and said timer, for modifying the address in said address register to address the measurement system program area in depen-dence upon the first and second interrupt signals.
storage means for storing an operating system program in an oper-ating system storage area and a measurement system program in a measurement system program storage area; and a central processing unit operatively connected to said storage means and comprising:
an instruction register; a control storage operatively connected to said instruction register and storing micro-operation words each having an invalidity indicator and corresponding to the invalid operation codes; a control storage data register opera-tively connected to said control storage and generating a first interrupt signal when the invalidity indicator is present; a timer for generating a second interrupt signal; an interrupt control circuit, operatively connected to said control data stor-age register and said timer, for outputting the address of the operating system storage area; an address register, operatively connected to said interrupt control circuit and said storage means, for receiving the output from said interrupt control cir-cuit and addressing said storage means; and address modifying means, operatively connected to said control storage data regis-ter and said timer, for modifying the address in said address register to address the measurement system program area in depen-dence upon the first and second interrupt signals.
14. A system according to claim 13, wherein said data pro-cessing system generates a third interrupt signal and said add-ress modifying means comprises: a system control latch opera-tively connected to said control storage data register and said timer and to receive the third interrupt signal; a system base register; and a control gate operatively connected to said system control latch, said system base register and said address regis-ter.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57113317A JPS593651A (en) | 1982-06-30 | 1982-06-30 | Performance measurement system by firmware |
| JP57-113317 | 1982-06-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1198825A true CA1198825A (en) | 1985-12-31 |
Family
ID=14609160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000431520A Expired CA1198825A (en) | 1982-06-30 | 1983-06-29 | Data processing system having a performance measurement system |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US4601008A (en) |
| EP (1) | EP0098169B1 (en) |
| JP (1) | JPS593651A (en) |
| KR (1) | KR870000115B1 (en) |
| AU (1) | AU546369B2 (en) |
| BR (1) | BR8303530A (en) |
| CA (1) | CA1198825A (en) |
| DE (1) | DE3379851D1 (en) |
| ES (1) | ES8405173A1 (en) |
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| US4905171A (en) * | 1987-11-09 | 1990-02-27 | International Business Machines Corporation | Workstation controller performance monitor |
| US5003462A (en) * | 1988-05-31 | 1991-03-26 | International Business Machines Corporation | Apparatus and method for implementing precise interrupts on a pipelined processor with multiple functional units with separate address translation interrupt means |
| US5369764A (en) * | 1990-04-25 | 1994-11-29 | Blair; Gary L. | Method for sharing access to database elements in a data processing system |
| DE69229517T2 (en) * | 1991-03-11 | 2000-05-04 | Sun Microsystems Inc | Method and device for optimizing cost-based heuristic instruction scheduling |
| US5301312A (en) * | 1991-08-21 | 1994-04-05 | International Business Machines Corporation | Method and system for utilizing benign fault occurrence to measure interrupt-blocking times |
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| AU1994695A (en) * | 1994-03-14 | 1995-10-03 | Green Hills Software, Inc. | Optimizing time and testing of higher level language programs |
| JP3727382B2 (en) * | 1994-12-26 | 2005-12-14 | 三菱電機株式会社 | Control software execution system control method |
| US5881222A (en) * | 1995-01-23 | 1999-03-09 | International Business Machines Corporation | Method and apparatus for detecting performance problems in a windows-based computer system |
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| JP5029245B2 (en) * | 2007-09-20 | 2012-09-19 | 富士通セミコンダクター株式会社 | Profiling method and program |
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| US3688263A (en) * | 1971-04-19 | 1972-08-29 | Burroughs Corp | Method and apparatus for diagnosing operation of a digital processor |
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-
1982
- 1982-06-30 JP JP57113317A patent/JPS593651A/en active Granted
-
1983
- 1983-06-27 KR KR1019830002878A patent/KR870000115B1/en not_active IP Right Cessation
- 1983-06-29 CA CA000431520A patent/CA1198825A/en not_active Expired
- 1983-06-30 US US06/509,610 patent/US4601008A/en not_active Expired - Lifetime
- 1983-06-30 DE DE8383303786T patent/DE3379851D1/en not_active Expired
- 1983-06-30 ES ES523749A patent/ES8405173A1/en not_active Expired
- 1983-06-30 EP EP83303786A patent/EP0098169B1/en not_active Expired
- 1983-06-30 BR BR8303530A patent/BR8303530A/en not_active IP Right Cessation
- 1983-06-30 AU AU16411/83A patent/AU546369B2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| EP0098169A3 (en) | 1985-10-09 |
| KR870000115B1 (en) | 1987-02-11 |
| AU1641183A (en) | 1984-01-05 |
| AU546369B2 (en) | 1985-08-29 |
| JPS6226732B2 (en) | 1987-06-10 |
| EP0098169A2 (en) | 1984-01-11 |
| ES523749A0 (en) | 1984-05-16 |
| ES8405173A1 (en) | 1984-05-16 |
| BR8303530A (en) | 1984-02-07 |
| EP0098169B1 (en) | 1989-05-10 |
| JPS593651A (en) | 1984-01-10 |
| DE3379851D1 (en) | 1989-06-15 |
| KR840005227A (en) | 1984-11-05 |
| US4601008A (en) | 1986-07-15 |
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