CA1199691A - High-pass filter of the first order and application thereof to telephony - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
The invention provides a high-pass filter of the first order, sampled and without offset. It is constructed according to the diagram of the accompanying figure with two operational amplifiers, four capacitors and eight switches actuated at each period in two separate phases a and b. In a particularly interesting application, this filter without offset is placed just upstream of an analog-digital converter sampled at the same frequency as the filter and the second amplifier serves as a comparator for conversion outside the phases a and b (aplication to digital telephone transmission).

Description

- OACKGROUND OF THE INVENTION
The present invention relates to filters snd it will be explained with reference to a particular application which is speech processing for converting it into digital signals before transmission over a telephone line. This very import-5 ant application shows very well the interest of the filterof the invention but other applications may of course be considered for this filter.
In digital telephone transmission, the speech frequen-cy signals from a microphone undergo filtering so as to 10 retain only signals in a desired frequency band (200 to 3400 Hertz for example) before being applied to an analog-digital converter which operates in a sampled fashion at a frequency for example of 8 kHz (much higher than the speech frequencies transmitted). The analog-digital converter examines then 15 every 125 microseconds the level of the filtered speech sig-nal and converts it into a binary digital value which is fed to the telephone line.
For reasons of ease of integration on very small-sized semiconductor wafers, the filtering is essentially provided 20 by means of switched capacity filters (according to a prin-ciple described more especially in the articles of the review IEEE Journal of Solid State Circuits, vol SC-12, n 6, December 1977, pages 5~2-608). In these filters, the resist-ances of the circuits are replaced by capacitors switched at 25 a switching frequency higher than the frequencies to be trans-mitted through the filter. For example, the switching frequ-ency may be 12a kHz.
The advantage of switched capacity filters is that they allow very low cut-off frequencies to be obtained (e.g.
30 a high-pass filter cutting off at 200 Hz) without requiring components which would take up too much room on a silicon surface in an integrated circuit. In the application under consideration9 they allow more especially filters and ana-log-digital coder to be placed on the same substrate 9 and a 35 filtering and coding circuit to be formed on the same sub-strate for emission and a decoding and filtering circuit for reception (codec ~ filter).
Figure 1 shows 8 possible filtering and coding arrange-ment with a first high-pass filter 10, for exarnple of the third Drder, with a cut-off frequency of about 200 Hz, then 5 a low-pass filter 12, for example of the fifth order with a cut-off frequency of about 3.4 kHz, then an analog-digital converter 14.
Unfortunately, the low-pass filter which is an active filter formed from operational amplifiers, presents at its 10 output a not inconsiderable off~et voltage (for example of the order of 200 millivolts) which is interpreted by the converter as a signal level to be coded digitally. This is particularly troublesome because the coding law of the con-verter is established with high compression for improvement 15 of the dynamic extent of the transmitted sigllals. Thus, the weak signals are identified with coding levels much closer together than the stronger signals. The variations of the offset voltage at the output shift the overall level of the weak signals and give them an apparent digital value all the 20 more erroneous since the dynamic compression is more pron-ounced.
One means for eliminating the residual output offset due to the amplifiers would be to insert an RC network with a capacitor 16 in series between the low-pass filter 12 and 25 coder 14 (figure 2)~ But, considering the fre~uencies to be transmitted, the capacitor 16 must be too large(of the order of 40 nanofarads~ for integration thereof on the same sub-strate as the filter and the coder. It must then be provided externally, with two terminals for accessto the integrated 30 circuit, and it is known that the number of external access terminals of an integrated circuit must be reduced as much as possible.
So provision has been proposed (figure 3`) of a control loop acting on a sour~e 15 for compensating the residual off-35 set, this loop taking as input signal the sign bit of theconverter 14 and acting on the compensation source so that on average the sign bit is as often at O as at 1 ; in fact9 over an average period of time, the speech signal must present a zero mean value. If a sign bit is more often at 1 than at 0, it is because there is positive residual offset to be compensated for. But the control loop thus fDrmed has 5 a not inconsiderable time constant which affects the response time of the coder. Moreover, it itself requires a filtering capacitor 2~, with however a single external access terminal in the integrated circuit (figure 3).
To avoid this high capacity and the external access 10 terminal(s), a different solution is proposed here by start-ing from the idea that the high-pass filter, which could as has been said be of the third order, i5 broken down into an upstream high-pass filter, for example of the second order~
and a high-pass filter of the first order which presents no 15 residual offset voltage and which is placed downstream of the low-pass filter, immediately upstream of the converter, SUMMARY OF THE INVENTION
More precisely, the invention relates to a sampled filter comprising a high~pass filtering element of the first 20 order, without offset, which, thus placed in front of a coder, eliminates the above-mentioned drawbacks but which may be used in many other applicationsthan the one which has just been set forth.
The high-pass filtering element without offset comp-25 rises in accordance with the invention two operational amp-lifiers each having an inverting input, a non inverting in-put connected to a fixed potential and an output ; the filter-ing element comprises an input connected through a first capacitor to the inverting input of the first amplifier and 30 an output connected to the output of this amplifier ; a first switch is connected between the inverting input and the out-put of the first amplifier and a second switch is connected between the inverting input and the output of the second amplifier ; the inverting input of the first amplifier is 35 connected to a terminal of a second capacitor whose other terminal is connected through a third switch to the output of the second amplifier and through a fourth switch to the - output of the first amplifier ; the inverting input of the second amplifier is connected to a terminal of a third capi-citor and a fourth capacitor, the other terminsl of the third capacitor being connected through a fifth and a sixth 5 switch respectively to the output of the second and of the first amplifier, and the other terminal of the fourth capaci-tor being connected through a seventh and an eighth switch respectively to the output of the second amplifier and to a reference potential ; a switching control circuit is 10 provided for ensuring periodic conduction of thc different switches according to two separate conducting phas~s at each period, the uneven rank switches being closed during the first phase and the even rank switches being closed during the second phase.
The switches are preferably formed by MOS (metal oxide semiconductor) switches.
The filter provided for this high-pass filtering 01ement without offset comprises preferably, upstream of the filtering element, a sampler-inhibitor operating at the 20 same frequency as the switches and applying to the input of the filtering element voltage samples taken at the time of the second phase of a sampling period and inhibited at least until the end of the first phase of the Following period.
According to a particularly interesting feature oF
25 the invention, the filter forms part of a filtering and analo~-digital conversion assembly and the high-pass filter-ing element without offset is placed immediately upstream of a converter of the type comprising a variable threshold com-parator in the form of an amplifier, this amplifier being 30 formed by the second operational amplifier of the high-pass filtering element which is used outside thc first and sscond phases properly speaking of each sampling period, at a time when the second switch is open.
BRIEF DESCRIPTION OF THE DRAWI~GS
Other features and advantages of the invention will appear from the following detailed description given with reference to the accompanying drawings in which :

36~

Figures 1 to 3, already described, show the general arrangement of a coder preceded by Filters in the prior art ;
Figure 4 shows the high-pass filtering element of the 5 firstorder in accordance with the invention ;
Figure 5 shows a timing diagram of the closing phases of the switches ;
Figure ~ shows a block diagram of a filter and analog-digital coder for implementing the invention ;
Figure 7 shows the sampler-inhibitor, ~he high-pass filter and the converter of figure 6 ;
Figure 8 shows a timing diagram of the control signals for closing the different switches of figure 7.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The structure of the filtering element of the first order of figure 4 has been defined above. The two amplifiers are designated respectively by Al and A2, the four capacitors by Cl, C2, C3, C4 and the eight switches by Il, I2, I3, I~, I5, I6, I7, I8.
The input E of the filtering element receives a voltage Ve which is sampled and inhibited at a frequency which is for example 8 kHz and which is the same as the actuating frequency of the eight switches.
The output S of the filtering element is the output 25 of amplifier Al.
The uneven rank switches Il, I3, I5, I7 are enabled for a first phase of each sampling period Te. The even rank switches are enabled during a second phase separate from the first one. The two phases are shown in figure 5, lines a and 30 b respectively. The letters a and b close to the switches in figure 4 recall the conduction phases of each switch. The third line of figure 5 shows how the voltage to be filtered (shown with a broken line) is sampled at the time of phase b, with a period equal to the Dperating period Te of the switches 35 and how it is inhibited at the sampled value at least until after the beginning of the first phase a of the first follow-ing period (in practice until the second phase of the next period)~
To show what the transfer function of this filter is and how the offset voltages of the amplifiers are eliminsted, we will reason from z transforms as is conventional for samp-5 led systems.
Taking as time reference a given sampling period Te (shown in figure 5), and designating as Us and Vs' the effective output voltages at the output of the amplifiers during this period, that is to say in practice Vs during the 10 high level of phase b and V's during the high level of phase a, we will designate by Vsz 1 and V'sz 1, in accordance with the Z notation, the effective output voltages of the amplif-iers at the corresponding times of the period preceding the reference periodO
Similarly, Ve, Vez 1 and Vez will represent the in-put voltages at the reference period, at the precedin~ period and at the period which again precedes. But, since Ve is sarnpled and inhibited from the second phase, it can be seen that Ve changes in the middle of each period and that there 2n is present simultaneously during phase a of the reference period an output voltage V's and an input voltage Vez 1, and simultaneously during phase b an output voltage Vs and an input voltage Ue.
If, finally, we call Voff and V'off the offset voltages;
25 at theinput of amplifiers Al and A2 respectively, these volt-ages being assumed to be practically invariable from one per-iod to the next since it is a question of very slow drift voltages, the operation of the filter may be defined in the following way :
In phase b of the period preceding the reference period, the second amplifier A2 is looped with unitary gain by switch I2 and potentials Vsz and zero are applied respectively to capacitors C3 and C4 which are accordingly charged or discharged.
The reference potential connected to switch I8 is for example a zero potential to which are connected the non inverting inputs of the amplifiers.

Considering the offset voltage V'off pre~ent at the input of s~plifier A29 the sum o~ the cha~ges of capacitors C3 and C4 is (Vsz 1 _ V'off)C3 - V'offC4.
At the end of phase b switch I2 opens snd this overall 5 charge is trapped ; switches I4, I6, I8 are also opened at the end of phase b but with a slight delay with respect to switch I2.
When phase a of the next period beings, switches Il, I3, I5, ~7 are closed so that :
1) the potential V's is applied simutaneously to C3 and C4 ; this a priori indeterminate potential is automatic-ally adjusted as a function of the charge trapped on C3 and C4 so that the conservation of the charges is respected :
V's must be such that :
(V's - V'off)(C3 + C4) = (Vsz 1 _ V'off)C3 - V'offC4 or V's = Vsz-lC3/(C3 + C4) (1)

2) V's is applied through switch I3 to C2 while the first amplifier Al is looped with unitary gain by switch Il and while Vez 1 is applied to Cl ; the result is that a 20 charge Cl (Uez 1 _ Voff) appears on capacitor Cl and a charge C2 (V's - Voff) on capacitor C2.
The sum of these charges on Cl and C2 is trapped at the end of phase a, at the time of opening of switch Il.
Switches I3, I5 and I7 are op0ned at the end of phase a, 25 very slightly after switch Il.
~he total trapped charge is (Vez l-Voff)Cl-~(V's-Voff)C2 In the next phase b, switches I2, I4, I6, I~ are closed so that the potential Vs is applied to capacitor C2.
But the input voltage Ve changes at this time (sampling on 30 the second phase) and passes from Vez 1 to VeO
The result is that the output voltage of amplifier Al is automatically adjusted so as to respect the conservation of the trapped charges Vs must take on a value such that:
(Vs-Voff)C2+(Ve-Voff)Cl = (Vez~l-Voff)Cl-~(V's-Voff)C2 35 or VsC2+VeCl = Vez~lCl+V'sC2 (2) Actually9 the voltages Voff and Voffz 1 or V'off and V'offz 1 should be considered but it is considered that Voff = ~o~fz 1 and V'off - V'offz 1 considering the very slow drift of these voltages with respect to the sampling rate.
Putting equations (1) and (2~ together; we obtain a 5 ~ranfer function independent of the two o~fset voltages, which is :
Vs Cl Ve C2 ~-C~/(C3~C4) It is indeed of a z transfer function of a 10 high-pass filter of the first order.
Of course, the voltage Vs must be "read" at the out-put of the filtering element during phase b.
One of the very important advantages of this partic-ular filter structure, besides elimination of the effect nf 15 the offset voltages, is the possibility o~ obtaining precise-ly the desired cut-off frequency despite the manufacturing dispersion of the capacities in the integrated circuits.
This cut-off fre~uency depends on the ratio C3/(C3+C4) and, in the applications where it is relatively low (telephony 20 applications for example), the ratio C3/(C3+C4) is fairly close to 1.
Physically, it will be readily understood that the fact of applying first of all Vs to one capacitor then U's to a capacitor of different value involves directly the ratio 25 of these two capacitors. But here Vs is applied first of all to capacitor C3 then V's to the same capacitor C3 plus a small capacitor C4. Only manufacturing dispersion comes as an inaccuracy into the corrective term C4/C3 which is small compared with unity.
The switches are preferably M05 transistors and it is particularly desirable for switches Il and I2 to be M05 transistors with very low parasite capacity. The control circuit for these transistors is not shown.
To ~ome back to the particularly interesting applicat-35 ion of filtering and digital conversion of speech signals in telephony 9 the circuit structure is shown in figure 6 which it is proposed constructing by using tha high-pass filtering element of the invention.

- Filtering in the useful frequency band is effected for example by means of a switched capacity high-pass filter 22, of the secon~ order 9 sampled at 128 kHz, having a cut-off frequency of about 200 Hz, followed by a switched capac-5 ity low-pass filter 24, of the fifth order, sampled at 128 kHz and hsving a cut-off ~requency of about 3.4 kHz, then by a sampler-inhibitor 26 which operates at 8 kHz, then by a high-pass filter of the first order ~8, without offset, in accordance ~ith the invention~ with a cut-off frequency of 10 about 200 Hz, which operates at the same frequency (a kHz) as the sampler-inhibitor 26 and whose switching phases are synchronized with those of the sampler-inhibitor in the way explained with reference to figures 4 and 5. A so-called "anti withdrawal" filter 32, non sampled, is plac~d upstream 15 of filter 22 ; this is a low-pass filter with a cut-off frequency of about 15 kHz (preferably a so-called Sal~n and Key cell) which eliminates more especially the frequencies in the 124 kHz to 132 kH~ band (centered on the sampling frequency), The output of the high-pass filter 28 is connected to an analog-digital converter 30 which also operates in a sampled fashion, at the same frequency of 8 kHz as filtPr 28, to supply every 125 microseconds a binary number repres-enting the amplitude of a signal sample applied to its input.
25 The operation of the converter is synchronized with that of switches Il to I8 of filter 28 so that the signal samples Vs applied to the converter for conversion are samples taken from the output S of filter 28 in phase b of the sampling period Te.
Converter 30 comprises at least one comparator For comparing the voltage Vs with reference values for defining a binary number repressntative of the level of Vs. According to one important fsature of the invention, this comparator is incorporated in filter 28 and is formed essentially by 35 the second amplifier A2 which operates periodically as a comparator outisde phases a and b. The voltage to be compared with reference values is defined by the charge ~rapped on capacitor C3 after the end of phase b.
This charge must be balanced by 8 ~uitable potcntial on capacitor C3 or on another capaicitor connected to the input of amplifier A2, or better still on a fraction of 5 capacitor C3 if it is formed from several capacitors in para-llel, so that the output of the amplifier remains at zero.
An imbalance in one direction or in the other causes the output of amplifier A2 to switch which is in an open loop.
The switching direction is used for defining a modification 10 of the potentials or of the input capacitors to which these potentials are applied, so as to draw nearer a state of equilibrium by successive approximations.
A logic search circuit automatically effects this drawing nearer in each sampling period, after the end of the 15 second phase b.
A particularly interesting implementation will be described, in which capacitor C3 is broken up into a plural-ity of parallel capacitors capable of being brought into use individually by respective switches, these capacitors, when 20 they are effectively connected in parallel, play the role of capacitor C3 in the filter of figure 3 ; when they are taken individually, they allow as it were a variable potent-ial to be established serving as reference for the converter during searching by successive approximations.
A diagram of this high-pass filter of the first order associated with an analog-digital converter and preced-ed by a sampler-inhibitor is shown in figure 7.
The sampler-inhibitor (at 8 kHz) comprises an operat-ional amplifier A3 having a grounded non inverting input, an 30 inverting input connected to a terminal of a capacitor C5 and an output connected both to the inverting input by a switch I10 and to the other terminal of capacitor C5 through a switch I12. This other terminal is connected by a switch Ill to a signal input which receives the signal to be sampl-35 ed and inhibited (signal coming in fact from the low-pass filter 24 in the chain of figure 6).
Since the low-pass filter 24 is itself sampled9 it ~C3~

should be noted that the conducting phase of switch Ill is synchronized with this ssmpling (12B kHz) 80 that the input voltage does not oscillate during closing of switeh Ill.
The output of the sampler-inhibitor, that is to say 5 the output of amplifier A3, is connectsd to the input E of the first order high-pass filter which is here again formsd by a two operational amplifier arrangement Al and A2 corres-ponding to the diagram of figure 4~ with this difference that capacitor C3 is rsplaced by seueral partial capacitors 10 (C31, C32, C33, C34 and C35 in figure 7 ), and that switches I5 and I6 are each replaced by as many switches (I51, I52, I53, I54, I55 and I61, I62, I63, I64; I65) as there are partial capacitors.
Switches I51 to I55 are all controlled together (at 15 the same time as switch I3) ; switches I61 to I65 are also all controlled together (at the same time as switch I4) so that operation of the circuit is the same as if there were a single capacitor C3 equal to the sum of the partial capacit-ors.
C3 = C31 + C32 + C33 + C34 + C35 Another difference with the diagram of figure 4, related to this breakdown of capacitor C3 into partisl capacitors isolated from each other by their respective switches, is the fact that a reference potential or zero 25 potential may be applied individually to each of the partial capacitors (or to several at the sam~ time), by means of the respective switches I91 and I'91 for C31, I92 and I'92 for C}2, I93 and I'93 for C33, I94 and 1 94 for C34 and I95 and I'95 for C35. This potential may itself assume several 30 values, for example a reference voltage Vref and the inverse thereof -Vref.
Finally, the filter associated with an analog-digital converter of ~igure 7 may comprise an additional amplifier A4 at the output of amplifier A2 for the case where this 35 latter dces not have sufficient gain for switching cleanly for the smallest voltage step to be detected.
The output of amplifier A4 (all or nothing output~ is applied to a logic b~lance search circ~it CL whose function is, as is moreo~er the case in sny analog-digital converter, to effect, Qccording to a pre-established search program, a comparison of the voltage t~ be converted successively with 5 different digitally coded reference values, until the refer-ence value is found which is the closest to the voltage to be converted, and whose function is to supply at its output a digital code corresponding to this value.
Here, use is nade of the fact that at the end of 10 phase b, the output voltage Vs of the filter (output S of amplifier Al) is stored in capacitor C~. If then the voltage at the terminals of C4 is maintained at zero (by leaving switch I8 closed) it can be seen that the charge stored on C3 is VsC3.
If a vDltage V is then applied to one of the capacit-ors C31 to C35, for example capacitor C31, by applying a zero voltage to the others, the output of amplifier A2, which is in an open loop, will switch in one direction or the other depending on whether V is greater or smaller than 20 VsC3/C31.
The partial capacitors C31 to C35 have weighted values, preferably in a geometrical progression with a co~mon ratio of 2;
for example C35 = Co, C34 = 2Co, C33 = 4Co, C32 = 8Co, and C31 - 16Co.
The balance search for effecting the conversion is carried out in the following way (while switches 11, I2, I51 to I55 and I61 to I65 are open):
The logic circuit CL applies a zero voltage to all the partial capacitors at the same time (closing of switches ~0 I'91 to I'95). Depending on the switching direction of ampli-fier A2, the sign bit of the Vs conversion is determined.
lhis sign bit determines, for the whole search program which follows, the sign of the reference voltage then applied to the partial capacitors (Vrefor -Vref).
The following phase consists in applying Vref (for ex-ample) to C31 only by opening switch I'91 and closing switch I91. Depending on the switching direction of amplifier A2, the logic circuit CL opens switch I91 agsin or leaves it closed.
Then switch 1'92 is opened and switch I92 is closed to apply Vref through C32. Depending on the switching direct-5 ion of the amplifier, the logic circuit opens switch I92again or leaves it closed snd so on as ~ar as the smallest capactor C35, according to a successive approximation proc-edure.
The state of switches I91 to I95 or I'91 to I'95 10 then forms a binary digital code of the value of voltage Vs, this code being supplied by circuit CL which controls closure of the switches.
The procedure may moreover continue with a more accurate measurement phase by then applying for example 15 successively different Vref values until a more accurate approximation af ~s is obtained.
Of course, this procedure is completely carried out during a sampling period Te (125 microseconds), the logic circuit CL operating at a considerably higher frequency so 20 as to allow the whole search to be carried out during this period.
The closing phases of the different switches Il to Ill of figure 7 will now be recalled, with reference to figure 8, except for switches I91 to I95 and I'91 to I'95 25 which are only actuated by the search logic circuit, so as to show how the analog-digital conversion phase may be carried out with the same amplifier A2 which serves for high-pass filtering, without disturbing the operation explain-ed in connection with figures 4 and 5. It should be noted 30 that actuation of switches other than I91 to I95 and I'91 to I'95 is effected at the frequency of 8 kHz by the switch-ing control circuit not shown, already mentioned in connect-ion with figures 4 and 5. The logic search circuit CL is synchronized with this switching control circuit so that the 35 search is effected completely outside phase b of conduction of switch Il, The closing phase of switch Il at the begin-ning of a sampling and conversion period of 125 microseconds 36~

is a square wave lasting 5 to 10 microseconds.
A slightly offset square wave, for example by means of two cascade inverters, forms a phase a*, the asterisk indîcat-ing the slight delay required between opening of switch Il 5 and opening of switches I3, I5 and I7. Here, switch I5 is replaced by switches I51 to I55, all controlled at the same time as I3 and I7 by the phase a*.
Switch I2 is closed during a phase b separate from phase a (and even froM a*), Switches I4 and I61 to I65 are 10 closed during a square wave b* which is slightly delayed with respect to the square wave of phase b. 5witch I8, which as has been explained must be closed during phase b* for operation of the filter~ is here closed not only for the duration of phase b* (for filtering) but for the whole of the 15 time required for the analog-digital conversion phase, In fact, it is only open at the time of phases a and a*. A
phase e of conduction of switch I8 has been shown in figure 1 : it comprises a long square wave beginning after phase a*
and finishing at the beginning of phase a of the following ~0 period.
Finally, the sampler-inhibitor is synchronized with phase b of the cycle in the following way : a phase c of conduction of switch I10 starts at the same time as phase b but is shorter. A phase c* of conduction of switch Ill 25 corresponds to phase c but finishes slightly afterwards. A
phase d of conduction of switch I12 begins after the end o~
phase c* but while phase b is still in progress (sampling during phase b) ; it lasts until phase b of the next period (in any case until after phase a) so that the inhibit-30 ed sample is always present at input E at phase a of thefollowingperiod.

Claims (6)

WHAT IS CLAIMED IS :

1. A sampled filter comprising a high-pass filtering element of the first order comprising two operational ampli-fiers each having an inverting input, a non inverting input connected to a fixed potential and an output, said filtering element comprising an input connected by a first capacitor to the inverting input of the first amplifier and an output connected to the output of this amplifier, a first switch being connected between the inverting input and the output of said first amplifier, a second switch being connected be-tween the inverting input and the output of the second ampli-fier, the inverting input of said first amplifier being connected to a terminal of a second capacitor whose other terminal is connected through a third switch to the output of said second amplifier and through a fourth switch to the output of said first amplifier, the inverting input of said second amplifier being connected to a terminal of a third capacitor and of a fourth capacitor, the other terminal of said third capacitor being connected through a fifth and a sixth switch respectively to the output of said second and of said first amplifier and the other terminal of said fourth capacitor being connected through a seventh and an eighth switch respectively to the output of said second amplifier and to a reference potential, a switching control circuit being provided for ensuring periodic conduction of the different switches according to two separate phases in each period, the uneven numbered switches being closed during the first phase and the even numbered switches during the second phase.

2. The filter as claimed in claim 1, further compris-ing, upstream of the input of said high-pass filtering elem-ment of the first order, a sampler-inhibitor operating at the same frequency as sampling of the filter and applying voltage samples taken at the time of the second phase and inhibited at least until the end of the first phase of the next samplingperiod.

3. The filter as claimed in claim 1,forming part of a filtering and analog-digital conversion assembly, said high-pass filtering element of the first order being connect-ed immediately upstream of a convertor of the type comprising a comparator in the form of an amplifier, this amplifier being said second amplifier used outside the first and second phases at a time when said second switch is open.

4. The filter associated with an analog-digital con-verter as claimed in claim 3, wherein said converter compris-es a logic balance search circuit adapted to apply to the input of said second amplifier, through capacitors, potentials chosen as a function of the switching direction of the output of the comparator.

5. The filter associated with an analog-digital con-verter as claimed in claim 4,wherein said third capacitor is broken up into a plurality of capacitors all connected at one side to the inverting input of the amplifier and capable of being connected individually by respective switches either to ground or to a reference analog-digital conversion potent-ial, or else to the output of said first amplifier or again to the output of said second amplifier under the control of the switching control circuit and the balance search circuit.

6. The filter associated with analog-digital convers-ion as claimed in claim 5, wherein said capacitors have respective values chosen according to a geometrical progress-ion of ratio 2.